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- Author / Uploaded
- R.K. Singh

This book comprehensively covers the undergraduate course on "Basic Electronics Engineering & Devices" and covers most of the syllabus of all Technical Universities and Technical boards, in fifteen chapters. This book is the valuable contribution in the field of Basic Electronics, Analog Electronics and Electronics Engineering which meets the expectations of the faculty and the students of all Technical Universities in particular and other Universities in general. Features of the book

Language is simple and easy to understand.

Analytical and mathematical approach has been provided wherever necessary.

Special note has been given at the end of the topic wherever necessary.

More than 300+ solved numerical problems for understanding the theoretical concepts.

Clear diagrams and complete mathematical steps.

ABOUT THE AUTHORS Dr. R.K. Singh is member of academic staff of Kumaon Engineering College, Dwarahat, Almora, where he is a professor in the department of Electronics and Communication Engineering. Dr. Singh has given his contribution to the area of Microelectronics, Fiber Optic Communications, and Solid State Devices. He has published several research papers in seminar/conference and journal papers. He is member of several institutional and educational bodies. Before joining Kumaon Engineering College, Dwarahat, he has worked in Birla Institute of Technology and Sciences (BITS), Pilani, and Central Electronics Engineering Research Institute (CEERI) Pilani. At present he is serving as OSD, in newly established Technical University of Uttarakhand known as Uttarakhand Technical University, Dehradun. He has Fabricated several microelectronics devices too.

ISBN:978-93-80386-30-0

9 789380 386300

BASIC ELECTRONICS ENGINEERING & DEVICES

Dr. R.K. Singh Ashish Dixit

Ashish Dixit completed his B.Tech. (Hons) Electronics & Telecommunication from U.P. Technical University Lucknow and M.Tech. (V.L.S.I Design) from C-DAC, Mohali affilated to Punjab Technical University, Jalandhar. Number of his papers have been published in national conferences and communicated in AIEEE journals. He has written number of Engineering Books. He is member of Indian Microelectronics Society, Chandigarh. Presently he is working as a lecturer in EC Department at Amity University Lucknow Campus.

BASIC ELECTRONICS ENGINEERING & DEVICES

ABOUT THE BOOK

Dr. R.K. Singh • Ashish Dixit

BASIC ELECTRONICS ENGINEERING & DEVICES

Basic Electronics Engineering & Devices

By Dr. R.K. Singh

Ashish Dixit

Prof. Electronics & Comm. Deptt. Kumaon Engineering College Dewarhat, Distt. Almora (U.P.) & Officer on Special Duty U.T.U., Dehradun Uttaranchal

B.Tech. (Hons.) E & T M.Tech. (V.L.S.I. Design) Lecturer, E.C. Deptt. Amity University Lucknow Campus, Lucknow Uttar Pradesh

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(v)

CONTENTS Chapters

Pages

Syllabus

...

(xi—xii)

Introduction

...

1—4

1. Semiconductor Materials and Properties

...

5—50

2. Junction Diode

...

51—76

3. Diode Applications

...

77—145

4. Breakdown Diodes

...

146—166

5. Bipolar Junction Transistor

...

167—230

6. Transistor Amplifier

...

231—263

7. Field Effect Transistor

...

264—303

8. Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

...

304—314

9. Number Systems and Logic Gates

...

315—403

10. Operational Amplifiers

...

404—460

11. High Frequency Transistor

...

461—505

12. Feedback Amplifiers

...

506—540

13. Multistage Amplifiers and Tuned Amplifiers

...

541—586

14. Large Signal (Power) Amplifier

...

587—630

15. Oscillator

...

631—664

Index

...

665—669

(vi)

FOREWORD Mr. Ashish Dixit is a well-known author of books on Electronics. His books are widely read by students of B.Tech. and B.E. programmes as well as by the candidates appearing in career oriented competitive examinations. The present book entitled “BASIC ELECTRONICS ENGINEERING & DEVICES” written by him and Dr. R.K. Singh also caters to all the requirements of students completely. The subject matter has been presented to the readers in a lucid and easy to understand manner. Great care has been taken to cover all the topics in detail and to uncover the subject matter of each and every topic completely. A number of solved problems is another attractive feature of this book. No effort has been spared to make this book an excellent one. I am sure that students of electronics will find this book very useful. I wish the readers as well as the authors best of luck and success.

PROF. S.T.H. ABIDI Dy. Director Amity School of Engineering (ASE) Amity University, Lucknow Campus

(vii)

FOREWORD I have briefly seen the complete manuscript of this book “BASIC ELECTRONICS ENGINEERING & DEVICES” and found that this is the best helpful for the students of B.E./B.Tech in developing the basics of the fundamentals of the Analog Electronics that plays an important role in developing the basics of the core of Electronics/Electrical Engineering. The presentation of the subject has been done in a nice way that the students will find it more lucid and easy to grasp the subject in totality. This “BASIC ELECTRONICS ENGINEERING AND DEVICES” book will also play a dominant role in developing the skills and knowledge of the students for their upcoming career oriented examinations. In conclusion, it has been observed that the overall benefit of this book is that the author has taken the utmost care in covering almost all of the topics and has solved problems related to the subject. WITH BEST COMPLEMENTS FOR FUTURE

PROF. NATHAI RAM. Head of Department (HOD) Amity School of Engineering (ASE) Amity University, Lucknow Campus Lucknow

(viii)

PREFACE It is a matter of great pleasure to present this book “BASIC ELECTRONICS ENGINEERING & DEVICES”. The object of this book is to bring out the subject matter in a most concise, compact, and lucid manner. This book is strictly for B-Tech. (first and second semester) students of all branches, affiliated to Indian Technical Universities. While writing this manuscript, we have constantly kept in mind the requirements of all the students, regarding the latest as well as changing trend of their examination. To make it really useful for the students, latest examination questions have been fully solved. The contents of this book are adequate, language is simple and easy to understand. In order to understand the topic in a very simple way, Analytical and Mathematical approach has been provided wherever necessary. Solved examples have been provided at places where the related concepts are discussed. In short, it is expected that the book will meet the needs of students, for whom it is meant. Chapter 1 describes the Basic Knowledge of Semiconductor Physics. Chapter 2 describes the junction diode under different bias condition. Chapter 3 describes the different diode applications such as rectification, clippers or limiters, clampers and logic gates etc. Chapter 4 describes the Detailed Knowledge of the Breakdown Diode. Chapter 5 describes Basic Knowledge of Bipolar Junction transistor and Chapter 6 describes the working principle and operation of Bipolar Junction transistor as an Amplifier. Chapters 7 and 8 describe the unipolar transistor such as FET and MOSFET. Chapter 9 describes the Basic Knowledge of Digital Electronics. Chapter 10 describes the Detailed Knowledge of Operational Amplifier. Chapter 11 describes the operation of transistor at high frequency. Chapter 12 describes different types of feedback Amplifiers. Chapter 13 describes the Basic Knowledge of multistage and tuned amplifier. Chapter 14 is about the power amplifiers and Chapter 15 describes different types of oscillators. Although every care has been taken to correct mistakes and misprints, yet it is very difficult to claim perfection. Any error, omission and suggestion, for the improvement of this book, brought to our notice will be thankfully acknowledged and incorporated in the next edition. —AUTHORS (ix)

ACKNOWLEDGEMENT We are thankful to the following colleagues for their adequate guidance and encouragement during the preparation of the manuscript of the book “BASIC ELECTRONICS ENGINEERING & DEVICES” like Technical Education Minister, Uttaranchal, Honorable Vice Chancellor Prof. V.K. Tiwari, U.T.U., Dehradun, Prof. Sudarsan Tiwari, HOD E.C.E, MNIT, Allahabad, Prof. B.R. Viswkarma, HOD. EE. Deptt., I.I.T., B.H.U., Prof. Nathai Ram, HOD Esc Amity School of Engineering, Lucknow Campus, Maj Gen K.K. Ohri, AVSM (Retd.), Director General, Amity University Lucknow Campus, Mr. Puneet Chandra Srivastwa, Senior Lecturer, R.K.G.I.T. Ghaziabad, Mr. Yogendra Prajapati, Senior Lecturer, VIET Bijnour, Mr. K.K. Mishra, Lecturer SITM Barabanki, Prof. Dr. P.K. Pandey, HOD E.C.E. Deptt., SITM Barabanki, Mr. A.N. Mishra, HOD E.C.E., B.B.I.E.T. & R.C. Jahangirabad, Miss Aparna Mishra, Lecturer B.M.A.S, Agra, Miss Nitu Aggrawal, Senior Lecturer, Amity University, Mr. Rafeek Ahmad, Lecturer A.I.E.T. Lucknow. Any constructive comment, suggestion, criticism from students and colleagues will be highly appreciated and gratefully acknowledged. —AUTHORS

(x)

SYLLABUS BASIC ELECTRONICS ENGINEERING & DEVICES CHAPTER 1 :

Semiconductor Materials and Properties Group IV materials, covalent bond, electron-hole concepts. Basic concepts of energy bands in materials, concept of forbidden gap. Intrinsic and extrinsic semiconductors, donors and acceptors impurities.

CHAPTER 2 :

Junction Diode p-n junction depletion layer v-i characteristics, diode resistance, capacitance diode ratings (average current, repetitive peak current, non-repetitive current, peak-inverse-voltage)

CHAPTER 3 :

Diode Applications rectifiers (half wave and full wave) calculation of transformer utilisation factor and diode ratings filter (C-filter), calculation of ripple factor and load regulation clipping circuits, clamping circuits, voltage multipliers

CHAPTER 4 :

Breakdown Diodes breakdown mechanisms (zener and avalanche) breakdown characteristics, zener resistance, zener diode ratings zener diode application as shunt regulator

CHAPTER 5 :

Bipolar Junction Transistor Basic construction, transistor action. CB, CE and CC configurations, input/output characteristics. Biasing of transistors-fixed bias, emitter bias, potential divider bias, comparison of biasing circuits.

CHAPTER 6 :

Transistor Amplifier Graphical analysis of CE amplifier, concept of voltage gain, current gain. h-parameter model (low frequency), computation of Ai, Av, Ri, R0 of single transistor CE and CC amplifier configurations

CHAPTER 7 :

Field Effect Transistor JFET : Basic construction, transistor action, concept of pinch off, maximum drain saturation current, input and transfer characteristics, characteristic equation CG, CS and CD configuration, fixed, self-biasing. (xi)

(xii)

CHAPTER 8 :

Metal Oxide Semiconductor Field Effect Transistor MOSFET : Depletion and enhancement type MOSFET-construction, operation and characteristics. Computation of Av, Ri, R0, of single FET amplifiers using all the three configurations.

CHAPTER 9 :

Number Switching Theory and Logic Design Number systems, conversion of bases. Boolean algebra, logic gates, concept of universal gate, canonical forms. Minimisation using K-map.

CHAPTER 10 : Operational Amplifiers Concept of ideal operational amplifiers, ideal op-amp parameters, inverting, non-inverting and unity gain amplifiers, adders, difference amplifiers, integrators. CHAPTER 11 : High Frequency Transistor Hybrid model for low frequency. Calculation of h-parameters for different transistor configuration. High frequency hybrid model. High frequency T-model. CHAPTER 12 : Feedback Amplifiers Introduction to feedback. Basic concept behind feedback. Types of feedback. Classification of negative feedback. Effects of feedback circuits and analysis of different feedback circuits. CHAPTER 13 : Multistage and Tuned Amplifiers Introduction to multistage amplifier. Cascade amplifier. Amplifier coupling. Different coupling used in multistage amplifier. Transformer coupled amplifier. Direct coupled amplifier. Darlington amplifier analysis. Bootstrapping. Tuned amplifier basics. Single tuned and Double tuned voltage amplifier. Stagged-tuned voltage amplifier. CHAPTER 14 : Large Signal (Power) Amplifier Introduction to large signal amplifiers. Direct coupled class-A amplifier. Transformer coupled class-A amplifier. Design theory of power amplifier. Conversion efficiency or collector efficiency. Harmonic distortion in amplifier. Complementary symmetry amplifier and thermal runaway. CHAPTER 15 : Oscillator Introduction to oscillator. Different conditions of oscillator. Bark hausen criterion. Different types of oscillators. Low frequency oscillators. Low frequency oscillators. Frequency stability of oscillator.

The word “Electronics” has been derived from the greek word ‘Electron’ plus ‘mechanism’. The meaning of this term signifies the study of electron behaviour under different field conditions. Thus electronics is that Branch of Science and Technology which deals with study of electron motion in various vacuum tubes, glass tubes and semiconductor devices. Generally, whole electronics dealwwws with two basic parts : (1) Physical Electronics and (2) Electronics Engineering. Physical Electronics deals with the actual phenomenon occurring within the device during its operation. However, in the part of Electronics, we study how an electronic device actually works. On the other hand, electronics engineering is the application part of core electronics and under this section we deal with successive development. Finally, electronics can be defined as “the field of science and engineering which deals with Electron devices and their utilization”.

Probably, the era of electronics started when a British Physicist “Thomson” invented the fundamental particle of all the atoms i.e., electron (in 1890). By the very advent of this particle many electron devices like vacuum tubes—diode, triode etc. came into existence. Their operating principle was solely based upon the controlled movement of these electrons. Inventions of fleming (Invented Diode valve in 1904, having capability of unidirectional current flow), Leedeforest (invented triode valve in 1907, having capability of amplifying A.C. signals of relatively lower magnitude) and many more revolutionized the development of Electronics. After that, in early 1920’s devices having more than three terminals like tetrode, pentode came into existence and this was the time when first picture tube (Kinescope developed by American’s in 1920’s) came into existence. During the second world war the major requirement was to establish long distance communication links, for this very purpose microwave devices like magnetron, klystron, travelling wave tube (TWT) and many more came into existence and as such they facilitated the researchers to invent Radar and other communication systems. Clearly it was the end of tube devices when in 1947, Walter Britain. John Bardeen and Shockley invented the first transistor at Bell Laboratories. General Electric (GE), RCA and Western Electric was producing the transistor commercially in 1951. The Discrete transistor, for Engineers and Researchers was like a panacia which solved their numerous problems. They started using this transistor as basic building block of all the Electronic circuits. In case of analog electronics, it was used as an amplifier. On the other hand, for digital circuits it served as an electronic switch. After further advancement in Electronic Industry several discrete components were fabricated on a single wafer and very first monolithic Circuits (ICs) came into existence after early 1960’s. The invention of IC fabrication technology reduced the size of devices through further miniaturization the packing density of the IC increasing many folds and the speed and accuracy were found to be up to the desired level. Several levels of IC series are given under here : 1

2

BASIC ELECTRONICS ENGINEERING & DEVICES Series

No. of Components

Years

SSI (Small Scale Integration) MSI (Medium Scale Integration) LSI (Large Scale Integration) VLSI (Very Large Scale Integration) First Commercial VLSI chip :

3 to 30 30 to 300 300 to 3000 more than 3000 64 K RAM 256 K RAM

1960–1965 1965–1970 1970–1975 late 1975 late 1970s early 1980s.

In 1947, the First Germanium transistor was introduced. The name transistor suggests that this device employs transfer of resistance. It means that whatever be the signal at input terminal, it will travel from low resistance side towards high resistance side and all this phenomenon depends upon the concentration profile of the semiconductor material used to form a three layer three terminal device i.e., so called transistor. This three terminal (Emitter, Base and Collector) device can be configured in many ways depending upon the use. At some instant it works as an amplifier (or oscillator) and at other instant it can be made to work as switch. The evolution of transistor as a discrete circuit component reduced size, cost and circuit complexity. At the same time the use of transistor increased reliability, portability and accuracy of the electronic circuits. This is the reason that’s why the transistors found tremendous and enormous applications in almost all the fields concerned with electronic industry.

For a beginner it has always been a confusion that why and how the electron tubes got abundant and their place substituted by the solid state (semiconductor) devices. The following table better describes the inherent characteristics and comparative study of the both class of the devices. S. No.

Particular

1.

Operating principle

2.

Size

3.

Portability

4.

Temperature dependency

Electron Tubes They were based upon the conduction of electron beam from cathode to anode i.e., they were based upon the principle of thermionic emission. These devices employed bigger size and delicate glass Jackets (valve). Because of their size and glass tube they were not easily transportable. Because of thermionic emission they suffer the problem of excessive heating and require extra circuitary for heat absorption. They require initial heating of cathode by other means.

Solid State Devices These are the Semiconductor (Si and Ge) based devices their operation solely depend upon the impurity concentration of dopants. Their size is comparatively very small. These are very portable and handy. Although their operation could be interrupted. Because of function temperature but they can sustain a wide range of external temperature.

3

INTRODUCTION 5.

Power consumption

They require high external field for thermionic emission and plate potential. Their turn-on and turn-off is very slow.

6.

Speed

7.

Reliability

By the passage of time their response get diminished.

8.

Durability

9.

Cost

They prove to be destructed easily because of delicate glass tubes. Their manufacturing cost is very high.

They require comparatively few volts for their biasing purpose. Their speed of operation is critical i.e., they can be used as excellent switches. For a particular-span of time (Several years) they remain equally reliable. They are highly durable.

They are relatively cheaper and so can be replaced easily if damaged.

Now-a-days there is not a single corner in which we can observe the absence of electronic devices and appliances. Life in today’s scenario offers many conveniences which utilize the foremost use of Electronics. The progress of a society and a country as a whole depends upon several factors. Among them, the development of Electronics and communication industry has got an indespensable and significant role. Various solid state devices like diode, transistor, oscillator, FET’s (Field Effect Transistor). MOSFET’s (Metal Oxide Field Effect Transistor) and OP-amp (operational amplifier) find particular uses in respective fields of developments. The tree representation given in next page shows a brief overview of various applications of electronics.

Usually electronic components may be broadly classified as active and passive components. Passive components are those which are to be connected with devices to perform particular mathematical and logical functions. These components are named as passive because they cannot generate their own signal and require external power to get energized. On the other hand, active components are the discrete electronic devices and they can generate internal signals for the circuit operation in which they are attached. One more difference between these components is that passive components have linear relationship between excitation variable and response (Output) variable, but the graph of active components is not linear. Any complex electronic circuit may contain thousands of components yet each component will necessarily be one of the following five types. Electronic Components

Passive Components

Resistors

Capacitors

Inductors

Active Components

Tube devices

Semiconductor devices

4

BASIC ELECTRONICS ENGINEERING & DEVICES

Table 1. Various Applications of Electronics ELECTRONICS

Defence Communications and Entertainment

Industry

Radar, Guided missiles, CodedCommunication

Medical Sciences

Automatic Control Systems, Computers

X-ray Electron Precision Microscope Measuring Electro Therapy Instruments e.g. Magnetic VTVM, CRO, Resonance Frequency Counters, Imaging (MRI) pH-meter Electrical Encep- Strain Guage, etc. lograph (EEG)

Line Communication

Wireless

Audio Systems

Telegraphy Telephony Telex Teleprinters

Radio Broadcasting

PA Systems Stereo Amplifiers Record Players Tape Recorders

Radio Broadcasting TV Broadcasting Fascsimile (Radio Photo) Satellite Communication

Instrumentations

In order to further classify various components of active class we have to go for following description. ACTIVE COMPONENTS

TUBE DEVICES

1. Vacuum tubes (rectifier, detector) 2. Vacuum triode (amplifier, oscillator) 3. Vacuum pentode (amplifier, oscillator)

1. Gas tubes (Voltage regulator, non-signs) 2. Thyratron (controlled rectifier)

SEMICONDUCTOR DEVICES 1. Function diode (rectifier, detector switching circuits) 2. Transistor (BJT amplifier, oscillator) 3. Field effect transistor (FET) (amplifier oscillator) 4. Unijunction transistor (UJT) (Power control switching circuits) 5. Silicon controlled rectifier (SCR) (speed control of motors, power electronics) 6. Tunnel diode (oscillators) 7. Zener diode (voltage regulator).

1

Semiconductors are those materials which have electrical conductivities lying between those of good conductors and insulators. The resistivity of semiconductors varies from 105 to 10+4 ohm-meter as compared to the values ranging from 108 to 106 ohm-meter for conductors and from 107 to 108 ohm-meter for insulators. The most important elemental semiconductors such as germanium (Ge) and silicon (Si) which belongs to Group IV of the periodic table and have resistivity of about 0.6 and 1.5 × 10 3 ohm-meter respectively. Besides these, there are certain compound semiconductors such as gallium arsenide (GaAs), indium phosphide (InP), cadmium sulphide (Cds) etc. which are formed from the combinations of the elements of group III and V. Another important characteristics of semiconductors is that they have small band gap. One thing that should be always kept in mind that all the semiconductors have negative temperature coefficient of resistance. This is due to the fact that the number of carrier in a semiconductor will increase significantly with temperature, resulting reduces the resistance of the semiconductor. The study of semiconductors resulted in development of discrete semiconductor devices such as diodes, transistors, field effect transistor, metal-oxide semiconductor field-effect transistor and latter on integrated circuits, microprocessors etc.

Group-IV Materials The conductivity of semiconductor is considerably greater than that of insulator but considerably less than that of good conductor. The elemental semiconductors such as germanium (Ge) and silicon (Si) which belongs to Group-IV of the periodic table and have resistivity of about 0.6 and 1.5 × 10 3 ohm-meter respectively. The band gap energies for the elements of group IV at 0K are as follows : C (diamond)

5.51 eV

Ge

0.75 eV

Si

1.16 eV

Sn (grey)

0.08 eV

Pd

0 eV 5

6

BASIC ELECTRONICS ENGINEERING & DEVICES

From the above figure it is clear that, at room temperature (i.e., 0K) diamond behaves as an insulator, Ge and Si as semiconductors and Sn and Pd as conductors. The importance of semiconductors is further increased due to the fact that the conductivity and the effective band gaps of these materials can be modified by the introduction of impurities which strongly affect their electronic and optical properties. The process of introduction of impurities in semiconductors in a precisely controlled manner is called doping.

The term semi is normally applied to a range of levels midway between two limits. The term conductor is applied to any material that will support a continuous flow of charge when a voltage source of limited magnitude is applied across its terminals. An insulator is a material that offers a very low level of conductivity under presence of an applied voltage source. However, a semiconductor, therefore, is a material that has a conductivity level somewhere between the extremes of an insulator and a conductor.

Resistivity () Resistivity is the property of the material. It is inversely related to the conductivity

1 ). That is, the higher conductivity level, the lower the resistance level. The term resistivity is often used in order to compare the resistance levels of materials. It is measured in ohm-meter. Mathematically, resistivity () may be defined as : of the material (i.e.,

=

RA ( cm) l

...(1.1)

R O

l

2

A = 1 cm

l = 1 cm

Fig. 1.1. Defining the units of resistivity.

From eqn. (1.1), R =

l A

...(1.2)

7

SEMICONDUCTOR MATERIALS AND PROPERTIES

where,

R = Resistance l = Length of the conductor A = Area of the cross-section = Resistivity of the material.

Some resistivity values for conductor, semiconductor and insulator are given below :

Conductor

106 cm

(copper)

Semiconductor

50 cm 50 × 103 cm

(germanium) (silicon)

Insulator

1012 cm

(mica)

Germanium (Ge) and silicon (Si) are the two most important semiconductors used in electronic devices. Some of the unique qualities of Ge and Si are due to their atomic structure. The atoms of both materials form a very definite pattern that is periodic in nature. One complete pattern is called crystal and the periodic arrangement of atoms a lattice. For Ge and Si the crystal has the three-dimensional diamond structure as shown in Fig. 1.2. Any material composed only of repeating crystal structures of same kind is called a single-crystal structure.

Fig. 1.2. Ge and Si single-crystal structure.

Let us now examine the structure of the atom itself and note how it might affect the electrical characteristics of the material. As we know that any atom is composed of three basic particles : the electron, the proton and the neutron. In the atomic lattice, the neutrons and protons form the nucleus, while the electrons revolve around the nucleus in a fixed orbit. The Bohr models of the two most commonly used semiconductors, germanium and silicon are shown in Fig. 1.3. Valence electrons (4 for each) Shells

Nucleus +

+

Orbiting electrons (a) Si-atom

(b) Ge-atom

Fig. 1.3. Atomic structure.

8

BASIC ELECTRONICS ENGINEERING & DEVICES

As indicated by Fig. 1.3 (a) silicon atom has 14 orbiting electrons, while germanium atom has 32 orbiting electrons. In each case there are 4 electrons in the outermost (valence) shell. In pure germanium or silicon crystal these 4 valence electrons are bonded to 4 adjoining atoms as shown in Fig. 1.4. Both Ge and Si are referred to as tetravalent atoms because they each have four valence electrons. Covalent bond Ge

+4

Valence electrons

Ge +4

+4

Ge

Ge Ge

+4

+4

+4

Ge

Ge

+4

+4

+4

Ge

Ge

Fig. 1.4. Crystal structure of germanium, illustrated symbolically in two dimensions.

A bonding of atoms, strengthened by the sharing of electrons is called covalent bonding. The binding forces between neighbouring atoms result from the fact that each of valence electrons of a germanium atom is shared by one of its four nearest neighbours. This electron-pair or covalent bond is represented in Fig. 1.4 by the two dashed lines which join each atom to each of its neighbours. A covalent bond is formed by sharing of one pair of electrons between the atoms is called a single covalent bond. The covalent bonds are not as strong as ionic bonds. Some of the interesting properties of covalent solids are as follows : 1. They are rigid, directional and crystalline in nature. 2. Usually, they are bad conductors of electricity. However, some of solids such as silicon and germanium can be made to conduct electricity by adding certain impurities in the controlled amount. 3. They have low melting and boiling temperature as compared to ionic solids.

The Hole. The absence of electron in the covalent bond is represented by the small circle as shown below in Fig. 1.5, and such a incomplete covalent bond is called a hole.

9

SEMICONDUCTOR MATERIALS AND PROPERTIES Free electron Ge Ge

+4

+4

+4

Ge Hole

Ge Ge

+4

+4

+4

Ge

Ge

+4

+4

+4

Ge

Ge

Fig. 1.5. Germanium crystal with a broken covalent bond.

The importance of the hole is that it may serve as a carrier of electricity comparable in effectiveness with the free electron. As we know that at a very low temperature (say 0 K) the ideal structure of Fig. 1.4 is approached, and the crystal behaves as an insulator. Since, no free carriers are available. However, at room temperature, some of the covalent bonds will be broken because of the thermal energy supplied to the crystal and conduction is made possible. This situation is illustrated in the above Fig. 1.5. The energy E G (will described latter) required to break such a covalent bond is about 0.72 eV for germanium and 1.1 eV for silicon at room temperature. Hole Mechanism. The mechanism by which a hole contributes to the conductivity is as follows : When a bond is incomplete so that a hole exists, it is relatively easy for a valence electron in a neighbouring atom to leave its covalent bond to fill this hole. An electron moving from a bond to fill a hole leaves a hole in its initial position. Hence, the hole effectively moves in the direction opposite to that of electron. This hole, in its new position, may now be filled by an electron from another covalent bond and the hole will correspondingly move one more step in the direction opposite to the motion of the electron. Here we have a mechanism for the conduction of electricity which does not involve free electrons. This phenomenon is illustrated in the Fig. 1.6, where a circle with a dot in it represents a completed bond and an empty circle represents a hole. Fig. 1.6 (a) shows a row of 12 ions, with a broken bond or hole at ion 5. Now imagine that an electron from ion 6 moves into the hole at ion 5, so that the configuration of Fig. 1.6 (b) results. If we compare this figure with Fig. 1.6 (a), it looks as if the hole (a) 1

2

3

4

5

6

7

8

9

10

11

(b)

Fig. 1.6. The mechanism by which a hole contributes to the conductivity.

12

10

BASIC ELECTRONICS ENGINEERING & DEVICES

in (a) has moved towards the right in (b) (from ion 5 to ion 6). This discussion indicates that the motion of hole in one direction actually means the transport of a negative charge an equal distance in the opposite direction. So, far as the flow of electric current is concerned, the hole behaves like a positive charge equal in magnitude to the electronic charge. We can consider that the holes are physical entities whose movement constitutes a flow of current.

Some Conclusions related to Electron-Hole Concept

1 eV is defined as that energy which an electron occupies in moving through a potential difference of 1 V.

An electron in the conduction band experiences almost negligible nuclear attraction. In fact electron in an conduction band does not belong to any particular atom. But it moves randomly throughout the solid. This is the reason why an electron in the conduction band are called free electron.

When an electron breaks a covalent bond and moves away, a vacancy is created in the broken covalent bond. This vacancy is called a hole. Whenever a free electron is generated, a hole is created simultaneously i.e., free electrons and holes are generated in a pairs. Therefore, the concentration of hole and free electrons will always equal in an intrinsic semiconductor. This type of generation of free-electron hole pairs is referred to as thermal generation.

The absence of electron in a covalent bond is called a hole. Hole acts as a virtual charge, although there is no physical charge on it.

It may be noted that hole current is due to movement of (unlike the normal current) valence electron from one covalent bond to another. Conduction band

Band gap (Eg)

Valence band

Fig. 1.6 (a)

Why it is called a hole current ? When the conduction is again by electron ?

The reason behind this is that the current flow in presence of holes in the Valence band.

Modern electronics is based on electrical conduction in solids. Electrical conductivity allows us to classify solids into three categories : Conductors, Semiconductors and

11

SEMICONDUCTOR MATERIALS AND PROPERTIES

Insulators. All three classes of materials are used in microelectronics. However, the key component is the semiconductor. The use of metals and insulators to design integrated circuits does not require specific knowledge. Yet, semiconductor devices does require a good knowledge in solid-state physics. The first fundamental notion is the band diagram. The band diagram defines the relationship between the energy of electrons and the momentum (P = mv). For electrons in the free space the E versus P relationship is quite simple; it is given by E =

P2 2m

derived directly from the basic laws of physics. Fig. 1.7 (a) shows a typical E versus P diagram. The diagram is drawn together with the parabola of free electrons and reveals that only given energy intervals (allowed bands) have a corresponding wave propagation vector. We can see that for large energies, the allowed bands become broad and the forbidden regions become a hit more larger. E

Allowed band Forbidden band

P

Fig. 1.7 (a). Simplified E versus P diagram for electrons in solids.

X-ray and other studies reveal that most metals and semiconductors are crystalline in structure. A crystal consists of a space array of atoms or molecules (strictly speaking, ions) built up by regular repetition in three dimensions of some fundamental structural unit. The large number of discrete but closely spaced energy levels is called an energy band. Because it has been found that when atoms come together to form a molecule, they exert an influence on one another. As a result of this, the allowed energy levels ‘split’ into closely spaced levels. A similar situation exists, when many atoms come together to form a solid. The splitted energy levels form continuous bands of allowed energy, which the electrons may occupy. Since the motion of electrons in a solid is controlled by the energy levels. Each material will, in fact, have its own set of permissible energy levels for the electrons in its atomic structure. The nature of energy bands is of primary interest in determining the electrical properties of the solid.

12

BASIC ELECTRONICS ENGINEERING & DEVICES

In the isolated atomic structure there are discrete (individual) energy levels associated with each orbiting electron as shown in Fig. 1.7 (b). Between the discrete Energy Valence level (outermost shell) Energy gap Second level (next inner shell) Energy gap Third level (next inner shell) Energy gap Fourth level (etc.) etc.

Nucleus

Fig. 1.7 (b). Discrete energy levels in isolated atomic structure.

energy levels no electrons in the isolated atomic structure can appear.

Some Important Points Regarding to Energy Bands 1. The number of energy bands in a solid is equal to the number of energy levels in any isolated atom of the same substance. 2. Each band consists of a large number of very closely spaced discrete energy levels. The number of such levels in each band is the same as that of number of atoms in the solids. 3. In considering the electrical properties, we are only interested in the two upper bands. These two bands are the conduction band and the valence band. The electrons, having energies in the conduction band, are those which take part in the conduction of current.

Fig. 1.8 shows a simplified representation of an energy level diagram of a solid. In this diagram only the conduction and the valence bands are shown. The inner (or lower) bands, which are completely filled, are not shown in the diagram. This has been done due to the fact that the inner bands are not important in determining the electrical as well as electronic properties of a solid. It may be noted that at absolute zero (0K) temperature, the electrons will occupy the lowest energy levels available to them. Thus at 0K, the valence band is filled, while the conduction band is completely empty. This arrangement of filled and empty energy bands has an important effect on the electrical as well as electronic properties of a solid.

SEMICONDUCTOR MATERIALS AND PROPERTIES

13

Energy

Conduction band

Forbidden energy gap (Eg)

Valence band

Fig. 1.8. Simplified energy level diagram of a solid.

The energy gap between the conduction band and the valence band is called the forbidden energy gap. It is represented by Eg and measured in electron volt (i.e., eV) mathematically : 1 eV = 1.6 × 1019 J If an electron in the valence band is to move throughout the crystal, it must be elevated first from valence band into the conduction band. This can be done only, if a certain amount of energy equal to energy gap is supplied or added to the material. When a electron in the valence band acquires enough energy to move into the conduction band, it is called a free electron. The free electron can move throughout the crystal. This provides an electric current, when a voltage source is connected across the material.

As a matter of fact, every solid has its own characteristics energy band structure. This variation in band structure is responsible for the wide range of electrical properties observed in various materials. Now, we shall discuss the electrical properties of insulators, conductors and semiconductors. Insulators. The materials, in which the conduction and valence bands are separated by a wide energy gap (Eg > 3 eV) as shown in Fig. 1.9 (a) are called insulators (also referred to as dielectric materials). A wide energy gap means that a large amount of energy is required, to free the electrons, by moving them from valence band into the conduction band. Since, at room temperature, the valence electrons of an insulator do not have enough energy to jump into the conduction band, therefore insulators do not have an ability to conduct current. Thus, insulators have very high resistivity (or extremely low conductivity) at room temperatures. However, if the temperature is raised, some of the valence electrons may acquire energy and jump into the conduction band. It causes the resistivity of insulators to decrease. Therefore, the insulators have negative temperature coefficient of resistance. Conductors. The materials in which conduction and valence bands overlap as shown in Fig. 1.9 (c) are called conductors. The overlapping indicates a large number of electrons available for conduction. Hence, the application of small amount of voltage results in a large amount of currents.

14

BASIC ELECTRONICS ENGINEERING & DEVICES Energy Conduction band

Electrons ‘‘free’’ to establish conduction

Energy

Energy

Conduction band

Eg > 3 eV

The bands are overlap

Eg

Valence band

Valence electrons bound to the atomic structure

Conduction band

Valence band Valence band

Eg = 1.1 eV (Si) Eg = 0.67 eV (Ge) Eg = 1.41 eV (GaAs) (a) Insulator

(b) Semiconductor

(c) Conductor

Fig. 1.9. Energy levels in insulator, semiconductor and conductor.

Semiconductors. The materials, in which the conduction and valence bands are separated by a small energy gap are called semiconductors shown in Fig. 1.9 (b). Silicon and Germanium are commonly used semiconductors. A small energy gap means that a small amount of energy is required to free the electrons by moving them from the valence band into the conduction band. The semiconductor behaves like insulators at 0K, because no electrons are available in the conduction band. However, at room temperature, a significant number of electrons are available in the conduction band. If the temperature is further increased, more valence electrons will acquire energy to jump into the conduction band. Thus, like insulators, semiconductors also have negative temperature coefficient of resistance. It means that conductivity of semiconductors increases with the increase in temperature. Table 1.1 given below shows the Energy gap of solid materials. Table 1.1 Material

Energy gap

Metal

None

Semiconductor

0.5 – 3.0 eV

Insulator

> 3 eV

The process of introduction of impurities in semiconductors in a precisely controlled manner is called doping. Depending on the nature of impurities added, the semiconductors are classified as follows : (a) Pure or intrinsic semiconductors. (b) Impurity or Extrinsic semiconductors.

15

SEMICONDUCTOR MATERIALS AND PROPERTIES

The semiconductors are in their pure form is referred to as pure or intrinsic semiconductors, whereas the extrinsic semiconductors are doped semiconductors in which suitable impurity atoms are added to modify the properties.

As stated above, a semiconductor, which is in its extremely pure form, is known as an intrinsic (or pure) semiconductor. The nature of semiconductors is such that even a small amount of certain impurities can change their electrical properties drastically. For Germanium, the impurity level is less than 1 part in 108 parts. And for silicon, it is less than 1 part in 1012 parts. In actual practice, however, a semiconductor material, with somewhat larger impurity concentrations, than those mentioned above is still called as an intrinsic semiconductor. The silicon and germanium are the two most widely used intrinsic semiconductors. The crystal structure of these materials consists of a regular repetition in three dimensions of a unit cell having the form of tetrahedron, with one atom at each vertex. The two dimensional representation of such a structure is shown in Fig. 1.10. For example, the silicon has a total 14 electrons in its atomic structure. Each atom in a silicon crystal contributes 4 valence electrons, so that the atom is tetravalent. These atoms are bonded together by a force, which results from the sharing of the neighbouring atoms. This bonding force is called a covalent bond and is shown by a pair of curved lines in the figure. Covalent bond

+4

+4

+4

Valence electrons

+4

+4

+4 Silicon or Germanium atom

+4

+4

+4

Fig. 1.10. Two dimensional representation of a silicon or a germanium crystal.

In order to make the intrinsic semiconductor useful, their characteristics have to be changed by adding a certain amount of desired impurity atoms. The resulting semiconductors are called impure or extrinsic semiconductors. As we have already discussed that the process of introduction of impurities in semiconductors in a precisely controlled manner is called doping. Generally, the impurities

16

BASIC ELECTRONICS ENGINEERING & DEVICES

are added at the rate of only one atom of impurity per 106 to 1010 semiconductor atoms. As a result of this, the impurity atoms are separated in the crystal by hundreds or thousand of semiconductor atoms in all directions. It may be noted that an impurity atom enters the crystal by substituting for one germanium or silicon atoms.

The purpose of doping i.e., process of adding impurity atoms, is to increase either the number of free electrons or holes in a semiconductor. Generally, two types of impurity atoms are added to the semiconductor namely the impurity atoms containing 5 valence electrons (called pentavalent impurity atoms) and the impurity atoms containing 3 valence electrons (called trivalent impurity atoms). Depending upon the type of impurity atoms added to the semiconductor, the resulting semiconductor (i.e., extrinsic semiconductor) may be of the following two types : (i) N-type Semiconductors (ii) P-type Semiconductors.

The semiconductors, which are obtained by introducing pentavalent impurity atoms, i.e., atoms containing 5 valence electrons are known as N-type semiconductors. The pentavalent impurity is an element from group V of the periodic table. The elements in this group contain 5 valence electrons. The example of pentavalent impurities are phosphorus (P), antimony (Sb), arsenic (As) and bismuth (Bi). These elements donate excess negative charge carriers (electrons). Therefore, such elements are known as donor or N-type impurities. Fig. 1.11 shows the structure of a silicon crystal lattice containing as antimony atom at the central position. It may be noted that out of 5 valence electrons, 4 electrons will form covalent bonds by sharing one electron each with electrons of the neighbouring atoms. The 5th electron is an extra electron and is loosely bound with +4

Conduction band

+4

+4

+4

Energy (eV)

Antimony atom

EF

Fermi level Donor level

ED

Free electron

Valence band

+4

Fig. 1.11. A silicon atom replaced by stationary atom in a crystal lattice.

Fig. 1.12. Energy band diagram of an N-type semiconductor.

SEMICONDUCTOR MATERIALS AND PROPERTIES

17

the antimony atom. This extra electron, if detached from the impurity atom will be available as a carrier of the current. The energy required to detach this electron is of the order of 0.05 eV for Silicon and 0.01 eV for Germanium. It will be interesting to know that if a pure semiconductor is doped with N-type impurities, the number of electrons in the conduction band increases above a level that would be available in a pure semiconductor. However, the number of holes in the valence band decreases below a level, that would be available in a pure semiconductor. It is due to the fact that a large number of electrons present in the semiconductor increases the rate of recombination of electrons with holes. Because of the greater number of electrons in a conduction band than that of holes in the valence band. The Fermi level shifts upward towards the bottom of the conduction band as shown in Fig. 1.12. One thing should always kept in mind that in an N-type semiconductor, the current flows due to the movement of electrons and holes. But a major part of the current flows due to the movement of electrons. Therefore, the electrons in an N-type semiconductor are known as majority carriers and holes as minority carriers.

The semiconductors which are obtained by introducing a trivalent impurity atoms (i.e., atoms containing 3 valence electrons) are known as P-type semiconductors. The trivalent impurity is an element of group III of the periodic table. The elements in this group contain 3 valence electrons. Typical examples of such elements are gallium (Ga), indium (In), aluminium (Al), boron (B) etc. These elements make available positive charge carriers because they create holes, which can accept electrons. Therefore, such elements are known as acceptor or P-type impurities. It has been observed that when a trivalent impurity is added to a pure semiconductor, it displaces some of the atoms. Fig. 1.12 shows the structure of silicon crystal containing an indium atom at the central position. The 3 valence electrons, of an indium atoms, forms 3 covalent bonds by sharing one electron with the electrons of neighbouring atoms. However, the fourth covalent bond is incomplete. A vacancy, which exists in the incomplete covalent bond constitutes a hole. Now, the indium atom seeks its surrounding atoms so as to acquire the 4th electron, to complete the covalent bond. Thus, an electron which is in a favourable position, is captured by an indium atom. After doing this, the indium atom becomes an immobile ion. The energy, involved in capturing the electron to 0.05 eV for silicon and 0.01 eV for Germanium. It will be interesting to know that if a pure semiconductor is doped with P-type impurities, the number of holes in the valence band increases above a level, which would be available in a pure semiconductor. However, the number of electrons in the conduction band decreases below a level, which would be available in a pure semiconductor. It is due to the fact, that a large number of holes present in the semiconductor increases the rate of recombination of holes with electrons. Because of the greater number of holes in the valence band than that of electrons in conduction band, the fermi-level shifts downwards towards the top of the valence band as shown in Fig. 1.13.

18

BASIC ELECTRONICS ENGINEERING & DEVICES

+4

Conduction band

+4

+4

+4

Energy (eV)

Indium atom

EV EF

Acceptor level Fermi level

Hole

Valence band

+4

Fig. 1.13. A silicon atom replaced by indium atom in a crystal lattice.

Fig. 1.14. Energy band diagram of a P-type semiconductor.

One thing should always kept in mind that in an P-type semiconductor, the current flows due to the movement of electrons and holes. But a major part of the current flows due to movements of holes. Therefore, the holes in an P-type semiconductor are known as majority carriers and electrons as minority carriers.

We have already discussed that a pure (or intrinsic) semiconductor has no free charge carriers at absolute zero temperature. However, as the temperature of the semiconductor is raised to room temperature, some of the covalent bonds are broken due to which few electron-hole pairs are created. These electron-hole pairs are called thermally generated charge carriers. For instance, an N-type semiconductor has a large number of electrons. Besides this N-type semiconductor also contains fewer number of thermally generated holes. Since, the number of electrons, are much larger than the number of holes in a N-type semiconductor, therefore electrons are called majority carriers and holes a minority carriers. This situation is as shown in Fig. 1.15 (a). Electron

Hole

Hole

Majority carriers : Electrons Minority carriers : Holes

Electron

Majority carriers : Holes Minority carriers : Electrons

(a) N-type

(b) P-type Fig. 1.15.

19

SEMICONDUCTOR MATERIALS AND PROPERTIES

Similarly, in a P-type semiconductor, the number of holes are much larger than the number of electrons. Therefore, in a P-type semiconductor, holes are called majority carriers and electrons as minority carriers. This situation is as shown in Fig. 1.15 (b).

Fermi level is a measure of the probability of occupancy of electrons or holes in the allowed energy states. We have already discussed that in N-type semiconductor the fermi level shifts upward towards the bottom of the conduction band. However, in the case of P-type semiconductor it shifts downwards towards the top of the valence band. One thing always should be kept in mind that in pure semiconductor having number of electrons in the conduction band is equal to the number of holes in the valence band, it lies between the middle of the conduction and valence band. From the equation of current density [i.e., J = (n.µn + p.µp ) q.E.] and conductivity of the material [ = (n.µn + p.µp ) q] it is clear that the electrical characteristics of a semiconductor material depend on the concentration of free electrons and holes. Also the change in the concentration of electrons and holes may shifts the Fermi level of the energy band. Thus, we conclude that the only parameter which changes with impurities is the Fermi level EF. Now we will discuss Fermi level in detail.

The equation for f (E) is called the Fermi-Dirac probability function and specifies the fraction of all states at energy E (in eV) occupied under the condition of thermal equilibrium. f (E) is given by relation : f (E) =

where,

1 E EF 1e kT

a

f

...(1.3)

k = Boltzmann constant, eV/K T = Temperature EF = Fermi level or characteristic energy, for the crystal, eV.

The Fermi level represents the energy state with 50% probability of being filled if no forbidden band exists. The reason for the last statement is that, for an energy E equal to the Fermi level energy EF, the occupation probability is : f (E) =

1 0

( E = EF )

1 e kT or

f (E) =

1 1 = 11 2

Thus, an energy state at the fermi level has a probability of by an electron.

1 of being occupied 2

20

BASIC ELECTRONICS ENGINEERING & DEVICES

A closer examination of f (E) indicates that 0 K the distribution takes the simple rectangular form shown in Fig. 1.16. With T = 0, in the denominator of exponent, f (E)

1 1 = 1, when the exponent is negative (i.e., EF > E ) and f (E) is = 0 when 1 0 1 the exponent is positive (i.e., E > EF ). This rectangular distribution implies that at 0 K every available energy state up to EF is filled with electrons and all states above EF are empty, since there are no electrons at 0 K which have energies in excess of EF . For better understanding at absolute zero temperature there exist two cases that are as follows: Case I. When E >> EF then is

1

f (E) =

= 0 1 e This shows that the probability of finding an occupied quantum state of energy greater than EF is zero at absolute zero temperature. Case II. When E EF Where, PE = distribution density of electrons in number of electrons per electron volt per cubic metre. = constant = 6.82 × 1027/m3ev3/2

{

It may be noted that Fermi energy is the maximum energy that any electron may possess at absolute zero temperature. f (E) T=0K 1 T2 > T1 1/2 T1 T2 EF

E

Fig. 1.16. The Fermi-Dirac distribution function. NOTE :

(i) Shift in energy level is given by equation E0 = kT ln

N DN A ni 2

21

SEMICONDUCTOR MATERIALS AND PROPERTIES where,

kT = 26 mV ND = Donor concentration NA = Acceptor concentration ni = Intrinsic concentration

(ii) Other expression for E0 is E0 = kT ln

Pp Pn

= kT ln

nn np

(iii) Einstein Relation : Since both diffusion and mobility are statistical phenomenon, D and µ are not independent. Dp p

=

kT Dn = q n

= VT = 26 mV.

This ratio depends upon : (a) Temperature of the semiconductor. (b) The type of semiconductor.

If in intrinsic silicon or germanium, there is added a small percentage of trivalent or pentavalent atoms, a doped, impure or extrinsic semiconductor is formed.

If the dopant has five valence electrons (example, Antimony), the crystal structure of Fig. 1.17 (a) is obtained. The impurity atoms will displace some of the germanium atoms in crystal lattice. Four of the five valence electrons will occupy covalent bonds and the fifth will be nominally unbound and will be available as a carrier of current. The energy required to detach the fifth electron from the atom is of the order of only 0.01 eV for Ge or 0.05 eV for Si. Such impurities donate excess (negative) electron carriers and are therefore referred to as donor or n-type impurities. Free electron Ge Ge

+4

+4

+4

Ge

Ge

+4

+4

+4

Ge

+4

Ge

Sb

Ge

+4

+4 Ge

Fig. 1.17 (a). Crystal lattice with a germanium atom displaced by a pentavalent impurity atom.

22

BASIC ELECTRONICS ENGINEERING & DEVICES

When donor impurity is added to Ge, the allowable energy levels are introduced at a very small distance below conduction band as shown in Fig. 1.17 (b). These new allowed energy levels are discrete levels. The energy of new levels is only 0.01 eV in Ge and 0.05 eV in Si below conduction band. Fifth electrons of donor material are raised into the conduction band. Conduction band EC ED Donor energy level

Eg

Allowed energy levels EV

Valence band

Fig. 1.17 (b)

If a trivalent impurity (boron, gallium or indium) is added to an intrinsic semiconductor, only three of the covalent bonds can be filled and the vacancy that exists in the fourth bond constitutes a hole as shown below in the Fig. 1.18 (a). Such impurities make available positive carriers because they create whole which can accept electrons. These impurities are consequently known as acceptor or p-type impurities. Ge Ge

+4

+4

+4

Ge Hole

Ge

+4

+3

+4

Ge

+4

Ge

In

Ge

+4

+4 Ge

Fig. 1.18 (a). Crystal lattice with a germanium atom displaced by an atom of a trivalent impurity.

When Acceptor impurity is added to Ge, the allowable energy levels are introduced at a very small distance above the valence band as shown in Fig. 1.18 (b). One thing should be always kept in mind that the conductivity of semiconductor increases by increasing the impurity atoms.

23

SEMICONDUCTOR MATERIALS AND PROPERTIES

Conduction band EC Allowed energy levels

Acceptor energy level

Eg

EA EV Valence band

Fig. 1.18 (b)

As we have already described that in a pure (intrinsic) semiconductor the number of holes is equal to the number of free electrons. Thermal agitation continues to produce new hole-electron pairs, whereas other hole-electron pairs disappear as a result of recombination. The hole concentration p must equal to the electron concentration n, so that, n = p = ni

...(1.4)

Where ni is called the intrinsic concentration. It may be noted that with increasing temperature, the density of hole-electron pairs increases and correspondingly, the conductivity increases. It is found that the intrinsic concentration ni varies with T as, ni2 Where,

= A0

T3

e

E Go kT

...(1.5)

EG0 = Energy gap at 0 K in electron volts k = Boltzmann constant i.e., eV/K A0 = Constant independent of T.

As we have already discussed that adding n-type impurities decreases the number of holes. Similarly, doping with p-type impurities decreases the number of electrons below a level which would have been available in pure semiconductor. It has been experimentally found that under thermal equilibrium, the product of number of holes and the number of electrons is constant and is independent of the amount of donor and acceptor impurity atoms. This relation is known as mass-action law and is given by the relation n . p = ni2 where,

...(1.6)

n = Free electron concentration (i.e., no. of free electrons per m3) p = Hole concentration (i.e., number of holes per m3) ni = Intrinsic concentration.

24

BASIC ELECTRONICS ENGINEERING & DEVICES

Charge Densities in a Semiconductor We have already discussed the relationship between free electron concentration (n) and hole concentration (p), which is known as mass-action law. These concentration are further related by the law of electrical neutrality as discussed below. Let,

ND = Concentration of donor atoms (i.e., the number of positive charges /m3 contributed by donor ions) p = Hole concentration (i.e., no. of holes/m3) NA = Concentration of acceptor atoms (i.e., the number of negative charges/m3 contributed by acceptor ions) n = Free electron concentration (i.e., number of free electrons/m3)

Total number of positive charges/m3 and total number of negative

charges/m3

= ND + p = NA + n

Since the semiconductor, as a whole is electrically neutral, therefore magnitude of total positive charge density is equal to the total negative charge density, i.e., NA + n = ND + p

...(1.7)

Consider an n-type material having NA = 0. Since, the number of electrons is much greater than the number of holes in an n-type semiconductor (n >> p), then eqn. (1.7) reduces to : n ND

...(1.8)

Thus, we can also say that in an n-type material the free electron concentration is approximately equal to the density of donor atoms. The concentration of holes (i.e., here minority carriers) in an n-type semiconductor, may be obtained by using mass-action law (i.e., n.p = ni2) and its value is given by the relation Pn

n i2 n i2 = = ND n

...(1.9)

where, Pn denotes the concentration of holes in n-type semiconductor at room temperature (300°K), ni 1013/cm3 for Ge and ni 1012/cm3 for Si. Similarly, in a p-type semiconductor, the concentration of donor atoms is zero (i.e., ND = 0) and the number of holes is much larger than the number of free electrons (i.e., p >> n). Therefore, for p-type semiconductor the eqn. (1.7) may be written as p = NA

...(1.10)

The above relation shows that in a p-type semiconductor, the hole concentration (p) is equal to the number of acceptor atoms/m3. The concentration of free electron is obtained by using mass action law and its value is given by the relation, np

n i2 n i2 = = p NA

...(1.11)

SEMICONDUCTOR MATERIALS AND PROPERTIES

25

where, np denotes the concentration of electrons in p-type semiconductor. It will be interesting to know that, It is possible to add donor atoms into a p-type semiconductor. Similarly, it is also possible to add acceptor atoms into an n-type semiconductor. If an equal concentrations of donors and acceptors is added into an intrinsic semiconductor, it remains intrinsic semiconductor. An extension of the above argument indicates that if the concentration of donor atoms added to a p-type semiconductor exceeds the acceptor concentration (ND > NA), the specimen is changed from p-type to an n-type semiconductor. NOTE :

One thing should be always kept in mind that the current in a metal is due to the flow of negative charges (electrons) whereas the current in a semiconductor results from the movement of both electrons and positive atoms so that the current is due to predominantly either to electrons or to holes. The transport of the charges in a crystal under the influence of an electric field (a drift current) and also as a result of non-uniform concentration gradient (a diffusion current).

If a steady Electric field (E = v/m) is applied to the metal, free electrons get accelerated. The velocity of free electrons increases considerably with time. Since electrons lose energy at every inelastic collision, a steady state is reached and resulted a finite value of drift velocity, vd in direction opposite to electric field. The term mobility may be defined as the drift velocity per unit electric field. Mathematically, µ = where,

vd E

...(1.12)

µ = Mobility of electrons (measured in square meters per-volt second) vd = Drift velocity E = Applied electric field.

Mobility means how freely charge carriers move in a crystal without collision. Mobility is a result of both lattice and impurity scattering. Mobility can also be represented as,

qt m Conductivity in terms of mobility is given by = nqµ µ =

Therefore, current density J is expressed as J = E = nqµE The drift velocity is related to Electric field as vd E or

vd = µE

The steady flow of electrons in one direction caused by the applied electric field constitutes currents and is called the drift-current.

26

BASIC ELECTRONICS ENGINEERING & DEVICES

It can be easily noted that the current in the conductor is proportional to the applied electric field, which is also true from the ohm's law. The electrons that constitute the current acquire energy from the applied field and transfer it to lattice ions through inelastic collisions. The parameter mobility (µ) of an intrinsic semiconductor varies as Tm over a temperature range (T ) of 100 to 400 K. For silicon, the value of m = 2.5 for electrons and 2.7 for holes. Similarly, for Germanium, the value of m = 1.66 for electrons and 2.33 for holes. It may be noted that drift velocity of a carrier depends upon the free path available to it for acceleration between two collisions (mean free path) as the mobility of an intrinsic semiconductor decreases with the increase in temperature because at higher temperatures, the number of carriers are more and they are more energetic also. This causes an increased number of collisions with the atoms causing scattering and thus the mobility decreases.

Fig. 1.19 shows a graph of drift velocity verses field intensity. It is linear for the initial portion, where field intensity is less than 103 V/cm (i.e., E < 103 V/cm). Beyond that the graph tapers off and velocity reaches an upper limit of 107 cm/sec when the field is increased to 105 V/cm. Ohmic Region Non-sat. region vd (cm/s)

High field region

E (V/cm)

Fig. 1.19. Variation of mobility with electric field.

For better understanding the variation in mobility with electric field under different condition given below: µ = constant µ

µ

1 E

1 E

when E < 103 V/cm. when 103 < E < 104 V/cm.

when E > 104 V/cm.

Mobility also depends upon the concentration of the charge carriers. The electrons in germanium more about 3 times faster than silicon and hence is suitable for high frequency applications.

27

SEMICONDUCTOR MATERIALS AND PROPERTIES µn (cm2/V-S)

µp (cm2/V-S)

Silicon

1350

480

Germanium

3900

1900

Gallium Arsenide

8500

4000

Type

As a matter of fact, the fundamental difference between semiconductor and metal is that the former is bipolar and latter is unipolar i.e., it conducts current by means of charge (electrons) of one sign only. If an electric field is applied to a metal, then due to the electrostatic force, the electrons would be accelerated and the velocity would increases indefinitely, if there would have been no collision with the ions. However, at each collision with the ion, the electron loses some energy. A steady-state condition is reached, when a finite value of drift velocity (Vd) is obtained. Thus, we can say that drift current is due to the influence of electric field. The drift velocity is in a direction opposite to that of the applied electric field. Now, let us obtain an expression for the drift velocity in a metal. We know that force experienced by the electron due to applied electric field. F = q.E where,

E = Applied electric field q = Charge of an electron

and acceleration, a =

q .E Force F = = Mass m m

Drift velocity, Vd = a . t =

q .E t = µE m

q .t and is known as mobility of an electron. The mobility is m expressed in m2/(volt-sec) and its value is different for different metals. where µ is equal to

Consider a piece of a metal or conductor in which electrons are uniformly distributed as shown in Fig. 1.20. (N electrons)

Cross-section area (A) L

Fig. 1.20. Metal or conductor.

28

BASIC ELECTRONICS ENGINEERING & DEVICES

Let,

N = No. of free electrons distributed in the conductor L = Length of the conductor A = Cross-sectional area of the conductor

We know that when an electric field is applied to the conductor, the electrons start moving in the semiconductor. Therefore, the average velocity of the electrons

L T where, T is the time taken by the electrons to travel through a distance. v =

The number of electrons passing through any area per second,

N T Total charge passing through any area per second (i.e., current) =

= charge × number of electrons per second passing through any area = q

N T

= q

N L T L

=

q . N .v L

Thus, the current in a conductor, I =

q . N .v L

J =

q . N .v I = A L .A

J = q

FH N IK v LA

current density

FH J I IK A

N = Concentration of LA electrons per unit volume

n =

J = q . n. v

From the relation of current density, J = q.n.v Also current density J (i.e., electric current per unit area) is given by the relation. J = .E where,

= Conductivity of a metal E = Applied electric field

So,

q.n.v = .E

29

SEMICONDUCTOR MATERIALS AND PROPERTIES

q . n . (E . µ) = . E q.n.µ =

or

= q.n.µ

or

1 = = q.n.µ

Also,

= Resistivity of a metal

where,

µ = Mobility of a metal. NOTE :

Electrical Conduction. In metal and semiconductor it is represented by relation : = nqµ

(a) In Metal where,

n = no. of charge carriers q = charge µ = mobility

(i) at T = 0, = max (i.e., maximum conductivity) (ii) n is independent of temperature (for metal T = 104 k) so,

µ

1 T

or

1 T

Thus in the case of metal, conductivity is inversely proportional to temperature.

Metal

T

Fig. 1.21 (b) In semiconductor (i)

NOTE :

at T = 0, = 0 (called carrier freeze-out effect)

(ii)

n T

(iii)

µ

1 T

In the case of semiconductor on increasing temperature there will be less change in mobility µ as compare to n. so,

T

30

BASIC ELECTRONICS ENGINEERING & DEVICES Thus in the case of semiconductor conductivity is directly proportional to the temperature.

Semiconductor

T

Fig. 1.22

We have already discussed that in an intrinsic semiconductor at room temperature (i.e., at 300 K) the thermal energy is sufficient to produce a large number of electron hole pairs. When an electric field is applied, the current flows through the semiconductor. The flow of current, in a semiconductor, is due to the movement of free electrons in one direction and holes in the opposite direction. As we know that electric current density in a metal (which is due to the movement of free electrons) is given by the relation, J = q.n.µ.E Using the above relation, we can write an equation for the current density in an intrinsic semiconductor. Thus, current density, which results due to the movement of electrons only is given by the relation, Jn = q . n . µn . E where,

q = Charge of an electron n = No. of electron per unit volume µn = Mobility of electrons in a semiconductor E = Applied electric field.

A similar expression can be written for current density due to holes in an intrinsic semiconductor and is given by the relation, Jp = q . p . µp . E where,

q = Charge of a hole and is equivalent to that of an electron p = Number of holes per unit volume µp = Mobility of holes in a semiconductor E = Applied electric field strength.

The total current density within an intrinsic semiconductor, J = Jn + Jp = q . n . µn . E + q . p . µp . E

31

SEMICONDUCTOR MATERIALS AND PROPERTIES

= q E (n . µn + p . µp ) = .E where,

= q (n . µn + p . µp ) called conductivity of a semiconductor.

We know that for an intrinsic semiconductor, the number of holes is equal to the number of electrons i.e., p = n = ni where, ni is called intrinsic carrier concentration. So, in the above equation substituting n = p = ni , we get, J = q . ni (µn + µp ) E and the conductivity of an intrinsic semiconductor, i = q . ni (µn + µp ) Thus, from above relation, it is clear that conductivity of an intrinsic semiconductor depends upon its intrinsic concentration (ni ) and the mobility of holes and electrons.

The term Diffusion may be defined as the transportation of charge carriers in a semiconductor due to result of non-uniform concentration gradient. Or in other words, we can say that in addition to a conduction current, the transport of charges in a semiconductor may be accounted by a mechanism called diffusion, not ordinarily encountered in metals. The essential features of diffusion are now discussed. It is possible to have a non-uniform concentration of particles in a semiconductor. Fig. 1.23 shows a concentration p (x) results in a diffusion current density for hole Jp, here the concentration p of holes varies with distance x in the semiconductor and dp there exists a concentration gradient, , in the density of carriers. dx Figure shows that the concentration gradient of

F dp I H dx K

of holes on one side of

surface is larger than other side. The holes are in a random motion as a result of their thermal energy. This means that, holes will continue to move back and forth across this surface. We may then expect that, in a given time interval, more holes will cross p (0)

p (x)

Jp

x=0

x

Fig. 1.23. A non-uniform concentration p (x) results in a diffusion current Jp .

32

BASIC ELECTRONICS ENGINEERING & DEVICES

the surface from the side of greater concentration than in the reverse direction. It should be noted that this net transport of charges is not the result of mutual repulsion among charges of like sign, but is simply the result of a statistical phenomenon. This diffusion is exactly analogous to that which occurs in a neutral gas if concentration gradient exists in the gaseous container. The diffusion hole-current density Jp is proportional to the concentration gradient and is given by Jp = q D p where,

dp dx

Dp = diffusion constant for holes (square meter per second)

dp is negative and dx the ve sign is taken here. A similar equation exists for diffusion electron–current density here p is replaced by n and minus sign is replaced by plus sign. Thus diffusion electron-current density is given by the relation Since, p in the above figure decreases with increasing x, then

Jn = q D n

dn dx

It is possible for both a potential gradient and concentration gradient to exist simultaneously within a semiconductor. In such a situation the total electron current is the sum of drift current (due to influence of applied electric field strength) and diffusion current, and given by the relation, Jn = drift current density + diffusion current density or

Jn = q . n . µn . E + q . Dn . dn dx Similarly, the net hole current is Jp = q . p . µp . E q . Dp .

dp . dx

When a current carrying conductor is placed in a magnetic field (B) a transverse effect (discovered by Hall in 1879) is pointed. This effect is called the Hall effect. Hall found that : “When a magnetic field is applied at right angles to the direction of the electric current, an electric field is set up which is perpendicular to both the direction of electric current (I) and the applied magnetic field (B).” In other words, “when any specimen carrying a current I is placed in the transverse magnetic field B, then an electric field E is induced in the specimen in the direction perpendicular to both B and I and the phenomenon known as Hall effect.” Fig. 1.24 shows a specimen bar carrying current I in the position-x direction. Let magnetic field Bz be applied in the positive-z direction. Then according to Hall effect, a force (due of electric field set up) gets exerted on the charge carriers (whether electrons

33

SEMICONDUCTOR MATERIALS AND PROPERTIES

or holes) in the negative-y direction. This current I may be due to holes moving in the positive-x direction or due to free electrons moving in the negative-x direction through the semiconductor specimen. Hence, irrespective of the nature of charge carriers, whether holes or electrons, these charge carriers get pressed towards face 1 of the specimen shown in Fig. 1.24. z

b

Face-2 Face-1

I

x

y

Fig. 1.24. Current carrying semiconductor bar subject to transverse magnetic field.

The current, in an n-type specimen is carried almost fully by electrons. These electrons, as a result of Hall effect, accumulate on face-1. As we know that atoms as whole electrically neutral therefore face-2 gets negatively charged. Consequently, a potential difference develops between face-1 and face-2 and is called the ‘Hall Voltage’ (VH). This Hall voltage for an n-type semiconductor is positive at face-2 and negative for an p-type semiconductor at face-1. These two results have been verified experimentally. The polarity of Hall voltage enables us to determine experimentally whether the semiconductor specimen is of n-type or p-type.

The Hall effect may be used for : (i) Determining whether a semiconductor is n-type or p-type. (ii) Determining the carrier concentration. (iii) Calculating the mobility, having measured the conductivity.

The equilibrium condition of the specimen shown in Fig. 1.24 requires that the electrical field intensity due to Hall effect exerts a force on the carrier equal in magnitude to that exerted by the field. q.E = qvB But

E =

VH d

...(1.13) ...(1.14)

34

BASIC ELECTRONICS ENGINEERING & DEVICES

Also current density J is given by J =

I = v b d

...(1.15)

By combining equation (1.13), (1.14) and (1.15), we get VH = E.d = vBd JBd

or

VH =

or

BI VH = b

...(1.16)

Thus the value of can be determined by measuring the quantities VH, B, I and b for a specimen. The Hall co-efficient RH is defined as 1 RH =

...(1.17)

Equation (1.16) yields RH = where,

V H .b BI

...(1.18)

I = Current carried by the specimen J = Current density B = Magnetic field E = Electric field VH = Hall voltage RH = Hall co-efficient = Conductivity q = Magnitude of charge of an electron or hole v = Drift velocity = Charge density d = Distance between face-1 and face-2 b = Width of the specimen along the magnetic field.

The conductivity, in any extrinsic semiconductor, is due to primarily charges of only one sign and given as = µ

...(1.19)

If both RH and are measured, the mobility may be defined from the following relation, µ = RH

...(1.20)

35

SEMICONDUCTOR MATERIALS AND PROPERTIES

In the above discussion it is assumed that all charge carriers move with mean drift speed v. In fact, the charge carriers have a random motion. Taking this distribution into consideration, we find that equation (1.18) is valid provided that RH is defined as instead of simply as

3 8

1 , so, equation (1.20) gets modified as below :

µ =

F 8 I R H 3 K

H

...(1.21)

?

1. Define Resistivity and Conductivity. 2. Explain hole Mechanism in brief. 3. Why energy bands are necessary ? 4. What is an insulator ? What is fermi level ? Why does a pure semiconductor behaves like an insulator at absolute zero ? 5. Differentiate between intrinsic and extrinsic semiconductors. Give examples. 6. Explain clearly the difference between acceptor and donor impurities and state what type of carriers are contributed to them. 7.

(i ) Differentiate between intrinsic and extrinsic semiconductors. (ii ) What is an insulator ? (iii ) What is a conductor ?

8. Define the terms conductivity, intrinsic concentration and energy gap of semi- conductors. 9. Differentiate semiconductors, conductors and insulators on the basis of band gap. What is the mechanism by which conduction takes place inside the semiconductor ? 10. What is meant by fermi level in semiconductors ? Where does the fermi level lie in an intrinsic semiconductor ? Prove that the fermi level in n-type material is much closer to the conduction band. 11. Which of the two semiconductor materials have Si or Ge has larger conductivity at room temperature and why ? What happens to the conductivity of the semiconductor with the rise in temperature ? 12. Sketch the energy-band picture for : (i ) an intrinsic semiconductor (ii ) an n-type semiconductor (iii ) an p-type semiconductor.

36

BASIC ELECTRONICS ENGINEERING & DEVICES

Example 1. A semiconductor wafer is 0.5 mm thick. (a) A potential of 100 mV is applied across the thickness, what is the electron drift velocity if their mobility is 0.2 m2/V-s ? (b) How much time is required for an electron to move across the thickness. Solution : (a) We know that, Mobility, µ = or

Vd E

Drift velocity, Vd = µ × E = µ ×

V d

= 0.2 ×

{ V = E × d }

100 10 3 .5 10 3

= 40 m/s. Ans.

(b) Time required, T =

d .5 10 3 = = 12.5 µ S. Vd 40

Ans.

Example 2. The mobilities of free electrons and holes in a pure germanium are 0.38 and 0.18 m2/V-s. Find the value of intrinsic conductivity. Assume ni = 2.5 × 1019/m3 at room temperature. Solution : Intrinsic conductivity for germanium i = q . ni (µn + µp) or

i = 1.6 × 1019 × 2.5 × 1019 (0.38 + 0.18) (-m)1

or

i = 2.24 (-m)1. Ans.

Example 3. Find the intrinsic carrier concentration of germanium, if its intrinsic resistivity at 300 K is 0.50 -m. It is given that the electronic charge is 1.6 × 1019 coulombs and that electron and hole mobilities at 300 K are 0.39 and 0.19 m 2/V-s respectively. Solution : Given :

= 0.50 -m q = 1.6 × 1019 C µn = 0.39 m2/V-s µp = 0.19 m2/V-s Let ni = Intrinsic carrier concentration of germanium.

We know that conductivity of a semiconductor, 1 1 = = = 2 (-m)1 .5

and the conductivity in intrinsic semiconductor ()

37

SEMICONDUCTOR MATERIALS AND PROPERTIES

= q . ni (µn + µp) 2 = 1.6 × 1019 . ni (0.39 + 0.19) or

ni =

2 1.6 10

19

0.58

= 2.155 × 1019/m3.

Ans.

Example 4. A sample of silicon is doped with phosphorous to a density of 1021/m3 as well as with boron to a density of 5 × 1020/m3. What will be conductivity of the Si sample. The electron mobility in silicon is 0.18 m2/V-s. Solution : Given :

ND = 1021/m3 NA = 5 × 1020/m3

Since, phosphorous atoms are donor and boron atoms are acceptor, therefore, net donor density. ND = ND NA = 1021 5 × 1020 = 5 × 1020/m3 Number of free electrons, n = ND = 5 × 1020/m3 We know that conductivity of silicon, = q . n . µn = 1.6 × 1019 × 5 × 1020 × 0.18 = 14.4 (-m)1. Ans. Example 5. Find the conductivity of the copper if the mobility is given as 34.8 cm2/V and density is given as 8.9 gm/cm3. Assume one free electron per atom. Atomic weight of copper is 63.54. Solution : Concentration of electrons n can be given as n = 6.023 × 1023(atom/mole) × (1 mole/63.54 gm) × 8.9 (gm/cm3) or

n = 8.44 × 1022 electrons/cm3. We know that = nqµ = 8.44 × 1022 × 1.6 × 10–19 × 34.8 = 4.7 × 105 mho/cm. Ans.

Example 6. Find the concentration of holes and electrons in a p-type germanium at 300 K, if the conductivity is 100 per ohm per cm [i.e., 100 ( -m)1]. Also find these values for N-type silicon, if the conductivity is 0.1 ( -m) 1. Given for Germanium, n i = 2.5 × 1013/cm3; µn = 3800 cm2/V-sec; µ p = 1800 cm2/V-sec and for silicon ni = 1.5 × 1010/cm3; µn = 1300 cm2/V-sec and µp = 500 cm2/V-sec. Solution : Given for Germanium,

= 100 (-m)1 ni = 2.5 × 1013/cm3 µn = 3800 cm2/V-sec µp = 1800 cm2/V-sec

38

BASIC ELECTRONICS ENGINEERING & DEVICES

Let

n = Concentration of electrons p = Concentration of hole

Concentration in p-type Germanium : We know that conductivity of a p-type Germanium (), = q . p . µp 100 = 1.6 × 1019 × p × 1800 p = or

100 1.6 10 19 1800

p = 3.47 × 1017/cm3. Ans. Therefore, concentration of electrons, n =

n i2 p

{ n p = ni2 (mass-action law)}

a2.5 10 f

13 2

n =

= 1.8 × 109/cm3. Ans.

3.47 1017

Concentration in n-type Silicon : = q . n . µn 0.1 = 1.6 × 1019 × n × 1300 0.1

n =

1.6 10 19 1300 and the concentration of holes,

n i2 p = = n

= 4.8 × 1014/cm3. Ans.

a1.5 10 f

10 2

= 4.7 × 105/cm3. Ans.

4 .8 1014

Example 7. In a germanium sample, a donor type impurity is added to the extent of 1 atom per 108 germanium atoms. Show that resistivity of the germanium sample drops to 3.7 ohm-cm. Given : µn = 3800 cm2/V-sec; µp = 1800 cm2/V-sec; ni = 2.5 × 1013/cm3; Nge = 4.41 × 1022/cm3 and q = 1.602 × 1019 coulombs. Solution : Given : µn = 3800 cm2/V-sec; µp = 1800 cm2/V-sec; ni = 2.5 × 1013/cm3;

Nge = 4.41 × 1022 cm3 and g = 1.602 × 1019 coulombs. We know that the number of donor atoms, ND =

N ge 10 8

=

4.41 10 22 10 8

= 4.41 × 1014/cm3

Since, the number of free electrons (n) is approximately equal to the donor atoms (ND), therefore n 4.41 × 1014/cm3. We know that number of holes, n i2 p = = ND

a2.5 10 f

13 2

4 .41 1014

= 1.417 × 1012/cm3

SEMICONDUCTOR MATERIALS AND PROPERTIES

39

It may be noted that the number of electrons (4.41 × 1014) is very large as compared to the number of holes (1.417 × 1012) in a doped germanium. Therefore, conductivity of an N-type germanium, = q . n . µn = (1.602 × 1019) × (4.41 × 1014) × 3800 = 0.268 (-cm)1 Resistivity of a doped germanium, =

1 1 = = 3.73 ohm-cm. Ans. 0.268

Example 8. Find the resistivity of intrinsic silicon. What will this change to when the silicon is doped with a pentavalent impurity to the extent of one impurity atom for each 50 million silicon atoms ? Following data may be used. Number of silicon atoms = 4.96 × 1022/cm3 Intrinsic carrier concentration = 1.52 × 1010/cm3 Electron charge = 1.6 × 1019 coulomb Electron mobility = 0.135 m2/Volt-sec Hole mobility = 0.048 m2/Volt-sec. Solution : Given : Nsi = 4.96 × 1022/cm3; ni = 1.52 × 1010/cm2; q = 1.6 × 1019 C; µn = 0.135 m2/V-sec = 1350 cm2/V-sec and µp = 0.048 m2/V-sec = 480 cm2/V-sec. Resistivity of intrinsic silicon We know that conductivity of an intrinsic silicon, = q . ni (µn + µp) = (1.6 × 1019) × (1.52 × 1010) × (1350 + 480) (-cm)1 = 4.5 × 106 (-cm)1 Resistivity of intrinsic silicon, =

1 1 = = 2.22 × 105 -cm. Ans. 4 .5 10 6

Resistivity of doped silicon We know that if the silicon is doped with a pentavalent impurity to the extent of one impurity atom for each 50 million (50 × 106) silicon atoms, then the number of donor atoms, ND =

N si 50 10

6

=

4.96 10 22 50 10 6

= 9.92 × 1014/cm3

Number of free electrons in a semiconductor, n = ND = 9.92 × 1014/cm3 We also know that number of holes in a doped silicon,

n i2 p = = n

a1.52 10 f

10 2

9.92 1014

= 2.33 × 105/cm3

40

BASIC ELECTRONICS ENGINEERING & DEVICES

Since, the number of electrons (equal to 9.92 × 1014) in a doped silicon is much larger than the number of holes (equal to 2.33 × 105), therefore, conductivity of a doped silicon, = q . n . µn = (1.6 × 1019) × (9.92 × 1014) × 1350 = 0.21 (-cm)1 Resistivity of a doped silicon, =

1 1 = = 4.67 -cm. Ans. 0.21

Example 9. In a n-type silicon, the donor concentration is 1 atom per 2 × 108 atoms. Assuming the effective mass of the electron is equal to true mass, find the value of the temperature at which the Fermi level coincides with the edge of the conduction band.

5 10 28

= 2.5 × 1020 m3

Solution :

ND =

The Fermi level,

EF = EC

We know,

NC = 4.82 × 1021 T3/2 m3

2 10 8

if NC = ND

2.5 × 1020 = 4.82 × 1021 × T3/2 T = 0.139 K. Ans. Example 10. In a semiconductor at room temperature (300K), the intrinsic carrier concentration and resistivity are 1.5 × 1016/m3 and 2 × 103 -m respectively. It is converted to an extrinsic semiconductor with a doping concentration of 1020/m3. For the extrinsic semiconductor, calculate the (a) minority carrier concentration (b) resistivity (c) shift in Fermi level due to doping and (d) minority carrier concentration when its temperature is increased to a value at which the intrinsic carrier concentration ni doubles. Assume (1) The mobility of majority and minority carriers to be the same. (2) kT = 26 meV at room temperature. Solution : (a) Minority carrier concentration =

n i2 Doping concentration

a1.5 10 f

16 2

=

(µn + µn) = 2µn = µn =

10 20

= 2.25 × 1012 atoms/m3 1

2 10 1.6 10 19 1.5 1016 3

1 4.8 1 = 0.1042 m2/volt-sec. Ans. 9.6

41

SEMICONDUCTOR MATERIALS AND PROPERTIES

(b)

Resistivity, = qn (µn)

As doping concentration >> minority concentration, only doping is to be considered. = 1.6 × 1019 × 1020 × 0.1042

= 1.6672 Resistivity = 0.5998 -m. Ans. (c) Shift in fermi level due to doping is given by relation :

n0 ni

EF Ei = kT ln

10 20

= 0.026 ln

1016 1.5 = 0.026 ln 66.67 × 102 = 0.229 eV EF lies 0.229 eV above fermi level Ei . Ans.

a1.5 2 10 f

16 2

(d) Minority carrier concentration =

=

10 20

9 10 32 10 20

= 9 × 1012 atoms/cm3. Ans.

Example 11. Determine the conductivity and resistivity of an intrinsic sample of Si at normal room temperature at 300 K. µn = 1350 cm2/V-sec µp = 480 cm2/V-sec ni = 1.52 × 1010/cm3 at 300 K q = 1.6 × 1019 C. Solution : We know that conductivity of an intrinsic sample = q . ni (µp + µn ) or

= 1.6 × 1019 × 1.52 × 1010 (1350 + 480)

or

= 4.451 × 106 (-cm)1 Ans.

and

Resistivity = =

1 Conductivity

1 1 = = 2.25 × 105 ohm-m. Ans. 4 .451 10 6

Example 12. Assuming standard values for silicon, find the resistivity if a donor type impurity is added to the extent of 1 in 108 atoms. Solution : Density of atoms in Si = 5.0 × 1022 atoms/cm3

ND =

5 10 22 10 8

= 5 × 1014 (i.e., no. of donor atoms)

42

BASIC ELECTRONICS ENGINEERING & DEVICES

By using law of mass-action, n p = n2i ND . p = n2i or

p =

n i2 = ND

a1.45 10 f

10 2

5 10 4

= 4.2 × 105/cm3

as n >> p, it is an n-type material with electron as majority carrier.

= q . µn . ni = 1.6 × 1019 × 1300 × 5 × 1014 = 0.104 (-cm)1

or

Resistivity =

1 1 = = 9.62 ohm-cm. Ans. 0.104

Example 13. A sample of Germanium is doped to the extent of 1014 donor atoms/cm3 and 5 × 1013 acceptor atoms/cm3. At 300 K, the resistivity of the intrinsic germanium is 60 -cm. If the applied electric field is 2 V/cm. Find the total conduction current density. Assume,

p n

=

1 and ni = 2.5 × 1013/cm3 at 300 K. 2

Solution : Given :

ND = 1014 atoms/cm3 NA = 5 × 1013 atoms/cm3 = 60 -cm E = 2 V/cm J = ?

We know that,

Since given,

= q . ni (µn + µp) p n

=

1 µn = 2µp 2

1 = 1.6 × 1019 × 2.5 × 1013 (2µp + µp)

or

µp = µp

1 19

60 1.6 10 2.5 1013 3 = 1.3889 × 103 = 1389

µn = 2µp = 2 × 1389 = 2778 We know,

np = n2i

...(1)

also, the charge neutrality equation, n + NA = p + ND or

p n = NA ND

or

p n = 5 × 1013 1014

...(2)

43

SEMICONDUCTOR MATERIALS AND PROPERTIES

p n = 5 × 1013

or

n = p + 5 × 1013

or

...(3)

Equation on putting in eqn. (1) we get, (p + 5 × 1013) . p = ni2 = (2.5 × 1013)2 p2 + 5 × 1013 p = 6.25 × 1026 p2 + 5 × 1013 p 6.25 × 1026 = 0 On solving the quadratic equation for p, we get, p = 1.0356 × 1013 n = 6.0356 × 1013

and

So, total conduction current density is given by the relation, J = q (nµn + pµp) E J = 1.6 × 1019 (6.0356 × 1013 × 2778 + 1.0356 × 1013 × 1389) × 2 = 3.2 × 106 (18205.34) = .0583 amp/m2. Ans. Example 14. A Si sample is doped with 1017 arsenic atoms/cm3 (i) find the minority carrier concentration at room temperature. (ii) find the location of fermi level with respect to the intrinsic fermi level. Given that ni = 1.5 × 1010 electrons/cm3. Solution : (i) Since from given data, { 1017 >> 1.5 × 1010}

ND >> ni So, by charge neutrality equation : n = ND = 1017 electrons/cm3

a

n i2 1.5 1010 p = = n 1017

f

2

= 2.25 × 103 holes/cm3. Ans.

(ii) As we know that,

ND EF Ei = kT ln n i = 0.026 ln

1017

1.5 1010 = .407 eV. Ans. The resulting energy band diagram is : EC EF 0.407 eV Ei

1.1 eV

EV

Fig. P (1.1).

44

BASIC ELECTRONICS ENGINEERING & DEVICES

Example 15. In N-type Si bar is 2 cm long and has a cross-section of 2 mm × 2 mm. When a 1 V battery is connected across it, a current of 8 mA flows. Find (a) doping level (b) drift velocity. Solution : (a) As we know that, R =

L ; A

R =

1 L A

=

L 2 = = .4 (ohm-cm)1 125 .2 .2 RA

R =

V 1 = = 125 I 8 10 3

As conductivity () is much higher than the intrinsic conductivity (= 4.3 × 106). This is heavily doped sample and so we can use approximate formula, n = ND and = n q µn { µn = 1300 cm2/V-sec} 19 .4 = ND . 1.6 × 10 × 1300 or

.4

ND =

or (b)

ND Drift velocity, Vd

1300 1.6 10 19 = 192 × 1013/cm3. Ans. = µ.E

FH V IK d

or

Vd = n .

or

Vd = 1300 ×

or

Vd

1 2 = 650 cm/sec. Ans.

Example 16. (a) Show that the conductivity of a semiconductor is minimum when it is lightly doped with p-type impurity such that p = ni

LM OP N Q

1/2

n

p

(b) Show that minimum conductivity is 2ni [µn µp ]1/2 q. Solution : (a) We know that, = (n µn + p µp ) q =

FG n Hp

2 i

n q p

...(1)

IJ q K

In order to find the minimum value of the conductivity, equate the derivative of to zero. d = dp

F n GH p

2 i 2

n p

Iq JK

= 0

45

SEMICONDUCTOR MATERIALS AND PROPERTIES

We get,

µp =

n i2 p2

p = ni

or

n

LM OP N Q

1/2

n

(Proved).

p

(b) To calculate minimum value, put, p = ni

min =

LM OP N Q

1/2

n

in eqn. (1)

p

LM n MM n FG IJ N H K 2 i

i

n

1/2

ni

n

FG IJ H K

1/2

n

p

OP PP Q

p q

p

= [ni (µn µp ]1/2 + ni (µn µp)1/2] q = 2ni (µn µp )1/2 . q.

(Proved).

Example 17. Find the following for a copper wire whose diameter is 1.03 mm and the resistance is given as 6.51 /1000 ft. (i ) Conductivity, (ii ) Mobility, (iii ) Drift velocity. The concentration of electrons is 8.4 × 1028 electrons/m3 and the current flowing in the wire is 2 amp. Solution : (i) 1000 ft = 1000 × 12 × 2.54 cm = 3.05 × 104 cm. So, the resistivity is given by =

6.51 3.05 10 4 cm

= 2.14 × 10–4 /cm

As we know that the conductivity is the reciprocal of the resistivity. =

1 1 = = 4.68 × 103 mho/cm 2.14 10 4 = 4.68 × 105 mho/m. Ans.

(ii) From, = nqµ Mobility, µ = or

4.68 10 5 = nq 8.4 10 28 1.6 10 –19

µ = 3.48 × 10–5 m2/V-s.

46

BASIC ELECTRONICS ENGINEERING & DEVICES

(iii) Drift velocity, V =

T nqA

But cross-section area, A = or

V=

D 2 = 8.33 × 10–7 m2. 4

2 8.4 10 28 1.6 10 –19 8.33 10 –7

= 1.79 × 10–4 m/s. Ans.

Example 18. A piece of silicon at room temperature is doped with 2 × 1016/cm3 concentration of Boron atoms and 5 × 1016/cm3 of phosphorous atoms. (i) Find the hole and electron concentration in this material. (ii) Is the silicon p- or n-type? Solution : Acceptor atoms added is NA and donor atoms added are ND. So, NA = 2 × 1016/cm3 and ND = 5 × 1015/cm3. Since the donor concentration is less than the acceptor concentration, the material is likely to be p-type. Hence the concentration of holes should be given as: ND – NA = pp = 2 × 1016 – 5 × 1015 = 15 × 1015/cm3 From Mass action law, the concentration of the electrons can be determined. np =

Ans. (i) np =

ni2/pp

=

(1012 )2 15 1015

=

1 × 109/cm3. 15

1 × 109/cm3 15

pp = 15 × 1015 (ii) Material is of p-type. Example 19. The resistivity of semiconductor material was known to be 0.005 -m at room temperature. The flux density in the Hall model was 0.45 wb/m 2. Calculate the Hall angle for a Hall co-efficient of 3.55 × 10–4 m3/coulomb. Solution : Given that,

= 0.005 -m Bz = 0.48 wb/m2 RH = 3.55 × 10–4 m3/C H = ?

From Fig. P (1.2)

Ex Resistivity, = J x Ex 0.005 = J x

47

SEMICONDUCTOR MATERIALS AND PROPERTIES 2

Bz = 0.48 wb/m

Jx

Ex

Ey

Exy

Fig. P (1.2)

or

Ex = 0.005 Jx

...(a)

and we know that, RH = 3.55 × 10–4 =

Ey BzJ x Ey 0.48 J x

Ey = 1.704 × 10–4 Jx tan H =

Now,

=

...(b)

Ey Ex

1.704 10 4 J x 5 10 3 J x

Example 20. Fig. P (1.3) shows a specimen of a silicon doped semiconductor having the Hall co-effieicnt of 3.55 × 10–4 m3/coulomb. Calculate the voltage between contacts when a current of 15 mA is flowing. 2

Bz = 0.48 wb/m

1 mm A = (15 mm × 1 mm)

Ex Ix = 0.015 A

15 mm

Ey

Exy

Fig. P (1.3)

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BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : Hall co-efficient, RH = 3.55 × 10–4 m3/C Current, Ix = 15 mA = 0.015 A Area, A = 15 mm × 1 mm = 15 × 10–6 m2 Flux density, Bz = 0.48 Wb/m2 Voltage between contacts = ? Now current density, Jx =

Ix A

=

0.015 15 10 6

= 1000 A/m2 Hall co-effieicnt is given by the relation : RH =

3.55 × 10–4 =

Ey BzJ x

Ey 0.48 1000

Ey = 3.55 × 10–4 × 0.48 × 1000 = 0.1704 V/m

and voltage between contacts = 0.1704 × (15 × 10–3) = 0.002556 V. Ans. Example 21. A silicon crystal having a cross-sectional area of 0.001 cm2 and a length of 20 µm is connected to its ends to a 20 V battery. At T = 300 K, we want a current of 100 mA in crystal. The concentration of donor atoms to be added is. Solution : Given,

A = 0.001 cm2 l = 20 µm = 20 × 10–4 cm V = 20 V I = 100 mA = 100 × 10–3 A

From relation, R = or

R =

V I 20 100 10 3

= 200

and we know that,

or

R =

1 l A

=

20 10 6 l = = 0.01 (-cm)–1 RA 200 .001 10 4

49

SEMICONDUCTOR MATERIALS AND PROPERTIES

= n.q.µn

and For

Silicon, µn = 1350 cm2/V-sec n = q . n

Now,

=

0.01 1.6 10 19 1350

= 4.6 × 1013 cm3 Ans.

Since,

n >> ni (intrinsic concentration)

It means,

n = N D.

Example 22. A thin film resistor is to be made from a GaAs film doped n-type. The resistor is to have a value of 2 k. The resistor length is to be 200 µm and area is to be 10–6 cm2. The doping efficiency is known to be 90%. The mobility of electrons is 8000 cm2/V-s. The doping needed is Solution : Given data,

R = 2 k = 2000 L = 200 µm = 200 × 10–4 cm A = 10–6 cm2 n = 0.9 ND

Now from relation, R =

l A

or

R =

1 l nq n A

or

=

L Rq n A

or

qNd =

20 10 4 2000 1.6 10 19 8000 10 6

Nd = 8.7 × 1015 cm–3

or

Ans.

Example 23. A silicon semiconductor sample at T = 300 K is doped with phosphorus atoms at a concentrations of 1015 cm–3. The position of the Fermi level with respect to the intrinsic Fermi level is. Solution : We know that, EF – EFi = KT In

Nd ni

3 = 26 10 In

= 0.287 eV

1015 1.5 1010 Ans.

.eV

50

BASIC ELECTRONICS ENGINEERING & DEVICES

Example 24. A silicon sample contains acceptor atoms at a concentration of Na = 5 × 1015 cm–3. Donor atoms are added forming and n-type compensated semiconductor such that the Fermi level is 0.215 eV below the conduction band edge. Calculate the concentration of donors atoms added. Solution : We know that, n = Nd – Na

= Nc e

bE

E F KT

C

g

For Si,

Nc = 2.8 × 1019 cm–3

Given,

Na = 5 × 1015 cm–3 = Na + N c e

bE

E F KT

C

g

Now,

Nd

or

Nd = 5 × 1015 + 2.8 × 1019 e

or

Nd = 1.19 × 1016 cm–3

FG 0 .215 eV IJ H 2610 eV K 3

[ given that Fermi level is 0.215 eV below the conduction band i.e., EC – EF = 0.215 eV] Ans. Example 25. A silicon sample doped n-type at 1018 cm–3 have a resistance of 10 . The sample has an area of 10–6 cm2 and a length of 10 µm. The doping efficiency of the sample is (µa = 800 cm2/V–s). Solution : Given data,

Nd = 1018 R = 10 A = 10–6 cm2 L = 10 mm = 10 × 10–4 cm, µn = 800 cm2/V–s

% doping efficiency = Now,

n =

or

n =

n Nd

× 100 = ?

L q . n . A.R

10 4 1.6 10 19 800 10 6 10

= 7.81 × 1017 cm–3 % doping efficiency =

7.81 1017 1 1018

= 78.1%.

× 100 Ans.

2 We have already discussed about the P-type and N-type semiconductors in the previous chapter. As a matter of fact, the P-type and N-type semiconductors taken separately, are of little use in actual practice. If we join a piece of P-type semiconductor to a piece of N-type semiconductor such that the crystal structure remains continuous at the boundary as shown in Fig. 2.1 (a), a P-N junction is formed.

P

N

P-N Junction

Fig. 2.1 (a). P -N Junction.

Such a P-N junction forms a very useful device and is called a semiconductor diode, PN junction diode or simply a crystal diode. The symbol of P-N junction diode is shown in Fig. 2.1 (b).

Anode (p-side)

Cathode (n-side)

Fig. 2.1 (b). Diode symbol.

It will be interesting to know that a P-N junction cannot be formed by simply joining or welding the two pieces together, because it would produce a discontinuous crystal structure. Special fabrication techniques are used to prepare P-N junction.

Fig. 2.2 shows the general structure of P-N junction. Here in the given figure donor ion is represented by a plus sign because, after the impurity atom ‘donates’ an electron becomes a positive ion. Whereas the acceptor ion is indicated by a minus sign because, after this atom ‘accepts’ an electron, it becomes a negative ion. Initially, there are nominally only 51

Comp-1/Laxmi-5/Computer/Revision/Belec-2—10.5.07

52

BASIC ELECTRONICS ENGINEERING & DEVICES

P-type carriers to the left of the junction and only N-type carriers to the right. P-type posses holes as a majority carriers and electrons as a minority carriers whereas N-type posses electrons as a majority carriers and holes as a minority carriers. Junction

Holes (mobile charge carriers)

Electrons (mobile charge carriers) P-type

N-type

Acceptor ion (immobile charge carriers)

Donor ion (immobile charge carriers)

In P-type Majority carriers = holes Minority carriers = electrons

In N-type Majority carriers = electrons Minority carriers = holes

Fig. 2.2. P N Junction with their charge carriers.

Since the junction diode is a two terminal device, the application of voltage across its terminals leaves three possibilities : 1. No bias. (i.e., VD = 0 V) 2. Forward bias. (i.e., VD > 0 V) 3. Reverse bias. (i.e., VD < 0 V)

Fig. 2.3 shows a semiconductor consisting of a PN junction which has been just formed. It may be noted that this entire sample is a single crystal. Its left half is a P-type and the right half is N-type. Holes and electrons are mobile charge carriers but acceptor ions and Donor ions are immobile charge carriers. The sample as a whole is electrically neutral and so are the P-region and N-region considered separately. Therefore in the P-region, the charges of moving holes equal the total charges on its free electrons and immobile ions. Similarly, in the N-region, the negative charge of its majority carriers is compensated by the charge of its minority carriers and immobile ions. It may be noted that no external voltage has been connected to the PN junction of Fig. 2.3. As soon as junction is formed, the conduction and valence bonds of P- and N-type material overlap. As a result of this the following processes are initiated : (a) The holes from the P-region diffuses into the N-region. They then combine with

53

JUNCTION DIODE

the free electrons in the N-region. Junction P-type

N-type

Fig. 2.3. A P N-Junction when just formed.

(b) The free electrons from the N-region diffuses into the P-region. These electrons combine with the holes. The process (a) and (b) can be easily understood by Fig. 2.4 as shown below : PN-Junction

Electron Hole

P-type

N-type

Fig. 2.4. Diffusion of holes and electrons which is responsible for the formation of depletion layer in a PN-Junction.

(c) The diffusion of holes (from P region to N region) and electrons (from N region to P region) takes place because they move haphazardly due to thermal energy, and also because there is difference in their concentration in the two regions. (d) One would normally expect the holes in the P region and free electrons in the N region to flow towards each other and combine. But in actual practice this does not occur. The diffusion of holes and electrons across the junction occurs for a very short time. After a few recombination of holes and free electrons, in the vicinity of the junction, a restraining force is automatically set up. This force is produced due to depletion region or the space-charge region or the transition region. Which exists on either side of the junction. The thickness of this region is of the order of wavelength of visible light ( 0. 5 m). As a result of this, further diffusion of holes and free electrons from one region to the other is stopped by this depletion region (layer). It may be noted that depletion region consists of only uncompensated acceptor ions and donor ions. Fig. 2.5 shows

54

BASIC ELECTRONICS ENGINEERING & DEVICES

the formation of depletion layer. Electric field P-type

N-type

Depletion region

Fig. 2.5. Space-charge region or depletion region is formed in the vicinity of the junction.

The electric field between the acceptor and the donor ion is called a barrier potential. For a silicon PN junction, the barrier potential is about 0.7 V, whereas for a germanium PN junction it is approximately 0.3 V. (e) The barrier discourages the diffusion of majority carriers across the junction. But here one important question arises—what happens to the minority carriers ? There are a few free electrons in the P region and a few holes in the N region. The barrier helps these minority carriers to drift across the junction. The minority carriers are constantly generated due to thermal energy. It will be interesting to know that the width of depletion layer depends upon the doping level of the impurity in N-type or P-type semiconductor. The higher the doping level, the thinner will be depletion layer and vice versa. This is due to the fact that potential barrier exerts a repelling force on the mobile charge carriers, trying to crossover the junction. This force stops the mobile charge carriers to crossover the junction, unless the energy is supplied from an external force. Does it mean there would be a current due to the movement of these minority carriers ? Certainly not. Electric current cannot flow since no circuit has been connected to the PN-junction. The drift of minority carriers across the junction is counter balanced by the diffusion of the same number of majority carriers across the junction. Thus, we conclude that a barrier voltage is developed across the PN-junctions even if no external battery is connected. NOTE :

The barrier potential of a silicon diode decreases by 2 mV for each degree celsius rise i.e.,

dV V = 2 mV/C = . dt T

55

JUNCTION DIODE

If we connect a battery to the PN-junction diode such that the positive terminal of the battery is connected to the P-side and negative terminal to the N-side, as shown in Fig. 2.6 (a). In this situation the PN-junction is said to be forward-biased. Reduced depletion layer

Depletion layer P

N

P

N

Holes Electrons V

V VB

(a)

VB (b)

Fig. 2.6. PN-Junction with forward bias.

When the PN-junction is forward-biased, the holes are repelled from the positive terminal of the battery and are compelled to move towards the junction. Similarly, the electrons are repelled from the negative terminal of the battery and drift towards the junction. Because of their acquired energy (from the voltage source), some of the holes and electrons enter the depletion layer and recombine themselves. This reduces the width as well as height of the potential barrier (VB) as shown in Fig. 2.6 (b). As a result of this, more majority carriers diffuse across the junction. Therefore it causes a large current to flow through the PN-junction. It may be noted that for each recombination of free electron and hole, which occurs, an electron from the negative terminal of the voltage source enters the N-type region. Then it moves towards the junction. Similarly, in the P-type region near the positive terminal of the voltage source, an electron breaks a covalent bond in the crystal and enters the positive terminal of the voltage source. Thus for each electron, which break its bond, a hole is created. This hole drift towards the junction. The current through the external circuit, is due to the movements of electrons only. On the other hand, the current within the PN-junction is the sum of electron current and hole current. Thus, the current in the external circuit continues to flow as long as the voltage source is present in the circuit. The current increases with increase in applied voltage and is of the order of several milliamperes. The maximum value of current depends upon the actual resistance, called bulk resistance of the semiconductor material. The bulk resistances are ohmic resistances of P-type and N-type semiconductor materials. Usually the values of bulk resistances are order of few ohms.

56

BASIC ELECTRONICS ENGINEERING & DEVICES

Effect of Barrier Potential on the Forward Biased PN-junction The barrier potential of the depletion layer can be considered as a small battery, which opposes the external d.c. voltage as shown in Fig. 2.7. The resistance Rp and Rn represent the bulk resistances of the P-type and N-type semiconductors.

P Rp

N VB

Rn

The PN-junction does not permit the V current to flow, until the external bias voltage overcomes the barrier potential, (i.e., (V VB). Fig. 2.7. Forward biased PN-junction. For example, the silicon PN junction, does not conduct as long as the external applied voltage is below 0.7 V. Similarly, the germanium PN junction does not conduct as long as the external voltage is below 0.3 V. It may be noted, that once the current starts flowing through the junction, the voltage drop across it remains equal to the barrier potential. It changes very little with the change in current, except for bulk resistance effects. The bulk resistances are the ohmic resistances of P-type and N-type semiconductor materials. Usually, their values are of the order of few ohms.

If we connect a voltage source to a PN-junction, such that positive terminal of the voltage source is connected to the N-region and negative to the P-region, then the PNjunction is said to be reversed biased. Fig. 2.8 shows a reverse biased PN-junction. P

Depletion layer

Increased depletion layer N

V

V V VB

VB

(a)

(b)

Fig. 2.8. PN-junction with reverse bias.

When a PN-junction is reverse biased, as shown in Fig. 2.8(a), the holes in the Pregion are attracted towards the negative terminal of the applied voltage source, whereas the electrons in the N-region are attracted to the positive terminal of the voltage source. Thus the majority carriers are drawn away from the junction. This widens the depletion layer and increases the barrier potential as shown in Fig. 2.8(b). The increased barrier potential makes it very difficult for the majority carriers to diffuse across the junction. Thus there is no current due to majority carriers in a

57

JUNCTION DIODE

reverse bias PN-junction. Or in other words we can say that the junction offers very high resistance under reverse biased condition. However, the barrier potential helps the minority carriers in crossing the junction. As a matter of fact, as soon as a minority carrier is generated, it is swept (i.e., drifted) across the junction because of the barrier potential. Hence a small amount of current (called reverse saturation current or leakage current or current due to minority charge carriers) does flow through the reverse biased PN-junction. The amount of this current depends upon the generation of minority carriers diffusing across the junction. NOTE :

(i) It may be noted that generation of minority carriers depends upon the temperature and is independent of the applied reverse voltage. Therefore the current due to flow of minority carriers remains the same whether the applied voltage is increased or decreased. Because of this reason, the current is known as reverse saturation current. (ii) The reverse saturation current is of the order of nanoamperes (nA) for silicon and microamperes (A) for Germanium PN-junctions. The reverse saturation current for, Si devices is smaller than that of Ge because silicon has a large energy gap ( 1.1 eV) between the conduction and valence bands compare to the energy band gap of ( .7 eV). As a result of this, less minority carriers are thermally generated at any temperature in silicon than that of germanium. This is the reason why Si is mostly preferred over Ge. (iii) Temperature dependency of reverse saturation current. It has been experimentally found that the value of reverse saturation current (I0) is about double in magnitude for every 10C rise in temperature. If I0 = I0, at T = T1, then at temperature T, I0 is given by I0 (T) = I0 × 2

(T T1 ) 10

... (2.1)

For example : if for silicon I0 is 5 A at 25C, then it is approximately 10 nA at 35C.

In order to know how a device responds when it is connected in an electrical circuit, V-I characteristics of PN-junction diode is analysed. It is the graph between the voltage applied across its terminals and the current that flows through it. The V-I characteristic of an ideal PN-junction diode is shown below in Fig. 2.9. For a PNjunction, the current I is related to the voltage V by the equation.

F H

V

I K

I = I 0 e VT 1 where

... (2.2)

I = Diode current (+ve value of I means current flows from p to n side) I0 = Reverse saturation current V = Applied voltage

R| +ve for forward biased S| T ve for reverse biased

58

BASIC ELECTRONICS ENGINEERING & DEVICES

VT

Volt equivalent by temperature T volt. 11, 600

=

|RS 1 for germanium, and |T 2 for silicon at rated current

At room temperature (T = 300 K), VT = 26 mV eqn. (2.2) represents the general form of V-I characteristics. I, mA 6

I

5 4 3 2 1 I0

0.1

0.5

0.3

0.6

V, V

1.0

–V

A

V VZ

(a) The volt-ampere characteristic of an ideal PN diode.

(b) The volt-ampere characteristic for a practical germanium diode. The dashed portion indicates breakdown at VZ.

Fig. 2.9.

When the voltage V is positive and several times VT (i.e., V >> VT) eqn. (2.2) may be written as : I = I0

FH IK e V V T

... (2.3)

When the voltage V is negative (i.e., diode is reverse biased) and |V| is several times VT (|V| >> VT), then the eqn. (2.2) may be written as : I

I0

... (2.4)

The reverse current is therefore constant, independent of the applied reverse bias. Therefore, I0 is called as reverse saturation current. As we have already discussed that temperature is main determining factor of leakage current. On increasing the value of temperature the value of cut in voltage continuosly decreases, this can be better understood by the Fig. 2.9 (c).

59

JUNCTION DIODE

Fig. 2.9 (c). Vartion in V-I characteristic of silicon diode due to temperature changes.

Practical PN-junction Diode and Concept of Cutin Voltage (Vr ) From Fig. 2.9 it is clear that for small value of applied voltage V there will be a definite value of the diode current I. But in actual practice it is not possible, as there is some voltage (equal to cut in voltage Vr ) is drop across the depletion layer of the junction, or in other words we can say that diode does not conduct well until the external voltage (i.e. V ) overcome the barrier potential. Cut is voltage (Vr ) also called knee voltage. For a silicon diode it is approximately 0.7 V for Si diode and approximately 0.3 V for Ge diode as shown in Fig. 2.10 (a). The cut in voltage of Si is equal to 0.7 V means

Imax

I

0.7 V

V

Fig. 2.10 (a). Forward characteristics of a silicon diode.

that we require minimum 0.7 external voltage in order to make the diode in conducting mode. NOTE :

PN-junction diode in forward biased ideally acts as a short circuit, whereas in reverse biased acts as a open circuit.

Figure 2.10 (b) shows a P-N junction diode with a forward bias with an external voltage V. Because of forward bias, there exists a potential gradient in P and N materials. Now, the holes from the P-region and electrons from the N-region are injected into the N-region and P-region respectively. The holes injected into the N-region and electrons

60

BASIC ELECTRONICS ENGINEERING & DEVICES

Current, I

injected into the P-region are the minority carriers. The minority carriers diffuse away from the junction exponentially with the distance as illustrated in figure 2.10 (c). Their concentration falls steadily due to recombination with electrons and holes respectively. Now, since the diffusion current due to minority carriers is proportional to the concentration gradient, therefore, this current must also vary exponen-tially with distance

P

P

+

V

Electron drift current, Ien

Hole drift current, Ihp

N

Electron diffusion current, Iep

–

Total current, I N

Hole diffusion current, Ihn x=0 Distance

Fig. 2.10 (b)

Fig. 2.10 (c). Current components in a forward biased P-N junction diode

There are two minority (i.e., diffusion) current denoted as Iep and Ihm as illustrated in figure 2.10 (c). Let the symbols Iep(x) and Ihn(x) represent the electron current in the P-region and the hole current in the N-region respectively. Electrons crossing the junction at x = 0 from right to the left constitute a current in the same direction as the holes crossing the junction from left to right. Hence, the total current I at junction (i.e., x = 0) may be expressed as under : I = Ihn(0) + Iep(0) Since the current is the same throughout a series circuit, therefore the total current I is independent of x and is shown as a horizontal line in figure 2.10 (c). Thus, in the P-region, there must be a second component of current Ihp which when combined with Iep gives the total current I. Therefore, the majority (i.e., hole) current, Ihp in the P-region is expressed as Ihp(x) = I – Iep(x) Similarly, the majority (i.e., electron) current, Ien in the N-region is expressed as Ien(x) = I – Ihn(x) The currents Inp and Ien are plotted as a function of distance in figure 2.10 (c). The figure 2.10 (b) is drawn for unsymmetrically doped diode, so that Iep Ihn

61

JUNCTION DIODE

Now, it may be noted that far away from the junction in P-region, the current is drift current Ihp of holes sustained by small electric field in the semi-conductor. As the holes approach the junction, some of them recombine with the electrons which have been injected into the P-region from the N-region. Hence, part of the current Ihp becomes a negative current just equal in magnitude of the diffusion current Iep. The drift current Ihp, therefore, decreases towards the junction. The rate of decrease is such that the total current remains constant, independent of distance. The reduced hole current at the junction now enters the N-region and becomes hole diffusion current Ihn. A similar statement can be made with respect to electron drift current in the N-region Ien. Hence, in a forward-biased P-N diode, the current enters the P-region as a hole current and leaves the N-region as an electron current of the same magnitude. From the above discussion, it may be concluded that the current in a P-N diode is bipolar in character (since it is made up of both positive and negative charge carriers) and the total current is constant throughout the device, but the proportion of current due to holes and that due to electrons varies with the distance as shown in figure 2.10 (c).

One thing should be always kept in mind that no diode can act as an ideal diode. An actual diode does not behaves as a perfect conductor when forward-biased, and as a perfect insulator when reverse-biased. It does not offer zero resistance when forwardbiased, also not infinite resistance when reverse biased. Generally there are two types of resistance of a PN-junction diode is considered namely : (i ) Static resistance (ii ) Dynamic resistance. (i ) Static Resistance. Static resistance of a PN-junction diode is calculated when the diode is connected in a d.c. circuit. This resistance is also known as d.c. resistance or static resistance, or we can say it is simply the ratio of d.c. voltage across the diode to the d.c. current flowing through it. It is denoted by RF. (ii ) Dynamic Resistance. Dynamic resistance of a PN-junction diode may be defined as the resistance offered by the diode to the a.c. signal is called dynamic or a.c. resistance. Dynamic resistance of a diode is equal to the slope of V-I characteristics

i.e., Consider the eqn. (2.2)

F dV H dI

rf =

or

V I

I K

of the diode.

Change in voltage Resulting change in current

FH

V

IK

I = I 0 e VT 1

=

dV dI

=

V I

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BASIC ELECTRONICS ENGINEERING & DEVICES

Differentiating above eqn. (2.2) with respect to V we get dynamic conductance dI g= dV

=

I 0e

V VT

V T

or

g=

I I0 V T

(From equation 2.2)

or

VT r = I I 0

...(2.5)

V >> ). g is extremely small and r is very V T large. On the other hand, for a forward biased junction, I > I0, so equation 2.5 becomes

For a reverse biased junction (i.e.,

r

VT I

...(2.6)

From above expression it is clear that dynamic resistance inversely proportional to the reverse saturation current.

There are usually two types of diode capacitances namely : (i) Depletion layer capacitance or Transition capacitance (CT ). (ii) Diffusion or Storage capacitance (CD).

(1) Depletion Layer Capacitance or Transition Capacitance (CT) We have already discussed that when a PN-junction is formed, a layer of positive and negative ions called depletion layer is formed on either side of the junction. Since this capacitance is formed in the junction area, therfore, it is also called space charge capacitance. This capacitance is arises due to immobile charges at the junction varying with the applied voltage, that’s why this is simply called junction capacitance. Figure 2.11 shows the formation of depletion layer capacitance. P-type

N-type

CT Plate

Dielectric

Plate

Fig. 2.11. Depletion layer capacitance.

The capacitance of a parallel plate capacitor is given by the equation C =

0 . A d

where 0 is the permitivity of dielectric (insulator) between the plates of area A separated

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JUNCTION DIODE

by a distance d. Since the depletion layer width (d) increases with the increase in reverse bias voltage, the resulting depletion layer capacitance will decrease with the increased reverse bias. The depletion layer capacitance depends upon the nature of a PN-junction, semiconductor material and magnitude of the applied reverse voltage. It is given by the relation : CT =

C0

FG1 V IJ H V K

... (2.7)

r

T

where,

C0 = Capacitance at zero bias condition Vr = Applied reverse voltage VT = Volt equivalent of temperature

R| =S || T

1 for step or abrupt alloy junction 2 1 for linearly graded junction or diffused junction. 3

It is evident from the above relation that the value of depletion layer capacitance (CT ) can be controlled by varying the applied reverse voltage. This property of variable capacitance, possessed by a reverse biased PN-junction is used in the construction of a device called varicap of varacter, which is chiefly used in FM circuits. Range of depletion layer capacitance is approximately in nF (nanofarad).

(2) Diffusion or Storage Capacitance (CD ) The capacitance which exists in a forward-biased junction is called a diffusion or storage capacitance. It is different from the depletion layer capacitance, which exists in a reversed biased junction. The diffusion capacitance arises due to the arrangement of minority carrier density. The value of diffusion capacitance is much larger than the depletion layer capacitance (i.e., CD >> CT ). Its value for abrupt junction is given by the relation : CD = Where

.I

... (2.8)

.V T

= Mean life time of the carriers I = Forward current VT = Volt equivalent of temperature = Constant =

R| 1 for Ge S| 2 for Si T

It is clear from the eqn. (2.8) that, the diffusion capacitance is directly proportional to the forward current (I). Consider a forward-biased PN-junction carrying a current of

64

BASIC ELECTRONICS ENGINEERING & DEVICES

(I) amperes through it. Suppose the junction is suddenly reverse biased. It causes the forward current to reduce quickly to zero. But it leaves a number of majority charge carriers stored within the depletion region. This charge represents a stored charge in the reverse biased condition and must be removed out of the space charge region. The removal of stored charge takes a finite time. It represents an effect similar to the discharging of a capacitor. Thus the quantity of the stored charge represents the magnitude of diffusion capacitance. It may be noted that the effect of diffusion capacitance is negligible for a reverse-biased PN-junction.

There are different types of rating in a diode given below : (i) Maximum power rating (ii) Peak inverse voltage rating (PIV) (iii) Maximum forward current rating. (i) Maximum Power Rating. Maximum power rating of a diode is defined as the maximum power that a pn-junction (or diode) can dissipate without damaging it is called its maximum power rating. Usually, maximum power rating in specified by the manufacturer in its data sheet. The power dissipated at the junction is equal to the product of junction current and the voltage across the junction. If the power developed across the junction is more than the maximum power dissipated by it, the junction will be over-heated and may be destroyed. (ii) Peak Inverse Voltage Rating (PIV). Peak inverse voltage rating of a diode may be defined as the maximum value of reverse voltage that a p-n junction (or diode) can withstand without damaging it is called the peak inverse voltage rating (PIV) of a diode. This rating of a p-n junction or diode is also specified by the manufacturer in its data sheet. However, it may be noted that here if we increase the voltage across the junction at reverse bias condition beyond this specified value, the junction will be destroyed. (iii) Maximum Forward Current Rating. The maximum forward current rating of a diode may be defined as the maximum value of forward current that a pn-junction or diode can carry without damaging itself called its maximum forward current rating of a diode.

? 1. What do you mean by p-n junction ? 2. Explain the phenomenon of the formation of depletion layer in the p-n junction. 3. What will be the effect on the depletion layer of a p-n junction diode under different biased condition ? 4. Differentiate between transition capacitance and diffusion capacitance of a p-n junction diode.

65

JUNCTION DIODE

5. What is an ideal diode ? How can it be represented as a switch ? Draw the equivalent circuit and its characteristics. 6. Define diffusion current in a semiconductor. 7.

(i ) Define cut-in voltage of a p-n junction diode. (ii ) Draw the reverse bias characteristics of a p-n junction.

8. Explain why the energy levels of an atom become energy bands in a solid. 9. Define a hole in a semiconductor. Explain why a semiconductor acts as an insulator at 0K and why its conductivity increases with increasing temperature. 10. Draw the energy band diagram for a p-n junction under open-circuit condition. Clearly indicate various energy levels in p-region, space charge region and n-region. How will it be modified if p-n junction is forward biased ? 11. For a semiconductor diode, define static and dynamic resistance. 12. Derive an expression for the dynamic resistance of a diode in forward bias condition and hence interrupt graphically its variation with (i ) current and (ii ) temperature. 13. Explain the construction and V-I characteristics of a p-n junction diode. 14. Is a hole a fundamental particles in an atom ? Between electron and hole which one has a greater mobility ? Give a reason for the difference.

Example 1. The current flowing in a certain PN-junction diode at room temperature is 2 × 107 A, when the large reverse voltage is applied. Calculate the current flowing, when 0.1 V forward bias is applied at room temperature. Solution : Given

I0 = 2 × 107 A V = 0.1 volt

We know that the current flowing through the diode under forward bias, I = I0 (e40V 1) = 2 × 107 (e40 = 1.16 µA.

× 0.1

1)

Ans.

Example 2. The current voltage characteristic of a PN-junction diode is given by the relation : I = I0 (eqV/ . k . T 1) The diode current is 0.5 mA at V = 340 mV and 15 mA at V = 440 mV. Determine the value of . Assume kT/q = 25 mV. Solution : Given : I1 = 0.5 mA = 0.5 × 103 A; V1 = 340 mV; I2 = 15 mA = 15 × 103 A; V2 = 440 mV and k . T/q = 25 mV. We know that the diode current (I1) 0.5 × 103 = I0 (eqV1/ . k . T 1) = I0 . eqV1/ . k . T = I0 . e340/25 = I0 . e13.6/

... (1)

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BASIC ELECTRONICS ENGINEERING & DEVICES

Similarly, the diode current (I2) 15 × 103 = I0 . e440/25 = I0 . e17.6/

... (2)

Dividing equation (2) by (1), 30 = e(17.6

13.6)/

= e4/

Taking natural logarithms on both sides, loge 30 = loge(e4/) =

4 4 . loge e =

3.4 = 4/ or = 4/3.4 = 1.18

(

loge e = 1)

Ans.

Example 3. An ideal germanium diode at a temperature of 125C has a reverse saturation current of 30 A. At a temperature of 125C, find the dynamic resistance for a 0.2 V bias (a) in the forward direction (b) in the reverse direction. Solution : (a) We know that the diode current is given by the relation

FH

IK

V

I = I 0 e VT 1

dI dV

=

V

I0 V T

e V T V

I0 e VT = VT We know that dynamic resistance, dI dV

rf = =

( = 1 for germanium)

dV dI

VT V

I 0 e VT =

=

T 1 11600 30 10 6

e

398 1 11600 30 10 6

F V H

1

0 .2 VT

1 0 .2 11600 e 398

or

398 1 11600 30 10 6

rf = .389 M.

Ans.

T 11600

I K

(T = 273 + 125 = 398K)

= 3.36 . Ans. (b) Dynamic resistance in reverse direction rf =

T

1 0 .2 11600 e 398

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JUNCTION DIODE

Example 4. (a) Find the voltage at which the reverse current in a Ge diode at room temperature will reach 90% of its saturation value. (b) Find the ratio of diode current with a forward bias of 0.05 V to the current with a reverse bias of 0.05 V. (c) The reverse saturation current of a Ge diode is 10 A. Find current under forward biases of 0.1 V, 0.2 V, 0.3 V. Solution : (a) From diode equation given by, I = I0 (eV/VT 1) Saturation value of I = I0

Putting I = 0.9 I0 in above equation we get 0.9 I0 = I0 (eV/VT 1)

eV/VT 1 = 0.9 V V T

= ln 0.1 = 2.3

V = VT × ( 2.3) = 1 × 0.026 × 2.3 = – 59.8 mV.

(b) (c)

If Ir

=

I 0 (e 0 . 05/0 . 026 1) I 0 (e

0 . 05/0 . 026

1)

=

Ans.

5.84 I 0 = 6.84 Ans. 0.854 I 0

I1 = 10 (e0.1/0.026 1) = 10 × 45.8 = 458 A I2 = 10 (e0.2/0.026 1) = 10 × 21900

or

I2 = 21900 A = 21.9 mA I3 = 10 (e0.3/0.026 1) = 10 × 1.02 × 105 A = 1.02 Amps.

Ans.

Example 5. A Si diode operates at a fixed forward bias of 0.4 V. Calculate the factor by which the current will get multiplied when its temperature is raised from 25C to 150C. Solution : In a practical diode, I0 doubles for every 10 rise in temperature.

I0 (150) = I0 (25) × 2(150

25)/10

= I0 (25) 212.5 = 5800 I0(25) Thus rev. sat. current is multiplied 5800 times VT (150) = kT = 8.62 × 105 × (273 + 150) = 0.0364 V Using diode equation

I 0 (150 )(e V /VT 1) I (150 ) (25) = I I 0 ( 25 )(e V /VT 1)

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BASIC ELECTRONICS ENGINEERING & DEVICES

e 0 .4/( 2

= 5800 × =

e

0.0364)

0 .4 /( 2 0.026)

5800 241 = 638. Ans. 2191

Example 6. In the circuit shown below. The diode is used has a threshold voltage of 0.5 V and a forward resistance of 1 . Find the operating point of the diode. 1 k

5V

Diode

Fig. P (2.1).

Solution : The redrawn circuit is shown in Fig. P (2.2) with diode having 1 resistance. 1 K ID

1

VD V D

5V

0.5 V

Fig. P (2.2).

In order to calculate the value of operating point we have to calculate the value of ID and VD. Applying KVL in the above circuit 5 ID × 1000 ID.1 0.5 = 0 ID = or

4.5 1001

ID = 4.49 mA.

Ans.

and

VD = ID × 1 + 0.5

or

VD = 4.49 × 103 × 1 + 0.5

or

VD = .5045 V.

Ans.

Example 7. (a) Two ideal and identical (ideality factor = 1) junction diodes are connected in series as shown in Figure. Show that exp. V1 and V2 are the voltage drops across the diodes.

FG eV IJ H kT K 1

+ exp.

FG eV IJ H kT K 2

= 2 where

69

JUNCTION DIODE

(b) Assuming that the reverse biased diode is saturated at I0. Calculate the voltage kT = 26 meV). q

drop across the forward biased diode. (Assume V2

V1

D2

D1

V

Fig. P (2.3).

Solution : (a) I = I0

Fe GH

eV1 kT

I JK

1 . As diode V2 is connected in the reverse-bias mode

I = I0, the reverse saturation current I = I0

Fe GH

eV1 kT

I JK

1

F for D and I = I G e H F 1I = I F e I Ge GH JK H 1

or

exp

F eV I H kT K 1

e

0

eV1 kT

0

eV2 kT

eV1 kT

exp

0

+ e

eV2 kT

F eV I H kT K 2

e

(b) eeV1/26e

I JK

1

eV2 kT

for D2.

I JK

1

= 2 = 2. Ans.

eV1 kT

= 2 kT = 26 meV

× 101

V1 26 10 3

= 2 = ln 2 = 0.693; V1 = 26 × 103 × 0.693 = 18 mV = 0.018 V. Ans.

Example 8. Find the space charge capacitance of germanium diode whose area is 1 mm2 and whose space charge thickness is 2 × 10–4 cm. Permitivity for germanium is

Ge =

16 36 1011

F/cm.

Solution : As we know that CT =

FG 16 IJ 10 H 36 10 K

0 A Ge A = d d

2

11

therefore, CT =

( 2 10 4 )

= 70.73 Pf Ans.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Example 9. Find CT , if conductivity of p-material is 0.286 ( cm)–1, barrier potential is 0.35 V and cross-section area is circular with diameter of 0.12 cm. The applied reverse voltage is 5 V. Solution : Given,

A =

( 0.102)2 D 2 = cm2 = 8.17 × 10–3 cm2 4 4

p = qµpNA or

p

NA =

0.286

=

1.6 10 19 500 Therefore, the transition capacitance, CT is q p

4 CT = 2.92 10

= 2.92 10

4

= 3.575 × 1015 atom/cm3

FG N IJ A Pf/cm HV K FG 3.575 10 IJ 8.17 10 H 5 0.35 K 1/2

A

2

b

15

1/2

3

= 61.25 Pf/cm2 Ans. Example 10. The transition capacitance CT is 15 Pf for a reverse bias of 8V. What will be the value of CT for a reverse bias of 12V. Solution : Transition Capacitance is inversely proportional to square root of junction potential

1 Vb

CT Therefore,

C T1 CT2

where, Vb = Junction potential or barrier potential

FV I GH V JK FV I C G H V JK F 8 I = 12.28 pf Ans. 15 H 12 K 1/2

=

b2 b1

1/2

CT2

=

b1

T1

b2

1/2

=

Example 11. At what voltage, the reverse current flowing through a diode (Ge) will reach 90% of its saturation value at room temperature (300°K). Solution : VT = 0.026 V at 300°K Using diode equation, we get T = or

I = For germanium,

So,

I0 I0

F He F He

V V T

V 0 . 026

b

I K

1

g

I K

1

= 1 I = 90% of I0 = – 0.9 I0

71

JUNCTION DIODE

– 0.9 I0 =

I0

– 0.9 =

eb

or e or Taking log both side

V 0 . 026

F b He

V 0 . 026

V 0 . 026

g

g

I K

1

1

= 1 – 0.9 = 0.1

V

loge e 0 . 026

or

= loge.1

V = (–2.3) 0.026 V = –59.8 mV.

or or NOTE :

I = – 0.9 I0, because direction of diode current is positive while flowing from p to n-side but reverse saturation current flows from n-side to p-side due to flow of minority charge carriers.

Example 12. Determine ID for each circuit given in Fig. P (2.4) 20 k

Si

100 k

ID

+ 20V

+ 10V

10 k

Si

(a)

(b)

Si

Fig. P (2.4).

Solution : (a) Given Vin = 20 V V = Cut in voltage = 0.7 V for Si Apply KVL, 20 – ID 20 – 0.7 = 0

20 0.7 V = 0.965 mA Ans. 20 k = 10 V

ID = (b) Given

Vin

V = 0.7 V Ans. NOTE :

Here, the arrangement of diode is back to back. hence, one will be reverse biased and other will be forward biased. But due to reverse biased diode, no current will flow through the branch containing diodes. The total voltage will be impressed on resistance of 100 k, since it is parallel to the branch containing diodes. Therefore, ID

=

10 V = 0.1 mA Ans. 100 k

72

BASIC ELECTRONICS ENGINEERING & DEVICES

Example 13. Calculate V0 and ID for the circuits given in Fig. P (2.5). 1 k +

+ 10 V

ID

2 k V0

Si

– Fig. P (2.5).

Solution : Apply KVL in the given loop, we get 10 – (1 k) ID – (2 k) ID – 0.7 = 0 ID (1 + 2) k = 10 – 0.7

9.3 V 3 k

or

ID =

or

ID = 3.1 mA Ans.

and,

V0 = ID (2 k) + 0.7 = 3.1 × 10–3 × 2 × 103 + 0.7 = 6.2 + 0.7 = 6.9 V Ans.

Example 14. For each of the ckt as shown in Fig. P (2.6). Determine the state of the diode—ON or OFF and calculate the current in each branch. Assume ideal diodes. 10

10 V

10

– +

+

D

–

D

(a) +

4V

(b) –

–

10

D

D

10 V +

6V –

+

(c)

(d) Fig. P (2.6).

10

10 V

73

JUNCTION DIODE

Solution : (a) The diode D is in forward biased so if will be in ON-State and current through V 10 resistance will be I = = = 1 amp. R 10 (b) The diode in ckt-D will be reversed biased and since diode is ideal so reverse bias resistance will be of. So the current through 10 resistance will be 0. D-OFF. (c) Here 4 V and 6 Volt batteries are connected in series with reverse polarity in total voltage across diode will become : 2 V; so diode will be OFF and current through this will be zero. (d) The diode will be ON and current through this =

10 V = 1A (i.e., ). 10 R

Example 15. In the ckt of Fig. P (2.7), diode has a threshold voltage of 0.5 V and RF = 1 k. Find the operating point of the diode. 1K

+ 5V

+ Vd –

–

Fig. P (2.7).

Solution : Apply KVL for loop we get, 5 – Vd – Ri Ii = 0 When

Ii = 0

Vd = 5 V

When

Vd = 0 Ii =

or

...(1)

5 RF

=

5 1 k

Ii = 5 mA

Now from equation (1)

Q = (0.505 V, 4.5 mA)

5 – Vd – Ri Ii = 0 Ii = =

Ii

5 0.5 RF

4.5 = 4.5 mA 1 k

The load line is shown in Fig. P (2.8). The operating point, Q = (0.505 V, 4.5 mA)

5V

Fig. P (2.8).

VD

74

BASIC ELECTRONICS ENGINEERING & DEVICES

Example 16. For the circuit shown in Fig. P (2.9), the input Vi has positive and negative swings. Find the output voltage, V0.

Fig. P (2.9).

Solution : From the Fig. P (2.9). It is clear that for vi < VR the diode will not conduct so output voltage equals to Vi. V0 = Vi

i.e.,

for

Vi < VR

and for Vi > VR the diode will conduct and output voltage becomes equal to VR. V0 = VR

i.e.,

for

Vi > VR

(neglecting the voltage drop

across R and cut in voltage of diode) Example 17. For the circuit shown in Fig. P (2.10). The output voltage V0. D +

+ R Vi

V0 VR –

–

Fig. P (2.10).

Solution : Try yourself. Example 18. The voltages at V1 and V2 of the arrangement shown in the figure P (2.11) will be respectively. (Assume cut-in voltage of diode is .6 V). +6V

V1 D2 + 6V

V2 D1 R +3V

Fig. P (2.11).

75

JUNCTION DIODE

Solution : From given Fig. P (2.11), for the diode D2 cathode is at higher potential than anode. Hence diode D2 will not conduct, i.e., no current in upper R resistance, so V1 = 6 V. But anode of D1 is at higher potential than cathode so the diode D1 will conduct. V2 = 6 – Vr = 6 – 0.6 = 5.4 V (where Vr = cut in voltage of diode) Example 19. Find I1 and I2 for the circuit shown Fig. P (2.12) terms of VS assume VT = 0.7 volt for all diode.

Fig. P (2.12).

Solution : From Fig. P (2.12) we see that here current I1 and I2 depends upon voltage Vx. I1 = Also,

5 Vx 2 k

If

0 < VS < 0.7 V

Vx = VS + 0.7

If VS > 0.7, the diode D1 will be in reverse biased, so, in this situation, I1 = I2 = 5 1.4 = 1.8 mA. Ans. 2 k Where, 1.4 V is the voltage drop across diode D2 and D3. Example 20. Consider the circuit shown in Fig. P (2.13). If the diode used here has the V-I characteristic as in Fig. P (2.14). Find the output waveform V0. Vi 2V

2

0 – 2V

Fig. P (2.13)

600

V0

76

BASIC ELECTRONICS ENGINEERING & DEVICES I

dV = 300 dI for V > 0.5 v

V

0.5 V

Fig. P (2.14).

Solution : From given Fig. P (2.14). Given that the resistance of diode, i.e., Rf = dV = 300 and the diode will conduct for input voltage greater than 0.5 V. dI So, for the given information the equivalent circuit of Fig. P (2.13) can be redrawn as shown below in Fig. P (2.15). 0.5 V +

Vi

300

600 V0

Diode equivalent

–

Fig. P (2.15).

From Fig. P (2.14), for positive half-cycle So,

V0 = (Vi – 0.5)

or

V0 = 1.5 ×

or

V0 = 1.0 V

F 600 I H 600 300 K

600 900

However, for negative half cycle of the input voltage Vi, the diode is in the nonconduction state and we get zero output. Finally the output wave form of Fig. P (2.13) is shown below in Fig. P (2.16)

1V

2

Fig. P (2.16).

3 Diode plays a very important role in various application. The most widely use of diode is in the field of rectification, (rectification is the process of a.c. to d.c. conversion) without diode rectification is not possible. The a.c. may be either in voltage or current form. a.c. power is easily produced in bulk form through different methods, but generally in many power control circuits and in other industrial applications d.c. power is very much required. Hence a.c. power necessarily has to be converted into d.c. power by means of electronic rectifier which is simple cheaper and highly efficient compared to rotatory converters or motor generators, and this process is achieved by the use of diode. The output obtained by the diode rectification is not pure d.c. there is some ripples in the output wave (current or voltage). So in order to get pure d.c. output filter circuit becomes necessary requirement. There are different filter circuits are used in order to filter the a.c. components. A rectifier is a diode circuit which facilitates the a.c. current to flow only in one direction. A single diode-rectifier circuit cuts off the negative portion of the a.c. current and allows only one positive portion of the signal. This operation can be termed as half wave rectification (HWR). Similarly, for both parts of the cycle, we require a two diode rectifier circuit. This operation can be termed as full wave rectification. The main application area of diodes can be listed as below : rectifiers clippers or limiters clampers voltage multipliers logic gates etc.

If we look around, we find that most of electronic devices, such as TV, radio transistor, stereo, VCD/DVD players and computers etc., require the d.c. supply to work properly. But we have the a.c. mains supply from the power grid at a higher voltage level i.e., 230 V, 50 Hz (Single phase) and 440 V, 50 Hz (Three phase) for domestic purpose. Now, we have two options to supply the d.c. voltage to the electronic equipments, either we use batteries or some systems, which can convert the a.c. mains supply into d.c. supply. The system for this purpose, used in power supply section of electronic equipments is known as Rectifier, and the process of a.c. to d.c. conversion is known as rectification. 77

Comp-1/Laxmi-5/Computer/Revision/Belec-3—10.5.07

78

BASIC ELECTRONICS ENGINEERING & DEVICES

There are three types of rectifier circuit configurations : Half wave rectifier. Full wave rectifier with center tapped transformer. Full wave bridge rectifier. These are discussed in detail below.

The basic circuit diagram of half-wave rectifier with a pure resistive load, is shown in Fig. 3.1. D

TF A

1 230 V 50 Hz

vi

vL

RL

B

Fig. 3.1. Half wave rectifier circuit.

In the circuit, TF is the step down transformer. The resistance of the diode is assumed to be Rf in forward conduction or ON state and the d.c. resistance of secondary winding is R2. This circuit utilizes the unidirectional conduction property of the p-n junction, i.e., the p-n junction allows to flow the current through it only when it is forward biased and restricts when it is reverse biased. In a.c. mains supply voltage, there are two half cycles, one is positive and second is negative. The operation of the circuit, can be well understood from the Fig. 3.2, and the waveforms are shown in Fig. 3.3. A

vi

D

A

i

RL

vL

D

vi

vi

B

RL

vL

0

B

(a)

(b)

Fig. 3.2.

During the positive half cycle, (0 t ) when terminal A of secondary is at higher potential than that of terminal B, diode D will get forward biased and hence possesses a low resistance path (often with a very low resistance Rf ) to the current. This will make the load voltage positive and almost equal to the instantaneous input (supply) voltage.

79

DIODE APPLICATIONS

[Fig. 3.2 (a)] Here, the effect of cut-in voltage of diode, i.e., VD, is ignored assuming that VD >> (Rf + R2), the general case, we get VL

Vm

dc

(v) RMS Load Voltage Similarly, the RMS value of load voltage can be find as, VL

rms

= Irms × RL =

Vm × RL 2 ( R f R2 R L )

... (3.11)

82

BASIC ELECTRONICS ENGINEERING & DEVICES

Making the assumption, RL >>> (Rf + R2), we get

VL

Vm 2

rms

... (3.12)

(vi ) Ripple Factor The rectifier output consists of a.c. as well as d.c. The ripple factor measures the percentage of a.c. component in the rectified output. The ideal value of ripple factor should be zero, i.e., output should be pure d.c. Ripple factor is defined as : Ripple factor, =

RMS value of the a.c. component of output d.c. or Average value of output

As the instantaneous value of a.c. fluctuations is measured with respect to the d.c. level (i.e., the difference of instantaneous total value and the d.c. value). Thus, the instantaneous a.c. value is given as : iac = i Idc ... (3.13) Therefore, the RMS value of a.c. components is given as : Iac

rms

L1 = M MN 2 L1 = M MN 2

z z z

2

(i I dc )

2

0

O d ( t ) P PQ

2

(i

2

2 I dc

2 i I dc

0

L1 = M MN 2

2

i 2 d ( t )

0

2 2 2 = I rms I dc 2 I dc

Iac

rms

1/2

2 2 = I rms I dc

1 2

z

O ) d ( t ) P PQ

1/2

2

0

z

O i d ( t ) P PQ

2 2 I dc d ( t ) 2 I dc

0

1 2

1 2

1 2

... (3.14)

Therefore, ripple factor, 1

=

I ac rms I dc

2 2 2 [ I rms I dc ] = I dc

LF I I = MG MNH I JK rms dc

2

O 1P PQ 1

= [(F.F.)2 1] 2

1 2

... (3.15)

83

DIODE APPLICATIONS

For half wave rectifier, ripple factor can be calculated by substituting the value of form factor into eqn. (3.15), therefore, 1

= [(1.57)2 1] 2 = 1.21

or

(vii ) Voltage Regulation Under d.c. conditions, the rectifier circuit can be modelled as shown in Fig. 3.4, where Rf is the forward resistance of diode, R2 is the d.c. resistance of transformer’s secondary winding and RL is the load resistance. V0

dc

Rf (On diode)

R2

VNL

+ VdC +

Ideal output voltage

IL

V0

dc

VFL

RL

– IL

(a)

Idc

(b)

Fig. 3.4.

The voltage at output terminals can be calculated by voltage dividing rule as : V0

dc

=

(R2

V dc × RL = Idc × RL R f RL )

The value of load current depends on the value of the load resistance, i.e., lower the value of RL and higher will be the current (Idc). Since, the secondary voltage Vdc is constant, the output voltage V0 will decrease with decreasing the value of RL. This dc variation in output voltage from no-load to full load is measured by voltage regulation, i.e., % V.R. = where,

V NL V FL × 100 V FL

... (3.16)

VNL = Voltage at no load VFL = Voltage at full load

The voltage regulation is also termed as load regulation. The ideal value of load regulation should be zero.

(viii ) Rectification or Power Conversion Efficiency The efficiency of a rectifier can be defined as the ratio of output d.c. power available at the load to the input a.c. power from the mains, and can be represented mathematically as Rectification efficiency =

Output d.c. power available at the load Input a.c. power from the mains

84

BASIC ELECTRONICS ENGINEERING & DEVICES

i.e.,

(%) =

Po D .C . Pi A .C .

× 100.

... (3.17)

Now, The d.c. power available at the load P0 = I 2dc RL d.c.

=

2 Im

2

... (3.18)

RL

And the input a.c. power from the mains, 2 Pi = I rms (RL + Rf + R2 ) a.c.

2 Im (RL + Rf + R2 ) ... (3.19) 4 where, RL is load resistance, Rf is resistance of diode in forward biased or ON condition and R2 is the resistance of secondary winding of the transformer. Therefore, from eqns. (3.17), (3.18) and (3.19), we get

=

(%) =

=

=

=

P0 D.C. Pi A.C.

× 100 % ( I m / )2 R L

( I m /2 ) 2 ( R L R f R 2 )

4 RL

2

( R L R f R2 )

× 100 %

× 100 %

( 0.4053 ) 100 % R f R2 1 RL

F GH

=

1

I JK

40.53 % R f R2 RL

As per assumption, if RL >> (Rf + R2 ), we have = 40.53%

... (3.20)

It is clear from eqn. (3.20) that maximum achievable rectification and conversion efficiency with the half wave rectifier circuit is only approximately 41%. In practical case, where (Rf + R2 ) is comparable to the load resistance RL, the efficiency is very less than this maximum value.

(ix) Transformer Utilization Factor (TUF) Transformer Utilization Factor (TUF) can be defined as the ratio of output d.c. power available at the load to the power rating (Volt Ampere) of the transformer used in the rectifier circuit. Mathematically,

85

DIODE APPLICATIONS

TUF =

TUF =

Output d.c. power available at the load Power rating (VA) of the transformer P0 d.C. VA rating of transformer

... (3.21)

The a.c. power rating or VA rating of transformer can be calculated with the RMS voltage developed across the winding and RMS current flowing through the winding, i.e., VA rating of transformer = Vrms × Irms As the voltage developed across the secondary winding is full sinusoidal cycle but the current flows only for the half cycle (for which diode conducts), so Vrms = and

Vm 2

= Irms =

Im 2

Therefore:

Vm

VA rating of transformer =

but

Im 2

×

2

=

Vm I m 2 2

Vm (R L R f R2 )

Im = Therefore, VA rating of transformer

2 Im (RL R f R2 )

=

... (3.22)

2 2

Hence, using eqns. (3.18) and (3.22) we can calculate the TUF as : TUF =

=

2 Im RL

2 2

×

2

2

2 2 2 Im

×

1

F GH

( RL R f R2 ) 1 R f R2 RL

I JK

If (Rf + R2 ) V1 > V2

Fig. P (3.20).

Ge V2

99

DIODE APPLICATIONS

Solution : Output waveform of the circuit is given below in Fig. P (3.21). R Vi

V

Ge

Si t

V0

V2

V1 V > V1 > V2

Fig. P (3.21).

As we know that Si diode has threshold voltage 0.7 and Ge have 0.3 we get the output waveform when +ve half cycle is input Ge diode is cut-off and Si diode is also cut-off till the V1 = Vi when Vi > (V1 + .7) it get on and current flows through it similarly for negative half cycle of Ge. Vout

V

V1 t

V1

V2

V2

Input Waveform

t

Output Waveform

Fig. P (3.22).

Unlike the HWR, in the full wave rectifier, we get the output across the load for the full cycle of the input signal. According to the circuit configuration the full wave rectifiers (FWRs) are classified into two : Full wave rectifier with center-tapped transformer Full wave bridge rectifier.

The basic circuit diagram for the FWR with center tapped transformer is shown in Fig. 3.6. In this circuit, two diodes D1 and D2 are used as the switching elements, one diode acts for one half cycle and second for a othelr half cycle. The transformer used is a center tapped transformer. TF

D1

A

+ i RL

1 , 230 V, 50 Hz Supply

O

B

vL –

D2

Fig. 3.6. FWR with center tapped transformer.

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BASIC ELECTRONICS ENGINEERING & DEVICES

In the positive half cycle of the input a.c. supply, the polarities of secondary voltages are as shown in Fig. 3.7 (a), i.e., terminal A of the winding is at a higher potential than the center terminal O and the terminal B is more negative, with respect to terminal O. This makes the forward biasing for the diode D1 and reverse biasing for the diode D2. Therefore in this positive half cycle diode D1 conducts and D2 remains off. Thus load current flows through the diode D1 and load RL producing a load voltage (i.e., output voltage) across RL. The path of current is shown in figure. D1

A

+ i

+ 1 , 230 V, 50 Hz

vL

RL

–O +

–

D2

– B

TF

Fig. 3.7(a).

In the negative half cycle ( t 2), terminal B of transformer secondary winding becomes positive to the center terminal O and A becomes negative with respect to the terminal. Therefore, diode D2 conducts for this duration due to forward bias and D1 is OFF [Fig. 3.7 (b)]. D1 A

+ –

1 , 230 V, 50 Hz

i

+O – +

TF

RL

vL –

D2

B

Fig. 3.7(b).

Now, the load currents flows through the diode D2 and load resistance RL. It is to be noted here that for both of the half cycles of a.c. supply voltage, load current flows in the same direction, therefore producing an equidirectional pulsating d.c. voltage. The waveforms for diode currents, load current and load voltage is shown in Fig. 3.8.

101

DIODE APPLICATIONS Secondary voltage VAO

Vm

O

t

3

2 Vm

Secondary voltage VBO

t

O

D1

Diode current iD1

D2

D1

D2

Im

O Diode current iD2

3

2

t

Im t

O Load voltage

Vm

O Load current

2

3

2

3

t

Im

O

t

Fig. 3.8. Voltage and current waveforms for a FWR.

Similar to the previous section, Vi = Vm sin t Now, if we neglect the drop of a diode in forward bias we have load voltage, VL = Similarly load current i =

R| V sin t S| V sin t T

; for 0 t

m

; for t 2

m

|RS I sin t |T I sin t

; for 0 t

m

; for t 2

m

where,

Im =

(RL

... (3.25)

Vm R f R2 )

... (3.26) ... (3.27)

where Rf is the forward resistance of diode and R2 is the d.c. resistance of secondary winding.

(i ) Average (d.c.) Load Current Putting the value of current i into eqn. (3.5) from eqn. (3.26), we have, Iav or Idc =

1 2

LM MN

z

2

0

i d ( t )

OP PQ

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BASIC ELECTRONICS ENGINEERING & DEVICES

=

LM MN I sin ( t ) d (t ) ( I LM( cos t ) (cos t ) OP N Q

z

z

2

1 2

m

m

sin t ) d ( t )

0

2

=

Im 2

=

Im [ cos + cos 0 + cos 2 cos ] 2

0

or

Idc =

2I m

or

Idc =

Vm 2 ( R L R f R2 )

OP PQ

... (3.28)

(ii ) RMS (a.c.) Load Current Substituting the value of current i from eqn. (3.26) into eqn. (3.7), we get Irms

L 1 R| = M MN 2 S|T

z

z

2 2 Im sin 2 t d ( t )

2 Im sin 2

0

U| O t d ( t ) V P |W PQ

1 2

F I IJ LM FG 1 cos 2 t IJ d ( t ) FG 1 cos 2 t IJ d ( t )OP = G H 2 K H 2 K MN H 2 K PQ m

1 2

z

z

2

0

1 2

After solving we get Irms = or

Irms =

Im

... (3.29)

2

1 2

Vm (R L R f R2 )

(iii ) Form Factor (F.F.) As we have from the definition of Form Factor that F.F. =

RMS value Average value

We have for full wave rectifier, F.F. = or

(I m 2) = (2 I m ) 2 2

F.F. = 1.11

103

DIODE APPLICATIONS

(iv) Average (d.c.) Load Voltage We have from Ohm’s Law, d.c. load voltage,

or

VL

dc

VL

dc

= Idc × RL = =

2

=

2

2 Im

× RL

Vm × RL (R L R f R2 )

1

F GH

Vm R f R2 RL

I JK

If (Rf + R2) 2 C

Where,

RL = Load Resistance = Frequency C = Capacitor L = Inductor

In actual practice we can’t get pure d.c. across the load because some ripples have not yet been filtered, however, in most of the applications it is practically avoidable. The rectified and filtered output for a L-section filter is given in following Fig. 3.17. From the Fig. 3.17, we can see that the filtered output starts traversing from zero instant and readily goes towards negative side i.e., below the constant d.c. level output. The reason behind this phenomenon in that the shunt capacitor when charges, takes the voltage from the d.c. level and the filtered output is diminished. When capacitor discharges during its operation, it adds up the current to the load RL and voltage level gets slightly increased.

126

BASIC ELECTRONICS ENGINEERING & DEVICES VL Rectified output Filtered output

Desired output

VLmax

Vdc

0

2

t

3

Fig. 3.17. Rectified and filtered output voltage waveform for FWR for L-section filter.

The expression for ripple factor for choke input filter can be expressed as : Ripple factor, =

=

or

=

V ac rms V dc

=

2 XC 3 XL

1 2 1 1 . = 3 2C 2L 6 2 2 LC 1 6 2 2 LC

In this class of configuration the output from a rectifier is first fed across the capacitor and named as capacitor input filter. The circuit diagram for capacitor input filter is given below in Fig. 3.18. Basically a -filter is a combination of two capacitors and one inductor. It consist of two stages: (i) Capacitor shunt filter, (ii) Choke input filter.

L +

+ IL Rectifier output

C1

C2

RL

VL

–

–

Fig. 3.18. Circuit diagram of a -Filter.

The Fig. 3.18 consists of a shunt capacitor C1 at the input terminal. An induction L in them connected to C1 in series. This inductor L is again shunted by another capacitor C2 and finally load is connected across the C2. This type of arrangement of filter circuit is often referred to as -filter just because of its shape which resembles to the symbol (Pie). -filter is result of need of higher output voltages at low magnitude loads. To form of -filter, a input capacitor is shunted to a choke input filter. The most important feature of this filter is that it can be used for a half wave rectifier circuit because rectifier output is directly connected to the capacitor. In general, both the capacitors are confined in a single metal container and the metal acts as a common ground for both the capacitors. It is notable here that in filter circuits we employ electrolytic capacitors. The main filtering action is performed by the input capacitor C1 in this case. The filtering action of capacitor used not to be explained again because it has been given

127

DIODE APPLICATIONS

in detail in the beginning of this article. The ripple factor of -filter is product of the ripple factor of capacitor shunt filter stage and ripple factor of choke input filter stage. If compared with L-section filter, -filter have a higher output voltage but the voltage regulation is poor. If any ripples are still present in the output C1, series inductor L and shunt capacitor C2 again smoothen the output and a desirable destabilized d.c. output gets associated with the load. The main disadvantage of -filter is that the output voltage of -filter falls off rapidly with the increase in load.

Comparison between L-section and -Filter 1. In a -filter ripples are less in comparison to shunt capacitor or L-section filter. 2. A -filter requires an inductor of relatively low magnitude than that used in L-section filter. 3. Voltage regulation in case of -filter is poor, so filters are generally employed with fixed loads, while L-section filters suit better for varying loads. 4. PIV is larger in case of a -filter than in case of L-section filter. 5. Current and therefore voltage-regulation for this filter circuit is usually poor. The rectified output and filtered-output in case of capacitor input filter is as given under here : VL

Filtered output Rectified output

VLmax

0

2

3

t

Fig. 3.19. Rectified and filtered output voltage waveforms for a full wave rectifier with capacitor input-filter.

6. -filter provides better d.c. output voltage than that obtained in the case of L-section filter under similar input conditions. Expression for ripple factor is given under here : Ripple factors,

=

=

=

or

V ac rms

V dc

=

2 I dc X C 1 X C 2 V dc X L

2 I dc X C1 X C 2 I dc R L X L 2 RL

.

2 X C1 X C 2 RL X L

1 2 1 1 . = 3 C1 C 2 L C1C 2 LR L

Advantages of -filter (i) Reduction in the ripples. (ii) Increase in the average load voltage. (iii) Simple circuitary.

=

(

Vdc = Idc . RL)

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BASIC ELECTRONICS ENGINEERING & DEVICES

Disadvantages of -filter (i) Ripple factor is dependent on the load. (ii) Regulation is relatively poor. (iii) Diodes-handle large peak currents.

? 1. What is the need of filters ? 2. List different types of filter used. 3. What is basic function of inductor and capacitor in the filter ? 4. What are the advantages of -filter over choke input filter ? 5. Compare different types of filter under different load condition.

Example 1. Design a filter for full wave circuit with LC filter to provide an output voltage of 2.5 V with a load current of 100 mA and its ripple is limited to 3%. Solution : Design of filter means to calculate the value of L and C used in LC filter. Given that,

VL = 25 V and IL = 200 mA

So load resistance

VL RL = I L

=

25 V = 125 200 mA

We know that ripple factor for a LC filter is given by = Given that

1 6 2 2 LC

= 3% = .03 .03 =

.03 =

LC =

1 6 2 ( 2 f )2 LC 1 6 2 4

2

50 2 LC

1 1 = .03 836614.8 25098.4

We know that L =

RL RL = 3.( 2 f ) 3

(

f = 50 Hz)

... (1)

129

DIODE APPLICATIONS

125 3 2 3.14 50 L = .1326 H Ans.

or

L =

or

C =

1 1 = = 300.25 F. .1326 25098.4 3330.46

Ans.

Example 2. (a) Find the output voltage, current and ripple for the circuit shown in Fig. P (3.37). (b) What is the maximum value of RL ? 50 mH

1000 µF

RL = 5

15 Vrms 50 Hz

Fig. P (3.37).

Solution : The circuit of L-C filter is shown in Fig. P (3.37). (a)

Vdc =

Idc = =

=

=

2V m 2 2V m 2 2 15 = = = 13.5 V

V dc RL

=

13.5 = 2.7 A 5

1

=

2

6 2 LC

1 6 2 ( 2 f )2 LC 1

6 2 ( 314 ) . 50 10 3 1000 10 6 2

1 = .024 41.83

Ans.

(b) Peak a.c. current through inductor Im

Vm XL 15 2 2fL

1.35 A.

15 2 2 3.14 50 50 10 3

130

BASIC ELECTRONICS ENGINEERING & DEVICES

Minimum d.c. current to avoid spiking (ILmin) = 1.35 A RLmax =

V dc IL

=

min

13.5 = 10 Ans. 1.35

Example 3. A single phase full-wave rectifier makes use of -section filter with two 10 F capacitors and a choke of 104. The secondary voltage is 280 Vrms with respect to centre tap output. If the load current is 100 mA, determine the percentage ripple. Given that Vdc = 346 V. Assume supply frequency of 50 Hz. Solution : Given

Vrms = 280 V VL max = Vm =

Load current,

2 Vrms =

2 × 280 = 396 V

Idc = 100 mA C1 = C2 = 10 F f = 50 Hz

Ripple factor in case of n-section filter is given by the relation =

or

=

or

RS R |T

2 3

8 C1C 2 LR L

L

V dc 346 3460 I dc 100 10 3

UV |W

2 8 ( 2 50 )

3

10 10

6

10 10 6 104 3460

.00165

Percentage ripple = .165%

Ans.

The circuit, in which the waveform is shaped by removing (or clipping) a certain portion of the input voltage wave above or below a certain specific level, is called clipping circuit, amplitude limiter, or amplitude slicer etc. The clipper circuits are classified as : (i) positive clipper (ii) negative clipper (iii) biased clipper (iv) combination clipper.

A clipper circuit, which clips off the positive half cycles of the input signals, is called the positive clipper. The clipping circuits use the switching property of the diode, similar to the half wave rectifier.

131

DIODE APPLICATIONS

The positive clippers are again classified into two : (a) Positive series clipper and (b) Positive shunt clipper, according to the output taken in the circuit. (a) Positive Series Clippers. The circuit configuration for the positive series clipper is shown in Fig. 3.20. For the positive half cycle of the input signal, the diode is reverse biased and as such no current flows through the circuit. Thus the output voltage vi

v0

Diode

T

T/2

t

vi

R

T/2

v0

T

t

Fig. 3.20. Positive series clipper.

is zero. During the negative half cycle of the input signal, the diode becomes forward biased and current flows through the circuit, thereby the output across the resistor R is half sinusoidal waveform. In this discussion, the diode is assumed to be ideal, but for practical region, reverse saturation current Is flows through the circuit, hence, there also a minute voltage appears across the resistance R. (b) Positive Shunt Clipper. The circuit for the positive shunt clipper is shown in Fig. 3.16. Here, the output is taken across the diode. During positive half input cycle the output is nearly zero, since, the forward biased diode resistance is very small. And during negative half cycle of the input the output is a negative half sinusoidal wave, as shown in Fig. 3.21. vi

vo

R

T/2

T

t

vi

v0

T/2

T

t

Fig. 3.21. Positive shunt clipper.

This is used to clip the negative half of the input signal. Like the positive clipper, these are also classified as series and shunt clipper circuits. (a) Negative Series Clipper. The circuit shown in Fig. 3.22 acts as negative clipper. The input signal applied, appears across the output only for the positive half cycle, because during the negative half cycle of input the diode is reverse biased, and

132

BASIC ELECTRONICS ENGINEERING & DEVICES

no current flows, while for positive half cycle of input, the diode is forward biased and applies very low resistance to the input. In actual practice, some saturated current Is does flows through the diode when diode is reverse biased. vi

vo

T/2

T

vi

t

v0

R

T/2

t

T

Fig. 3.22. Negative series clipper.

(b) Negative Shunt Clipper. The action of the negative shunt clipper is quite to that of negative series clipper as during the positive half input cycle, the diode does not conduct, and hence the entire input voltage appears across the diode. During negative half cycle of the input, diode is forward biased, and current flows through it, but the voltage drop is nearly zero, hence the output voltage is zero, for ideal case.

R vi

v0

Fig. 3.23. Negative shunt clipper.

We can adjust the level of clipping to a certain level by adding a biased voltage in series with the diode or resistor. The positive and negative biased clipper circuits are shown in Fig. 3.24(a) and Fig. 3.24(b), respectively. D R

vi

R

VB

v0

D

vi

+ VB

–

(a) Biased series positive clipper

+ –

(b) Biased shunt positive clipper

Fig. 3.24. Biased clippers.

v0

133

DIODE APPLICATIONS

+ VB t

Fig. 3.25.

In both the circuits, clipping takes place during the positive half cycle, when the input voltage is more than bias voltage VB, as shown in Fig. 3.25. During the half cycle when the input voltage, is more than the bias voltage VB, the diodes conduct and the output voltage is at a constant level in shunt biased clipper. During the negative half cycle the diode does not conduct in series clipper and thus the all the input appears across output. If the battery connection in the above circuit are reversed then the circuit is known as biased negative clipper. In this situation clipping takes place during the negative half cycle when input voltage Vi () VB. This level can be changed by adjusting the bias voltage VB. It is a combination of the biased positive clipper and biased negative clipper when connected together as shown in Fig. 3.26 is called a combination clipper. vi

V0

R +

vm

t – vm

Vi

D1

D2

VB1

VB2

VB1 t

RL V0

VB2 –

(a)

(b)

(c)

Fig. 3.26. Combination clipper.

Here the biasing voltage VB and VB are unequal in magnitude. When the input 1 2 voltage signal goes positive the diode D1 acts as short circuit and D2 is reversed biased; so D1 act as short circuit and D2 as open circuit. The output voltage waveform follows the input voltage wave till it attains a value (+)VB, after which it remains constant since vi > VB till the input voltage is below VB . Now it follows the input waveform. During 1 1 negative half cycle of the input voltage, the o/p voltage waveform follows.

134

BASIC ELECTRONICS ENGINEERING & DEVICES

The input voltage waveform till it attains a value VB since diode D1 act as open 1 circuit and diode D2 as a short circuit, and it remains constant for interval during which input voltage is less than VB and then it follows input then again the process is 2 repeated.

There are numerous clipper applications and it is not possible to discuss all of them. However, in general, clippers are used to perform one of the following two functions. (i) Changing the shape of the waveform. (ii) Circuit transient protection.

A circuit that places either the positive or negative peak of signal at a desired d.c. level is known as a clamping circuit. On the other hand we can say that a clamping circuit (or a clamper) essentially adds a d.c. component to the signal. Clamping circuits broadally divided into two groups namely (i) Positive clamper. (ii) Negative clamper. Fig. 3.27 shows the key idea behind clamping. The input signal is a sine wave having a peak-to-peak value of 20 V. The clamper adds the d.c. component and pushes the signal upwards so that the negative peaks fall on the zero level. vi

vi

+ 10 V + 20 V t

Positive Clamper

– 10 V

O

t

Fig. 3.27.

From figure we see that the shape of original signal has not changed : only there is vertical shift in the signal such a clamper is called a positive clamper. The negative clamper does the reverse i.e., it pushes the signal downwards so that positive peaks fall on the zero level. Things to be remember about the clamper circuit. (i) The clamping circuit does not change the peak-to-peak or rms value of the waveform. From Fig. 3.27, the input waveform and clamped output has the same peak-to-peak value i.e., 20V in this case. (ii) A clamping circuit changes the peak and average value of a waveform. From the above circuit it is clear that input waveform has a peak value of 10V

135

DIODE APPLICATIONS

and average value over a cycle is zero. The clamped output voltage varies between 20V and 0V. Therefore the peak value of clamped output is 20V

20 + 0 = 10V) is 10V. Hence we conclude 2 that a clamper changes the peak value as well as the average value of a waveform. and average value (or d.c. value =

Fig. 3.28 shows a circuit of a positive clamper. Vin

C +V

O

T/2

t

T

Vin

RL

D

Vout

–V

Fig. 3.28. Positive clamper.

Here the input signal is assumed to be a square wave with time period T. The clamped output is obtained across RL. One things should be remember that for the proper operation of the circuit the charging time (c = Rf × C ) where Rf is the forward resistance of the diode and C is the capacitor connected. Between the diode and input supply is small as compared to the discharging time (d = RL × C ). Where RL is the value of the load resistance, this condition is based on the fact that voltage across the capacitor will not discharge significantly during the interval of diode in non-conducting. Therefore the discharging time is deliberately made much greater than the charging time.

Operation (i) During the negative half cycle of the input signal, the diode is forward biased. Therefore the diode behaves as a short circuit (S.C.) as shown in Fig. 3.29. Under this situation the capacitor will charge to V volts very quickly. From figure it is clear that during this interval, the output voltage is directly across the short circuit. Therefore Vout = 0V. I – Vin = V

V

C +

+ S.C.

RL

Vout

– + Vin = V –

+

+ O.C.

RL

Vout

I

–

–

Fig. 3.29.

Fig. 3.30.

136

BASIC ELECTRONICS ENGINEERING & DEVICES

(ii) During the positive half-cycle, the diode is reverse biased and behaves as an open circuit (O.C.). Since the discharging time ( = CRL) is much greater than the time period of the input signal, the capacitor remains almost fully charged to V volts during the off time of diode. Now, applying KVL to the input loop, we have V + V Vout = 0 or

Vout = 2V.

The resulting waveform is shown in Fig. 3.31. It is clear that it is a positively clamped output. Or in other words we can say that input signal has been pushed upward by V volts, so that negative peaks fall on the zero level. Vout

Vin

2V V

T/2

Positive Clamper

t

T

O

t

T/2

–V

Fig. 3.31. Input and output waveform of a positive clamper.

Fig. 3.32 shows the circuit of a negative clamper. The main difference between the positive clamper and negative clamper is that in the case of negative clamper the terminal (p and n) are reversed as compare to the connection of diode terminal in positive clamper. Vin C

V

T/2

T

t

Vin

D

RL

Vout

–V

Fig. 3.32.

Operation (i) During the positive half-cycle of the input signal, the diode is forward biased. Therefore, the diode behaves as a short circuit as shown in Fig. 3.33. The charging time ( = Rf × C) is very small so that the capacitor will charge to V volts very quickly. From the figure. It is clear that, the output voltage is directly across the short circuit. Therefore, Vout = 0 volt.

137

DIODE APPLICATIONS +

V

–

+

+

+

S.C.

–

RL

V

–

+

– V +

Vout

Vout

RL

O.C.

–

–

Fig. 3.33.

Fig. 3.34.

(ii) During the negative half cycle the diode is reverse biased and behaves as an open circuit as shown in Fig. 3.34. Since the discharging time ( = RL × C ) is much greater than the time period of input signal, the capacitor almost remains fully charged to V volts during the off time of the diode. Applying KVL in Fig. 3.34, we have V V Vout = 0 Vout = 2 V The resulting waveform is shown in Fig. 3.35. Vout

Vin +V

T/2

T

t

Negative Clamper

T/2

T

t

–V – 2V

Fig. 3.35. Input and output waveforms of a negative clamper.

? 1. What do you mean by clipper ? 2. List different types of clipper. 3. List the application of the clipper circuit. 4. What do you mean by clamper ? 5. List different types of clamper. 6. What is basic difference between the clipper and clamper circuit ? 7. What are the main features of clamper circuit, with reference to the time constant ? 8. What do you mean by biased clipper ? 9. Compare biased clipper with the positive and negative clipper. 10. Does a clamper circuit changes the peak-to-peak (i.e., rms value) ? Justify.

138

BASIC ELECTRONICS ENGINEERING & DEVICES

Example 1. The negative series clipper shown in Fig. P (3.38). What is the peak output voltage from the circuit ? Assume diode is ideal. Vin + 15 V

D RL

Vin

Vout

– 15 V

Fig. P (3.38).

Solution : When the diode is connected in series with the load, it is called a series clipper. Since it is a negative clipper, it will remove negative portion of the input a.c. signal. During the positive half cycle of the input signal diode is forward biased. As a result, the diode will conduct the output voltage. Fig. P (3.39) shows the output waveform.

Vout + 15 V

t

Vout = Vin = 15 V During the negative half cycle of the input signal, the diode is reverse biased and consequently it will not conduct. Therefore Vout = 0 volt.

Fig. P (3.39).

Example 2. The negative shunt clipper shown below in Fig. P (3.40) has a peak input voltage of + 5V. What is the peak output voltage from this circuit. Vin

R = 2 k +

+ 5V t

Vin

RL = 2 k

D

– 5V

Vout

–

Fig. P (3.40).

Solution : During the positive half-cycle of input a.c. signal, the diode is reverse biased and it will behave as an open circuit. Output voltage in this case can be calculated by applying potential divider method. Vout = =

RL R RL

× Vin

2 × 5 = 2.5 volt. 2 + 2

The output waveform is shown in Fig. P (3.41).

Ans.

139

DIODE APPLICATIONS Vout 2.5 V

t

Fig. P (3.41).

However during the negative cycle the diode will conduct and output equal to zero volt. Example 3. Sketch LR and V0 for the following circuit. Vi

10 k

10 V

+

+

Vi

D1 5.3 V

– 10 V

–

+ –

D2 – +

V0 7.3 V –

Fig. P (3.42).

Solution : We know that when a diode is forward biased then a voltage Vf = 0.7 V drops across the diode (D1 and D2). When a diode in reverse biased it behaves like an open circuit and all the voltage drops across it. To make diode D1 forward biased Vi should be positive and 0.7 V more than 5.3 V. i.e., 6V (5.3 + 0.7). Once D1 is forward biased the current iR flows through 10K resistor and diode D1 and 5.3 V battery. At this time V0 becomes constant at 6V and extra voltage of Vi drops across the resistor. Maximum positive current iR will flow when Vi = + 10V iR

max

=

10 V 6 V = 0.4 mA. 10 K

Similarly when v1 is negative, diode D2 will be forward biased when input voltage Vi is 0.7 V more negative than ( 7.3 V) i.e., ( 7.3 0.7 = 8 V). Once Vi becomes more negative than 8 V, a negative current iR flows in resistance R and V0 becomes constant at ( 8 V) and extra voltage drops across R. Maximum negative current will flow when Vi = 10V iR =

10 V 8 V = 0.2 mA. 10 K

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Required waveforms are shown in Fig. P (3.43) Vi 6V t1

t2

t1

t2

t3

t4

2

t

0 – 8V

6V t3

t4 2

t

0 – 8V iR

0.4 mA

t1

0

t2

t3

t

t4

0.2 mA

Fig. P (3.43).

Example 4. For the given circuit, what will be the output voltage and voltage across R when the input voltage is 12 V ? Vin

R = 1 k

t

– Vin +

– D

+

.7 V

RL = 2 k

– 12 V

Fig. P (3.44).

Solution : During the negative half-cycle of input signal, the diode is forward biased Vout = 0.7 V Voltage across R, or

VR = 12 ( .7) VR = 11.3 V

141

DIODE APPLICATIONS

The waveform for the output voltage is shown below in Fig. P (3.45). Vout

t

– .7 V – 12 V

Fig. P (3.45). Output waveform for the above circuit.

Example 5. Sketch the output waveform for the circuit shown in Fig. P (3.46). It is given that discharging time is much greater than the time period of charging time. Vin

C

+ 10 V

+ D

t

T

T/2

Vin

RL 2V

– 10 V

–

Fig. P (3.46).

Solution : During positive half-cycle of the input signal, the diode is forward biased. The network under this situation is shown below in Fig. P (3.47). C +

+

–

S.C.

10 V

RL Vout

2V –

Fig. P (3.47).

Applying KVL, we have 10 VC 2 = 0 VC = 8 V (Therefore, the capacitor will charge upto 8 V) and

Vout = Vin VC

or

Vout = 10 8 = 2 V.

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BASIC ELECTRONICS ENGINEERING & DEVICES

During the negative half-cycle of the input signal, the diode is reverse biased and the diode will behave as an open circuit as shown below in Fig. P (3.48). 8V + –

–

O.C. RL Vout

Vin = – 10 V 2V +

Fig. P (3.48).

Applying KVL to the loop, we have 10 8 Vout = 0 Vout = 18 V The complete output waveform is shown below in the Fig. P (3.49). Vout

+ 2V

T/2

t

T

– 18 V

Fig. P (3.49). Outwave waveform.

Example 6. Sketch the output waveform for the circuit shown in Fig. P (3.50). It is given that discharging time is much greater than the time period of input wave. Vin C

+ 10 V

+

T/2

T

t

Vin

– +

– 10 V

RL

D

Vout

2V –

Fig. P (3.50).

Solution : During the positive half cycle, the diode is forward biased. The circuit becomes like Fig. P (3.51).

143

DIODE APPLICATIONS +

+

C

–

+ S.C.

Vin = 10 V

RL

Vout

2V –

–

Fig. P (3.51).

Applying KVL to the loop, we have 10 VC + 2 = 0 VC = 12 V and

Vout = Vin VC

or

Vout = 10 12

or

Vout = 2 V

Ans.

During the negative half cycle the above circuit looks like as shown below in Fig. P (3.52). 12 V –

+

+

– O.C.

Vin = 10 V

RL

Vout

2V +

–

Fig. P (3.52).

Applying KVL, we have 10 12 Vout = 0 or

Vout = 22 V The complete output waveform is shown below in Fig. P (3.53). Vout

T/2

T

– 2V

– 22 V

Fig. P (3.53).

t

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BASIC ELECTRONICS ENGINEERING & DEVICES

Example 7. Sketch V0 for the following circuit in Fig. P (3.54). Vi

C

+ 20

t

Vi

V0 – +

R 5V

– 20

Fig. P (3.54). Given circuit.

Solution : First of all that condition is considered when diode will be forward biased and will behave as almost short circuit. This will happen when negative half cycle occurs and circuit behaves like Fig. P (3.55). Capacitor charges upto 15 V C – +

Vi

+

S.C.

– 20 V +

– +

R

V0 = – 5 V

5V

–

Fig. P (3.55). Circuit during negative half cycle.

As the input voltage is opposing the 5 V battery. So capacitor charges in the shown polarity upto Vc = Vi 5 V = 20 5 = 15 volts. During this period diode is almost short circuited hence battery voltage (5 V) appears across the output. So

V0 = 5 V.

Now consider the positive half cycle. Now diode is reverse biased and the circuit is shown in Fig. P (3.56). Diode is open circuited, battery is disconnected. Input voltage Vi and capacitor voltage (due to charging during previous negative half cycle) come in series and output voltage. V0

=Vi + Vc = 20 + 15 = 35 volts.

145

DIODE APPLICATIONS Capacitor charged previous half cycle 15 V – + + O.C.

+ Vi

20 V –

– +

R

V0 = 35 V

5V

–

Fig. P (3.56). Circuit during positive half cycle.

Waveform for input and V0 is shown in Fig. P (3.57). Vi + 20

– 20 V0 + 35

–5

Fig. P (3.57).

4 We have already discussed about rectifiers and PN-junction diode. Now, we shall discuss the Breakdown diodes, which are used for specific purpose like voltage regulation, short circuit protection etc. Diodes which are designed with adequate powerdissipation capabilities to operate in the Breakdown region may be employed as voltagereference or constant-voltage devices. Such diodes are known as avalanche, breakdown or zener diodes.

The Breakdown mechanism of a zener diode made up of a silicon PN-junction devices, differs from a rectifier diode, in the sense, that it is operated in the reverse break down region (i.e., when the PN-junction is highly reverse biased). The reverse-voltage characteristic of a semiconductor diode, including the Breakdown region is shown as in Fig. 4.1. Diodes which are designed with adequate power-dissipation capabilities to operate in the breakdown region may be employed as voltage-reference or constant-voltage devices.

IF

VZ

Breakdown

VF

VR (Reverse bias region)

IR

(Forward bias region)

IZ

Fig. 4.1. The V-I characteristic of a zener diode.

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Comp-1/Laxmi-5/Computer/Revision/Belec-4—10.5.07

147

BREAKDOWN DIODES

Fig. 4.2 shows the symbol of zener diode which is quite different from the simple diode. K

A

Fig. 4.2. Symbol of zener diode.

Two mechanism of diode Breakdown for increasing reverse voltage are namely : (i) Zener Breakdown, and (ii) Avalanche Breakdown. One thing should be always kept in mind that the Zener Breakdown and avalanche Breakdown are usually differentiated on the basis of doping concentration. Zener Breakdown occur when the PN-junction is highly doped while avalanche Breakdown occurs only when the PN-junction is very lightly doped. The Zener Breakdown occurs when the electric field across the junction, produced due to reverse voltage is sufficiently high. This electric field exerts a force on the electrons in the outer most shell. This force is so high that the electrons are pulled away from their parent nuclei and become free carriers. This ionization, which occurs due to the electrostatic force of attraction is known as zener effect. Also known as high-field emission. One thing should be always kept in mind that zener effect will occur only when a diode is heavily doped. Because when the diode is heavily doped depletion layer becomes very narrow. Due to this the electric field across the depletion layer is very intense, when the field strength reaches approximately 300,000 V/cm. It causes an increase in the number of free carriers and hence an increase in the reverse current. The zener diodes, with Breakdown voltages of less than 6 V, operate predominantly in Zener Breakdown. However, the Breakdown voltages greater than 6 V, operates predominantly in Avalanche Breakdown.

A thermally generated carrier falls down the junction barrier and acquires energy from the applied potential. This carriers collides with a crystal ion and imparts sufficient energy to disrupt a covalent bond. In addition to the original carrier, a new electronhole pair has now been generated. These carriers may also pick up sufficient energy from the applied field, collide with another crystal ion and create still another electronhole pair. This cumulative process is referred to as avalanche multiplication. It results in large reverse saturation currents and the diode is said to be in the region of avalanche breakdown. However, Zener Breakdown does not involve collisions of carriers with the crystal ions as does avalanche multiplication.

The temperature coefficient of any device may be defined as the percentage in reference voltage per centrigate degree change in diode temperature. This coefficient may be either positive or negative and will normally be lie in the range ± 0.1 percent /C.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Here with reference to the Breakdown diode, if the reference voltage (i.e., applied reverse voltage) is above 6 V, where the physical mechanism involved is avalanche multiplication, the temperature coefficient is positive, however below 6 V, where true Zener Breakdown is involved, the temperature coefficient is negative. Explanation of why Zener Breakdown have negative temperature coefficient while Avalanche Breakdown have positive temperature coefficient ? A junction having a narrow depletion-layer width and hence high field intensity, will breakdown by the zener mechanism. An increase in temperature increases the energies of the valence electrons, and hence makes it easier for these electrons to escape from the covalent bonds. Less applied voltage is therefore required to pull these electrons from their positions in the crystal lattice and convert them into conduction electrons. Thus, the Zener Breakdown voltage decreases with temperature i.e., negative temperature coefficient. However, if a diode having very highly doping which gives a broad depletion layer, and therefore low field intensity, will break down by avalanche mechanism. In this case, we rely on intrinsic carriers to collide with valence electrons and create avalanche multiplication. As the temperature increases, the vibrational displacement of atoms in the crystal of grows. This vibration increases the probability of collisions with the lattice atoms of the intrinsic particles as they cross the depletion width. The intrinsic holes and electrons thus have less of an opportunity to gain sufficient energy between collisions to start the avalanche process. Therefore, the value of the avalanche voltage must increases with increased temperature.

We have already discussed that a zener diode is operated in the reverse-bias region. That is why we shall examine its characteristic in this region only. Fig. 4.3 shows the reverse characteristic of a zener diode.

VR (Volts)

VZ

O

A

IZK

Breakdown or Regulation region B

Regulated range of IZ (mA) current IZM

Fig. 4.3. Reverse characteristic of a zener diode.

149

BREAKDOWN DIODES

It may be noted from above figure that as the reverse voltage (VR) Starts to increase the reverse current (usually called zener current, IZ ) remains negligibly small up to the ‘Knee’ of the curve (Point A in Fig. 4.3). At this point, the effect of Breakdown process begins, at this point, the voltage is called zener Breakdown voltage or simply zener voltage VZ , remains essentially constant. This ability of diode is called regulating ability and is important feature of zener diode. It maintains, an essentially a constant voltage across its terminals over a specified range of zener current values. Two important point about the characteristics of zener diode : 1. There is a maximum value of zener current designated as IZM or IZ (max) above which diode may be damaged. The value of this current is given by the maximum power dissipation of zener diode. As long as the maximum power dissipation is not exceeded the diode will not be damaged. 2. There is a minimum value of zener current called breakover current designated as IZK or IZ (min) which must be maintained in order to keep the diode in breakdown (or regulation). When the current is reduced below the knee of the curve, the voltage changes drastically and the regulation is lost.

Fig. 4.4 (a) shows a ideal approximation of a zener diode in reverse breakdown. It shows that a zener diode is simply equivalent to a battery having a voltage equal to the zener voltage (VZ ). Fig. 4.4 (b) shows a practical equivalent circuit of zener diode. This circuit shows that a zener diode is equivalent to a battery with voltage (VZ ), in series with a resistance (RZ ) called zener resistance, also called dynamic resistance or a.c. resistance. VR (Volts) VZ

0

rZ + –

VZ

VZ

IZ (mA)

+ –

Q

VZ

IZ P

(a) Ideal zener equivalent diode circuit

(b) Practical zener diode equivalent circuit

(c) Reverse V.I. characteristic curve illustrating zener resistance

Fig. 4.4.

In order to calculate the value of zener resistance, consider any two points P and Q on the reverse V-I curve as shown in Fig. 4.4 (c).

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BASIC ELECTRONICS ENGINEERING & DEVICES

Let,

VZ = Change in the values of zener voltage between the points P and Q IZ = Change in the values of zener current at the corresponding points

Now, the zener resistance is given by the relation : rZ =

VZ IZ

... (4.1)

Any zener diodes are generally specified in terms of four factors namely : (i) Zener voltage (VZ ) (ii) Maximum power dissipation (PZM or PD (max)) (iii) Breakover current (IZK ), and (iv) Zener resistance (rZ ). Zener diodes are available in market with Breakdown voltages ranging from 1.8 V to 2000 V. The power dissipation of a zener diode is the product of breakdown voltage (VZ ) and reverse current (IZ ). Mathematically, the power dissipation, PZ = VZ × IZ

... (4.2)

The maximum value of power dissipation, which a zener can dissipate, without failure is called power rating and is designated by PZM. The zener diodes are available with power rating from 150 mW to 50 W. The value of maximum zener current is given by the relation, IZM = where,

PZM VZ

... (4.3)

PZM = Maximum power rating of zener diode, and VZ = Breakdown voltage.

IZM or IZ(max) = Max. value of zener diode current.

Fig. 4.5 shows a circuit in which zener diode is used to regulate the voltage across RL against changes due to variations in load current and supply voltage. IR IL IZ

R V

+ –

+ VZ

RL VL

–

Fig. 4.5. Application of zener diode as a shunt regulator.

151

BREAKDOWN DIODES

Working : The source voltage V and resistor R are selected, so that, initially, the diode is operating in the breakdown region. Here, the diode will now regulate the load voltage against variations in load current and again variations in supply voltage changes in diode voltage. In order to better understanding. Consider : Case 1 : When the input voltage increases. Since, the zener diode is equivalent to a battery, VZ as shown in Fig. 4.5. It is clear that output voltage remain constant at VZ (VL). The excess voltage is dropped across the series resistance R. This will cause an increase in the value of total current I. The zener will conduct the increase of current in I while the load current remains constant. Hence, output voltage VL remains constant irrespective of the changes in the voltage V. Case 2 : When the input voltage (V ) is constant but the Load Resistance RL decreases. This will cause an increase in load current. The extra current cannot come from the source because drop in R will not change as the zener is within its regulating range. The additional load current will come from a decrease in zener current IZ . Consequently, the output voltage stays at constant value. Voltage drop across, R = V VL Current through R, I = IZ + IL R= where,

V VL IZ IL

V = Input voltage

Moreover, as load current or supply voltage changes, the diode current will accommodate itself to these changes to maintain a nearly constant load voltage. The diode will continue to regulate until the circuit operation requires the diode current to fall to IZK, in the neighbourhood of the knee of the diode volt-ampere curve. The upper limit on diode current is determined by the power-dissipation rating of the diode. A zener diode is chosen whose breakdown voltage VZ is the same as output voltage VL. Regulation takes place only for Vi > VZ . IZ (max) =

V i max V Z I L min R

IZ (min) =

V i min V Z I L max R

Rmin =

V i min V Z I Z max I L min

Rmax =

V i min V Z I Z min I L max

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BASIC ELECTRONICS ENGINEERING & DEVICES

Other Applications of Zener Diodes (a) As a fixed reference voltage in transistor biasing circuit. (b) As peak clippers or limiters in waveshaping circuits. (c) For meter protection against damage from accidental applications.

Advantages of Zener Diode Regulator It is simple circuit, light weight, more reliable and provides regulation over a wide range of current.

Disadvantages of Zener Diode (a) As there is power dissipation in series resistor and the diodes, it results in poor efficiency. (b) The stablised output is determined by the zener breakdown voltage and cannot be varied.

? 1. What do you mean by breakdown diode ? 2. List the different types of breakdown diode. 3. Describe the physical mechanism for zener breakdown diode. 4. What are the various breakdown mechanism in junction diode ? Give examples of at least one type, for each of these mechanism and elaborate their applications. 5. Qualitatively explain how mobility affects conductivity. 6. Distinguish between zener breakdown and avalanche breakdown. 7. What is the main application area of a zener diode ? 8. Breakdown diode with a breakdown voltage greater than 5 V generally have a positive temperature coefficient but those with lower breakdown voltage have a negative temperature coefficient. Do you agree with the statement ? Justify.

Example 1. When the reverse current in a particular zener diode increases from 20 mA to 30 mA, the zener voltage changes from 5.6 V to 5.75 V. What is the resistance of device ? Solution : Given : IZ = (30 20) mA = 10 mA = 10 × 103 A and

VZ = 5.75 5.6 = .15 V

153

BREAKDOWN DIODES

We know that the resistance of the zener diode, rZ =

VZ IZ 015 .

or

rZ =

or

rZ = 15 . Ans.

10 10 3

Example 2. A 4.7 V zener has a resistance of 15 , what is the terminal voltage, when the current is 20 mA ? Solution : Given :

VZ = 4.7 V rZ = 15 IZ = 20 mA VZ = ? A IZ = 20 mA 15 = rZ

VZ + 4.7 V = VZ –

B

Fig. P (4.1).

The terminal voltage VZ is given by relation : VZ = VZ + IZ rZ or

VZ = 4.7 + 20 × 103 × 15

or

VZ = 4.7 + 300 × 103

or

VZ = 4.7 + .3

or

VZ = 5 V. Ans.

Example 3. A zener diode has a dc power dissipation rating of 500 mW and a zener voltage rating of 6.8 V. What is the value of IZM for the device ? Solution : Given :

PZM = 500 mW = 500 × 103 W VZ = 6.8 V

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BASIC ELECTRONICS ENGINEERING & DEVICES

We know that the maximum current of zener diode is given by relation, IZM =

=

PZM VZ

500 10 3 6.8

= 73.5 × 103 A = 73.5 mA. Ans. NOTE :

One thing always remember that while designing circuits using zener diodes, we must sure that the current through the zener diode does not exceed the IZM value.

Example 4. A motorola’s IN754 zener diode is being operated at 85C. What is the maximum power dissipation for the device ? Assume that the dc power dissipation rating of the device is 1500 mW and the derating factor is 3.33 mW/ C above 60C. Solution : Given :

PZM = 1500 mW, and

Derating factor = 3.33 mW We know that so long the zener diode is being operated at or below 60C, its maximum power dissipation is 1500 mW. However, if it is so operated at 85C, its maximum power dissipated will be below 1500 mW, because of the excessive heat generated inside. We know that total derating value = Derating factor (85 60) = 3.33 × (85 60) = 83.25 mW Maximum power dissipation for the device, PZM = 1500 83.25 = 1416.75 mW. Ans. Example 5. For the zener diode network of Fig. P (4.1), determine VL, VR, IZ and PZ . +

VR

–

R

+ 1 k Vi = 16 V

IZ VZ = 10 V

PZM = 30 mW

Fig. P (4.2).

RL

VL

1.2 k

–

155

BREAKDOWN DIODES

Solution : NOTE : Before solving this type of problem, consider two situation : Situation 1 : Applying kVL to the given Fig. P (4.3). R

Vi

+

+ –

VZ

RL VL

–

Fig. P (4.3). Where the application of voltage divider rule, we get, VL =

R L .V i

bR

L

R

g

If VL VZ , the zener diode is “on” and the equivalent model of Fig. P (4.2) can be substituted. VL = VZ

i.e.,

Situation 2 : If VL VZ , the diode is “off ” and the open circuit equivalent as shown below in Fig. P (4.4) is substituted. R

+ VZ –

Vi

+ VL

RL

–

Fig. P (4.4). In short, we can quickly memorize as shown below :

+

+

+

VZ

–

–

“On”

VZ

VZ –

“Off ”

156

BASIC ELECTRONICS ENGINEERING & DEVICES

Now, from Fig. P (4.1), applying potential divider we get, VL =

R L .V i R RL

=

b g b1 k + 1.2 kg 12 . k 16 V

= 8.73 V

Since, V = 8.73 V is less than VZ = 10 V, the diode is in “off ” state. So, in order to calculate the parameter, substitute the open circuit equivalent. VL = 8.73 V VR = Vi VL = 16 8.73 = 7.27 V IZ = 0 A PZ = VZ IZ = VZ . 0 = 0 W. Ans. Example 6. Determine the range of value of Vi that will maintain the zener diode in the ‘on’ state as shown in Fig. P (4.5). +

R

IR

220 Vi

IL

IZ RL

VZ = 20 V

+

1.2 k VL

IZM = 60 mA –

–

Fig. P (4.5).

Solution : For fixed values of RL, the voltage Vi must be sufficiently large to turn the zener diode on. The minimum turn-on voltage Vi = Vi (min) is determined by relation, VL = VZ =

RL Vi b min g RL R

bR

L

R

g

or

Vi (min) =

or

Vi (min) =

or

Vi (min) = 23.67 V

RL

a1. 2

VZ

. 220 1. 2

f

20

However, the maximum value of Vi is limited by the maximum zener current IZM. Since,

IZM = IR IL IR (max) = IZM + IL

So,

Vi (max) = VR (max) + VZ

or

Vi (max) = IR (max) . R + VZ

or

Vi (max) = (IZM + IL) . R + VZ

157

BREAKDOWN DIODES

=

FG 60 mA + H

20 V 1.2 k

IJ . (0.22 k) + 20 K

= 16.87 + 20 = 36.87 V. Ans. Example 7. Check whether the zener diode of Fig. P (4.6) operating in the Breakdown region. 270

+ +

+

18 V

10 V

–

1 k

VL

– –

Fig. P (4.6).

Solution : The zener diode will be operated in the Breakdown region if VL > VZ . Applying potential divider method, we get, VL = or

1 k 270 + 1 k

b

g

18 V

VL = 14.2 V Since,

VZ (14.2 V) > VZ (10 V)

Hence, the zener diode is operating in the Breakdown region.

Ans.

Example 8. Calculate the value of zener current as shown in Fig. P (4.7). 250

A

B

+ Power supply

IR 18 V

+ –

IZ 10 V

IL 1 k

–

Fig. P (4.7).

Solution : From figure, IR =

18 10 8 = = 32 mA 250 250

IL =

10 = 10 mA 1 k

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BASIC ELECTRONICS ENGINEERING & DEVICES

Apply KCL at node B. We get, IR = IL + IZ 32 = 10 + IZ IZ = 32 10 = 22 mA. Ans.

or

Example 9. Find the current flowing through the resistance R as shown in Fig. P (4.8). R

I

IL = 1 mA

= 10 k Vi = 20 V

+

+ VZ = 10 V

–

RL = 10 k

VL

–

Fig. P (4.8).

Solution : First of all we will calculate VL VL =

FG 10 IJ H 10 10 K

Vi =

10 20 = 10 V 20

Since, VL VZ = 10 V, therefore, the zener diode is on. So, I =

VI V Z R

=

b20 10g V 10 k

= 1 mA. Ans.

Example 10. (a) Determine VL , IL , IZ and IR for the network shown in Fig. P (4.9), if RL = 300 . (b) Determine the value of RL that will establish maximum power conditions for the zener diode. (c) Determine the minimum value of RL to ensure that the zener diode is in the “on” state. R IR Vi = 20 V

+

+

+ –

IL

IZ

200 10 V = VZ

– Pz (max) = 400 mW

Fig. P (4.9).

Solution : Given :

RL = 300

(a)

VL =

300 20 300 200

RL

VL –

159

BREAKDOWN DIODES

or

VL =

3 20 = 12 V 5

Since VL > VZ , it means zener diode is “on”. So,

VL= VZ = 10 V IL =

VL 10 = = 33.333 mA 300 RL

IR =

Vi V Z R

=

20 10 10 = = 50 mA 200 200

IZ = IR IL IZ = 50 33.33

or

IZ = 16.67 mA.

Ans.

(b) In order to ensure that the zener diode is in the “on” state. VL VZ

RL V I VZ RL R RL 20 10 R L 200 2 RL RL + 200 RL 200 (RL) min = 200 . Ans. NOTE :

From above result we conclude that the minimum value of RL to ensure that the zener diode is in the “on” state is equal to the value of R.

Example 11. The circuit diagram of a regulated power supply is shown in Fig. P (4.10). The zener diode characteristic is given by VZ = 8 + RIZ , where VZ and IZ are the diode voltage and current respectively and RL = 10 ohms. If the maximum rated current of zener diode is 0.2 A. Calculate the minimum value of Ri . Ri IZ

Unregulated voltage = 15 V

VZ

Fig. P (4.10).

RL

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BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : For maximum current of 0.2 A, the voltage of zener diode is, VZ = 8 + RIZ = 8 + 10 × 0.2 = 10 V This maximum current is drawn where the regulated voltage of 15 V is regulated to 10 V. So, the load current is

10 = 1 A. 10 = 0.2 A

IL (min) = Given :

IZ (max)

so,

Ri (min) =

=

Vi b max g V Z IZ

bmax g I L bmin g

15 10 5 = = 4.7 . 0 . 2 1. 0 1.2

Ans.

Example 12. For the circuit of the following figure, find (a) the output voltage, (b) voltage drop across RS and (c) the current through the zener diode. +

12 V

RS = 5 K

VZ = 8 V

+

10 K

–

RL

V0

–

Fig. P (4.11).

Solution : While trouble shooting Zener regulator circuits, the first thing to check for its breakdown operation of the zener diode. Because of the load resistor, the Thevenin voltage driving the zener diode is less than the source voltage. See a zener regulator act as below: RS = 5 K +

VS = 12 V + –

VZ = 8 V

RL = 10 K

VL = V0

–

Fig. P (4.12).

161

BREAKDOWN DIODES

Here, output voltage, VL =

RL Rs R L

or

VL =

10 12 5 10

or

VL = 8 V

VS

For breakdown operation the zener diode must be greater than VZ . But, here,

VL = VZ = 8 V

So, zener diode will not be in the breakdown condition. Hence, no current will flow through it and it will behave as open circuited as shown in following circuit. RS = 5 K +

VS = 12 V + –

RL = 10 K

V0 = VL

–

Fig. P (4.13).

So, (a) Output voltage V0 = VL = 8 V (b) Voltage drop across RS = VS V0 = 12 8 = 4 V. (c) Current through zener diode IZ = 0. Ans. Example 13. Determine VZ , IZ , PZ for the following circuit : RS = 1 K + IZ VS = 16 V

IL RL = 1.2 K

VZ = 10 V Pzm = 300 mW

V0 = VL

–

Fig. P (4.14).

Solution : First of all we will check whether the zener diode conduct or not. VL =

RL V Rs R L s

162

BASIC ELECTRONICS ENGINEERING & DEVICES

1.2 16 1 1.2

or

VL =

or

VL = 8.72 V

as

VL < VZ , so diode will not conduct. No, current will flow through diode. IZ = 0

i.e.,

PZ = 0 V0 = VL = 8.72 V. Ans. Example 14. For the circuit shown in Fig. P (4.15), determine VL , IL , IZ and IR with RL = 200 ohm and RL = 200 ohm. Comment on the operation of the circuit. Vin = 20 V, Vz = 10 V, PZ, max = 400 mW and RS = 220 ohm. RS

IR

+ IZ

IL RL

Vin

VL

–

Fig. P (4.15).

Solution : When RL = 200. Checking for the operation of zener diode. The diode is open circuited and VL is calculated VL =

RL 200 V = 20 = 9.52 volts. RS R I in 220 200

as this value VL < Vz i.e., 10 volts. Zener breakdown cannot occur and diode will remain in off state so IZ = 0

V in 20 20 V Amp. = = 420 RS R L 220 + 200 ohms

and

IR = IL =

so,

IR = IL = 47.62 m amp. VL = 9.52 volts. IZ = 0. When RL = 50 ohm.

163

BREAKDOWN DIODES

Checking for the operating of zener diode

RL 50 V in = 20 = 3.7 volts RS R L 220 50

VL =

Which is less than VZ = 10 volts. So, zener diode remains off. Hence, IZ = 0 and

IR = IL =

V in 20 = = 74.1 m amp. Ans. RS R L 220 50

IZ = 0. Ans. VL = 3.7 volts. Ans. Example 15. The circuit in Fig. P (4.16) shows a zener-regulated d.c. power supply. The zener diode voltage is 15V. The minimum value of RL down to which the output voltage remains constant is 27 +

I 15V

24 V

RL

–

Fig. P (4.16).

Solution : From given Fig. P (4.16) VZ = 15 V I =

RL(min) =

24 V Z 27

=

24 15 1 = A 27 3

VZ 15 = = 45 Ans. I L (max) 1/ 3

Example 16. The 6V zener diode shown in Fig. P (4.17) has zero zener resistance and Knee current of 5 mA. The minimum value of R so that voltage across it does not fall below 6V. 50

10 V

6V

Fig. P (4.17).

R

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BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : Given that IZ(min) = 5 mA = Knee current from Fig. P (4.17) current in 50 resistance, say I I =

10 V Z 50

=

4 10 6 = 50 50

I = 80 mA

I = IZ + IL IR(max) = I – IZ(min) = 80 – 5 = 75 mA

Now,

R =

VZ 6V = = 80 . Ans. I R(max) 75mA

Example 17. In the voltage regulator shown below in Fig. P (4.18). The power dissipation in the zener diode will be 150

VZ = 15V RZ = 0

50 V +

75 K

Fig. P (4.18).

Solution : From Fig. P (4.18), we have RZ = 0. So, in order to calculate the power dissipation across the zener diode. We must calculate the current flowing in zener diode i.e., IZ . And IZ is given by Relation.

Vth IZ = R where, Vth = therenin voltage; th Rth = therenin resistance From Fig. P (4.18) Vth = 50 ×

75K 50 = V (75 150)K 3

Rth = (150 75)K = 50 K IZ =

50 / 3V = 0.33 mA. 50K

Now, Power dissipation, PZ = VZ · IZ or

PZ = 15 × 0.33 = 0.5 mW

Ans.

165

BREAKDOWN DIODES

Example 18. In the voltage regulator circuit shown below in Fig. P (4.19). The power rating of zener diode is 400 mW. Calculate the value of RL that will establish maximum power in zener diode. 222 I

IZ

IL VZ = 10V RZ = 0

20 V +

RL

Fig. P (4.19).

Solution : From Fig. P (4.19)

P IZ(max) = V Z or

IZ(max) =

400mW = 40 mA 10V

I = IZ + IL =

20 – V Z 222

=

20 – 10 = 45 mA 222

IL(min) = 45 – IZ(max) = 45 – 40 = 5 mA Now, RL =

VZ I L (min)

=

10V = 2k. 5mA

Example 19. In the voltage regulator circuit shown below in Fig. P (4.20). The zener diode current is to be limited to the range 5 iz 100 mA. 12 k I 6.3V +

IZ

IL VZ = 4.8V RZ = 0

RL

Fig. P (4.20).

Calculate (i) The range of possible load currnet. (ii) The range of possible load resistance. (iii) The power rating required for load resistance.

166

BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : From Fig. P (4.20) I =

6.3 – V Z 12 k

=

1.5 V 0.5 6.3 – 4 .8 = = mA = 125 mA 12 k 12 k 4

The range of IL : when, IZ = 5 mA IL = I – IZ = 125 – 5 = 120 mA when, IZ = 100 mA IL = 125 – 100 = 25 mA Hence the range of IL is 25 mA IL 120 mA Ans. (c) The range of possible load resistance RL = IL·VZ RL = 25 × 10–3 × 4.8 = .120 RL = 120 ×

10–3

× 4.8 = .576

(when IL = 25 mA) (when IL = 120 mA)

.120 RL .576 Ans. (a) Power rating, PZ(max) = IL(max) × VZ = 120 × 10–3 × 4.8 = 5.76 mW. Ans.

5 The transistor was invented in 1948 by John Bardeen, Walter Brattain and William Shockley at Bell Laboratory in America. The invention of transistor completely revolutionized the electronic industry. Since then, there has been a rapidly expanding effort to utilize and develop many types of semiconductor devices such as FET, MOSFET, UJT, SCR etc. transistors have replaced bulky vacuum tubes in performing many jobs. When a third doped element is added to crystal diode in such a way that two PN-junctions are formed, the resulting device is known as transistor. The transistor— an entirely new type of electronic device is capable of achieving amplification of weak signals.

A transistor consists of two p-n junctions formed by sand-wiching either p-type or n-type semiconductor between a pair of opposite types. There are two types of transistors possible namely : (i) n-p-n transistor (ii) p-n-p transistor. An n-p-n transistor is composed of two n-type semiconductors separated by a thin section of p-type as shown in Fig. 5.1(a). However, a p-n-p transistor is formed by two p-sections separated by a thin section of n-type as shown in Fig. 5.1(b). n

p

n

p

Fig. 5.1(a). n-p-n transistor.

n

p

Fig. 5.1(b). p-n-p transistor.

Some points regarding transistor : (1) There are two PN-junctions. Therefore a transistor may be regarded as a combination of two diodes connected back to back. (2) The middle section is very thin layer. This is the most important factor in the function of a transistor.

Meaning of the Transistor As the transistor has two PN-junction. As discussed latter, one junction is forward biased and the other junction is reversed biased. The forward biased junction has a low 167

Comp-1/Laxmi-5/Computer/Revision/Belec-5—10.5.07

168

BASIC ELECTRONICS ENGINEERING & DEVICES

resistance path whereas a reverse biased junction has a high resistance path. The weak signal is introduced in the low resistance, circuit and output is taken from the high resistance circuit. Therefore, a transistor transfers a signal from a low resistance to high resistance. The prefix ‘trans’ means the signal transfer property of device while ‘istor’ classifies it as a solid element in the same general family with resistors. Transfer + Resistor = Transistor

i.e.,

A transistor is basically a silicon or germanium crystal containing three separate regions. Transistor may be either npn-type or pnp-type. Fig. 5.2(a) shows an npntransistor. It has three region namely : (1) Emitter (2) Base (3) Collector The section on one side is the Emitter and the section on the opposite side is the collector. The middle section is called the base and forms two junctions between the emitter and the collector. One junction is between the emitter and the base, and is called emitter-base junction or simply the emitter junction. The other junction is between the base and the collector, and is called the collector base junction, or simply collector junction. Thus, a transistor is like two PN-junction diode connected back-to-back. n

p

C

n B

E Emitter

Collector

E

Base

(a) Junction transistor npn-type. p

n

(b) Symbol of npn-transistor. C

p B

Emitter

Collector

E

Base

(c) Junction transistor pnp-type.

(d) Symbol of pnp-transistor.

Fig. 5.2. Junction transistor of npn- and pnp-type.

Now we will discuss in brief about : (a) Emitter. The section on one side of the junction that supplies charge carriers (i.e., electrons or holes) is called the emitter. The emitter is always forward biased with respect to base so as to supply a large number of majority carriers. Fig. 5.3 shows the

169

BIPOLAR JUNCTION TRANSISTOR

arrangement of forward biased for npn as well pnp-transistor. In the case of npntransistor forward biased, emitter supplies electrons to the junction whereas in the case of pnp-transistor forward biased emitter supplies holes to the junction. It may be noted that emitter is a heavily doped region. Emitter n

Forward Biased Junction

Base Collector p

Emitter

n

Reverse Biased Junction

p

Forward Biased Junction

Base Collector n

p

Reverse Biased Junction

Fig. 5.3. Forward and reverse bias in different types of transistor.

(b) Base. The middle section which forms two pn-junctions between the emitter and collector is called the base. The base-emitter junction is forward biased, allowing low resistance for the emitter circuit. The base-collector junction is reverse biased and provides high resistance in the collector circuit. The base is very lightly doped and very thin so that all charge carriers easily passed through the junctions. (c) Collector. The section on the one side of junction that do the job of collecting or gathering these charge carriers (electrons or holes) from the base is called collector. The function of collector is to remove charges from its junction with the base. The collector is always reversed biased with respect to base. The doping of the collector is between the heavy doping of the emitter and light doping of the base. It may be noted that the collector of a transistor is always larger than the emitter and base of a transistor. Reason why collector region is larger than that of the emitter and base : As we know that the main function of collector is to collect the charge carriers in the collector region. Because due to the interaction of the charge carrier, the collector region becomes heat up, as all the heat dissipates through this region and the transistor may burn out. So, in order to save the transistor from the burning the collector is always larger than that of the emitter and base region.

As we have already discussed that a transistor has two junctions emitter-base junction and collector-base junction. There are four possible ways of biasing these two junctions. Table 5.1 shows all four combination with their region (will be discussed later) of operation. Table 5.1 S.No.

Emitter-Junction

Collector-Junction

Region of Operation

1. 2. 3.

Forward-biased Forward-biased Reverse-biased

Reversed-biased Forward-biased Reverse-biased

Active Saturation Cutoff

4.

Reverse-biased

Forward-biased

Inverted

170 NOTE :

BASIC ELECTRONICS ENGINEERING & DEVICES The modes of operation are the same for both NPN and PNP transistors. However, in PNP transistor biasing (which is discussed later), the polarity of battery voltages are opposite to that of NPN transistor.

Operation (Working) of an NPN Transistor Fig. 5.4 shows an NPN transistor biased in forward-active mode i.e., the emitter base junction of a transistor is forward biased while the collector-base junction of a transistor is reverse biased. The emitter-base junction is forward biased only if VEB is greater than barrier potential or cut in voltage which 0.7 V for silicon and 0.3 V for Germanium transistors. The forward bias on the emitter-base junction causes the free electrons in the N-type emitter to move towards the base region. This constitutes the emitter current (IE). Due to the forward biased of the junction, the barrier potential is reduced. Holes move from base to the emitter region. Thus the resulting current consists of electrons and holes. However, it may be noted that only the electron current is useful in the action of the transistor as the doping of the base region is more lightly than emitter region which gives very low quantity of hole current. N

P

N

1

E

C

5 2

IE

3

4 7

6

IC

8 9 B

+

– VEE

IB

+

– VCC

Fig. 5.4. Operation of an npn-transistor.

From Fig. 5.4 we see that electrons 1, 2, 3 crossing from the emitter to the base, and hole 4, 5 from the base to the emitter. The total sum of these charge-carrier movements constitutes the emitter current IE electrons 1, 2, 3 are injected by the emitter into base. The ratio of the electron current to the total emitter current known as emitter injection ratio as the emitter efficiency. Typically this ratio is equal to 0.995. Once the electrons are injected by the emitter into the base, now these electrons become the minority carriers in the base region. These electrons do not have separate identities from those which are thermally generated in the base region itself. As the base region is very narrow and very lightly doped, because of this, most of the minority carriers (electrons) travelling from the emitter end of the base region to its collector end do not recombine with holes in this journey. Only a few electrons (like 7) may recombine with holes (like 8). The ratio the number of electrons arriving at collector to the number of emitted electrons is known as the base transportation factor. Typically its value is 0.995. Referring to the Fig. 5.4 movement of hole (like 6) from the collector region and electron 9 from the base region constitutes leakage current, ICBO. Actually, the number of electrons and holes crossing the emitter-base junction is much more than the number

171

BIPOLAR JUNCTION TRANSISTOR

of electrons and holes crossing the collector-base junction. The difference of these two currents in the base region makes the base current IB. The collector current is less than the emitter current, there are two reasons for this. Firstly a part of emitter current consists of holes that do not contribute to the collector current. Secondly, not all the electrons injected into the base are successful in reaching the collector. The ratio of collector current to the emitter current is called the d.c. alpha (dc) of the transistor. Relation between different currents in a transistor. The emitter current is equal to the sum of the collector and base currents, i.e., IE = IB + IC NOTE :

... (5.1)

(i) The emitter current of a transistor consists of two components namely base current and collector current. The base current is about 2% of the emitter current, while collector current is about 98% of the emitter current. (ii) The collector current is mainly due to the electrons injected from the emitter. However, there is another small component of collector current due to thermally generated carriers. This small value of collector current is called leakage current or reverse saturation current.

There are three types of transistor configuration possible, namely : (i) Common base configuration (CB) (ii) Common emitter configuration (CE) (iii) Common collector configuration (CC) Here it is interesting to note that transistor may be connected in any one of the three configuration stated above. Now, we will discuss these three configuration briefly one by one. (i) Common Base (CB) Configuration : The circuit diagram of npn-transistor and pnp-transistor for common base configuration is shown below in Fig. 5.5(a) and (b) respectively. In this case the input is connected between emitter and base. However output is taken across collector and base. Thus the base of transistor is common to both input and output circuits and hence the name common base configuration. IC

IC n

Input signal

n

VEE

+

P RL

P –

IC

Output

Input signal

IB

VEE

(a) Common base configuration with npn transistor

RL

n +

VCB

P

–

IB

+

– VCB

(b) Common base configuration with pnp transistor

Fig. 5.5.

Output

172

BASIC ELECTRONICS ENGINEERING & DEVICES

Emitter current amplification factor () : Current amplification factor () may be defined as the ratio of output current to the input current. Or in other words the ratio of change in collector current to emitter current at constant collector base voltage (VCB ) is known as current amplification factor of transistor in common base configuration. It is generally represented by Greek letter. i.e.,

I C = I E

at constant VCB

We know that IE = IC + IB or IE = IC + IB, then from the above relation it is clear that value of current amplification factor is always less than or equal to unity. The value of approaches to unity if value of IB reduces to zero. This can be achieved by doping the base lightly and making very thin. Total collector current of a common base (CB) configuration : During the recombination process very small percentage of electrons combine with holes in the base region. Due to this, whole of the emitter current could not reach the collector. On the other hand, the collector current is slightly increased because of leakage current that flows due to minority carriers as the collector-base junction is reversed biased. It means the total collector current consists of : (i) A large value of emitter current that reaches the collector terminals i.e., IE. (ii) The leakage current (ICBO) means current between collector and base at open emitter terminal. This current is due to movement of minority carriers across the collector-base junction as the junction is heavily reverse biased. This value is much smaller than IE. Thus, total collector current IC = IE + Ileakage or

IC = IE + ICBO

Here, ICBO (leakage current) is due to minority charge carriers i.e., collector base junction open emitter (or IE = 0). Characteristic of common base (CB). There are two important characteristics of CB. Configuration namely : (1) Input characteristics. (2) Output characteristics. 1. Input Characteristics. It is the curve between base current IB and emitter-base voltage VBE at constant collector-base voltage VCB. The emitter current is generally taken along y-axis and emitter-base voltage along x-axis. Fig. 5.6 shows the input characteristics of a typical transistor in CB arrangement. The following points may be noted from these characteristics :

IB(µA)

5 4

VCB = – 5 V

3

VCB = 0 V

2

VCB = 5 V

1 0.2 0.4 0.6 0.8

Fig. 5.6.

VBE(V)

173

BIPOLAR JUNCTION TRANSISTOR

(i) The emitter current IE increases rapidly with small increase in emitter-base voltage VEB. It means that input resistance is very small. (ii) The emitter current is almost independent of collector-base voltage VCB. This leads to the conclusion that emitter current (and hence collector current) is almost independent of collector voltage. NOTE :

In fact, input resistance is the opposition offered to the signal current. As a very small VEB is sufficient to produce a large flow of emitter current IE, therefore, input resistance is quite small, of the order of a few ohms.

2. Output Characteristic. It is the curve between collector current I C and collectorbase voltage VCB at constant emitter current IE. Generally, collector current is taken along y-axis and collector-base voltage along x-axis. Fig. 5.7 (a) shows the output characteristics of a typical transistor in CB arrangement.

Fig. 5.7 (a).

The following points may be noted from the characteristics : (a) The collector current IC varies with VCB only at very low voltages (< 1V). The transistor is never operated in this region. (b) When the value of VCB is raised above 1 2 V, the collector current becomes constant as indicated by straight horizontal curves. It means that now IC is independent of VCB and depends upon IE only. This is consistent with the theory that the emitter current flows almost entirely to the collector terminal. The transistor is always operated in this region. (c) The collector current is not zero when IE = 0. It has a very small value. This is the reverse leakage current ICO. The conditions that exist when IE = 0 for CB configuration as shown in Fig. 5.7(b). The notation must frequently used for ICO is ICBO.

174

BASIC ELECTRONICS ENGINEERING & DEVICES

C

E IE = 0 B

VCC

ICBO = ICO

Fig. 5.7 (b). Reverse leakage current in CB configuration.

The meaning of ICBO is that the current due is collector and base when emitter is open-circuited. (d) A very large change in collector-base voltage produces only a tiny change in collector current. This means that output resistance is very high. Output resistance. It is the ratio of change in collector-base voltage (VCB) to the resulting change in collector current (IC) at constant emitter current i.e., Output resistance, ro =

V CB I C

at constant IE

The output resistance of CB circuit is very high, of the order of several tens of kiloohms. This is not surprising because the collector current changes very slightly with the change in VCB. (ii) Common Emitter (CE) Configuration : The common emitter circuit arrangement for npn and pnp transistor is shown in Fig. 5.8(a) and (b) respectively. In this type of arrangement, the input is applied between base and emitter while output is taken between the collector and emitter. Thus, the emitter of transistor is common to both input and output circuits and hence the name common emitter configuration. IC

n

p

IB

IC

RL Input signal

n

Output

IE – VCC

(a) Common emitter circuit of npn transistor

Output

IE + – VBB

+

RL p

Input signal

n

+ – VBB

p

IB

– VCC

+

(b) Common emitter circuit of pnp transistor

Fig. 5.8.

Base current amplification factor () : The ratio of output current (IC ) to the input current (IB ) in common emitter configuration is known as base current amplification factor.

175

BIPOLAR JUNCTION TRANSISTOR

Thus, the ratio of change in collector current to the change in base current is known as base current amplification factor. It is represented by Greek letter . =

i.e.,

I C I B

=

Variation in collector current Variation in base current

From this relation it is clear that base current amplification factor is much higher than , as IB is very small as compared to IC. Relation between and We know that

and Also

=

I C I E

... (5.2)

=

I C I B

... (5.3)

IE = IC + IB

... (5.4)

Eqn. (5.4) divided by IC

I C I B I E = + I C I C I C 1 1 =1 +

=

1

Therefore, above relation shows that as approaches to unity, approaches to infinity. In other words, the current gain in common emitter configuration is very high. Total collector current in common emitter configuration. As we know that in CE configuration, the input current is IB and the output current is IC, so from the relation : and Apply (5.5) in (5.6)

IE = IC + IB

... (5.5)

IC = IE + ICBO

... (5.6)

IC = (IC + IB) + ICBO IC = IC + IB + ICBO

IC (1 ) = IB + ICBO IC = or

1 . IB + .I 1 CBO 1

IC = IB + (1 + ) ICBO

R| S| T

=

1

1 + =

1 1

176

BASIC ELECTRONICS ENGINEERING & DEVICES

In CE configuration, if the base circuit is open (i.e., IB = 0) the collector current will be the current to the emitter, denoted by ICEO (means leakage current of collectoremitter, junction at open base) ICEO =

1 .I 1 CBO

IC = IB + (1 + ) ICBO may be written as

So relation

IC = IB + ICEO Reason why leakage current ICEO is very much larger than the leakage current ICBO (ICEO > ICBO) Ans. There are two factors responsible for this reason : (i) There exists a leakage current which flows, not through the function, but around it and across the surface the leakage current is proportional to the voltage across the junction. (ii) New carriers may be generated by collision in the collector junction region, leading to avalanche multiplication of current. It is clear from the relation : ICEO = (1 + ) . ICBO Characteristics of Common-Emitter (CE) There are two important characteristics of CE configuration namely : (1) Input characteristics. (2) Output characteristics. (1) Input Characteristics. It is the curve between the base current IB and baseemitter voltage VBE at constant collector emitter voltage VCE. The input characteristics of a CE connection can be determined by the circuit shown in Fig. 5.8 keeping VCE constant (say at 10 V), note the base current IB for various values of VBE. Then plot the reading obtained on the graph, taking IB along yaxis and VBE along x-axis. This gives the input characteristic at VCE = 10 V as shown in Fig. 5.9. Following a similar procedure, a family of input characteristics can be drawn. The following points may be noted from the characteristics : iB (µA) VCE = – 2 V

–80

– 6V

–70 –60

– 10 V iB

P

–50 –40 –30 –20 –10 0

–0.5

–1.0

VBE(V)

Fig. 5.9. Common-emitter input characteristics of a PNP transistor.

177

BIPOLAR JUNCTION TRANSISTOR

(i) The characteristic resembles that of a forward biased diode curve. This is expected since the base-emitter junction of transistor is a diode and it is forward biased. (ii) As compared to CB arrangement, IB increases less rapidly with VBE. Therefore, input resistance of CE circuit is higher than that of CB. Input Resistance. It is the ratio of change in base-emitter voltage (VBE) to the change in base current (IB) at constant VCE i.e., Input resistance,

V BE I B

ri =

at constant VCE

Input resistance for a CE circuit is of the order of a few hundred ohms. (2) Output Characteristics. It is the curve between collector current IC and collectoremitter voltage VCE at constant base current IB. The output characteristics of a CE circuit is shown in Fig. 5.10. The following point may be noted from the characteristics : (i) The collector current IC varies with VCE for VCE between 0 and 1 V only. After this collector current becomes almost constant and independent of VCE. This value of VCE upto which transistor current IC changes with VCE is called the knee voltage (Vknee). The transistors are always operated in the region above knee voltage. IC

IC

Vknee Vknee 1 mA

VCE

1V

IB = 10 A

2 mA

IB = 5 A 0

IB = 30 A

IC

0

4 mA

IB = 20 A

3 mA

IB = 15 A

2 mA

IB = 10 A IB = 5 A

1 mA

VCE

1V

(i )

(ii )

IB = 0 0

Cut-off region Saturation region

VCE

(iii )

Fig. 5.10.

(ii) Above knee voltage, IC is almost constant. However, a small increase in IC with increasing VCE is caused by the collector depletion layer getting wider and capturing a few more majority carriers before electron-hole combinations occur in the base area. (iii) For any value of VCE above knee voltage, the collector current IC is approximately equal to × IB. Output resistance. It is the ratio of change in collector-emitter voltage (VCE) to the change in collector current (IC) at constant IB i.e., Output resistance, ro =

V CE I C

at constant IB

It may be noted that whereas the output characteristics of CB circuit are horizontal, they have noticeable slope for the CE circuit. Therefore, the output resistance of a CE circuit is less than that of CB circuit. Its value is of the order of 50 k.

178

BASIC ELECTRONICS ENGINEERING & DEVICES

(iii) Common Collector (CC) Configuration : The common collector circuit arrangement for npn and pnp transistor is shown in Fig. 5.11 (a) and (b) respectively. In this arrangement, the input is connected between base and collector while output is taken across the emitter and collector. Thus, the collector of a transistor is common to both input and output circuits and hence the name common collector configuration. IE

IE

RL n

IB

RL

–

p

IB

Output

p

Output

n p

Input signal

+

+

n

Input signal

–

IC

IC + – VBB

–

(a) Common collector circuit of npn transistor

+

VBB

(b) Common collector circuit of pnp transistor

Fig. 5.11.

Current amplification factor () The ratio of output current to the input current is known as current amplification factor. Thus, the ratio of change in emitter current to the change in base current is known as current amplification factor. It is generally represented by Greek letter . i.e.,

=

I E I B

Relation between and We know that =

I C I E

... (5.7)

=

I E I E

... (5.8)

IE = IC + IB

... (5.9)

From eqn. (5.7), (5.8) and (5.9) =

1 1

The above relation shows that value of is nearly equal to . However, the common collector circuit is seldom used for amplification because in this arrangement input resistance is high (above 700 ) and output resistance is very low (about 25 ). Due

179

BIPOLAR JUNCTION TRANSISTOR

to this reason voltage gain of common collector configuration is nearly equal to unity. However current gain is very large (about 100 to 150).

We have seen that a transistor can be connected in any one of the three configuration discussed earlier. Transistor behaves differently in different configuration. In which configuration should we connect a transistor ? This depends upon the particular application as we desire. A configuration may be suitable for some application, whereas it may not be suitable for the other. What are the important parameters that govern the suitability of the configuration ? We should know the input dynamic resistance, output dynamic resistance, d.c. current gain, a.c. current gain, a.c. voltage gain and leakage current of the transistor in a given configuration. Table shown below describes the comparison of CB, CE and CC configurations. Table 5.2 Parameters

C-B configurations

C-E configuration

C-configuration

1. Input dynamic resistance 2. Output dynamic resistance 3. Current gain 4. Voltage gain

Very low (20 )

Low (1 K)

Very high (1 M)

Very high (1 M)

High (10 K)

Very low (25 )

Less than unity Very high (150)

Large (50 to 100) Large (100 to 125)

Very high (150) Less than unity.

From the Table 5.2 as shown above we see that : NOTE :

CB-configuration circuit gain A 1 is less than unity, voltage gain A V is high (approximately equal to that of CE stage), input resistance, Ri is lowest and output resistance Ro is highest of the three configuration. The CB stage has few applications. It is sometimes used to match a very low impedance source, to drive a high-impedance load. It is also used as a constant-current source.

NOTE :

In the case of CE-configuration we see that only the common-emitter stage is capable of both a voltage gain and current gain greater than unity. This configuration is the most widely used of the three configurations. We also observe from the above table that the magnitudes of Ri and Ro lie between those for the CB and CC configurations. It may be remember that CE-configuration is usually used in the intermediate stages.

NOTE :

In the case of CC-configuration, we observe that voltage gain is approximately unity while the current gain A1 is very high. Input impedance is the highest and Ro output impedance Ro is the lowest of the three configurations. That's why this circuit finds wide application as a buffer stage between a high-impedance source and a lowimpedance load.

Although a transistor can perform a number of other functions, its main use lies in amplifying electrical signals. Here the transistor (npn) is connected in commonemitter configuration. The transistor is biased (biasing and their types will be discussed latter) to operate in the active region. In the given C-E configuration B-E. (Baseemitter) junction is forward biased however (C-E (collector-emitter) junction is reversed biased.

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Input signal

IC

C

IB

B

VBE

(VS) –

+

E

VEE

RL = 5 k

IE

+

VBB Ri = 1 k

VCC Ro = 10 k

Fig. 5.12. A basic transistor amplifier in common-base configuration.

A signal source VS is connected in the input circuit. A load resistance of 5 k is connected across the output terminal. Assumed that, the input impedance of the transistor is approximately 1 k while output impedance is approximately 10 k. An output voltage V0 is developed across this resistor when the signal VS is superimposed on the d.c. voltage VBB, the base voltage VBE varies with time. As a result, the base current IB also varies with time as a result collector as well as emitter current varies with time. This varying current when passes through the load resistor RL, a varying voltage is developed across it. This varying voltage is the output voltage V0. Here, an interesting question arises, how the signal voltage is magnified (or amplified) ? to understand this, let us consider how the transistor responds to the a.c. signal. Since the base-emitter junction is forward biased, it offers very low resistance to the signal source VS. However, the collector-emitter (CE) junction due to reverse biased, offers high resistance. Typically, the input and output resistance for a CE transistor vary from 500 to 2 k and 10 k to 50 k respectively. Assume that the input signal voltage is 20 mV (rms or effective value). Using an average value of 1 k for the input resistance we get the effective value of the emitter-current variation as :

20 10 3

= 20 A 1 10 3 Assumed d.c. current gain () of CE transistor is 100. So, the effective value of collector current variation is : IB =

IC = IB = 100 × 20 A = 2 mA Now, the output resistance of the transistor is very high. So output voltage is approximately : V0 = IC RL = 2 mA × 5 k = 10 V The ratio of output voltage (V0) to the input voltage (VS) is known as voltage amplification or voltage given (AV) of amplifier. So,

V0 10 AV = V = 20 mV = 500 S Thus we say that the transistor’s amplifying action is basically due to its capability of transferring its signal current from a low resistance circuit to high resistance circuit or we can say that i.e.,

Transfer + Resistor = Transistor

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BIPOLAR JUNCTION TRANSISTOR

Why CE configuration is widely used in amplifier circuits.

The main utility of a transistor lies in its ability to amplify weak signals. The transistor alone cannot perform this function. We have to connect some passive components (such as resistors and capacitors) and a biasing battery, such a circuit is then called an amplifier. Thus an amplifier is an electronic circuit which is capable of amplifying or increasing the level of signal. It may be noted that, a single transistor amplifying stage is not sufficient. In almost all applications we use a number of amplifier stages, connected in cascaded (in which output of one stage is connected to the input of next stage) form. Such a connection of amplifier stages is known as cascaded amplifier. Voltage gain and current gain of CE configuration is high. That’s why CE configuration is mostly used for intermediate stage in cascaded configuration. In other words reasons why CE-configuration is mostly used due to : 1. high voltage gain 2. high current gain and 3. high power gain.

Generally regions of a transistor is divided into three parts : 1. Active region 2. Saturation region 3. Cut-off region. 1. Active Region. In this region the collector junction is biased in the reverse direction while the emitter junction is biased in the forward direction. If we want to use transistor as a amplifier, we will biased it in such a manner its operating point or quiescent point (will be discussed later) remains in the active region after applying the signal. 2. Saturation Region. In this region both the input output terminals are biased in forward direction. If we wants to transistor as a switch in one condition, we will biased transistor in this region. Condition for saturation : IB where

(IB)min

IC (IB)min = h , FE

hFE = d.c. current gain IB = Base current IC = Collector current

If this condition is satisfied then the transistor will in the saturation region. 3. Cut off Region. In this region both the input and output terminals are biased in reversed direction. If we wants to transistors as a switch in off condition, we will biased transistor in this region. In simple words OFF means there is no current i.e., open circuit. Which is possible when both the junctions are reverse biased. Because it offers very high impedance i.e., open circuit.

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In short, cut off means that IE = 0, IC = ICO, IB = IC = ICO, and VBE is a reverse voltage whose magnitude v of the order of 0.1 V for germanium and 0.5 V for silicon transistor. Required condition of cut off region is given by the relation : VBE = VBB + RBICO 0.1 V

for Ge transistor.

? 1. What do you mean by transistor ? 2. Explain the basic construction of a transistor. 3. List different types operation of a transistor. 4. Explain why collector region is larger than that of the emitter and base. 5. Which type of transistor is widely used npn or pnp and why ? 6. What are the different types of transistor configuration. 7. Explain with the help of input characteristics of CB-configuration the input resistance is very small while output resistance is very high. 8. Explain why leakage current ICEO is very much larger than the leakage current ICBO (i.e., ICEO > ICBO). 9. Explain the reason behind the amplification action of a transistor. 10. Why CE configuration is widely used in amplifier circuits. 11. Explain the required condition for the transistor to be in saturation region. 12. Explain why CE configuration is generally used in intermediate stage while CB-configuration in input section and CC-configuration in the output section. 13. For a common emitter transistor, define 1 Bdc = hFE and 1 = hFC. Derive the relationship between hFE and hfe . For what condition is hFE. 14. Define h-parameters of a common emitter amplifier. How can these parameters be determined from the characteristic curve ? 15. (i ) Determine common-emitter hybrid equivalent model and (ii ) Determine common-base hybrid equivalent model. 16. Draw and describe h-parameter equivalent circuit for a common collector transistor amplifier. Show how the values of hic , hrc , hfc and hoc are obtained from the common collector input characteristic curves and CC output characteristic curves. 17. Define the active, saturation and cut-off regions in a transistor. Sketch a family of CB output characteristics for a transistor. Indicate the active, cut-off and saturation regions. 18. Draw output characteristics for an n-p-n transistor used in common base configuration and label clearly the cut-off, active and saturation regions on the diagram.

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BIPOLAR JUNCTION TRANSISTOR

19. List three factors that contribute to thermal instability in transistor amplifiers. Also, draw a circuit for CE amplifier with fixed bias and show that stability factor ‘S’ for the circuit is ( + 1). 20. If a transistor has its collector-base junction forward bias and the other junctions reverse biased, will it work ? Explain.

Example 1. In CB-configuration, the value of a = .98, a voltage drop of 4.9 V is obtained across of 5 kW when connected in collector circuit. Find the base current. Solution : = .98, V0 = 4.9 V, RL = 5 k. So, also

V0 IC = R L

=

IC = I E

= .98

IE = We know that

4.9 V = .98 mA. 5 k

.98 = 1 mA .98

IB = IE IC = (1 .98) mA = .02 mA.

Ans.

Example 2. The emitter current IE in a transistor is 3 mA. If the leakage current ICBO is 5 A and = .95 calculate the collector and base current. Solution : We know that IC = IE + ICBO Given

IE = 3 mA ICBO = 5 µA = .95

So,

IC = .95 × 3 × 103 + 5 × 106 = 2.855 mA.

Ans.

IB = IE IC = (3 2.855) mA or

IB = .145 mA. Example 3. Find the value of if

Ans.

(i) = 0.9 (ii) = .99 (iii) = .98

Solution : We know that the relation between the and is given by the relation = 1

(i)

.9 = 1 .9 = 9 Ans.

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BASIC ELECTRONICS ENGINEERING & DEVICES

(ii)

.99 = 1 .99 = 99 Ans.

(iii)

.98 = 1 .98 = 49 Ans.

Example 4. For a transistor, = 50 and voltage dross across 2 k which is connected in the collector circuit is 2 V. Find the base current for common emitter connection. Solution : Fig. P (5.1) shows the required common emitter connection. IC

RC

IB

2 k 2 V

IE VCC

VBB

Fig. P (5.1).

The voltage drop across RC (= 2 k) is 2 volt IC =

2V = 1 mA. 2 k

IB =

IC

=

1 mA = 20 A. Ans. 50

Example 5. Find rating of the transistor shown in Fig. P (5.2). Hence determine the value of IC using both and rating of the transistor. IC

Solution : We know that

C

= 1 IB = 240 A

49 = = .98 1 + 49

or

= 49

B

The value of IC can be found by using either or rating, as under :

E IE = 12 mA

IC = IE = .98 (12 mA) = 11.76 mA IC = IB = 49 (240 A) = 11.76 mA.

Ans.

Fig. P (5.2).

Example 6. (a) A transistor has an = .975. What is the value of , (b) What is the value of , if = 200. Solution : (a) Where = .975 From relation,

=

1

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BIPOLAR JUNCTION TRANSISTOR

.975 1 .975

or

=

or

= 39 (b) Where = 200.

Ans. =

From relation,

1

200 1 + 200 = .995. Ans. =

or or

Example 7. A certain transis has = .98, ICO = 5 A, IB = 100 A. Find the values of collector current and emitter current. Solution : Given

= .98 ICO = 5 A IB = 100 A

We know that the collector current given by the relation, IC = IB + (1 + ) ICO and .98 = = 49. 1 .98 1

From relation,

=

Then

IC = 49.100 × 106 + (1 + 49) 5 × 106 = 4900 × 106 + 250 × 106 A = 5150 × 106 A = 5.150 mA

Ans.

Also we know that the emitter current IE = IC + IB or

IE = 5.150 mA + 100 µA

or

IE = 5.25 mA.

Ans.

Example 8. A germanium transistor used in a complementary symmetry amplifier has a collector cut-off current ICBO (i.e. ICO) equals to 10 A at a temperature of 20C and hFE = 50. (a) What is the collector current, when the base current is 0.25 mA ? (b) Assuming hFE does not increase with temperature, what would be the value of new collector current, if the transistor’s temperature rise to 50C. Solution : Given

ICBO = 10 A hFE = = 50

(a) We know that collector current, IC = IB + (1 + ) ICBO or

IC = 50 × 0.25 × 103 + (1 + 50) × 10 × 106

or

IC = 13.01 mA.

Ans.

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BASIC ELECTRONICS ENGINEERING & DEVICES

(b) Value of new collector current if temperature rises to 50C. 50C

or

Also we know that ICBO doubles for every 10C rise in temperature. Thus ICBO at 2

T1 10

g

at 50C

= ICBO

ICBO

at 50C

= 10 × 22.5 A = 56.56 A.

at 25C

× 2

bT

ICBO

Collector current at 50C IC = . IB + (1 + ) ICBO (at 50C) or or or

IC = 50 × 0.25 × 103 + (1 + 50) 56.56 × 106 here, T2 = 50C IC = 12.5 × 103 + 2884.56 × 106 T1 = 25C IC = 15.384 mA. Ans.

As we have discussed earlier that quiescent point or operating point is nothing but zero signal values of collector current (IC) and collector emitter voltage (VCE). If either of the two changes, the operating point is shifted. Cause of unstabilization ? A transistor is said to be unstabilized when its operating point is shifted. Usually unstabilization in a transistor is occurred because of the change in collector current. The collector current in a transistor changes rapidly due to following two reasons namely : 1. If the transistor is replaced by another one of same type. Because no two transistor can have same transistor parameters (i.e., ) 2. The temperature changes affects IC. It can be more clearly understood by the equation IC = IB + (1 + ) ICO. We know that leakage current (ICBO or ICO) increase due to increase in temperature, results increase in collector current IC. The rise in collector current further increases the temperature resulting in further increase in ICBO. Such a cumulative effect leads to thermal runaway (which will be discussed later.) Effect of inherent variations of transistor parameter Inherent variations of a transistor parameter is nothing but a replacement of one transistor by another of the same type, that may have different parameters. The inherent variations of transistor parameters shifts the operating point when it is not properly stabilised. Here it is important to note that in order to avoid thermal runaway or the selfdestruction of transistor because of rise in temperature and to overcome the effect of inherent variations of transistor parameters, it is very necessary to stabilize the operating point or to fix the operating point at all connection, we require stabilisation. Thus stabilisation may be defined as the process of making operating point independent of temperature changes or inherent variations in transistor parameters is called stabilisations.

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BIPOLAR JUNCTION TRANSISTOR

We have been already discussed that stability of the operating point means the value of VCE and IC remains constant even though there is variation in leakage current ICBO (or ICO) because of rise in temperature. Stability factor may be defined as the rate of change of collector current IC with respect to rate of change of collector leakage current. ICBO at constant IB and is called stability factor. Mathematically, it may be written as Stability factor,

d IC S= d I at constant IB and . CBO

Note : A circuit having stability factor is equal to 5 and another circuit having stability factor is equal to 10 which one is the better circuit and why ? Explain it with reference to stability factor. The circuit having lower the value of stability factor, greater is the thermal stability of the transistor. Because lower the value of stability factor means that there is large change (variation) in leakage current (which is temperature dependent) there is less change in the collector current (IC). Thus we can say that the circuit having stability factor equal to 5 is better circuit than the circuit having stability factor equal to 10. Another form of stability factor S and S. Stability factor (S). The stability factor S is defined as the rate of change of IC with VBE keeping ICBO and constant. Mathematically, Stability factor

d IC S = d V BE

at constant ICBO and .

Stability factor (S ). The term stability factor S may be defined as the rate of change of IC with respect to , keeping ICBO and VBE constant. Mathematically, Stability factor,

dI C S = d

at constant ICBO and VBE.

Steps involved during the calculation of stability factor for any configuration : Step 1. Apply the KVL the input of the given circuit, write the expression and let eqn. (1). Step 2. Use IC = IB + (1 + ) ICO Step 3. Calculate the value of IB from eqn. (1) in terms of IC and other parameters and substitute in eqn. (2) which gives eqn. (3).

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BASIC ELECTRONICS ENGINEERING & DEVICES

Step 4. Differentiate eqn. (3) with respect to IC and put

d IC S= d I and then solve for S. CBO These four steps find use in determining the stability of any transistor-amplifier.

The D.C. operating point and load line We have discussed earlier that of proper operation of a transistor, in any application, we set a fixed levels of certain currents and voltages in a transistor. These values of currents and voltages define the point at which transistor operates. This point is known as operating point or quiescent point or simply Q-point. Since the level of the currents and voltage are fixed therefore the operating point is also called d.c. operating point. Or in other words, zero signal values of VCE and IC are called the operating point or Q-points. Here zero signal means in the absence of signal (i.e., V S ). In order that the circuit amplifies the signal properly, a judicious selection of the operating point is very necessary. Operating point can be better understood by considering the circuit as shown below in Fig. 5.13. IC IC

RC = 200 C

IB

RB

10 V B

100 k

dc = 100 E IE

VBB = 2 V

Fig. 5.13. CE-Configuration circuit.

Neglecting the cut-off voltage VBE applying KVL to the input section. VBB = RB IB or

IB =

V BB RB

=

2 = .2 mA 10

IC = Ib = 100 × .2 = 20 mA Again applying KVL to the output section. VCE + ICRC = 10 VCE = 10 20 × 200 × 103 = 6 V Here the values

IC = 20 mA and VCE = 6 V define a Q-point.

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BIPOLAR JUNCTION TRANSISTOR

Transistor load line analysis : Transistor load line or d.c. load line is a graphical representation of quiescent point. Before applying a transistor, the transistor circuit is generally required to be analysed, this can be obtained by plotting the output characteristics and then determining the collector current at a derived collector-emitter voltage. This (drawing of d.c. load line) can better understand by considering the output characteristics of a common emitter transistor shown below in Fig. 5.14. Saturation point D.C. load line 50 40

Q1

IB = 0.4 mA Q2

30

IB = 0.3 mA Q3

IC (mA) 20

IB = 0.2 mA Cut-off point

10 0

IB 2

4

6 VCE (in volt)

8

0

10

Fig. 5.14.

In the given figure there are three operating point Q1 (4 V, 30 mA), Q2 (2 V, 40 mA) and Q3 (6 V, 20 mA) on both sides, we shall obtain a straight line as shown in Fig. 5.14. The values of base current, collector current and collector-to-emitter voltage can be read at any point along this line. The d.c. load line gives us the information about the following two important points. 1. The load line intersects the horizontal axis at a point marked VCE, which is equal to 10 V. This point is called transistor cut-off point or lower end of the load line. At this point the values of base current and collector current are zero (ideally). But actually, there is a small value of reverse saturation current (ICBO) at cut-off point as indicated in the figure. Due to this reason, the VCE is slightly less than VCC. 2. The load line intersects the vertical axis at a point marked IC equal to 50 mA. This point is called transistor saturation point or upper end of the load line. At this point, the collector current in maximum and collector-to-emitter voltage is very small equal to VCE(Sat). It may be noted that if the upper and lower ends of the load line are known, the load line can be obtained by joining the upper and lower ends. Simpler way of drawing a d.c. load line : Steps involved in drawing a d.c. load line : Step 1. Applying KVL in he output of the circuit. Step 2. On putting the value VCE = 0 we get IC in terms of VCC and RC.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Step 3. On putting the value of IC = 0 we get value of VCE. Step 4. Join the values obtained in step 2 and step 3 to understand the above steps more clearly. Consider a circuit having RC = 10 k, VCC = 20 V, RB = 47 k, VBB = 10 V and = 100 as shown below in Fig. 5.15. VCC = 20 V IC

RC = 10 k V0

n RB = 47 k

p+ VCE

IB n VBE

IE

VBB = 10 V

Fig. 5.15.

Step 1. Applying KVL in the output of circuit. VCC ICRC VCE = 0 or

VCC = ICRC + VCE Step 2. On putting

VCE = 0 in eqn. (5.10), we get

V CC IC = R C Step 3. On putting

... (5.10)

20 = 10 k = 2 mA.

IC = 0 in eqn. (5.10) we get, VCE = VCC = 20 V

Step 4. Join these values (i.e., IC = 2 mA and VCE = 20 V) as shown in Fig. 5.16. 2 mA D.C. Load line

IC (in mA)

Q (17.87 V, .213 mA) 0

20 V VCE (in volts)

Fig. 5.16.

If we want to calculate the Q-point for the same problem then from eqn. (5.10) VCC = ICRC + VCE

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BIPOLAR JUNCTION TRANSISTOR

Again applying KVL at the input section (neglecting VCE i.e., cut in voltage) VBB = IB RB IB =

V BB RB

=

10 = .213 mA 47 k

IC = IB = 100 × .213 = 21.3 mA Again for eqn. (5.10) VCE = VCC ICRC or

VCE = 20 .213 × 103 × 10 × 103

or

VCE = 17.87 V. The quiescent point (17.87 V, .213 mA) is shown in the above figure.

Biasing is nothing but a selection of operating point (i.e., quiescent point) to operate a transistor in a desired region. Here an interesting question arises, what is need of biasing ? The solution is that when the signal is applied across the input, if the transistor is not properly biased then there is more chances to clip the input signal or in other words we can say that we get distorted output. To avoid this difficulty we need biasing. The circuitary which provides the necessary conditions of transistor biasing is known as biasing circuit. Selection of operating point : As we have discussed earlier biasing is nothing but a selection of operating point. Let us assume that we want to transistor work as an amplifier, so we will bias a transistor in such manner that its quiescent point () always remain VCC B in the active region after applying I max RC IB = B the input signal. Here an important question arises that in which place Active region in the active region we bias the D C IC transistor. For simple understanding (mA) there are three possibilities i.e., D, C, E to bias a transistor which will E Saturation work as an amplifier. The points D, region IB = 0 C, E are shown below in the figure. From the figure it is clear that there O Cut-off region are three possibilities to bias a tranVCE (in volts) sistor in active region to work as an amplifier (namely D, C and E Fig. 5.17. points). If point D is selected as the operating point, the upper portion of the positive half will be clipped off as this point lies very near to the saturation region [see in Fig. 5.18(a)].

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BASIC ELECTRONICS ENGINEERING & DEVICES

IC

Output current O

Clipped

B

2

t

t 2

Input signal

D C E

0

A

O Clipping

VCE

Output voltage

2 t

Fig. 5.18(a). Output characteristics if D is selected as the operating point.

On the other hand, if point E is selected as the operating point, the peak of the negative half will be clipped off as this point lies very near to the cut-off region [see in Fig. 5.18(b)]. Thus, in both the cases distorted signal is obtained at the output. However, if point C is selected as the operating point, full cycle of the signal is obtained in the amplified form at the output [see Fig. 5.18(c)]. In this case, signal is not distorted at all. IC

B 2

D

Output current

C

O

t 2

l na sig t u Inp

E

O

Clipping

t

A

VCE

Output voltage

2 t

Fig. 5.18(b). Output characteristics if E is selected as the operating point.

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BIPOLAR JUNCTION TRANSISTOR

IC

B

Output current

D

O

C

2 O

t

2

t

l na sig t u Inp

E

O

A

VCE

Clipping Output voltage

2 t

Fig. 5.18(c). Output characteristics if C is selected as the operating point.

The basic principles of the biasing circuitary is to obtain the required value of IC and VCE from the given circuit in the zero signal conditions. From the above discussion, it clear that transistor biasing is required for faithful amplification (when an amplifier does not distort the original shape of input signal after amplification process except increased magnitude, the phenomenon is referred to as faithful amplification). The biasing circuit should have following : (i) It should ensure proper zero signal collector current and VCE i.e., it should establish the operating point in the centre of the active region of the characteristics, so the signal may not cut-off at any part. (ii) It should make the operating point independent of transistor parameters. (iii) It should ensure that VCE does not fall below the required limit (i.e., 1.0 V for Si and 0.5 V for Ge transistors) The following methods are used for obtaining transistor biasing : (i) Fixed biasing or base resistor biasing (ii) Collector-to-base biasing or voltage feedback biasing (iii) Emitter resistor biasing (iv) Potential divider or self biasing.

(i ) Fixed Biasing or Base Resistor Biasing The circuit arrangement of fixed biasing for an npn transistor is shown below in the Fig. 5.19. In this biasing a high valued resistance is connected between supply and base of the transistor. The required zero signal base current IB is provided by VCE. The supply also keeps the base positive with respect to emitter and hence makes the base

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BASIC ELECTRONICS ENGINEERING & DEVICES

emitter junction forward biased. However, on the other hand in case of pnp transistor, the negative end of the supply is connected to the collector through RC and base resistor RB . Circuit analysis for the stability factor : To calculate the stability factor for the given circuit we will apply the steps discussed earlier. VCC

Apply KVL to the input section VCC IBRB VBE = 0

... (5.11)

also we know that

RC

RB

IC = IB + (1 + ) ICO ... (5.12)

V CC V BE From eqn. (5.11) IB = , on putting RB the value of IB in eqn. (5.12) we get, IC =

LM V N

CC

V BE RB

OP + (1 + ) I Q

CO

... (5.13) Now differentiating eqn. (5.13) w.r.t. IC , we get d d .I = C dI C dI C

LM FG V N H

CC

V BE RB

or

dI CO 1 = 0 + (1 + ) dI C

or

1 = 0 + (1 + ).

1 S

IB

B + VBE

– E VCE IE

Fig. 5.19. Fixed biasing circuit for npn transistor.

IJ (1 ) I OP K Q CO

RS S dI UV dI T W C

CO

S=1 + Thus, from the above relation it is clear that the value of stability factor in fixed biasing method is very high which shows its poor thermal stability. Advantages : (i) In this method, calculations are simple. (ii) Simple in construction as only one resistor RB is required to set the conditions. (iii) There is no loading of the source as no resistor is employed across base emitter junction. Disadvantages : (i) It provided high stability factor or in other words poor thermal stability and therefore chances of thermal run way. (ii) This method provides poor stability against inherent variations of transistor parameters. Due to the disadvantages, this method is rarely employed in practical circuits.

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BIPOLAR JUNCTION TRANSISTOR

(ii ) Collector-to-base Biasing or Voltage Feedback Biasing The biasing arrangement for an npn transistor is shown in Fig. 5.20. In this biasing a very high value resistance RB is connected between collector and base and resistance RC is connected between supply voltage and collector of the transistor. Here the required zero signal base current is determined by collector-base voltage VCB and not by VCC. Hence, the base-emitter junction is forward biased and base current IB flows through RB. VCC IE RC IB

C IC

B RB

– E VCE

VBE

VBE

–

–

VCE

IE

Fig. 5.20. Collector-to-base biasing for an npn transistor.

It may be noted that the collector C is connected to base (input) through RB. Through this resistance (RC) current IB feedbacks from the output. In other words base current depends upon the collector voltage. This is why this circuit is also called a voltage feedback biasing circuit. Circuit analysis for stability factor (S) Taking into account the steps discussed earlier, applying KVL in the input i.e., VCC IERC IBRB VBE = 0 Also we know that

... (5.14)

IC = IB + (1 + ) ICBO

... (5.15)

From eqn. (5.14), VCC (IB + IC)RC IBRB VBE = 0 or

IB =

V CC V BE I C RC ( RC R B )

... (5.16) { IE = IB + IC}

On putting the values of IB in eqn. (5.15), we get IC =

LMV N

CC

V BE I C RC RC R B

OP Q

+ (1 + ) ICBO

... (5.17)

Now, differentiating eqn. (5.17) w.r.t. the IC , we get d d .IC = dI C dI C

RS LV T MN

CC

V BE I C R C RC R B

OP (1 ) I Q

CBO

UV W

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BASIC ELECTRONICS ENGINEERING & DEVICES

1=

1 +

RS S d I UV d I T W

RC d I CBO + (1 + ). ( RC R B ) d IC

C

CBO

RC 1 = (1 + ) . RC R B S

RC (1 + ) + RB = (1 + ) S=

1 S

(1 ) ( RC R B ) = R B (1 ) RC

( RC R B ) RB RC (1 )

The main advantage is that it is a simple biasing arrangement as only one resistance RB is required. Disadvantages : (i) The stability factor of this biasing method is quite high. Hence, the frequency point does change, although to lower extent, due to temperature rise or inherent variations in parameters. (ii) The resistor RB not only provides d.c. feedback for stabilization of operating point, but it also causes a.c. feedback. This reduces the voltage gain of the amplifier which is not desirable. Because of this drawback, this circuit is seldom used in operational amplifiers.

(iii ) Emitter Resistance Biasing Circuit arrangement for emitter resistance biasing for an npn transistor is shown below in Fig. 5.21. This arrangement is just a modification to the collector-to-base biasing circuit. In this biasing an additional resistance RE is connected in the emitter. Thus we can say that this circuit contains three resistors RB, RE and RC.

IC

IB

RC

RB

C B

Circuit analysis for stability factor : Taking into account the steps discussed earlier applying KVL in the input section VCC IB RB VBE IERE = 0

VCC

... (5.18)

VBE

E VCE IE RE

Also we know that IC = IB + (1 + ) ICBO ... (5.19) From eqn. (5.18) VCC IBRB VBE (IC + IB) RE = 0 IB =

V CC V BE I C R E RE RB

Fig. 5.21. Emitter biasing circuit for an npn transistor.

... (5.20)

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BIPOLAR JUNCTION TRANSISTOR

On putting the value of IB in equation of IC =

LMV N

CC

V BE I C R E RE RB

OP Q

+ (1 + ) ICBO

Now, differentiating the eqn. (5.21) w.r.t. IC d d I = dI C C dI C

1 =

1 +

RS FG V T H

CC

V BE I C R E RE RB

IJ (1 ) I K

... (5.21)

CBO

UV W

d I CBO RE + (1 + ) dI C (RE RB )

RE 1 = (1 + ) (RE RB ) S

RE RB RE (RE RB ) or

= (1 + )

S =

1 S

( R E R B ) . (1 ) R E (1 ) R B

From the above expression it is clear that the stabilization is improved by inserting RE in the emitter circuit. The emitter resistance is present in outside as well as input side. Therefore, a feedback occurs through this resistor. The feedback voltage is proportional to the emitter current IE. Hence, the circuit is also called current feedback biasing circuit. This arrangement provides better stabilization than other biasing circuits. Disadvantages : (i) The stability factor of the biasing is quite high. Hence the operating point does change, although to lower extent, due to temperature rise or variations in parameters. (ii) The d.c. feedback helps in the stabilization of operating point but at the same time a.c. feedback reduces the voltage gain of the amplifier. However, this drawback can be removed by putting a capacitor CE across the resistor RE. This is possible due to the fact that CE offers very low impedance to the a.c. signal (current) and does not allow it to pass through RE and hence a.c. feedback is restricted. However for d.c. supply it (capacitor) offers very high impedance (ideally open circuit) this property of capacitor provides better d.c. stabilization. Thus the process of amplification remains unaffected.

(iv) Potential Divider Biasing or Self Biasing The potential divider or self biasing for an npn transistor of common emitter configuration is shown below in the Fig. 5.22. This biasing circuit consist of two resistors R1 and R2 connected across the supply voltage VCC and provide the necessary biasing. Whereas, a resistor connected in the emitter circuit RE provides thermal stability and improves stability factor. Since the resistor R1 and R2 form the potential divider

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BASIC ELECTRONICS ENGINEERING & DEVICES

hence the name potential divider biasing. This biasing is the most widely used method of providing biasing and stabilisation to transistor since the operating point, in this case can be made almost independent of . + VCC RC

I1

IC

RB

C IB

I2

B VBE

– E

VCE

RE

R2

IE

Fig. 5.22. Potential divider biasing for an npn transistor.

Circuit analysis of stability factor : Let us consider the base-emitter loop of the voltage divider bias circuit. A basic assumption is that the resistance looking into the base is much longer than that of the resistor R2. If this is so, then, the current through resistor R1 flows almost completely into resistor R2 and the two resistors may be considered effectively. Before applying the steps discussed earlier, first of all we will draw Thevenin equivalent model (i.e., in which an equivalent voltage source (Vth) followed by equivalent series resistance (Rth)). + VCC RC

R1

R1 A

VCC

R2

RE

A

A R2

Vth

A

Fig. 5.23. Potential divider biasing circuit to calculate Vth.

Voltage across terminals AA is called the Thevenin voltage, given by applying potential divider method i.e.,

Vth =

R2 × VCC R1 R 2

Comp-1/Laxmi-5/Computer/Revision/Belec-5a—10.5.07

199

BIPOLAR JUNCTION TRANSISTOR

To determine Thevenin resistance Rth, reduce the circuit as shown in Fig. 5.24.

R1

As we know that Rth can be calculated by taking all the energy sources replaced by their internal resistance (i.e., voltage source as a short circuit and current source as a open circuit) so,

R th = R1

A

S.C. R2

R1 R 2 R1 R 2

R2 =

A

Rth

Fig. 5.24.

The resultant thevenin equivalent model circuit is shown in Fig. 5.25.

VCC

Applying KVL to the input side. Vth IB Rth VBE IE RE = 0

RC

... (5.22)

IC

We know that

C

IC = IB + (1 + ) ICBO

... (5.23)

IB Rth

B

From eqn. (5.22)

VCE

IB =

VBE

V th V BE I C R E ( R E Rth )

... (5.24)

{ IE = IB + IC, ICO

Vth

LMV N

th

V BE I C R E R E Rth

OP Q

IE

Fig. 5.25.

+ (1 + )ICO

... (5.25)

Differentiating eqn. (5.25) w.r.t. IC, we get

dI C d = dI C dI C 1=

1 +

LM FG V NH

th

V BE I C R E ( R E R th )

IJ (1 ) I OP K Q

R E . dI CO + (1 + ) . ( R E R th ) dI C

RE 1 = (1 + ) . R E Rth S

R E Rth R E 1 = (1 + ) . S R E Rth R E (1 ) Rth 1 = (1 + ) . R E Rth S

E RE

ICBO}

On putting the value of IB in eqn. (5.23), we get IC =

–

CO

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BASIC ELECTRONICS ENGINEERING & DEVICES

LM 1 R R S = (1 + ) M MM1 R R N th E

or

th E

OP PP PQ

or S = (1 + )

R E Rth Rth R E (1 )

The voltage divider or self bias circuit provides magnificent stabilization, therefore this biasing circuit is invariably employed for transistor biasing.

? 1. What do you mean by stabilization ? 2. List the causes of unstabilization. 3. What do you mean by stability factor ? 4. Define the stability factor S, S and S . 5. What are the operating points or Q-points of a transistor. 6. List the steps involved in drawing a d.c. load line. 7. What do you mean by biasing ? 8. List the different types of biasing. 9. What is the need of biasing ? 10. What do you mean by fixed or Base Resistor Biasing. 11. What are the advantages and disadvantages of Base Resistor biasing. 12. Describe emitter biasing and list their advantages and disadvantages. 13. Describe potential divider biasing and explain why it is most widely used among the biasing. 14. Compare merits and demerits of different types of biasing. 15. Define and of a transistor and derive the relationship between them. 16. Why is biasing needed for a transistor to work as an amplifier ? Explain with the help of a neat diagram. 17. Differentiate between JCO and ICBO. What is the effect of temperature on ICBO ? 18. Sketch the circuit of a common collector configuration and also the input and output curves. 19. Draw npn and pnp transistors. Label all the currents and show the direction of flow. How are all the currents of a transistor related ? 20. The common base configuration factor < 1, why this is called amplification factor ? 21. Compare CE, CB and CC transistor amplifiers for their parameters e.g., AV, AI , R0 , Ri.

201

BIPOLAR JUNCTION TRANSISTOR

VBE

Example 1. A base resistor biasing circuit is shown in Fig. P (5.3a). Determine (assume = 0.6 V and = 60). (i) The collector current IC. (ii) Collector emitter voltage VCE Solution : Given

VBE = 0.6 V VCC = 10 V = 60 RB = 20 k RC = 300 10 V RC = 300 RB

IC

20 k

C

IB

VBE

E – – VCE IE

Fig. P (5.3a).

Applying KVL in the input section. For easy to understanding the circuit diagram of input section is shown in Fig. P (5.3b). IB RB

VCC = 10 V

B

+

VBE

Fig. P (5.3b).

10 IBRB VBE = 0.

E –

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BASIC ELECTRONICS ENGINEERING & DEVICES

IB =

10 V BE 10 .6 9.4 V = = = .47 mA. RB 20 k 20 k

IC = IB = 60 × .47 = 28.2 mA.

(i)

IC RC

Ans.

10 ICRC VCE = 0.

VCE

VCE = 10 ICRC

–

= 10 28.2 × 300 × 103 = 1.54 V.

10 V

+

(ii) Again, applying the KVL in the output section

Ans.

Fig. P (5.3c).

Example 2. Draw the dc load line and locate the operating point for the fixed biasing transistor circuit shown in Fig. P (5.4a) (assume VBE = .6 V) Solution : For drawing load line taken into account the steps discussed earlier. Applying KVL to the output the circuit. VCC ICRC VCE = 0

... (1)

On putting the value VCE = 0 in eqn. (1), we get IC =

V CC 9 = = 4.5 mA (assume OA) RC 2 k

On putting the value of IC = 0. In eqn. (1), we get, VCE = VCC = 9 V (assume OB) To draw the load line join the values OA and OB. VCC = 9 V 2 k IC

8 k

IC (mA) 4.5 mA A

IB

Q (4.8 V, 2.1 mA)

=2 IE

Fig. P (5.4a).

Now,

IB =

B

O

9V

Fig. P (5.4b).

V CC V BE 9 .6 8.4 = = = 1.05 mA RB 8 k 8

VCE = VCC ICRC = 9 IBRC = 9 2 × 1.05 × 2 = 9 4.2 = 4.8 V IC = IB = 2 × 1.05 = 2.1 mA Hence, operating point Q (VCE, IC) = 4.8 V, 2.1 mA.

Ans.

VCE

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BIPOLAR JUNCTION TRANSISTOR

Example 3. For the circuit determine the emitter current the collector voltage . Comment + VCCV=C12 V on the result. Neglecting VBE.

}

Solution : Here one thing is interesting to note that collector voltage VC 600 is nothing but VCE. 600 k Since emitter is grounded so

VCE = VC

IB

IE

VCE = VC VE = VC 0

= 100 VCE

VBE

= VC

IE

Now applying KVL to the input side VCC IE (600) IB × 600 × 103 VBE = 0 or

VCC (IB + IC) 600 IB × 600 × 103 = 0 { VBE = 0}

Fig. P (5.5).

VCC ( IB + IB.) 600 IB × 600 × 103 = 0 IB =

=

V CC 600 10

3

600 10

3

100 600

12 100 600

= 18.18 A

IC = IB = 100 × 18.18 mA = 1.818 mA. IE = IC + IB = 1.818 mA + 18.18 A (

1.818 mA. 18.18 A is nearly equal to zero)

Now, applying KVL to the output circuit. VCE = VC = VCC IERC = 12 1.818 × 103 × 600 = 10.91 V.

+ VCC = 10 V

Comments. It may be noted that transistor VCE = 10.91 V which is slightly less than VCC. Hence the operating point is very near to the cut-off region. Or in other words we can say that given transistor is used as a switch in Ithe off condition. B IC Example 4. Calculate the value of RB in the biasing circuit shown in Fig. P (5.6) so that the operating point becomes IC = 6.4 mA and VCE = 8.4, = 80. Neglecting VBE. Solution : Here it is important to note that for DC analysis capacitor acts as an open circuit. Applying KVL in the input side,

250

RB

C +

+

VBE

–

E

VCE

IE 500

VCC IBRB VBE IE (500) = 0 VCC IBRB 0 (IB + IC) (500) = 0 RB =

RB =

V CC ( 1) 500 . I B IB 10 ( 80 1) 500 80 10 6 80 10 6

Fig. P (5.6).

+ –

100 F

204

BASIC ELECTRONICS ENGINEERING & DEVICES + V = + 4.5 V

CC IC 6.4 mA {IB = = = 80 A, VBE = 0 given} 80 1.5 k

or

RB = 84.5 k.

R1

Ans.

Example 5. For the circuit given in Fig. P (5.7a) is used in self-biasing arrangement with = 44, RL = 1.51 k, RE = 270 k, and VCC = 4.5 V. (Assume VBE = 0) Estimate (a) quiescent point

27 k = 44 2.7 k

R2

RE = 270

(b) Stability factor. Solution : (a) First of all we will take the Thevenin equivalent model. Vth = 4.5 ×

Fig. P (5.7a).

2.7 = .40 V 2.7 + 27

VCC = 4.5 V

R1R 2 27 ( 2.7 ) Rth = R R = = 2.45 k. 27 + 27 1 2

1.5 k IC Rth = 2.45 k

Now applying KVL to the input circuit,

IB

Vth IBRth VBE IERE = 0 Vth IBRth VBE (IB + IC ) RE = 0 or

Vth IBRth VBE (IB + IB) RE = 0

V th . IB = Rth R E IC = IB = or

IC = IB)

(

Vth = .40 V

IE 270

( VBE = 0)

44 (.40 ) 2.45 k + 44 .270 k

Fig. P (5.7b).

IC = 1.228 mA And, applying KVL to the output section, VCC ICRC VCE IERE = 0 VCE = VCC IC (RC + RE)

( neglecting IB)

= 4.5 1.228 (1.5 + .270) = 4.5 – 2.173 = 2.326 V Stability factor for potential divider biasing

LM 1 R OP R S = ( + 1) M MM1 R PPP R Q N LM 1 2.45 OP .27 = (44 + 1) M .45 PP MN1 44 2.27 Q th E

th E

(As we derived earlier)

205

BIPOLAR JUNCTION TRANSISTOR

= 45

LM 1 + 9.07 OP = 8.38 N1 + 44 + 9.07 Q

Ans.

(b) The quiescent points are Ans.

IC and VCE = (1.28 mA, 4.01 V)

Example 6. For the two battery transistor circuit shown in Fig. P (5.8 a), prove that the stabilization factor S is given by S =

1 RC 1 RC R B

Solution : Taken into account the steps discussed earlier. Applying KVL to the input circuit. Draw its equivalent circuit. IC

C IB

RC

VBE

RE

RB

VCE

– +

RB

RE

V2

V1

RC

E IE

V1

Fig. P (5.8a).

V2

Fig. P (5.8b).

VI IERC + VEB IBRB = 0

... (1)

We know that IC = IB + (1 + ) ICBO

... (2)

V I I C RC V BE ( R B RC )

... (3)

From eqn. (1) IB =

On putting the value of IB in eqn. (2), we get IC =

LMV N

1

I C R C V BE ( R B RC )

OP Q

+ (1 + ) ICO

... (4)

Now, differentiating eqn. (4) w.r.t., IC

d IC d IC

=

d d IC

1 =

1 +

LM FG V NH

I

I C R C V BE R B RC

.RC d I CO + (1 + ). R B RC d IC

RC 1 = (1 + ). ( R B RC ) S

IJ (1 ) I OP K Q CO

206

BASIC ELECTRONICS ENGINEERING & DEVICES V = 16 V

or

S =

CC (1 ) Hence proved. RC 1 ( R B RC )

RC = 1.5 k

R1

Example 7. A germanium transistor is used in the self biasing arrangement with VCC = 16 V and RC = 1.5 k. The quiescent point is chosen to be VCE = 8 V and IC = 4 mA. A stability factor S = 12 is desired if = 50 find R1, R2 and RE.

C B E

R2

RE

Solution : The circuit arrangement of self biasing as shown in Fig. P (5.9a). Given

S = 12 VCC = 16 V

Fig. P (5.9a).

RC = 1.5 K

VCC = 16 V

VCE = 8 V

IC

IC = 4 mA

RC = 1.5 k

= 50 R1 , R2 , RE = ?

IB

Taking Thevenin’s equivalent circuit Vth = V CC R th =

R2 R1 R 2

VBE

Rth +

R1R 2 R1 R 2

–

C+

B +

VCE –

E RE

Vth

IE N

Applying KVL to the input side Vth IB Rth VBE IERE = 0

Fig. P (5.9b).

... (1)

IC 4 mA IB = = = 80 A. 50 IE = IB + IC = IB (1 + ) = 4.08 mA

and

Applying KVL to the output section RE = =

V CC I C RC V CE (I B I C ) 16 4 10 3 1.5 10 3 8 = 0.49 k 4 .08 mA

Given that S =

( Rth R 3 ) (1 ) = 12 Rth (1 ) R E

(Rth + RE) (1 + ) = 12 {Rth + (1 + ) RE}

FG R HR

th E

IJ K

1 (1 + ) = 12

RS R TR

th E

(1 )

UV W

... (2)

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BIPOLAR JUNCTION TRANSISTOR

FG R HR

th E

IJ K

1 (1 + 50) = 12

RS R TR

th

51

E

UV W

Rth Rth Rth + 50 + 1 + 50 = 12 + 12 × 51 RE RE RE Rth RE

or or

= 14.4

R th = .49 × 14.4 = 7.05 k

R1 R 2 R th = R R = 7.05 k 1 2

and

VBN = VBE + IERE = 0.2 + 4.08 × .49 = 2.2 V

... (3)

{for Ge transistor VBE = 0.2 V} Vth = VBN + IBRth = 2.2 + 0.08 × 7.05 = 2.764 V ... (4) From eqn. (4) Vth =

V CC . R 2 R2 = 16 R1 R 2 R1 R 2

2.764 = 16

R2 R1 R1 R 2

2.764 = 16

Rth R1

2.764 = 16

( 7.05 ) R1

... (5)

(Multiplying and dividing by R1)

R1 = 41 k and

R2 = 8.56 k R1 = 41 k R2 = 8.56 k Ans. RE = 0.49 k.

Example 8. A potential divider biasing circuit is shown in Fig. P (5.10). What will happen when (i) Biasing resistor R2 is shorted. (ii) Biasing resistor R1 is opened. (iii) Biasing resistor R2 is opened. (iv) Biasing resistor R1 is shorted.

208

BASIC ELECTRONICS ENGINEERING & DEVICES

+ grounded. Solution : (i) When the biasing resistor R2 is shorted, the base will be VCC The emitter-base junction will no more be forward biased and the transistor will be cutoff. Hence the output will be reduced to zero. RC

(ii) When the biasing resistor R1 is opened, the emitter-base junction will no more remain in the forward biased and the transistor will be cut-off. Hence, the output will be reduced to zero.

R1

C B

(iii) When the biasing resistor R2 is opened, the emitter base junction will be highly forward biased through R1. This will rise the collector current IC to large value and the transistor will be saturated. Or in other words we can say that VCE (collector to emitter voltage) will be reduced to zero.

E

R2

RE

Fig. P (5.10).

(iv) When the biasing resistor R1 is shorted, the emitter base-junction will be highly forward biased. Since the voltage at the base is VCE. This will raise the collector current IC to large value and the transistor will be saturated. Hence, the collectoremitter voltage VCE will be reduced to almost zero.

Example 9. Determine the stability factor S for the circuit shown in Fig. P (5.11a). V CC

Solution : To determine the stability factor (S) first of all we will make its equivalent R R (i.e., Thevenin equivalent) circuit. V C

1

A

R th =

R1 R 2 R1 R 2

Vth = V A

R2 R1 R 2

... (1) R2

RE

... (2)

where VA = (VCC IERC) Applying KVL to the input section,

Fig. P (5.11a).

Vth RthIB VBE IERE = 0 or

VCC = IERC Rth IB VBE ICRC = 0

... (3)

VCC

Also we know that IC = IB + (1 + ) ICO

RC

... (4)

From eqn. (3)

V CC V BE I C ( RC R E ) IB = ( Rth RC R E ) On putting the value of IB in eqn. (4), we get

IB

... (5)

C

Rth B + VBE

Vm

+

VCE

– E RC

Fig. P (5.11b).

209

BIPOLAR JUNCTION TRANSISTOR

IC =

LMV N

V BE I C ( RC R E ) ( R th R C R E )

CC

OP Q

+ (1 + ) ICO ... (6)

Now, differentiating eqn. (6) w.r.t. IC

d IC d IC

=

1 = or

1 +

d d IC

RS LV T MN

CC

OP Q

V BE I C ( R C R E ) (1 ) I CO ( R th RC R E )

UV W

( RC R E ) d I CO + (1 + ) ( Rth R C R E ) d IC

( RC R E ) 1 = (1 + ) ( Rth RC R E ) S

or

S =

R1 R 2 (1 ) ( Rth RC R E ) where Rth = . Rth ( RC R E ) (1 ) R1 R 2

Example 10. Prove that for the circuit shown the stability factor S is given by

S S = R R × 1 B E

FG i .e ., S I IJ V H K d I I F First of all we must calculate the value of S G i .e ., S JK d I H C

Solution : To calculate stability factor S

BE

Rb

IB

We know that

C

CO

+

VBE

S=

(1 ).( R E R B ) R B R E (1 )

... (1)

+ –

V

IC RE C + VCE – E IE

+ –

VCC

RE

Now, applying KVL to the input section V IBRB VBE IERE = 0

... (2)

We know that IC = IB + (1 + ) ICO

... (3)

Fig. P (5.12).

From eqn. (2), the base current IB =

V V BE I C R E (RB RE )

... (4)

On substituting the value of Ib in eqn. (2) IC =

LMV N

V BE I C R E (RB RE )

Now, differentiating eqn. (5) w.r.t. VBE

OP Q

+ (1 + ) ICO

... (5)

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BASIC ELECTRONICS ENGINEERING & DEVICES

IC = V BE V BE

RS FG V T H

S=

RS T

S 1

RE RB RE

V BE I C R E RB RE

RB

UV = W R

B

RE

(RB RE ) ( R B R E ) R E (1 ) R B

S=

(1 ) ( R E R B ) R B R E (1 )

Rb + Rc (1 + ) =

(1 ).( R E R B ) S

From eqn. (1)

Now

CO

RE S RE RB RE

S=

or

IJ (1 ) I UV K W

S =

... (6)

... (7)

S Hence proved. 1 RB RE

Example 11. If for the given circuit hFE = 100, determine the region of transistor. IC 3 k IB

C +

B 50 k

+ VBE .8 V

–

VCE = 0.2 V

10 V

E

5V

Fig. P (5.13).

Before solving the problem, it is necessary to discuss following three steps. There are three steps which will decide the region of transistor. Step 1. If the input (i.e, B-E junction) is in forward biased and output (i.e., C-E junction) in the reverse biased, it means transistor will be in the active region. Step 2. If IB (base current) greater than or equal to minimum base current (IB min) then transistor will be in saturation region or in other words IB

(IB)min

IC where (IB)min = h FE

Step 3. If both input and output section are in reversed biased the transistor

211

BIPOLAR JUNCTION TRANSISTOR

will be in cut-off region. Solution : From Fig. P (5.13) it is clear that input side (i.e., B-E junction) is in forward biased so transistor will never be in the cut-off region. If the condition (IB) IB otherwise in active region.

min

is satisfied the transistor will be in saturation region

Now, applying KVL in input side, 5 50 × 103 IB 0.8 = 0 or

IB = .084 mA. Again KVL at output side, we have 10 3 × 103 IC 0.2 = 0 IC =

Now, Since IB

(IB)min = IB

min

9.8 3 10 3

= 3.266 mA.

IC 3.266 = = 0.03266 mA h FE 100

is satisfied. Hence the given transistor will be in saturation region.

Example 12. For the circuit shown, assume = hFE = 100. (a) Find if the silicon transistor is in cut-off, saturation or in active region. (b) Find VO. (c) Find the minimum value for the emitter resistor R C for which the transistor operates in the active region. [Assume (VBE)sat = 0.8 V and (VCE)sat = 0.2 V] Solution : (a) Since the input side is in forward biased so, it will never in cut-off region, i.e., either it will be in saturation or in active region. Now, applying KVL in the input side, we have 3 (IB + IC) 500 0.8 7 × 103 IB = 0 or

10 V

2.2 (500 + 7000) IB 500 IC = 0 Again applying KVL to the output side, we have,

3 k

10 + 3 × 103 IC + 0.2 V + 500 (IB + IC) = 0 From eqn. (1) and (2) IC =

or

IB =

9.8 3500 2.78 10 500

IB =

9.8 9.746 500

VO

9.8 = 3500 IC +7 k 500 IB

144.8 = 2.78 mA 52000

3V

... (1)

... (2)

– +

RC

500

3

Fig. P (5.14).

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BASIC ELECTRONICS ENGINEERING & DEVICES

or

IB = 1.4 × 104

or

IB = .14 mA (IB)min =

IC 2.278 = = 0.027 mA. h FE 100

Now, since IB > (IB)min. So the transistor will be in saturation region.

Ans.

(b) We have, VO = VCE (IB + IC) 500 = 0.2 (2.99 × 103) 500 = 1.69 V.

Ans.

(c) According to the question for the transistor to be in active region. 0.5 V

VBC

(Note that but for npn transistor VBC > 0.5 V) 0.5 V is the emitter voltage of the collector junction 3 = IB × 7 + (IB + IC) RC 0.7 IC = IB ( VBE (active) = .7 V) 2.3 = IB (7 + 101 RC) (Note that all the resistors are taken in k)

Put

IB =

Now

2.3 mA ( 7 101 RC )

IC = IB =

230 mA ( 7 101 RC )

VBN = 0.7

232.30 RC ( 7 101 RC )

VCN = 10 +

3 230 7 101 RC

VBC = VBN VCN

and

232.30 RC 7 101 RC

0.5

3 230 7 101 RC

0.5

After calculating we get RC

819

Ans.

Example 13. Calculate the Q-point values for the d.c. bias circuit shown in Fig. P (5.15).

213

BIPOLAR JUNCTION TRANSISTOR + 10 V IE RB = 100 k

10 k = RC IB

C IC dc = 100

B

E IE

Fig. P (5.15).

Also draw the load line and locate Q-point on it. Assume VBE = 0.7 V. Solution : Given

VCC = 10 V RC = 10 k RB = 100 k dc = 100 VBE = 0.7 V.

Q-point. Applying KVL to the input section, VCC = IERE + IBRB + VBE IC =

or

IC =

V CC V BE R RC B 10 0.7 10 10 3

100 10 3 100

or

IC = .845 × 103 A

or

IC = .845 mA.

Ans.

and

VCE = VCC ICRC

or

VCE = 10 .845 × 103 × 10 × 103

or

VCE = 10 8.45 VCE = 1.55 V.

Ans.

Q-points = (1.55 V, .845 mA) D.C. load line is shown in the Fig. P (5.16). IC(sat) =

V CC 10 = = 1 mA RC 10 10 3

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BASIC ELECTRONICS ENGINEERING & DEVICES

VCE(cut-off) = VCC = 10 V. IC (mA) 1 mA (1.55 V, .845 mA)

.845 mA

D.C. Load line

1.55 V

10 VCE (V)

Fig. P (5.16).

Example 14. Determine the d.c. bias current and voltage for the d.c. bias current as shown in Fig. P (5.17). + 5V

33 k

1.8 k

dc = 90

Fig. P (5.17).

and also find the stability. Solution :

VCE = 1.1 V IC = 1.06 mA Stability, S = 16.1

Example 15. A silicon transistor with = 100 is to be used in the self-biasing circuit shown in Fig. P (5.18) such that the quiescent point corresponds to VCE = 12 V and IC = 2 mA and RE if VCC = 24 V and RC = 5 k.

215

BIPOLAR JUNCTION TRANSISTOR

VCC = 24 V RC = 5 k R1 = 100 R2 RE

Fig. P (5.18).

Solution : Applying KVL to the output section, VCC = ICRC + VCE + IERE or

VCC = ICRC + VCE + (IC + IB) RE

or

VCC = ICRC + VCE + ICRE +

or

VCC = IC (RC + RE +

V CC V CE IC

or

or

or

or

24 12 2 10 3

12 2 10 3

FG H

= RC + RE 1

IC .RE

RE ) + VCE 1

IJ K

F 1I H 100 K F 101 I H 100 K

RC = RE 1

5 × 103 = RE

RE =

2 2.02 10 3

= .99 × 103 = 990 .

Example 16. If in the case of example 15 it is desired to have S values of R1 and R2 , assuming VBE (active) = 0.65 V.

Ans.

3. Find the limiting

Solution : We know that stability factor in case of potential divider biasing is given by the relation, S =

( 1) ( Rth R E ) Rth R E (1 )

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BASIC ELECTRONICS ENGINEERING & DEVICES

3 =

(100 1) ( Rth 990 ) Rth 990 (1 100 )

RS Where R T

th

R1 R 2 R1 R 2

UV W

3Rth + 299970 = 101 Rth + 9990 or

R th = 2040.6 ohm Rth < 2.041 k for S 3 Also,

R th =

R1 R 2 R1 R 2

Vth = V CC

... (1)

R2 R1 R 2

... (2)

Vth = IBRth + VBE + IERE

... (3)

From eqn. (1), (2) and (3)

Now

or

FG H

R1 R 2 V CC V th R1 R 2

R2 =

V th . R1 V CC V th

Vth =

IC Rth + VBE + (IB + IC) RE

Vth =

2 10 3 × 2.041 × 103 + .7 100 +

or After manipulation we get,

IJ K

R1 =

F 2 10 GH 100

3

=

V CC R V th th

I JK

2 10 3 990

Vth = 2.691 V. R1 = R2

24 2.041 10 3 = 18.203 k 2.691

18.023 10 3 2.691 = = 2.299 k. 24 2.691

Ans.

Example 17. Determine the values of the resistors in figure such that IC = 5 mA, VCE = 8 V, VE = 6 V, S = 10, hfc = 200 and VCC = 20 V, VBE = .6 V.

217

BIPOLAR JUNCTION TRANSISTOR R2 RC C

B

IC

E

VCC = 20 V

IE

R1

RE

Fig. P (5.19).

Solution : From Fig. P (5.19). Voltage at point C, IC RC = VCC VCE VE or IC RC = 20 8 6 = 6 V or IC RC = 6 or

RC =

6 6 = = 1.2 k. IC 5 10 3

Ans.

We know that IB =

IC 5 10 3 = = 0.025 mA. 200

Voltage at point E VE = IE RE 6 = (IC + IB) RE 6 = (5 × 103 + 0.025 × 103) RE RE = Given

6

= 1.194 k.

5.025 10 3

S = 10

RS where R T

10 =

( 1) ( R B R E ) R B R E (1 )

10 =

( 200 1) ( R B 1.194 k ) R B 1.194 k (1 200 )

10RB + 10 (2399.940 k) = 201 (RB + 1.194 k) or

Ans.

RB = 11308.62 Vth = VCC

FG HR

R2 1 R2

IJ K

B

R1 R 2 R1 R 2

UV W

218

BASIC ELECTRONICS ENGINEERING & DEVICES

or

Vth = VCC

RB R1

... (1)

Applying KVL we get, Vth = IBRB + VBE + VE or

Vth = 0.025 × 103 × 11308.62 + 0.6 + 6

or

Vth = 6.883 V. From eqn. (1)

or

R1 =

V CC RB V th

R1 =

20 × 11308.62 6.883

R1 = 32.861 k. R2 =

R1 . V th V CC V th

=

Ans.

32.861 6.883 20 6.883

= 17.243 k.

Ans.

Example 18. In the circuit shown in Fig. P (5.20), determine VBB to saturate the transistor. Given VCE sat = 0.1 V, VBE sat = 0.6 V, hfc = 50 (i.e., = 50). + 12 V

10 k

VBB

Fig. P (5.20).

Solution : From Fig. P (5.20). IC =

or

so,

V CC V CE

( Sat )

RC

IC =

12 0.1 1 k = 11.9 mA

IB =

IC 11.9 = 50 = 0.238 mA

VBB = IBRB + VBE sat

219

BIPOLAR JUNCTION TRANSISTOR

or

VBB = 0.238 × 103 × 10 × 103 + 0.6

or

VBB = 2.38 + .6

or

VBB = 2.98 V.

Ans.

Example 19. For the circuit shown below, given ICBO = 10 µA, hFE = 100. Calculate the value of IC and VO. VCC = 30 V RC = 5 K

R1 = 90 K

VO

C B VBE = 0.6 V E RE = 5 K

R2 = 45 K

Fig. P (5.21).

Solution : Given hFE = 100, ICBO = 10 A. From Fig. P (5.21),

Vth = VBB = 30 × R th = RBB =

45 = 10 V 45 + 90

R1 R 2 90 45 = = 30 K. R1 R 2 90 + 45

IC =

V CC V BE R th RE

or

IC =

( 20 0.6 ) V 30 5 K 100

or

IC = 1.757 mA.

F H

I K

ICEO = ( + 1) ICO = 101 (10 × 106) = 1.01 mA. Total

IC = 1.757 mA + 1.01 mA = 2.767 mA.

Ans.

VO = VCC ICRC or

VO = 30 2.767 × 103 × 5 × 103 = 16.165 V.

Ans.

Example 20. Find the ICO and VCEQ for the following Fig. P (5.22), given dc = 130. (Assume VBE = 0.7 V)

220

BASIC ELECTRONICS ENGINEERING & DEVICES + VCC = 18 V

R1 = 510 k

CC

RC = 9.1 k

+

CC + V1

V0 R2 = 510 k

CE

RE = 7.5 k

–

–

Fig. P (5.22).

Solution : First of all we will draw DC equivalent circuit by open circuiting the capacitors as shown in Fig. P (5.23). VCC

R1

510 k

RC +

V0 R2

510 k

RE –

Fig. P (5.23). DC equivalent circuit of the given circuit.

This circuit can be redrawn using Thevenin’s equivalent in the base circuit, as below in Fig. P (5.24). Here,

Vth = V CC R th =

R2 510 = 18 = 9 V R1 R 2 510 150

R1 R 2 510 510 = = 255 k R1 R 2 510 510

221

BIPOLAR JUNCTION TRANSISTOR ICQ

Rth =

R1R2 R1+R2

B IB

Vth =

VCC.R2 R1+R2

RC

C VCE

+ VBE

VCC = 18 V

– E RE

Fig. P (5.24). Thevenin equivalent circuit of the above circuit.

Applying KVL equation in the input loop Vth = IB Rth + VBE + IE RE ( IE = IC + IB)

V th = IB Rth + VBE + (IC + IB) RE Vth =

or

or

FG H

IC ICQ =

ICQ =

IJ K

IC I Rth V BE I B C R E

FG R H

V th V BE

th

RE

RE

(IC = IB)

IJ K

9 0.7 255 10 130

3

7.5 10 3

7.5 10 3 130

ICQ = 0.872 × 10–3 Amp = .872 mA. Ans. Again applying KVL at the output loop, we get, VCC = ICRC + VCEQ + IERE or

VCEQ = VCC – ICRC + IERE

or

VCEQ = VCC – IC R C R E

or

VCEQ = 18 – .872 × 10–3

or

VCEQ = 3.475 V. Ans.

FG H

RE

IJ K

F 9.1 10 GH

3

7.5 10 3

7.5 10 3 130

I JK

Hence the required values are ICQ = 0.872 mA, VCEQ = 3.475 V. Example 21. What will happen to VCE if R2 in open circuited in the above example.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : The circuit becomes like afer opening the R2 is given below : + VCC = 18 V

R1

RC

+

V0

+

Vth

RE

CE

–

–

Fig. P (5.25).

DC equivalent for this circuit will be as below : VCC

IC RC

RC

IB

IE RE

Fig. P (5.26).

For better understanding this circuit is replaced by a redrawn circuit having two supplies in place of one supply. IC RC R1 IB VCC

+ –

+ IE RE

Fig. P (5.27).

–

VCC

223

BIPOLAR JUNCTION TRANSISTOR

This circuit is similar to the Thevenin equivalent circuit shown in above problem. The only difference is Vth is replaced by VCC and Rth is replaced by R1. By similarty, ICQ =

or

ICQ =

V CC V BE R1 R RE E

F 510 10 GH 130

7.5 10 3

ICQ = 1.507 mA. Ans.

or And

FG H

VCEQ = VCC – ICQ RC R E

103

or

VCEQ = 18 – 1.507 ×

or

VCEQ = 7.103 V. Ans.

NOTE :

BE

18 0.7 3

RE

FG V H I

7.5 10 130

3

I JK

C

= 0.7 V = IB

IJ K

F 9.1 10 GH

3

7.5 10 3

7.5 10 3 130

I JK

Here it may be noted that, VCEQ can not become negative it means base current is too much so that transistor gets saturated and reduces and will not remain 130. VCEQ VCE

(sat)

0.2 V.

Example 22. Consider a DC bias circuit with voltage feedback, given below. Determine the quiescent points ICQ and VCEQ. The of transistor is 90, and cut in voltage is 0.7 V. What will be the effect on ICQ and VCEQ if is increased by 50% ? VCC = 10 V 4.7 K IB

250 K

IE V0

IC C B 0.7 V = VBE

= 90 E 1.2 K

Fig. P (5.28).

224

BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : Apply KVL for the input loop : VCC = 10 = 4.7 × 103 IE + 250 × 103 IB + VBE + IE × 1.2 × 103

FG H

3 10 – 0.7 = 4 .7 10 I C

or

IJ 250 10 K

FG H

IC I IC C

3

IJ 1.2 10 K

3

(10 0.7 )

IC = ICQ =

or

IC

(1 ) ( 4 .7 10 3 1.2 10 3 ) 250 10 3

ICQ =

90 ( 9.3 ) (1 90 ) ( 5.9 10 3 ) 250 10 3

ICQ = 1.06 mA. Ans.

or

Again applying KVL for the output loop, VCC = (IC + IB) 4.7 × 103 + VCEQ + (IC + IB) 1.2 × 103

F GH

–3 VCEQ = 10 1.06 10

1.06 10 –3 90

I JK

4.7 10 3 1.2 10 3

VCEQ = 3.68 V. Ans.

or

If in increased by 50% i.e., = 90 + 45 = 135. Now,

I CQ = I CQ =

VCEQ or

(V CC V BE ) ( 1) ( 4 .7 10 3 1.2 10 3 ) 250 10 3 135 (10 0.7 ) (135 1) ( 5.9 10 3 ) 250 10 3

F GH

–3 = 10 – 1.06 10

1.06 10 –3 135

= 1.19 mA. Ans.

I d4.7 10 JK

3

1.2 10 3

i

VCEQ = 2.93 V. Ans. Example 23. Given IE = 1.2 mA, = 120, and r0 = 40 K ohm. Sketch the (i) Common emitter hybrid equivalent model. (ii) Common base hybrid equivalent model. Solution : Try yourself.

Example 24. Sketch the circuit of a common collector configuration and also the input and output curves. Solution : Try yourself. Example 25. Draw npn and pnp transistors. Label all the currents and show the direction of flow. How are all the currents of a transistor related ? Solution : Try yourself.

225

BIPOLAR JUNCTION TRANSISTOR

Example 26. Find the value of , VCC and RB of the following circuit. + VCC

IC RB

2.7 k

20 µA = IB

C VCE = 7.3 V E

2.1 V

IE .68 k

Fig. P (5.29).

Solution :

IE =

VE RE

or

IE =

2.1 V = 3.088 mA 0.68 k

IE = IC + IB or

IC = IE – IB

or

IC = 3.088 20 × 103 mA

or

IC = 3.068 mA.

we know,

=

(IB = 20 × 10–6 Amp.)

IC 3.068 10 3 = = 153.4. Ans. IB 20 10 6

Apply KVL to the output loop, we get, VCC = ICRC + VCE + IERE or

VCC = 3.068 × 103 × 2.7 × 103 + 7.3 + 3.088 × 103 × 0.68 × 103

or

VCC = 17.684 volts. Ans. Again apply KVL to the input loop, we get VCC = IBRB + VBE + IERE RB =

or

RB =

V CC V BE I E R E IB 17.684 0.7 3.088 10 3 20 10

6

.68 10 3

226

BASIC ELECTRONICS ENGINEERING & DEVICES

RB = 744.2 k . Ans.

or

Example 27. Find Av , Ri and R0 of the following circuit. VCC

I0 RB

RC

CC

CC

+

+

Vi

Ii V0 CE

RE –

–

Fig. P (5.30).

Solution : Try yourself. Example 28. Draw the load line for the following Fig. P (5.31), what is IC at saturation point ? Find VCE at cut off point. + 20 V 3.3 K RC C

RB + 10 V

1M

VCE B

E

Fig. P (5.31).

Solution : Equation for DC load line will be, IC =

V 1 V CC RC CE RC

It cuts the X-axis on output characteristics at, VCE = VCC

( VCE at cut-off)

227

BIPOLAR JUNCTION TRANSISTOR

= 20 volts. It cuts the Y-axis on output characteristics at, IC =

V CC 20 = 3.3 K RC

(IC is at saturation)

= 6.06 mA. Ans. Load line in draw joining two points having co-ordinates i.e., (0, 6.06 mA) and (20 V, 0) as shown in Fig. P (5.32). IC (mA) 6.06 Saturation Point

DC Load Line

Cut of Point

VCE (volts)

O 20 V

Fig. P (5.32).

Example 29. Find VCE and IE in the Fig. P (5.33). + 10 V

3.6 K 10 K = 100 2.2 K 1K

Fig. P (5.33).

FG 0 V IJ H R K CC C

and (VCC , 0)

228

BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : Thevenin’s equivalent circuit is drawn in Fig. P (5.34) for the given circuit. RC Rth = 1.8 K

IC

IB + VBE

–

Vth = 1.8 V

IE

RE

VCC = + 10 V

Fig. P (5.34).

Here,

Vth =

R2 2.2 V CC = 10 = 1.8 volts R1 R 2 10 2.2

R th =

R1R 2 2.2 10 = = 1.8 K R1 R 2 10 2.2

KVL is input loop Vth = IBRth + VBE + IERE We know that So or

IE = (+ 1) IB Vth = IE =

here

IE R + VBE + IERE 1 th V th V BE R th RE ( 1)

Vth = 1.8 V VBE = 0.7 V RE = 1 K R th = 1.8 K = 100 So

IE =

1.8 0.7 = 1.081 mA. Ans. 1800 1000 101

IB =

IE 1.081 = 1 101

= 10.7 A = 1.07 mA.

KVL in output loop VCC = ICRC + VCE + IERE VCE = VCC – ICRC – IERE = 10 – 1.07 × 103 1.081 × 10–3 × 103

229

BIPOLAR JUNCTION TRANSISTOR

= 5.067 volts. Ans. Example 30. Determine Zi , Z0 and Av for the following network in Fig. P (5.35). Given hfc = 110, hie = 1.6 K, hre = 2 × 10–4 and hoe = 20 A/V. 8V

RC = 4.7 K

RB = 470 K

CC

Zi

Fig. P (5.35).

Solution : AC equivalent circuit using C-E, h–parameter model of transistor is drawn in Fig. P (5.36). +

C

B ic

ib Vi

+

hre VCC hfe Ib

+

RB

Vbc

–

– Zi

hoe

Vcc

RC

V0

Z0

–

E Ri

Fig. P (5.36). CE, h-parameter model.

Here,

Rin = h ie

h fe h re R C 1 h oe R C

3 = 1.6 10

110 2 10 4 4.7 10 3 1 20 10 6 4.7 10 3

= 1.51 K ohm Zi = RB

Ri =

R B Ri 470 10 3 1.51 10 3 = R B Ri 470 10 3 1.51 10 3

= 1.50 K ohm. Ans. We know

AV =

FG H

h fe

Z in h oe

1 RL

IJ K

230

BASIC ELECTRONICS ENGINEERING & DEVICES

here

RL = RC So

AV =

We know

Z0 =

here

110

F H

1.5 10 3 20 10 6

h oe

1 4 .7 10 3

I K

= 313. Ans.

1 h fe h re Z in R s

Rs = 0 So

Z0 =

1 20 10 6

110 2 14 4 1.51 10 3

=

10 6 20 14 .57

= 184 K ohm. Ans. Example 31. Determine the dc level of IB, IC and VC for the following circuit Fig. P (5.37). Solution : The level of IB , IC , VC may be obtained as follow: VCC R1

RC

R2

(

C

C Cin (

RE

Fig. P (5.37).

We obtain the IB considering the current eqn. of IB as follows. Applying KVL in the loop of R1 and R2 VCC ICRC + (R1 + R2) IB VBE IERE = 0 IC = IC + IB = IE and we get,

IC = IB IE = ( + 1) IB

Substituting the values, we get, or

VCC IERC (R1 + R2) IB VBE IERE = 0

or

VCC ( + 1) IBRC + (R1 + R2) IB VBE ( + 1) IBRE = 0

or

IB [( + 1) RC + R1 + R2 + ( + 1) RE] = VCC VBE IB =

a 1f a

V CC V BE RC R E R1 R 2

f

+ 1 or

IB =

V CC V BE R1 R 2 ( R C R E )

IC = IB

6 Sometimes when we are not able to hear a stereo system, we increase the volume, when the picture on our television is too dark, we increase the brightness control. In both of these cases, we are talking a relatively weak signal and making it stronger by changing the d.c. power into a.c. power. Thus, the process of increasing the power of an a.c. signal is called amplification. One things should be always kept in mind that an amplifier never changes the shape of the actual signal i.e., input signal. However, it increases the level of the actual signal or in other words an amplifier may also be defined as a device, which produces a larger electrical output of a similar characteristics than that of the input parameters. It increases the magnitude of current or voltage input by means of energy drawn from an external source i.e., Battery. As discussed above, an amplifier needs a source of energy for amplification. This may be provided by a battery or a d.c. source resulting from a rectifier and filter. An amplifier also contains at least one active device. This may be an electron tube, BJT or FET transistor, which can provide a control function. Basically the active device converts the energy from the d.c. source into energy at the output of the amplifier, which is proportional to the input signal. The amplifier, in which the instantaneous output signal is directly proportional to the corresponding input signal, is called a linear amplifier. On the other hand, an amplifier, in which the output is not directly proportional to the input, is called a nonlinear amplifier.

The linear amplifiers may be classified according to their mode of operation : Small-signal amplifier As based on the input Large-signal amplifier Common-emitter (CE) amplifier As based on transistor configuration

Common-base (CB) amplifier Common-collector (CC) amplifier

231

Comp-1/Laxmi-5/Computer/Revision/Belec-6—10.5.07

232

BASIC ELECTRONICS ENGINEERING & DEVICES

Class-A amplifier As based on biasing conditions

Class-B amplifier Class-AB amplifier Class-C amplifier Single-stage amplifier

As based on the number of stages Multi-stage amplifier The amplifier can be analysed for its performance by the following two methods : (i) Graphical method. (ii) Equivalent circuit method. Graphical method. For analysing an amplifier by the graphical method, we need the output characteristics of the transistor. When the a.c. voltage (i.e., signal) is applied to the input, the base current varies. The corresponding variations in collector current and collector voltage can be seen on the characteristics. As the graphical method involves no approximations, therefore the results obtained by this method are more accurate than the equivalent circuit method.

Fig. 6.1(a) shows a basic circuit of an CE amplifier, which uses potential divider biasing here potential divider biasing is used as its circuit is simple and provides good stabilization of the operating point. If this circuit is to amplify a.c. voltages, some more components must be added to it. The result is shown in Fig. 6.1(b), here we have added three capacitors. + VCC + VCC

RC R1

R1

RC

CC

Cb +

V0

Vi ~

RLC

R2

R2 RE

RE

CE

–

(a) Potential divider biasing circuit

(b) Basic common emitter amplifier circuit

Fig. 6.1.

As we have discussed that here circuit uses three capacitors namely : (i) Cb called blocking capacitor. (ii) CC called coupling capacitor. (iii) CE called bypass capacitor.

V0

233

TRANSISTOR AMPLIFIER

A coupling capacitor passes an a.c. signal from one side to the other, at the same time, it does not allow the d.c. voltage to pass through. Hence it is also called blocking capacitor, usually the main function of coupling capacitor in the cascading of the amplifier (i.e., multistage amplifier). Thus we can say that coupling capacitor and blocking capacitor do the same job, however its working time is different. In other words, we can say that blocking capacitor used to provide good stability to the circuit as it blocks the a.c. signal at the time of biasing of the circuit. The main function of bypass capacitor (CE) to bypass all the a.c. currents from the emitter to the ground. If CE is not put in the circuit, the a.c. voltage developed across RE will affect the input a.c. voltage. Such a feedback of a.c. signal is reduced by putting the capacitor CE, resulting increases the gain of the amplifier i.e., transistor. As we 1 know that capacitance is given by the relation XC = 2fC which depends upon the

value of capacitor and the frequency of the signal. For a particular circuit arrangement value of capacitor is fixed, now we have full control on the frequency of the signal. For a high frequency signal capacitance XC becomes lowest as compared to RE. As a practical guide, we make the reactance of the capacitor CE at the lowest frequency, not more than one-tenth the value of RE i.e., XCE

RE 10

... (6.1)

The resistor R0 represents the resistance of whatever is connected at the output. To what extent an amplifier enlarges signal is expressed in terms of its voltage gain. The voltage gain of an amplifier is given as : Av =

V0 Output a.c. voltage Input a.c. voltage = V i

... (6.2)

One things should be always kept in mind that amplifier never changes the frequency of the input signal. However, it increases the amplitude of the input signal.

In order to calculate the current gain and voltage gain by the graphical method, we consider a typical amplifier circuit as shown in Fig. 6.1(b). In this circuit let the values of R1 = 33 k, R2 = 3.3 k, Vi = 5 mV, RC = 1 k, VCC = 9 V, RE = 100 , and CE = 250 F, R0 = 470 . The output characteristics of this circuit is shown below in Fig. 6.2. The simplest way to analyse the circuit is to split the analysis into the following two parts. (1) d.c. analysis. (2) a.c. analysis.

234

BASIC ELECTRONICS ENGINEERING & DEVICES 10

ic (mA)

9

DC load line

8

IB = 60

AC load line

A

A 50

7 40 A

6

5.1 mA

Q1

5 4.0 mA

0

2.9 mA

2 t

Q

4 3

30 A

2 t

20 A 10 A

Q2

2 0 A

1 0

0

1

2

3

4

5

6

7

8

9

4.1 4.5 4.9

10 vCE (V)

2 t

Fig. 6.2. Graphical method for calculating gain.

The following procedure is adapted for the d.c. analysis : 1. First of all, reduces the a.c. sources to zero. It means the voltage source is replaced by a short circuit and the current source is replaced by an open-circuit. 2. Now open all the capacitors, as they block direct current. The circuit, which remains after applying the above two steps, is called a d.c. equivalent circuit. The d.c. equivalent circuit for the Fig. 6.1(b) is shown below in Fig. 6.3. + VCC

R1

RC +

V0

R2 RE –

Fig. 6.3. D.C. equivalent circuit of Fig. 6.1(b).

The following procedure is adapted for the a.c. analysis : (i) First of all, reduces the d.c. sources to zero. It means that a voltage source is replaced by a short-circuit and a current source by an open circuit.

235

TRANSISTOR AMPLIFIER

(ii) Now short all the capacitors as they pass alternating current. (iii) Then replace the transistor with its small signal (which will discussed later) equivalent circuit. The circuit, which remains after applying the above three steps, is called an a.c. equivalent circuit. The circuit can be used to determine the a.c. currents and voltages, which are required for analysis. The a.c. equivalent circuit for the Fig. 6.1(b) is shown below in Fig. 6.4. R1R2 R1 + R2

Vcc.R2 R1 + R2

R2

C

+

RC

E

RO

V0

–

Fig. 6.4. a.c. equivalent circuit of Fig. 6.1(b).

Now, we first plot the d.c. load line on the output characteristics (as shown in Fig. 6.2). The equation of this d.c. load line is given by the relations : VCC = ICRC + VCE + IERE or

VCC = VCE + IC (RC + RE)

or

IC =

{ IC

IE }

V CC V CE ( RC R E ) ( RC R E )

V CC The line is drawn by simply joining the points. (VCC, 0) and (0, R ). This may dc be seen that the slope of the d.c. load line is

1 . Rdc

Here Rdc = RC + RE. Thus the two points for plotting the d.c. load line are (9 V, 0) and (0, 8.2 mA). Let us assume that the biasing arrangement is such that the d.c. base current is 30 A. The quiescent operating point Q is given by the intersection of the d.c. load line and the output characteristics corresponding to IB = 30 A. The d.c. collector current and collector-to-emitter voltage of the Q-point may be seen to be 4 mA and 4.5 V respectively. When we apply an a.c. input Vi, the circuit behaves like the one shown in Fig. 6.1(b). It is clear that Rac = RC RO (i.e., here 1 k 470 = 320 ). The a.c. load line will have a slope of

1 . Since the Q-point describes the zero-signal conditions of the Rac

circuit, the a.c. load line should also pass through Q-point. To draw such a line we first draw any line AB with the given slope. We can then draw the a.c. load line parallel to this line and passing through the Q-point.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Fig. 6.5 explains how a line with the given slope

Slope =

tan =

1 is drawn. Rac

1 = tan = tan (180 ) = tan Rac

1 Rac

OB OA

=

Let us take OA = 1 V. Then OB =

OA 1 = = 0.0031 A = 3.1 mA. 320 Rac

After locating the points B and A, line AB whose slope = 1/Rac can be drawn.

B ic (mA)

O

vC (volts)

A

Fig. 6.5. To draw a line with a slope of 1/Rac.

Suppose an a.c. voltage of 5 mV is applied at the input. This corresponds to a peak-to-peak variation of 5 × 2 × 2 = 14.14 mV. Assume that the input characteristics of the transistor are such, as to produce a 20 A peak-to-peak variation in the base current corresponding to this input a.c. voltage. When the base current varies within these limits (from 20 µA to 40 µA), the instantaneous operating point moves along the a.c. load line between points Q1 and Q2. The corresponding variations in collector current and collector-to-emitter voltage are shown in Fig. 6.2. The collector current varies between the limits 2.9 mA to 5.1 mA. The collector-to-emitter voltage varies between the limits 4.1 V to 4.9 V. The current gain and the voltage gain of the amplifier are given as : Current gain =

Voltage gain =

I C (max) I C (min) I B (max) I B (min) V CE

(max)

=

V CE (min)

V i (max) V i (min)

( 5.1 2.9 ) mA = 110 ( 40 20 ) A

=

( 4.9 4.1) V = 56.58 14 .14 mV

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TRANSISTOR AMPLIFIER

? 1. What are the different classification of amplifiers ? 2. List different classification of amplifier on the basis of biasing. 3. What is the basic difference between the graphical method and the equivalent circuit method ? 4. What is the main function of blocking capacitor, coupling capacitor and bypass capacitor ? 5. What do you mean by gain ? 6. Explain the procedure adapted for the a.c. analysis and d.c. analysis. 7. Explain why common emitter configuration is most widely used as an amplifier.

Very often transistor is used in one or another form in almost all amplifier circuits. Biasing arrangement, resistances used and capacitances of junctions altogether force to analyze the behaviour of BJT amplifier in different configurations and working conditions. As we know that transistor parameters like , ICBO etc. vary considerably by change in temperature, they can’t be uniquely used to describe efficiently the performance of the BJT in the amplifier circuits. So, in order to analyze the various amplifier circuits using BJT, we will use h-parameters. For low frequency applications, various parameters will be defined and interpreted physically in forthgoing topics. The equivalent model for BJT based upon these parameters will be drawn. A very clear procedure for a.c. and d.c. analysis for BJT amplifier and evaluation of performance parameters (voltage gain, current gain, input impedance and output impedance) of transistor are the basic ideas to be discussed in this unit. Furthermore, we will discuss about hybrid model (for high frequency applications) and representation of tuned amplifiers, cascade amplifier will also be discussed.

Here, first of all we learn about the representation of electrical networks, in general, using h-parameters and then the model so obtained is implemented for the transistor amplifier. For this purpose, let us consider the two port network given in Fig. 6.6 as below : 1 I/P Port V1 1

I1

I2

2 V2 O/P Port 2

Fig. 6.6. Representation of general two port (four terminal) electrical network.

h-parameter representation is often used in modelling of electronic components and circuits, particularly transistors. The name hybrid parameter comes out from the fact that here we use both types of terminal conditions i.e., open circuit and short circuit for the purpose of evaluating the unknown parameters. In this form of

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BASIC ELECTRONICS ENGINEERING & DEVICES

representation, the voltage of the input port and the current of the output port are expressed in terms of the current of the input port and the voltage of the output port. Thus, mathematically we can say that, (V1, I2) = f (I1, V2)

... (6.3)

The above function f shows that in the h-parameter representation, the input voltage and output current are to be expressed as input current and output voltage. The function defined by eqn. (6.3) can be represented in the form of matrix as under :

LMV OP = LMh N I Q Nh 1

11

2

21

h12 h 22

OP LM I OP Q NV Q 1

... (6.4)

2

The matrix representation of eqn. (2) yields following two equations : V1 = h11 I1 + h12 V2

... (6.5)

I2 = h21 I1 + h22 V2

... (6.6)

Here, in eqn. (6.4); the matrix other than [I1, V2] represents the h-parameter matrix for the electrical network depicted in Fig. 6.6. Thus, the parameters h11, h12, h21 and h22 which relate the input and output variables of the two port network are called h-parameters. Now, we can draw easily the equivalent circuit of the Fig. 6.7 using eqns. (6.5) and (6.6) as under : I1

+ V1 –

h11

h12 V2 Controlled voltage

I2

h21 I1

Controlled current

h22

+ V2 –

Fig. 6.7. h-parameter equivalent circuit.

As the name suggests, a two port network consists of two ports i.e., input port and output port. We can say that in reference of amplifier circuits working linear (active) region ; at input port, the signal is applied and at the output port we get the amplified or replicated version of the input signal. With the help of h-parameters given in previous subsection, the two port network can be easily replaced by its equivalent hybrid model. The analysis of this hybrid model yields the required performance parameter of the amplifier circuit under consideration.

Considering again the equations given by (6.5) and (6.6) V1 = h11 I1 + h12 V2 I2 = h21 I1 + h22 V2

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TRANSISTOR AMPLIFIER

As mentioned earlier, the representation of h-parameters utilizes both terminal conditions. Now, if we arbitrarily set V2 = 0 i.e., short circuiting the output terminals and solve for h11, the following result is obtained. h11 =

V1 I1

V2 0

V1 = h11 I1 + h12 V2 at V2 = 0

Clearly, the unit of h11 is ohms, because the ratio indicates that the parameter h11 is an impedance parameter. Since, it is the ratio of the input voltage to the input current with the output terminals shorted, it is called the short-circuit input impedance parameter. The subscript 11 of h11 defines the fact that the parameter is determined by a ratio of quantities measured at the input terminals. Now, if I1 in eqn. (6.5) is set to zero by opening the input port, the following relation is obtained : h12 =

V1 V2

I1 0

V1 = h11 I1 + h12 V2 at I1 = 0

The parameter h12, being the ratio of the input voltage to the output voltage is a unit less quantity. Clearly, it is defined and obtained under open circuit condition, so it is called the open-circuit reverse transfer voltage ratio parameter. The subscript 12 of the h12 reveals that the parameter is a transfer quantity determined by a ratio of input to output measurements. Now considering eqn. (6.6) as under : I2 = h21 I1 + h22 V2 If in above equation, V2 is set to zero by again shorting the output terminals the following result is obtained for h21 : h21 =

I2 I1

V2 0

I2 = h21 I1 + h22 V2 at V2 = 0

It is to be noted that we now have the ratio of an output quantity to an input quantity. The term forward will now be used rather than reverse as indicated for h12. The parameter h21 is the ratio of the output current to the input current with the output terminals shorted. It is normally called as the short-circuit transfer current ratio parameter. The last parameter, h22, can be found by again opening the input leads to set I1 = 0 and solving for h22 the eqn. (6.6) :

I2 h22 = V 2

I1 0

I2 = h21 I1 + h22 V2 at I1 = 0

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BASIC ELECTRONICS ENGINEERING & DEVICES

Since, it is the ratio of the output current to the output voltage, it is the output conductance parameter. The subscript 22 in h22 reveals that it is determined by a ratio of output quantities. The units of h22 is of conductance i.e., ohm1 or mho or siemens. Instead of using digits 1 and 2 for h-parameter designations, we now will use following relations in all forthgoing subtopics :

h11 h12 h21 h22

input resistance hi reverse transfer voltage ratio hr forward transfer current ratio hf output conductance or admittance ho

Depending upon the transformed notation of h-parameters i.e., hi, hr, hf , ho, the complete hybrid model for a transistor can be generalized as under in Fig. 6.8. Ii

+

hi

I0

+

+ Vi

hr V0

–

hf Ii

h0

V0

–

–

Fig. 6.8. Complete hybrid-equivalent circuit for transistor.

Here, Vi input voltage Ii input current Vo output voltage Io output current Now, we shall discuss the equivalent hybrid models for each of the configurations of transistor i.e., CE, CC or CB. The circuit of Fig. 6.9 is applicable to any linear three-terminal device with no internal independent sources. The transistor is a three terminal device i.e., emitter, base and collector. For the purpose of converting a three terminal electronic device into an equivalent two port electrical network one terminal must be made common to both input and output terminals. Thus, we obtain three configurations in which a transistor can be placed in an amplifier circuit. These are as under : 1. Common emitter (CE) configuration. 2. Common collector (CC) configuration. 3. Common base (CB) configuration. The h-parameters, however, will change with each configuration. To distinguish which configuration has been used or which is available, a second subscript has been added to the h-parameter notation. * The first letter of subscript defined in h-parameters takes the position in Numerator and the second in Denominator. If Numerator has I subscript we use reverse otherwise we use forward.

241

TRANSISTOR AMPLIFIER

The following Table (6.1) better describes the arrangement for configurational distinction : Approximate conversion formulas for hybrid parameters Common collector to common emitter hic = hie hrc = 1 hfc = (1 + hfe) hoc = hoc Common base to common emitter hib =

h ie 1 h fe

hrb =

h ie h oe hfe 1 h fe

hfb = hob =

h fe 1 h fc h oe 1 h fe

Table 6.1 S. No.

Particular parameter

CE

CC

CB

1.

hi

hie

hic

hib

2.

hr

hre

hrc

hrb

3.

hf

hfe

hfc

hfb

4.

ho

hoe

hoc

hob

Common emitter configuration C

+

IC Ib B

Vce

+ Vbe –

Ie

Ib

Ic

hie

C

B + hre Vce –

Vbe

hoe hfe Ib

–

+

Vce

– Ie

E

E

(a) Graphic symbol

(b) Hybrid equivalent circuit

Fig. 6.9.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Common base configuration

E

Ie

IC

+

+ Veb

C

C hrb Vcb

V

Vcb –

Ic

hib

Ie

+ E

–

+ hob

–

hfb Ie

–

Ib

– Vbe

B

+

Vcb

Ib B

(a) Graphic symbol

(b) Hybrid equivalent circuit

Fig. 6.10.

Similarly, we can draw the hybrid equivalent circuit for CC configuration where subscript c will be used for second designation. The parameter hfe For a common emitter connection the output characteristics are shown in Fig. 6.11 as below : ic

ib2

ic2 ICQ

B Q

A

ic1

ib = Ib ib1

VCQ

VCE

Fig. 6.11. Determination of hf and ho from the CE output characteristics. e

e

From the definition of hfe : hfe =

i C iC i B iB

=

iC 2 iC1 i B 2 i B1

The current increments are taken around the Quiescent point Q which corresponds to the base current iB = IB and to the collector voltage VCE = VC. The parameter hfe is the most important small signal parameter of the transistor. This common-emitter current transfer ratio, or CE alpha () is also written as e or , and called the small-signal beta () of the transistor. The relationship between = hfe and hFE (large signal beta).

243

TRANSISTOR AMPLIFIER

The parameter hoe By the definition of output admittance discussed earlier, we have, hoe =

i C iC V C VC

I E constt.

The value of hoe at the Quiescent-point Q is given by the slope of the output characteristics curve at that point. This slope can be evaluated by drawing the line AB in Fig. 6.11 tangent to the characteristics curve at the point Q. Similarly, we can find out the parameters hie and hre graphically from the input CE characteristics, in a manner analogous to that illustrated above for hfe and hoe. Hybrid-parameter variations Generally it is assumed that once the transistor has been manufactured, the specified h-parameters for the transistor do not change. But, in actual practice, it is not so. The h-parameters vary greatly as the Quiescent point shifts up and down. Generally, it is seen that the h-parameters are affected by the change in following quantities : 1. IB 2. VCE 3. Junction temperature Following table depicts the values of h-parameters for three different transistor configurations of a typical BJT : Table 6.2. Typical h-parameter values at IE = 1.3 mA Parameter

CE

h11 = hi

1,100 104

CC

CB

1,100

21.6

1

2.9 × 104

h12 = hr

2.5 ×

h21 = hf

50

51

0.98

h22 = ho

24 A/V

25 A/V

0.49 A/V

1 h0

40

40 k

2.04 M

A transistor amplifier typically consists of a transistor, external load and the source of signal as depicted in Fig. 6.12 shown on next page. Proper biasing arrangement must be prevailed before applying the signal because in absence of it there is no meaning of amplification. The transistor appearing in above network can have any of the three configurations. This transistor, in general, can be replaced by its small signal hybrid model. The Fig. 6.13 is valid for any type of the load, whether it be pure resistance, an impedance, or even another transistor. This is true

244

BASIC ELECTRONICS ENGINEERING & DEVICES

because transistor hybrid-model has been derived irrespective of the external circuit in which the transistor is employed. RS

I1

1

+

+

+ VS –

V1

I2 IL

V2

Transistor

–

–

ZL

1

Fig. 6.12. A basic amplifier circuit.

Here it is noteworthy that the h-parameters of transistor don’t get changed by the presence of external circuit. RS

1

Hi

I1

+ VS –

I2

hr V2

hf I1

2

ZL VL = V2

h0

1

+

2

Hybrid model of the transistor

Source of signal

–

External load

Fig. 6.13. The transistor in Fig. 6.12 replaced by its h-parameter model.

Following quantities are of utmost interest while analyzing the amplifier circuit : (a) Current gain (b) The input impedance (c) The voltage gain (d) The output impedance. Now, we shall determine each performance parameter in succession. Care must be taken that all these expressions so obtained are for transistor, not for the amplifier circuit as a whole. The current gain or current amplification AI The current gain of a transistor amplifier, AI is defined as the ratio of output to input currents or

I2 IL AI = I = I 1 1

(

IL and I2 are in opposite direction)

Referring to Fig. 6.13, we have I2 = hf I1 + ho V2 Substituting V2 = I2ZL in above expression, we obtain

(Using KCL)

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TRANSISTOR AMPLIFIER

I2 = hf I1 + ho ( I2ZL) or

I2 (1 + hoZL) = hf I1

or

hf I2 = I1 1 ho Z L

or

A1 =

hf I2 = I1 1 ho Z L

The input impedance Zi The resistance RS appearing in Fig. 6.12 and Fig. 6.13 represents the signal-source resistance. The amplifier input impedance is obtained by looking into the amplifier input terminals (1, 1) and is expressed as :

V1 Zi = I 1 Applying KVL in input side of Fig. 6.13 we have V1 = hi I1 + hr V2 Hence,

Zi =

hi I 1 hr V2 V2 = hi + hr I1 I1

Again, substituting above expression V2 = I2 ZL = AI I1 ZL Zi = hi + hr AI ZL Zi = h i

Here AI is replaced by

hf 1 ho Z L

h f hr L ho

and ZL is replaced by

1 . L

From above it is clear that the input impedance is a function of the load impedance. Voltage amplification or voltage gain, AV The ratio of output voltage V2 to input voltage V1 gives the voltage gain of the transistor or equivalently. AV =

V2 V1

We already have, V2 = I2 ZL = AI I1ZL

246

BASIC ELECTRONICS ENGINEERING & DEVICES

AV =

AI I 1 Z L AI Z L = V1 V1 I1

FG IJ H K

=

AI Z L Zi

* Cor. The voltage amplification, AV , taking into account the resistance RS of S the source. This overall voltage gain AV is defined by S

AV = S

V2 V 2 V1 V1 = = AV VS VS VS VS

The value of V1 can be calculated using following input circuit of transistor amplifier : RS

I1

+ VS –

1

+ V1

Zi

–

1

Fig. 6.14. Input circuit of a transistor amplifier using Thevenin’s equivalent.

Now, referring to Fig. 6.14 V1 =

Then,

AV = S

VS Z i V i RS

{Using voltage-divider rule}

AV Z i AI Z L = Z i RS Z i RS

It is to be notable here that if RS = 0 the AV reduces to AV. S

Hence, V is the voltage gain for an ideal voltage source. The current amplification AI , taking into account the source resistance RS S

If the input source is a current generator with a resistance RS in parallel as in Fig. 6.15 below, then this overall current gain AI is defined by S

AI = S

I2 I 2 I1 I1 = = AI IS I1 I S IS

Where AI also called current gain for the circuit S

1 + IS

RS

+ Zi

V1

– 1

–

Fig. 6.15. Norton’s equivalent for the source.

247

TRANSISTOR AMPLIFIER

Referring to Fig. 6.15, I1 =

I S RS Z i RS

AI =

A I RS Z i RS

{Using current-division rule}

and hence,

S

It is to be that noted here that if AI AI. S

Hence, AI is the current gain for an ideal current source (one with infinite source resistance). Imp.

AV = AI S

S

ZL RS

This relationship is obtained by making use of expressions for AI

S

and AV . S

The output admittance

1 By definition, the output impedance Zo = is obtained by setting the source 0 voltage VS to zero and the load impedance ZL to infinity and by driving the output terminals from a generator V2.

Let us assume that the current drawn form V2 is I2, then 0 =

I2 with VS = 0 and R2 = V2

We have already, 0 = hf

Due to Norton’s equation,

I2 + ho and V2

Due to Thevenin’s equation, RS I1 + hi I1 + hr V2 = 0 or

I1 V2

=

hr h i RS

Thus, from initial expression o = ho

h f hr h i RS

It is interesting to note that the output admittance is a function of the source resistance. If the source impedance is resistive, as we have assumed, then o is a real (i.e., conductance).

248

BASIC ELECTRONICS ENGINEERING & DEVICES

For quick review, following Table 6.3 must be memorized : Table 6.3. Small signal analysis of a transistor amplifier AI =

hf 1 ho Z L

Zi = hi + hr AI ZL

AV =

AI Z L Zi

o = h o

AV = S

AI = S

h f hr

=

h i RS

AV Z i

=

Z i RS A I RS Z i RS

1 Zo

AI Z L Z i RS

= AV

S

RS ZL

Procedural analysis of a transistor circuit Upto now we have studied about the various transistor configurations, various biasing techniques and a sophisticated tool (h-parameter) for analysis of transistor circuits. This section basically deals with the analysis of transistor circuit in a very lucid manner. There are many transistor circuits which do not employ simply CE, CB or CC configurations. Every configuration has its own advantages and disadvantages. There may be requirement of feedback from output to input in any manner or there may be more than two transistors connected in cascade. So, an analytic determination of the small-signal behaviour of complicated amplifier circuits may be made by following these simple rules : 1. Draw the actual wiring diagram of the circuit. 2. Designate the points, B, C and E for base, collector and emitter respectively. 3. Locate these points as the start of the equivalent circuit. Maintain the same relative positions as in the original circuit. 4. Replace each transistor by its h-parameter model. 5. Transfer all circuit elements (resistors, sources, capacitors, external load etc.) from the actual circuit to the equivalent circuit of the amplifier. 6. Replace each independent d.c. source by its internal resistance. The ideal voltage source is replaced by short circuit and the ideal current source by an open circuit. 7. Solve the resultant linear circuit for mesh or branch currents and node voltages by applying Kirchhoff’s current and voltage laws.

? 1. What do you mean by hybrid ? 2. What are the different hybrid parameters ?

249

TRANSISTOR AMPLIFIER 3. Draw the equivalent circuit of h-parameter model. 4. List conversion formulas for hybrid parameters under different configurations.

5. List procedural analysis for a.c. and d.c. equivalent of different transistor configuration. Using h-parameters.

The circuit diagram of common collector transistor amplifier is shown in Fig. 6.16. This configuration is also called the emitter follower, because its voltage gain is close to unity, and hence a change in base voltage appears as an equal voltage, change across the load at the emitter. In other words, the emitter follows the input signal. It is shown below that the input impedance Ri of an emitter follower is very high and the output impedance Ro is very low. Hence the most common use for the common collector (CC) configuration is as a Buffer stage which performs the function of resistance transformation (from high to low resistance) over a wide range of frequencies, with voltage gain close to unity. In addition, the emitter follower increases the power level of the signal. +

VCC

C

RS

B + Ib

+ VS –

IC

Vi

–

Ri

RO

E

+ RL

VO –

Fig. 6.16. A common-collector or emitter follower.

Current gain

AI =

h fc 1 h fc IC = = Ib 1 h oc R L 1 h oc R L {from approximate conversion formula}

Input impedance

Ri =

Vi Ib

= hic + hrc AI RL = hic + AI RL

( hrc = 1)

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BASIC ELECTRONICS ENGINEERING & DEVICES

Voltage gain

AV =

Vo Vi

=

AI R L

= 1

Ri

h ic Ri

(slightly less than one and no phase reversal between input and output voltages). o = h oc

Output admittance,

o = h oc

or

h rc .h fc h ic RS

1 h fe h ic RS

1 h fe h ie R S

(1) Voltage gain 1, no phase reversal. (2) Very high input impedance. (3) Very low output impedance. (4) Uses negative voltage series feedback which increases good stability.

(1) As an impedance matching device between a source of high internal impedance and a load of low impedance. (2) Since current gain is high. It can be used as a current amplifier. (3) As a buffer stages between oscillator and load to avoid the effect of loading on the oscillator.

The circuit diagram of common-emitter transistor amplifier is shown in Fig. 6.17. This configuration provides adequate voltage gain as well as current gain that’s why this configuration is most widely used for the intermediate stages in cascaded amplifier. +V

CC

IC RC RS

C

Ib B

+

+ E + VS –

VO

Ie

Vi RI

RO

–

Fig. 6.17. Common-emitter configuration.

–

251

TRANSISTOR AMPLIFIER

Now, in order to describe voltage gain, current gain, input impedance and output impedance, the above circuit is replaced by its h-parameter model. (i ) Current gain or current amplification. AI for the transistor amplifier stage, AI is defined as the ratio of output to input currents, or AI =

IC

h fe

=

Ib

{where RL = RC

1 h oe R L

R0 }

(ii ) Input impedance, (Ri). The resistance RS in Fig. 6.17 represents the signalsource resistance. The impedance we see looking into the amplifier input terminals is the amplifier input impedance Ri, or Ri = or

VI Ib

Ri = hie + hre AI . RL

(iii ) Voltage gain, or voltage amplification, (AV ). The ratio of output voltage to the input voltage gives the voltage gain of the transistor, or

or

AV =

Vo Vi

AV =

AI . R L Ri

(iv) Voltage amplification AV , taking into account the resistance RS of the source S the overall voltage gain AV is defined by S

AV = S

or

Vo Vi = AV . VS VS

Ri R i RS

AV = AV . S

(v) The current amplification, AI AI = S

or

IC IS

AI = AI . S

S

=

AI . R L R i RS

taking into account the source resistance RS

= AI .

Ib Is

Rs R S Ri

(vi ) The output admittance, (o). By definition the output impedance Zo =

1 o

is

obtained by setting the source voltage VS to zero and the local impedance to infinity. o = hoe

h fe h re h ie R S

252

BASIC ELECTRONICS ENGINEERING & DEVICES

Note that the output admittance is a function of the source resistance. If the source impedance is resistive, then o is real (a conductance).

Example 1. Determine the value of h-parameters for the circuit shown below in Fig. P (6.1).

2

1

4

6 4

2

1

Fig. P (6.1).

Solution : Parameter h11 and h21 We know that the values of h11 and h21 can be determined by putting a short circuit across the output terminals of the given circuit. i1 1

i2

N

2

4

6 4

2

1

Fig. P (6.2).

h11 = 6 + (4 = 6 +

4) {Input resistance looking into the terminals 11}

4 4 = 8 . Ans. 4 + 4

It may be noted that the input current is divided into two equal parts at point N. A current of i1/2 flows outwards and i1/2 flows downwards. The output current i2 = i1/2

i2 i1 / 2 1 h21 = i = = = 0.5. Ans. i 2 1 1

Parameters h12 and h22 We know that the values of h12 and h22 may be determined by keeping the input terminals open and applying a voltage source V2 across the output terminals as follows :

253

TRANSISTOR AMPLIFIER

i1

1

2

N

i2

4

6 V1

4

V2

N

1

2

Fig. P (6.3).

Due to the open input i1 = 0. The current flowing through 6 resistor is zero, and hence there is no voltage drop across it. The voltage (V2) produces a current (i2) in the circuit. This current will produce equal voltage drops across the two 4 resistors. The voltage drop across the 4 resistor connected between N and N appears as the V1. Thus,

V1 =

V2 2

V2 / 2 V1 h12 = V = V = 0.5. Ans. 2 2

The output resistance (i.e., the resistance looking from the output terminals 2, 2 with input open) = 4 + 4 = 8 h22, output conductance 1 1 = Z = = 0.125 mho. 8 0

Ans.

Alternative method Assuming V1 and V2 as input and output voltages respectively. Also, I1 and I2 are input and output currents respectively. Applying KVL in input side. V1 = 6 I1 + 4 (I1 + I2) V1 = 10 I1 + 4 I2

... (1)

Similarly applying KVL in output side V2 = 4 I2 + 4 (I1 + I2) V2 = 4 I2 + 4 I1 + 4 I2 V2 = 4 I1 + 8 I2 From eqn. (2),

I2 =

V2 4 I 1 8

Substituting this result in eqn. (1) V1 = 10I1 + 4

(V 2 4 I 1 ) 8

... (2)

254

BASIC ELECTRONICS ENGINEERING & DEVICES

= 10I1 +

V2 4 I1 2 2 V2 2

V1 = 8 I1 + Now, comparing above with

V1 = h11 I1 + h12 V2 We have,

h11 = 8 h12 = 0.5

Similarly,

I2 =

V2 4 I1 8 8

h21 = 1.25 h22 = 0.125

Thus, we obtain same results. Example 2. Determine the h-parameter for the circuit shown below in Fig. P (6.4). I2

I1 3

2 6

V1

V2

Fig. P (6.4).

Solution : Applying KVL in the input and output terminal. V1 = 3 I1 + 6 (I1 + I2) = 9 I1 + 6 I2

... (1)

V2 = 2 I2 + 6 (I1 + I2) = 6 I1 + 8 I2

... (2)

On comparing eqn. (1) and (2) with standard h-parameter equation V1 = h11 I1 + h12 V2 and V2 = h21 I1 + h22 I2 we get h11 = 9,

h12 = 6

h21 = 6,

h22 = 8

Ans.

Example 3. Find the CC h-parameters in terms of the CE h-parameters. Solution : In CE configuration, Vbe = hie ib + hre Vce and ic = hfe ib + hoe Vce

... (1) ... (2)

By KCL for any configuration ib + ic + ie = 0 or

ic = (ib + ie)

... (3)

255

TRANSISTOR AMPLIFIER

For CE circuit, Vbe = Vbc + Vce

... (4)

= Vbc Vec Putting these values in (1) Vbc Vec = hie ib + ( hre Vec)

Vbc = hie ib + (1 hre) Vec (ib + ie) = hfe ib + hoe ( Vec)

ie = (1 + hfe) ib + hoe Vec

In CC configuration we know that Vbc = hie ib + hrc Vec and ie = hfe ib + hoc Vec Comparing eqns. (2), (3) and (4), we get hic = hie hrc = 1 hre 1 hfc = (1 + hfe) hoc = hoe. Ans. Example 4. In a single stage amplifier the h-parameter hic = 1.1 k, hrc = 1, hfc = 51, hoc = 25 A/V, Calculate : AI , AV , AVS , Ri and Ro for CC configuration with RS = RL = 10 k Solution :

AI =

=

h fc 1 h oc R L

51 1 ( 25 10 6 10 10 3 )

Ri = hic + hrc AI RL = 409.1 k. AV =

= 40.8. Ans.

AI R L 40.8 10 4 = = 0.997. Ri 409.1 10 3

o = hoc

h fc h rc h ic R S

= 25 × 106 +

( 51) (1) 1100 + 10,000

= 4.62 × 103 mho.

Ans.

Ans.

Ans.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Thus,

Ro =

AVS =

=

1 o

= 216

AV Ri Ri RS

0.998 + 409.1 409.1 + 10 Ans.

= 0.974.

Example 5. Draw the equivalent circuit for CE and CC configurations subject to the restriction that RL = 0. Show that the input impedances of the two circuits are identical. Solution : B

hie

C

Ib

+

Vbe

hre, Vce = 0

Ri

–

hfe ib

hoe

RL = 0

E

Fig. P (6.5a). CE hybrid model. hic

B

Ri

E

ib

Vbc

+ hrc, Vec = 0

–

hfc ib

hoc

C

C

Fig. P (6.5b). CC hybrid model.

Input resistance in CE Ri =

V be ib

By definition

hie =

V be ib

Hence,

Ri = hie

V ce 0

Similarly for CC configuration Ri =

V bc ib

V ec 0

But we know that hie = hic Hence,

RL = 0

Ri = Ri

= hic

257

TRANSISTOR AMPLIFIER

Example 6. For any single-transistor amplifier prove that,

hi . 1 h r AV

Ri =

Solution : For single stage amplifier, input resistance Ri = hi + hr AI RL and

AV =

AI R L Ri

RL =

AV Ri AI

Substituting RL in the expression of Ri we get Ri = hi +

h r AI AV Ri AI

= hi + hr AV Ri

hi 1 h r AV

Ri =

Hence proved.

Example 7. For the transistor amplifier shown in Fig. P (6.6). hie = 1.5 hfe = 100 hre = 3 × 104 hoe = 25 mho s =

1 . 40 k

Calculate Ai, Ri, AV, o. + VCC = 20 V

50 K

1K +

R1

RC = 5 K

RS 5K

R2

VS –

Fig. P (6.6).

RL = 10 k

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BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : The a.c. equivalent is as follows : C

Ib

I

B

E

Vbe

RB

RL = 3.3 k

VCE

1K

VS E 1 R1

R1

Fig. P (6.7). AC equivalent of Fig. P(6.6).

RB = R1

R2 =

R1R 2 = 4.5 k R1 R 2

RL = RL

RC =

R L RC R L RC

= 3.3 k

(i) Ai (current gain for transistor) =

Ic Ib

=

h fe 1 h oe R L

=

100 = 92.4 3.3 1 40

The overall current gain AI =

Ic = I

= Ai + But

Ib I

=

FG I IJ FG I IJ HI K H I K c

b

b

Ib I

RB R B Ri

Ri = hie + hre AI RL = 1.4 k

Ib I

=

4.5 = 0.76 4.5 + 1.4

Hence,

AI = Ai × 0.76 = 92.4 × 0.76 = 70.2.

(ii)

R1 = RB

Ri =

4.5 1.4 = 1.0 k. 4.5 + 1.4

Ans.

Ans.

259

TRANSISTOR AMPLIFIER

(iii) AV (for transistor)

=

= The overall voltage gain

AVS =

V ce Ai R L = V be Ri 70.2 3.3 = 165.4 1.4

V ce V ce V be V be = = AV . VS V be V S VS

V be Ri = VS R S Ri

But

=

1 = 0.5 1 + 1

AVS = 165.4 (0.4) = 82.7. o = hoe

(iv)

RS =

Ans.

h re h fe h ie R S

RS R B = 818.18. RS R B

o = 1.2 × 105 mho = 12 mho.

Ans.

Example 8. A CE amplifier is driven by a voltage source of internal resistance RS = 800 . The load impedance is a resistance of 2 k. The h-parameters are hie = 1.1 k, hfe = 50, hoe = 25 µ ohms, hre = 2.5 × 104. Compute the current gain Ai , input resistance Ri, voltage gain Av, output resistance Ro and output terminal resistance Ro1. Also calculate power gain Ap. Using (a) exact analysis (b) approximate analysis. Compute % error in AI. Solution : (a) Exact analysis (i) Current gain Ai =

h fe 1 h oe R L

=

(ii) Input resistance

50 1 ( 25 10 6 2000 )

= 47.6.

Ans.

Ri = hie + hre Ai RL = 1100 (2.5 × 104) × 47.6 × 2000 = 1076.2 = 1.0762 k.

(iii) Voltage gain

AV =

Ai R L Ri

Ans.

= 88.46

Overall voltage gain (i.e., including signal source) AVS =

=

88.46 1076.2 = 50.75. 800 + 1076.2

AV Ri R i RS Ans.

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BASIC ELECTRONICS ENGINEERING & DEVICES

(iv) Output admittance

h re h fe

0 = hoe

h ie R S 2.5 10 4 50 = 18.42 ohms 1100 800

= 25 × 106

R0 =

1 = 54.28 k. 0

Ans.

(v) Power gain Ap = Ai × Av = ( 47.6) ( 88.46) = 4210.6. (vi) Output terminal resistance Rot = Ro

RL =

54.28 2 = 1.92 K. 54.28 + 2

(b) Approximate analysis Assume hre = hoe = 0 h fe

(i) Ai = [

1 h oe R L

hfe 50.

Ans.

hoe since RL = 25 × 106 × 2000 < 0.1].

(ii) Ri = hie + hre Ai RL hie 1100 . [

Ans.

Since hre Ai RL < 0.1 hie].

Ai R L Ri

(iii) AV =

AVS =

h fe R L h ie

AV Ri AV h ie RS R i RS h ie

50 2000 90.91 1100

52.62.

Ans.

(iv) 0 = 18.42 ohms 0 ohms R0 =

1 = 54.28 k (large value). 0

Ans.

(v) AP = Ai × AV = ( 50) ( 90.91) = 4545.5. (vi) Rob = R0 % error =

Ans.

RL 20 k (i.e., only RL neglecting R0).

FG Exact – approximate IJ H Exact value K

% error in AI =

× 100%

47.6 ( 50 ) × 100 = 5.04%. 47.6

Ans.

Ans.

Ans.

261

TRANSISTOR AMPLIFIER

Example 9. For the following Fig. P (6.8). Calculate Zi , Ai , Av and Z0. VCC R1

RC

CC

CC

RS

R2 +

RE

~

VS –

V0

CE

Fig. P (6.8).

Solution : By considering the basic rc model we get the form as shown below in Fig. P (6.9). I1 R1

RS VS

+

R2

Bre

Zi

IB

–

Thus we get Zi = R1 || R2 || re Ans. Z0 = RC || RL

Ans.

And we obtain the AV as follows: AV =

( RC ||r 0 ) V0 = re Vi

As we know from the above that I1 = and

RC Z0

Fig. P (6.9).

and

r0

Vi re

V0 = Ib (RC ||r0) V0 =

V0 =

FG V IJ ( R H r K i

e

C ||r 0

Vi ( RC ||r 0 ) re

)

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BASIC ELECTRONICS ENGINEERING & DEVICES

AV =

V0 ( RC ||r 0 ) = Ans. Vi re

A1 =

AV

Zi r0

FG R ||r IJ FG R || R || r IJ H r KH r K 0

C

1

2

0

e

e

Ans.

Example 10. A source with an internal resistance Rs = 600 drives a non-ideal amplifier whose input resistance is 400 . The source voltage is 1 mV. The amplifier feeds a load of 5 k and the load voltage is found to be 100 mV. Determine

}

(i) Voltage gain (ii) Current gain (iii) Power gain

of the amplifier

Solution : We can draw the circuit for the given information. RS +

VS

Io ri

vi

gm vi

ro

–

+

RL VL

–

Fig. P (6.10).

From Fig. P (6.10) Input voltage, Vi = Vs ×

aR

= 1 mV ×

ri S ri

a

f

400 400 + 600

f

= 0.4 mV Input current, Ii = =

VS R S ri

a

1 mV = 1 µA 400 + 600

f

263

TRANSISTOR AMPLIFIER

Vo Output current, Io = R L =

100 mV = 20 µA 5 k

Vo Voltage gain, AV = V i Current gain, AI =

VL = V i

=

( VL = 100 mV, RL = 5 k)

100 mV = 250. 0.5 mV

Io IL 20 A = = = 20. Ii Ii 1 A

Ans.

Ans.

Power gain, P = Av × Ai = 250 × 20 = 5000.

Ans.

7 In the previous unit, we have studied about Bipolar Junction (BJT). We discussed several configurations and operating regions alongwith concerned biasing techniques. The forthgoing unit describes another class of transistors, the field-effect transistors abbreviated as FET. The FET is also a three terminal device. It has got numerous applications in electronic circuits like BJT. There are several similarities and dissimilarities between FET and BJT. Constructional features, operating mechanism and performance characteristics differ greatly from those of BJTs. The main difference between BJT and FET is that former has got two junctions (JE and JC) but later has no any junction. Because of this advantage, several qualities have been enhanced in the transistors which were lacking in BJT. Another interesting difference between the BJT and FET is that a bipolar junction transistor is a currentcurrent device. That is why, the output characteristics of this device are controlled by the base current and not by the base voltage. While the FET is a voltage-controlled device. That is why, the ouput characteristics of FET are controlled by input voltage and not by the input current. In this unit, we will study about the FET and BJT comparatively and will be able to know why and how FET replaced the BJT in most specific applications.

Depending upon the constructional features and operating principles, FETs broadly classified in two main types field-effect transistors. 1. Junction field-effect transistor (JFET) 2. Metal oxide semiconductor field-effect transistor (MOSFET) or insulated gate field-effect transistor (IGFET). Both of these type further divided into n-channel and p-channel. For better understanding about the classification tree form is shown below in Fig. 7.1.

264

Comp-1/Laxmi-5/Computer/Revision/Belect-7—10.5.07

265

FIELD EFFECT TRANSISTOR FET

JFET

n-channel JFET

MOSFET or (IGFET) p-channel JFET Depletion type MOSFET

n-channel Depletion type MOSFET

Enhancement type MOSFET

p-channel Depletion type MOSFET

n-channel Enhancement type MOSFET

p-channel Enhancement type MOSFET

Fig. 7.1. Different types of field effect transistors.

The basic differences between BJT and FET is that the former is a currentcontrolled device and later is a voltage-controlled device. In the case of BJT the prefix ‘Bi’ comes out from the fact that a BJT have both types of charge carriers i.e., electrons and holes, but in the of a FET, either electrons or holes constitute the drain current, so named as unipolar transistor. Depending upon the type of charge carriers, FETs have been classified as n-channel or p-channel FET, discussed later or in other words we can say that the operation of FET depends upon the flow of majority carries only. There are a large number of advantages of FET over BJT. But, the main disadvantage of FET is its relatively small gain bandwidth-product in comparison with that which can be obtained with a conventional bipolar transistor. The Fig. 7.2 illustrates the difference between BJT and FET.

IC (Collector)

(Base)

ID (Drain)

IB

(Gate)

BJT

FET

(Control current)

V

GS

IE (Emitter)

(Control-voltage)

Fig. 7.2.

(Source)

266

BASIC ELECTRONICS ENGINEERING & DEVICES

Following are the few differences between BJT and FET which must be known to the students before discussing FET’s operation in detail. FET

BJT

1. FET is an unipolar semiconductor device because its operation depends upon the flow of majority carriers i.e., either holes or electrons as the case may be.

1. BJT is a bipolar semiconductor device because the current constituting elements are both majority carriers as well as minority carriers in this case.

2. The input impedance of FET is much more larger (ranging in Megaohms) than BJT. The reason behind this is that the input terminal i.e., gate to source of FET is reverse biased and reverse bias offers ideally infinite resistance.

2. The input impedance of BJT is very less in comparison to FET.

3. FET is a voltage controlled device.

3. BJT is a current controlled device.

4. FET is less noisy. Because there are no junctions.

4. Much noisy than FET.

5. Higher frequency response.

5. Frequency variation performance.

6. Good thermal stability because of absence of minority carriers.

6. Temperature dependent, runaway may cause.

7. Costlier than BJT.

7. Relatively cheaper.

8. Small sized.

8. Comparatively bigger.

9. In FET, relationship between input and output quantities is nonlinear due to square term in shockley’s equations

9. The BJT is an almost linear device or we can say that BJT works linearly in active region as an amplifier.

ID = IDSS

FG1 V IJ H V K GS

affects

the

thermal

2

P

10. No offset voltage; so it works better as a switch or chopper.

10. There is always an offset voltage before switching.

11. Small gain bandwith product.

11. Greater than FET.

The junction field-effect transistors (JFET’s) can be divided depending upon their structure into the following two categories : (i) n-channel JFET (ii) p-channel JFET The basic construction of an n-channel JFET is as shown in Fig. 7.3(a). It consists of an n-type semiconductor substrate (here substrate is nothing but a very lightly doped bar which is used as channel) with two p-type heavily doped regions diffused on opposite sides of its middle part. The p-type regions form two pn-junctions. The space between the junctions (i.e., n-type region) is called a channel. Both the p-type regions are connected internally and a single wire is taken out in the form of a terminal called

267

FIELD EFFECT TRANSISTOR

the gate (G). The electrical connections are made to both ends of the n-type semiconductor and are taken out in the form of two terminals called drain (D) and source (S). Thus the typical structure of a junction field-effect transistor consists of four basic elements : (a) Source. Referring to the Fig. 7.3 given below the source S is the terminal through which the majority carriers enter the bar. Conventional current entering the bar at S is designated by IS. (b) Drain. The drain D is the terminal through which the majority carriers leave the bar. Conventional current entering at the bar at D is designated by ID. The drain to source voltage VDS is positive when drain is more positive than source. (c) Gate. On both sides of the n-type bar, heavily droped p regions of acceptor impurities have been formed by alloying or by diffusion, or by any other means. These impurity regions are called the gate G and between the gate and source a reverse bias voltage VGS is applied. The conventional current entering the bar at G is designated by IG. (d) Channel. The region of n-type material between two gate regions is the channel through which the majority carriers move from source to drain. Drain D

p-type G

n-type channel

Gate

Drain D

n-type

p-type VDS

p-type channel

n-type VDS

G

S Source

S Source

(a) n-channel FET

(b) p-channel FET

Fig. 7.3. JFET’s type.

Whenever a voltage is applied across the drain and source terminals, a current flows through the n-channel. The current consists of only one type of carriers (i.e., electrons) therefore the FET (field-effect transistor) is called a unipolar device. The symbols for JFET’s for both n-channel and p-channel devices are given below in Fig. 7.4.

268

BASIC ELECTRONICS ENGINEERING & DEVICES D

D

G

G

S

S

(a) n-channel FET

(b) p-channel FET

Fig. 7.4. Symbols for FET’s.

A p-channel JFET is shown in Fig. 7.4(b). Its construction is similar to that of nchannel JFET, except that it consists of p-channel and n-type junctions. The current carriers in p-channel JFET are the holes. The operation of p-channel JFET is similar to n-channel except that all voltage and currents are reversed. Analogies are seldom perfect and at times can be misleading, but the water analogy as shown in Fig. 7.5 does provide a sense for the JFET control at the gate terminal and the source of water pressure can be likened to the applied voltage (i.e., VDS) from drain to source that will establish a flow of water (electrons) from the source. The “gate” through an applied potential which controls the flow of water (i.e., here charge) to the “Drain”.

Source

Gate

Drain

Fig. 7.5.

Consider an n-channel JFET as shown in Fig. 7.6(a) here the p-type gate and ntype channel constitutes pn-junction. This PN-junction is always reverse biased in JFET operation. When the circuit with very small reverse voltage is applied across the gate (VG) as shown in Fig. 7.6(a). Due to this reverse bias the width of the depletion layer is increased over the pn-junction. Since, the doping of the p-type region is more than n-type, therefore depletion layer penetrates, n-type region deeply, so that the width of the n-type channel is decreased. Now, the electrons coming from the source have to pass through narrow width n-channel. Because of reduced channel-width, the resistance of the path of electron is increased and hence the drain current (ID) is decreased. As discussed earlier that p-region of a n-channel JFET is heavily doped, as compared to the n-channel. Incidently, when there is no applied voltage between the drain and the source, the depletion region is symmetrical around the whole junction. The conductivity of depletion region is zero because there are no mobile charge carriers in this region. Hence the effective width of n-channel is reduced which is better illustrated

269

FIELD EFFECT TRANSISTOR

D

P-region

D

Depletion region

P-region

n-channel

G

G

S

S

VGG

VGG

(a) n-channel FET

(b) depletion regions in FET Fig. 7.6. Basic operation of FET.

in the Fig. 7.7. It further reduces with the increased reverse-bias voltage applied across the gate and source terminals of the JFET. IG

p-type gate Depletion region

(Source) S

2a

IS

Drain (D)

2b (x)

Pinch off x

VGG

w (x)

G (Gate)

ID n-type channel

VDD

Fig. 7.7. Detailed structure of an n-channel FET.

From the above Fig. 7.7 we see that : 2a = width of channel. 2b (x) = effective width of the channel after the formation of depletion region. w (x) = is the width of depletion region. Both the effective width b (x) and width of depletion region w (x) are the function of x, it means both vary with varying the reverse voltage applied across gate terminal and the source terminal. The reverse-bias across the gate source junction of a JFET may also be achieved by applying a voltage across the drain and source terminal as shown in Fig. 7.8. It may be noted that drain (D) is connected to the positive terminal of the d.c. supply (VDD) and source (S) is connected to the negative terminal.

270

BASIC ELECTRONICS ENGINEERING & DEVICES

Before the study of the characteristics in detail, we should memorize following Table 7.1 for JFET. Table 7.1 S. No.

Particular

n-channel FET

p-channel FET

1.

VDS

+ ve

ve

2.

VGS

ve

+ ve

3.

ID

D to S

S to D

4.

IG

incoming

outgoing

BJT to FET terminals analogy BJT

Collector (C)

Base (B)

Emitter (E)

IC

VCE

FET

Drain (D)

Gate (G)

Source (S)

ID

VDS

There are two types of FET characteristics. 1. Drain characteristics 2. Transfer characteristics

It is the relationship between VDS and ID at constant VGS i.e., we assume any fixed value for VGS. Now, depending upon the values of VDS, following cases arise. zero.

Case 1. When VGS = 0 and VDS = 0. In this condition the drain current is

Case 2. When VGS 0 and VDS = 0. Under this condition pn-junction being reverse biased and increases the width of the depletion layer. Now, if VGS is increased more negatively then the situation of pinch off occurs. At this instant, ID also decreases max because channel becomes narrower due to reverse bias. Case 3. When VGS = 0 and VDS > 0, i.e., a positive voltage VDS has been applied across the channel. The gate and source are connected directly i.e., VGS = 0. In this situation ID = IS (i.e., VDS = VDD). Under this condition the flow of charge is relatively uninhabited and limited only by the resistance of the n-channel between drain and source. It is important to note that depletion region is wider near the drain side as compared to source side because when current flows in silicon bar, there occurs a voltage drop across the channel along whole length due to this reverse bias voltage across the drain and the gate is comparatively much larger than the reverse bias voltage across the gate and source. This can be easily understood by analysing Fig. 7.8(b) given as follows :

271

FIELD EFFECT TRANSISTOR

D

ID

D

+ 2V

Depletion region

R P

G VGS = 0 V

e

e

e

VGS = 0 V

P

IG = 0 A

n-channel e e

1.5 V

R P

R

P

1.0 V

VDS = 2 V

0.5 V

R S

IS

S

(a) N-channel FET

0V

(b) Diagram showing voltage drops in succession through channel

Fig. 7.8.

Fig. 7.8(b) shows that the reverse bias voltage is directly proportional to the depletion region. Thus, we can say that the width of the depletion layer is maximum at drain terminal side where there is maximum reverse bias voltage. It is to be noted here that IG = 0 is the important characteristic of the JFET. The drain current ID depends upon following factors : 1. Number of majority carriers 2. Length of the channel 3. Cross-sectional area of the channel 4. VDS Mathematically, ID = Where,

V DS R

=

V DS A l

... (7.1)

VDS = Voltage between drain and source R = Resistance of the channel A = Area of the channel = Resistivity of the material used l = Length of the channel.

In order to explain, the typical shape of drain characteristics, let us select the curve with VGS = 0 volt as shown in Fig. 7.9. The curve may be subdivided into the following regions.

272

BASIC ELECTRONICS ENGINEERING & DEVICES

Drain current ID (mA)

IDSS

VGS = 0 V 1V 2V 3V 4V

0

12 3 4 Drain to source voltage VDS (V)

Fig. 7.9. Drain characteristics of JFET.

1. Ohmic region. This region is shown as a curve OA in Fig. 7.10. In this region, the drain current increases linearly with the increase in drain-to-source voltage, obeying Ohm’s law. The linear increase in drain current is due to the fact that n-type semiconductor bar acts like a simple resistor.

Drain current ID (mA)

Ohmic region

0

Pinch-off or B Saturation region A

VGS = 0 V

D Breakdown region C Increased resistance due to narrower channel

VP Drain to source voltage VDS

VBR

Fig. 7.10. Drain characteristics with VGS = 0 volt.

2. Curve AB. In this region, the drain current increase at the reverse square law rate with the increase in drain-to-source voltage. It means that drain current increases slowly as compared to that in ohmic region. It is because of the fact, that with the increase in drain-to-source voltage, the drain current increases. This in turn increases the reverse bias voltage across the gate-source junction. As a result of this, the depletion region grows in size, thereby reducing the effective width of channel. At the drain-tosource voltage, corresponding to point B, the channel width is reduced to a minimum value and is known as pinch off. The drain-to-source voltage, at which the channel pinch-off occurs, is known as pinch-off voltage (VP). 3. Pinch off region. This region is shown by the curve BC. It is also called saturation region or constant current region. In this region, the drain current remains constant at its maximum value (i.e., IDSS). The drain, current in the pinch off region, depends upon the gate-to-source voltage and is given by the relation,

273

FIELD EFFECT TRANSISTOR

FG H

ID = IDSS 1

V GS VP

IJ K

2

The above relation is known as Shockly’s equation. The pinch off region is the normal operating region of JFET, when used as an amplifier. 4. Breakdown region. This region is shown by the curve CD. In this region, the drain current increases rapidly as the drain-to-source voltage is also increased. It happens because of the breakdown of gate-to-source junction due to avalanche effect. The drain-to-source voltage corresponding to point C is called breakdown voltage. Important points regarding drain characteristics of n-channel FET 1. Drain current is maximum when VGS = 0 i.e., VD = IDSS (saturation current) 2. In FET, generally avalanche breakdown occurs (due to excessive amount of electric field) 3. VP is a particular value of VGS with either positive or negative sign depending upon the case of the FET. 4. From the characteristics, it is clear that there is a region from end of ohmic portion up to pinch off voltage where current decreases due to increase in mobility. There are also called transconductance curves, which gives us the relationship between drain current (ID) and gate to source voltage (VGS) for a constant value of drainto-source voltage (VDS). The transfer characteristics may be obtained by using the circuit arrangement as shown in Fig. 7.11.

As mentioned earlier, the FET works as an amplifier in the region beyond pinch off (or current saturation region or constant current pentrode). It may be noted that curve is part of parabola. Following equation governs the transfer characteristics of FET.

FG H

ID = IDSS 1 where,

V GS VP

IJ K

2

... (7.2)

ID = Drain current IDSS = Saturated (max) value of drain current VGS = Gate to source voltage (i.e., control variable) VP = Pinch-off voltage.

Here in this eqn. (7.2), VGS is control variable and IDSS is the saturation current (having constant value). The linear relationship does not exist between the output and input quantities of a JFET. The above relation is known as the Shockley’s equation. The approximate parabolic equation given in above eqn. 7.2 is a best fit for transfer characteristics obtained for FET by experimental approach i.e., diffusion process.

274

BASIC ELECTRONICS ENGINEERING & DEVICES

(Drain current) in mA

ID

VGS(off) = VP O VGS (Gate-to-source voltage)

Fig. 7.11. Transfer characteristics of n-channel.

As we have already discussed that if the magnitude of reverse bias voltage is applied to gate is increased sufficiently, drain current ID becomes zero. This situation of JFET operation is known as pinch-off. To understand the concept of pinch-off voltage is very necessary. It can be better understand by the Fig. 7.12. +

D P-type

n-channel

P-type

VDS = VP VGS

Pinch off

S

–

Fig. 7.12. The situation of pinch-off.

Above discussion reveals that when gate to source voltage (VGS) approaches to pinch off voltage (i.e., VP), drain current (ID) becomes zero, but in fact it is not so. This can be easily understood by the mathematical relation of drain current : ID = A q ND n E or where,

ID = 2b(x) w q ND n E

... (7.3)

{

}

Area A = 2b(x).w, From Fig. 7.7 VDS = E × L

ID = Drain current 2b(x) = Effective channel width

275

FIELD EFFECT TRANSISTOR

w = Depletion region width ND = Doping concentration n = Mobility of electron E = Applied electric field L = Length of the channel q = Change of the electron (or hole) Thus, from the relation (7.3) we see that as VDS increases, E and ID increases, whereas b(x) decreases because the channel narrows, and hence the current density J

ID = 2b ( x ).w

RS J I UV AW T

increases. We now see that complete pinch-off (b = 0) cannot

takes place because, if it did, J would become infinite, which is a physically impossible condition. It is found experimentally that the mobility is a function of electric field (as discussed in unit 2) intensity and remains constant only for E < 104 V/cm in n-type silicon. For moderate fields, 103 to 104 V/cm, the mobility is approximately inversely proportional to the square root of the applied field

FG i .e ., H

n

IJ . For still higher EK

1

fields, such as encountered at pinch-off µn is inversely proportional to the applied electric field

F i .e ., H

n

I K

1 . In this region the drift velocity of the electrons (Nd = nE) E

remains constant, and ohm’s law is no longer valid. Finally we concluded that pinch-off voltage (Vp ) is the minimum drain-to-source voltage at which the drain current essentially becomes constant. NOTE 1 :

As we have discussed already that the P-region is highly doped as compared to the n-channel, it means number of acceptor ions in a p-type is very much higher than the Donar-ions (i.e., NA >> ND). Under this situation the space-change width w(x) at a distance x along the channel in Fig. 7.7 : W(x) = a b(x)

or where

R 2E W(x) = S T qN

D

UV W

1/2

(V 0 V ( x ) )

... (7.4)

= Dielectric constant of the channel material q = Magnitude of electronic charge ND = Donar concentration V0 = Junction contact potential at x. V(x) = Applied potential across space-charge region at x and is negative number for an applied reverse bias.

If the drain current is zero, b(x) and V(x) are independent of x and b(x) = b. If in eqn. (7.4) we substitute b(x) = b = 0 and solve for V, on the assumption that |V0| rd, then AV

1 for > 1 1

rd + Rd +1

+

S

Vi +1

+

RS

id

N

V02

Fig. 7.21. Equivalent circuit for the generalized FET amplifier when the output is taken from the source.

Hence for source follower with Rd = 0 and >> 1 R0 =

rd R d 1

or

R0 =

rd

or

R0 =

rd g m rd

or

R0 =

1 gm

{Rd = 0 µ >> 1}

Unity voltage gain means that the output (at the source) follows the input (at the gate). Hence, the CD configuration is called a source follower (analogous to the emitter follower for a BJT amplifier). Comparison of n-channel and p-channel devices As we have discussed earlier that the construction of p-channel is exactly same as that of the n-channel devices. However there are some differences between the n-channel and p-channel, are given below in Table 7.2. Table 7.2 S.No.

Particular

n-channel

p-channel

1.

Nature of charge carriers

In an n-channel JFET the Here, charge carriers are current carriers or charge holes. carriers are electrons.

2.

Mobility of the charge carriers

Mobility of electrons in nchannel is higher because their masses are smaller than holes.

The mobility of holes in pchannel devices is lower than that of electrons in n-channel devices.

287

FIELD EFFECT TRANSISTOR 3.

Noise

They are less noisy.

They are more noisy than n-channel.

4.

Transconductance

Larger.

Smaller.

5.

Manufacturing process

Its manufacturing process is very difficult.

Its manufacturing process is comparatively easy.

JFET’s have numerous industrial applications because of its inherent properties. They can be used as amplifiers, oscillators, choppers, switches etc. Following are the few applications of FET : 1. As a buffer. A buffer is an amplifier whose amplification factor is one. The purpose of inserting a buffer between stages of amplifying system to provide isolation of one stage from its successive stage. For this very purpose the device applied as a buffer should have very large input impedance so that it draws negligibly small current from the stage attached to its input. At the same time, the ouput impedance of the buffer should be as minimum as possible because the buffer has to operate very large loads at its output terminals. Here from heavy loads mean that the loads which draw more currents because of their low resistances. The FET has input impedance in the range from several mega ohms to hundred ohms and low output impedance (ranging in few hundred ohms). Thus, FET can work as a buffer between two stages to avoid loading effects. Amplifier

Amplifier FET as a buffer

A1 Ri 0 (ideally)

A2 RO 0 (ideally)

Fig. 7.22.

2. As an amplifier. FET’s are considered to be the better amplifiers than BJT’s because of good noise immunity. Noise, in one form or another deteriorates the original message signal. In various communication systems, we need to minimise the effect of noise on the message signal. As we know that FET is a very good low-noise device (because of absence of junctions in its structure), it can work as an error minimising device when employed before the point end of receivers and other electronic equipments. 3. As a phase shift oscillator. The high input impedance of FETs make them valuable for designing phase shift oscillators where they avoid loading effects. 4. FET as a voltage variable resistor. As we know from the characteristics of the FET that it works most effectively in the constant-current portion. But if it is operated on the region prior to pinch-off (i.e., when VDS is very small) it will behave as a voltage variable resistor (VVR). It is due to the fact that in this region drain to source resistance RDS can be controlled by varying the bias voltage VGS. In such applications the FET is also referred to as a voltage-variable resistor or voltage dependent resistor.

288

BASIC ELECTRONICS ENGINEERING & DEVICES

The following mathematical relationship describes the control of voltage variations over the resistance of the device.

r0

rd =

1

FG V IJ HV K

2

GS P

where r0 is the resistance with VGS = 0 V and rd is the resistance at a particular level of VGS. The drain to source conductance gd =

ID can be expressed as, V DS

gd = gdo

LM F V I OP MM1 GH V JK PP N Q GS

1 2

P

RSg T

do

2 I DSS VP

UV W

where gdo is the value of drain conductance when the bias voltage VGS is zero. The variation of her rd with VGS can be closely approximated by the empirical expression : rd = where

r0 1 kV GS

rd = Drain resistance at zero gate bias k = Constant whose value depends upon the type of the FET used. VGS = Gate-to-source voltage.

FET as a voltage variable resistor can be used in Automatic Gate Control (AGC) circuit of a multistage amplifier.

? 1. Draw the symbol and characteristics of an n-channel JFET and mark the linear region, saturation region and breakdown region. 2. What do you mean by drain and transfer characteristics in reference to JFET ? 3. What is meant by depletion region in JFET ? Explain with suitable diagrams. What are the basic difference between BJT and JFET ? 4. What are the relative merits and demerits of a FET amplifier over a transistor amplifier ? 5. With the help of a neat sketch explain the working of a FET amplifier. 6. Define the parameters of JFET. 7. Define pinch off voltage of JFET.

289

FIELD EFFECT TRANSISTOR 8. Explain with the help of circuit diagram how an FET used as a VVR ? 9. List different methods of biasing used in FET. 10. How does a p-channel JFET differ from an n-channel JFET ? 11. Why FETs have better thermal stability ? 12. Why does a FET acts as an excellent buffer amplifier ?

Example 1. Fig. P (7.1) show the transfer characteristics of a JFET, write the equation for drain current. Solution : Referring to the transfer characteristic in Fig. P (7.1), we have IDSS = 14 mA VGS(off) = 6 V

ID (mA) 14 mA

From the relation : ID = IDSS

F1 V GH V

ID = 14

FG1 V IJ H 6K

GS

GS (off)

I JK

2

2

GS

mA.

Ans.

VGS

6V

O

Fig. P (7.1).

Example 2. A JFET has the following parameters : IDSS = 30 mA ; VGS (off) = 8 V ; VGS = 5 V. Find the value of drain current. Solution : We know that, ID = IDSS

= 30

F1 V GH V

GS

GS (off)

LM1 F 5 I OP N H 8 K Q

I JK

2

2

= 30 (1 .625)2 = 30 × .140625 = 4.218 mA.

Ans.

Example 3. In a self-bias n-channel JFET, the operating point is to be set at ID = 1.5 mA and VDS = 10 V. The JFET parameters are IDSS = 5 mA and VP = 2 V. Find the value of RS and RD. Given that VDD 20 V.

290

BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : Fig. P (7.2) shows the circuit arrangement. ID = IDSS

or

1.5 = 5

FG V H 2

GS

or

IJ K

1

V GS 2

or

=

FG1 V IJ H V K

VDD = 20 V

2

GS

RD

P

FG1 V IJ H 2K

ID D

2

GS

G

VDS = 10 V IS S

1.5 5

RS

= .55 1

VGS = 0.9 V

or Now,

Fig. P (7.2).

VGS = VG VS VGS = 0 VS

{VG = 0 V}

VS = VGS = ( .9) = 0.9 V

or

VS 0.9 V RS = I = 1.5 mA = 0.6 k. D

Ans.

Now, applying KVL at the output section, we have VDD = IDRD + VDS + IDRS 20 = 1.5 × RD + 10 + 1.5 × .6 20 = 1.5 RD + 10 + .9 1.5 RD = 20 10.9

or

RD = VDS

9.1 1.5

6 k.

VDD = 30 V

Ans.

Example 4. In the JFET circuit shown in Fig. P (7.3), find (i) (ii) VGS. Solution : (i) Applying KVL, we have

or

VDS = VDD ID (RD + RS)

or

VDS = 30 2.5 mA (5000 + 200)

or

VDS = 30 (2.5 × 103 × 5200)

or

VDS = 30 13 = 17 V. VGS = IDRS

or

VGS = 2.5 × 103 × 200

or

VGS = 0.5 V.

Ans.

ID = 2.5 mA D

G

VDD = IDRD + VDS + IDRS

(ii)

RD = 5 k

S RS = 200

Ans. Fig. P (7.3).

291

FIELD EFFECT TRANSISTOR

Example 5. For an n-channel silicon FET with a = 3 × 104 cm and ND = 1015 electrons/cm3, find (a) the pinch off voltage and (b) the channel half-width for VGS = 1/2 VP and ID = 0. Given that,

ND = 1015 electrons/cm3 ND = 1021 electrons/m3

or

= 120 Solution : (a) As we know that for Si, the relative dielectric constant is 12, so = 120 As per the relation |VP| =

q ND 2 a 2

... (1)

Substituting the values of q, , ND and a in MKS units in above expression (1) |VP| =

1.60 10 19 10 21 ( 3 10 6 )2 2 12 ( 36 10 9 ) 1

= 6.8 V. Ans.

(b) We have for VGS, VGS =

F1 b I H aK

2

... (2)

VP

Solving eqn. (2) for b, we have

b =

L F V I OP a M1 G MM H V JK PP N Q GS

1 2

P

Substituting the approximate values given,

b = (3 ×

104)

LM F 1 I OP MN1 H 2 K PQ 1 2

= 0.87 × 104 cm.

Ans.

Example 6. The amplifier given in following Fig. P (7.4) utilizes an n-channel FET for which VP = 2.0 V and IDSS = 1.645 mA. It is desired to bias the circuit at ID = 0.8 mA, using VDD = 24 V. Assume rd >> Rd. Find (a) VGS (b) gm (c) RS (d) Rd, such that the voltage gain is at least 20 dB, with RS bypassed with a very large capacitance CS.

292

BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : (a) Above Fig. P (7.4) is an arrangement of self-bias circuit. Using following relationship :

FG1 H

ID = IDSS

we have,

0.8 = 1.65

FG1 H

V GS VP

IJ K

V GS 2.0

VDD Rd

2

VO Vi Cb

IJ K

2

Rg

S RS

CS

Solving above expression VGS = 0.62 V. Ans. (b) Also,

gmo =

2I DSS VP

Now,

gmo =

2 (1.65 ) = 1.65 mA/V 2

gm = gmo

FG1 H

V GS VP

Fig. P (7.4).

IJ K

Substituting, required values in above expression gm = (1.65)

F1 0.62 I H 2.0 K

= 1.14 mA/V. Ans. (c)

RS =

VG ID

0.62 = 0.77 k = 770 . Ans. 0.8 (d) It is given that gain is 20 dB =

Now,

AdB = 20 log10 (A) 20 = 20 log10 (A)

A = 10

It is given that, rd >> Rd

|AV| = gm Rd 10 Rd 10/1.14 = 8.76 k. Ans.

or

Example 7. Determine the following for the network given in following Fig. P (7.5) (where Q indicates quiescent condition) (a) VGS (b) IDQ

293

FIELD EFFECT TRANSISTOR

(c) VDS

16 V

(d) VD

2 k

(e) VG

D

(f) VS. Solution : (a) (b)

IDQ = IDSS

FG1 H

= 10 mA

V GS VP

FG1 H

IJ K

+ VGS 1 M

2

– +

2V 8V

IJ K

IDSS = 10 mA VP = 8 V

G

VGS = VGG = 2V. Ans.

S

2V

2

Fig. P (7.5).

= 5.625 mA. Ans. (c)

VDS = VDD IDRD = 16 5.625 × 103 × 2 × 103 = 16 11.25 = 4.75 V. Ans.

(d)

VD = VDS = 4.75 V. Ans.

(e)

VG = VGS = 2 V. Ans.

(f)

VS = 0 V. Ans.

Example 8. When a reverse voltage of 10 V is applied between gate and source of JFET the gate current is 0.001 A. Determine resistance between gate and source. Solution : Gate to source voltage, VGS = 10.0 V Gate current IG = 0.001 A = 1 × 109 A Now, gate to source resistance, RGS =

V GS IG

=

10 1 10 9

= 10000 M. Ans.

Example 9. When a drain-source voltage is changed by 1.5 volts, the change in drain current is of 120 A, the gate-source voltage remaining unchanged. Determine the ac drain resistance of the JFET. Solution : Change in drain-source voltage, VDS = 1.5 V Change in drain current, ID = 120 × 106 A AC drain resistance of the JFET, rd =

V DS ID

=

1.5 120 10 6

= 12.5 k. Ans.

Example 10. In a JFET the drain current changes from 1.2 mA to 1.5 mA when the gate to source voltage is varied from 4.25 V to 4.10 V, keeping the drain source voltage constant. Determine the transconductance for the given JFET.

294

BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : Change in drain currents, ID = ID ID 2

1

= 1.5 1.2 = 0.3 mA Change in gate to source voltage, VGS = VGS VGS 2

1

= 4.10 ( 4.25) = 0.15 V Transconductance,

gm =

ID V GS

0.3 mA 0.15 V

=

= 2 mA/V. Ans. Example 11. An FET follows the following relation, ID = IDSS

LM1 V OP N V Q

2

GS P

IDSS = 8.4 mA, VP = 3 V, what is the value of ID for VGS = 1.5 V ? Find gm at this point. Solution : Drain source saturation current, IDSS = 8.4 mA Pinch off voltage, Gate-source voltage,

VP = 3 V VGS = 1.5 V

FG1 V IJ H V K FG1 1.5 IJ H 3 K

2

Drain current

ID = IDSS

= 8.4

GS P

Ans.

= 2.1 mA. Transconductance,

gmo = =

Transconductance,

2

2 I DSS VP 2 8.4 = 5.6 mA/V 3

gm = gmo

= 5.6

FG1 V IJ H V K FG1 1.5 IJ H 3 K GS

= 2.8 mA/V.

P

Ans.

295

FIELD EFFECT TRANSISTOR

Example 12. For a p-channel silicon FET a = 2 × 104 cm, = 10 . cm, find (a) The pinch off voltage (VP) for Si (b) The pinch off voltage (VP) for Ge Given that for Si,

= 120

For Ge,

= 160

where

0 = 8.86 × 1012 c2/Nm2 P = 500 cm2/V-sec for Si P = 1800 cm2/V-sec for Ge.

Solution : We know that

VP =

q N Aa 2 2

... (1)

= n q

Also, we know that or

= NA q

or

1 = NA q

NA =

1 q

... (2)

Now, from eqns. (1) and (2) VP =

q a2 1 a2 = 2 2 q

VP =

a2 2

For Si,

VP =

a2 2 p (12 0 )

{ = 120 for Si}

Ans.

For Ge,

VP =

a2 2 p (16 0 )

{ = 160 for Ge}

Ans.

or

Example 13. Show that for small values of VGS compared with VP , the drain current is given approximately by ID IDSS + gmo VGS. Solution : We know that

FG1 V IJ H V K LM1 + F V I MN GH V JK 2

ID = IDSS

= IDSS

GS P

GS P

2

2V GS VP

OP PQ

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BASIC ELECTRONICS ENGINEERING & DEVICES

R|F V I S|GH V JK T R|I .V S| V T

2

GS

= IDSS + IDSS

2

P

= IDSS + VGS

DSS

GS 2 P

V GS VP

U| V| W

2I DSS VP

U| V| W

Provided that VGS > RD. Find the quiescent drain current, quiescent drain to source voltage, and small signal voltage gain AV. VDD (30 V) RD = 12 k V0 Vi

1 M

RG

470

RS

CS

Fig. P (7.9).

Solution : We know that

ID = IDSS

ID = 3

FG1 V IJ H V K

2

GS P

FG1 0.47 IJ H 2.4 K

2

1 I = (1 0.1958 Id)2 3 D 0.03835 Id2 0.7249 + 1 = 0

0.7249 [0.5255 – 0.1534]1/2 2 0.03834 = 1.496 mA 1.5 mA

Id =

VD = VDD IdRD = 30 1.5 × 12 = 12 V

300

BASIC ELECTRONICS ENGINEERING & DEVICES

VS = IdRS = 0.47 × 1.5 = 0.7 V Quiescent point

VDS = 12 0.7 = 11.3 V

FG1 V IJ = 2 I FG1 V IJ V H V K H V K 2 3 F 0.7 I 1 G J = 1.76 mA/V H 2.4 K 2.4

=

DSS

GS

gm = gmo

GS

P

P

P

AV = gmRD = 1.76 × 12 = 21.18.

Ans.

Example 18. The FET of given Fig. P (7.10) has IDSS = 5.6 mA and VP = 4 V. Find the voltage gain AV of the source follower circuit using the small signal ac model and gm = 2 mA/V. Find the changes in V0 due to a 10 V change in Vi. 24 V 4.7 k D

G +

V0

S Vi

10 k 12 V

Fig. P (7.10).

Solution : Using the source follower formula, AV =

g m RS 2 10 = = 0.952 1 + g m RS 1 + 2 10

V0 = Av Vi = 9.52 V

{

Vi = 10 V}

Ans.

Example 19. Referring to source follower circuit of Fig. P (7.10), compare the result obtained by using the large signal model and Vi swings from 0 to 10 V. Solution : Consider

Vi = 0

ID = IDSS

FG1 V IJ H V K FG1 12 10 I IJ 4 H K 2

= 5.6

GS P

D

On simplifying we get, 35 ID2 113 ID + 89.6 = 0

ID = 1.4 mA or 2.32 mA

Taking lower value,

ID = 1.4 mA

2

301

FIELD EFFECT TRANSISTOR

V0 = VSS + IDRS = 12 + 1.4 × 10 = 2 V

Now consider

Vi = 10 V

ID = IDSS

FG1 V IJ H V K FG1 10 + 12 10 I IJ 4 H K 2

= 5.6

GS P

2

D

Simplifying, we get 6.25 ID2 32.678 ID + 42.225 = 0

ID = 2.34 or 2.78 mA

Again taking lower value,

ID = 2.34 mA

V0 = 12 + 10 × 2.34 = 11.4 V

V0 = 11.4 2 = 9.4 V

This compares well with 9.52 V of small signal model.

Ans.

Example 20. Find the quiescent values of VDS, Id and VGS for the amplifier shown in Fig. P (7.11). The FET parameters are IDSS = 4 mA, VP = 4 V. VDD = – 60 V

60 V RD

18 k

R = 1.3 M

ID

ID

RG

D +

R2 = 200 k

18 k

–

4k

+

4k

VGG

(a)

RS

(b)

Fig. P (7.11).

Solution : Replace the biasing network of Fig. P (7.11 a) by its Thevenin equivalent as shown in Fig. P (7.11 b). Now,

VGG = 60 × RG =

200 = 8 V 200 + 1300

200 1300 = 173.3 k 200 + 1300

Id = IDSS

FG1 V IJ H V K GS P

2

... (1)

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BASIC ELECTRONICS ENGINEERING & DEVICES

VGS = VG VS

Since

VGS = Id

or

... (2)

Now, from eqn. (1) and (2), we have Id = 4

FG1 8 4 I IJ 4 H K

2

d

0.25 Id = (3 + Id)2 = Id2 + 6Id + 9 Id2 + 6.25 Id + 9 = 0

Id =

6.25 ( 6.25 2 36 )1/2 = 2.25 mA. Ans. 2

VGS = 8 4 × ( 2.25) = 1 V. Ans.

VDS = VDD ID (RD + RS) = 60 + 2.25 (18 + 4) VDS = 10.5 V. Ans.

Example 21. For the network shown in Fig. P (7.12), determine 12 V

(a) IDQ and VGSQ (b) VDS. Solution : Since

IDQ

IG 0 A

1.2 k

VG = IGRG = 0 V VGSQ = VG – VS = 0 – ISRS For FETs, So,

IDSS = 6 mA

ID = IS

VP = – 4 V

VGSQ = – IDRs

1 m

0.43 k

We know that IDQ =

FG H

I DSS 1

FG H

V GS VP

= 6 mA 1

ID = or or

F H

6 1

IJ K

2

Fig. P (7.12).

( I D RS ) ( 4 )

I D 0.43 4

I K

IJ K

2

2

0.069 ID2 – 2.2 ID + 6 = 0 IDQ =

2.2 1.78 = 28.84 mA, 3.04 mA 0.138

303

FIELD EFFECT TRANSISTOR

Neglecting ID = 28.84 mA (because for this value of IDQ, voltage drop at RD = 1.2 k will be (1.2 × 103 × 28.84 × 10–3 = 34.60 V) which is impossible with a supply of 12 V) So, and

IDQ = 3.04 mA

Ans.

VGSQ = –IDRS = – (3.04)(0.43) = – 1.307 V. (b) Apply KVL we get VDS – IDRD – VDS – ISRS = 0

or

VDS = VDD – ID(RD + RS)

or

VDS = 12 – 3.04 mA (1.2 + 0.43) × 103

or

VDS = 12 – 3.04 × 10–3 × 1.63 × 103

or

VDS = 7.045 V

Ans.

8

In the preceding chapter we have discussed the drain and transfer characteristics and small signal properties of junction field-effect transistor (JFET). We now turn our attention to the metal oxide-semiconductor field effect transistor (MOSFET) or insulatedgate field-effect transistor (IGFET). The MOSFET transistor has become one of the most important devices used in the design and construction of integrated circuits for digital computers. Its thermal stability and other general characteristics make it extremely popular in computer circuit design. MOSFET can be broadly classified in depletiontype MOSFET and enhancement type MOSFET and each is further divided in n-channel and p-channel MOSFET. The characteristics and properties of depletion-type MOSFET is same as that of JFETs, both follow the Shokley equation. However, the properties of enhancement-type MOSFET and JFETs are quite different. The basic difference between the depletion and enhancement MOSFET is that in the depletion-type MOSFET the channel is already formed while in the enhancement-type MOSFET channel is not initially formed. Other main important difference between these two is that in the depletion gate is always reverse biased with the drain however, in the enhancement MOSFET gate is forward biased with drain that’s why drain current increases with increasing the gate voltage i.e., enhance the drain current, that’s why called enhancement MOSFET. One more interesting difference between the JFET and MOSFET is that in the MOSFET there is no direct electrical connection between the gate terminal and the channel of MOSFET which were present in the JFET, this is due to the fact that MOSFET transistor uses an additional insulator layer of SiO 2 which provides good electrical isolation, this is the region why the input impedance of MOSFET is very high as compare to the JFET.

The basic construction of the n-channel depletion-type MOSFET is shown in Fig. 8.1. For the n-channel depletion type MOSFET substrate (which is very highly doped acts as a base) is p-type formed. It may be noted that substrate is the foundation upon which the device will be constructed. In some cases the substrate is internally connected to the source terminal. However, may discrete devices provide an additional terminal labelled SS, resulting in a four terminal device. 304

Comp-1/Laxmi-5/Computer/Revision/Belec-8—10.5.07

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) (Drain) D

SiO2

305

n-channel

n Metal contacts (Gate) G

n

p Substrate

Substrate SS

n

S (Source)

n-doped regions

Fig. 8.1. n-channel depletion-type MOSFET.

From the figure it is obvious that source (S) and drain (D) terminals are connected through metallic contacts to n-doped regions linked by n-channel. The gate is also connected to a metal contact surface but remains insulated from the n-channel by a very thin silicon dioxide (SiO2) layer. This SiO2 layer acts as a dielectric that sets up opposing electric fields within the dielectric when exposed to an externally applied field. Reason why SiO2 layer is used as a dielectric. There are two main reason why SiO2 layer is used as a dielectric : (1) It provides better electrical isolation between gate and channel, or in other words we can say that there is no electrical connection between the gate terminal and the channel of a MOSFET. (2) Due to better electrical isolation its input impedance becomes very large. Which is very good to overcome the loading effect, which is generally occurred in the device. The very high input impedance continues to fully support the fact that the gate current (IG) is essentially zero amperes for dc-biased configurations. Fig. 8.2 shows n-channel depletion type MOSFET with a gate to source voltage (VGS) is zero volt and applied voltage VDD. As soon as an voltage VDS (or VDD) is applied across the drain-to-source terminals. The result is an attraction for the positive potential at the drain by the free electrons of the n-channel and a current similar to that established through the channel of the JFET. From the Fig. 8.2 it is obvious that the resulting current with VGS = 0 V is IDSS (i.e., saturation current)

306

BASIC ELECTRONICS ENGINEERING & DEVICES D

n

ID = IS = IDSS

e VDD

+

G

–

e e

VGS = 0 V

P-substrate n-channel

e n

S

Fig. 8.2. n-channel depletion type MOSFET with VGS = 0 V and an applied voltage VDD.

Now, consider the situation when the drain-to-source (VDS) voltage is held constant while the gate-to-source (VGS), voltage is varied. As VGS has been set a negative voltage such as 1 V, the negative voltage at the gate will tend to pressure electrons towards the p-type substrate, this is due to the fact that dielectric creates the opposite sign on the left side while the same sign (i.e., potential) on the right side. Resulting this attract opposite charges and repel the like charges (i.e., electrons here). Due to this result the recombination (as discussed earlier) phenomenon takes place. This can be better understand by the Fig. 8.3. Depending on the magnitude of the negative bias established by VGS, a level of recombination between electrons and holes will occur that will reduce the number of free electrons in the n-channel available for conduction. SiO2 layer (dielectric)

Metal contact G ( ve)

+ + + + + + + + + + + + +

n-channel +

e e

e e e e

e

e

+ p-substrate

e

e e e e e

+

e

+

Recombination process

+ + Electrons repelled by negative potential at gate

Fig. 8.3. Reduction in free carriers in channel due to a negative potential at the gate terminal.

307

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)

Thus, the value of drain current is therefore decreases with increasing negative bias for VGS as show in Fig. 8.4. For VGS = 1 V, 2 V, 3 V, 4 V, and so on, to the pinch off level of 8 V. From the Fig. 8.4 it is clear that the drain and transfer characteristics for an n-channel depletion type MOSFET is same as that were exactly described for the JFET. However, for the positive value of gate-to-source voltage (VGS) the positive gate will draw additional electrons from the p-type substrate due to the reverse leakage current and establish new carriers through the collisions resulting between accelerating particles. ID (mA)

Depletion mode transfer curve

ID (mA)

Enhancement mode transfer curve

VGS = + 1 V

IDSS

VGS = 0 V VGS = 1 V VGS = 2 V VGS = 3 V

VGS

VGS

O

(a) Transfer characteristics for an n-channel depletion type MOSFET

VGS = 5 V VDS VGS = VP = – 8 V

(b) Drain characteristics for an n-channel depletion type MOSFET

Fig. 8.4.

From the Fig. 8.4, it is clear that, the application of a positive gate-to-source voltages (VGS) has enhanced the level of free electrons (charge carriers) in the channel compared to that encountered with VGS = 0 V. For this reason the region of positive gate voltages on the drain or transfer characteristics is often referred to as the enhancement region.

Although there are some similarities in construction and mode of operation between depletion-type and enhancement-type MOSFET, the characteristics of the enhancementtype MOSFET are quite different from anything discussed so far. The basic construction of n-channel enhancement type MOSFET is shown in Fig. 8.5. The n-channel enhancement-type MOSFET consists of a highly doped p-type substrate into which two highly doped n-regions are diffused. From Fig. 8.5 it is obvious that the main difference between the construction of depletion-type MOSFET and enhancement-type MOSFET is that in the former case the channel is already formed, however in the latter case (i.e., in enhancement type MOSFET) the channel is initially no formation of channel. The source (S) and drain (D) terminals are again connected through the metallic contacts to n-doped regions. The SiO2 layer is still present to isolate the gate between drain and source, but now it is simply separated from a section of the p-type material.

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BASIC ELECTRONICS ENGINEERING & DEVICES

D

SiO2

n-doped region

No-channel n Metallic contacts

p-type substrate

G

Substrate SS

n

S

n-doped region

Fig. 8.5. n-channel enhancement-type MOSFET.

Finally we conclude that the construction of an enhancement-type MOSFET is quite similar to that of the depletion-type MOSFET except for the absence of a channel between the drain and source terminal.

If VGS is set at 0 V and a voltage applied the drain and source of the device of Fig. 8.5, the absence of an n-channel will result in a current (ID) effectively zero amperes quite different from the depletion-type MOSFET and JFET where ID = IDSS at VGS = 0 V. When both VGS > 0 V and VDS > 0 V. When both VDS and VGS have been set at positive voltage greater than zero volts, establishing the drain and gate at a positive potential with respect to the source as shown in Fig. 8.6. As the positive potential is applied between gate and source, due to the presence of SiO2 layer which acts as a dielectric, is attracts the charge carrier (i.e., electrons) from the substrate. The SiO2 layer and its insulating qualities will prevent the negative carriers from being absorbed at the gate terminal. As VGS increases in magnitude the concentration of electrons-near the SiO 2 surface increases until eventually the induced n-type region can support a measurable flow between drain and source, resulting the formation of inversion layer. This inversion layer is formed when a certain gate-to-source voltage (VGS) is applied. Thus, the minimum value of gate voltage at which inversion of semiconductor surface-take place is known as threshold voltage (VT). Since the channel is non-existent with VGS = 0 V and “enhanced” by the application of a positive gate-to-source voltage, this type of MOSFET is called an enhancement-type MOSFET.

309

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)

SiO2 insulating layer + D

ID

+ + + + + + + +

G (+ ve) + –

+ –

VDS

Region depleted of p-type carriers (holes)

n

VGS

e

+

e e

+ p-substrate +

e

+

n

S

+

Formation of channel with the voltage applied to gate terminal (inversion layer) SS

Electrons attracted to positive gate

Fig. 8.6. Channel formation in the n-channel enhancement-type MOSFET.

As VGS is increased beyond the threshold level the density of free carriers in the induced channel will increase, resulting in an increased level of drain current. However, if we hold VGS constant and increase the level of VDS, the drain current will eventually reach a saturation level as occurred for the JFET and depletion-type MOSFET. In short : At VDS < VGS VT

:

An increase in VDS causes the ID to increase linearly and the MOSFET behaves as a resistance.

At VDS = VGS VT

:

This results in a slow increase of ID with increase in VDS.

At VDS > VGS VT

:

Further increase in VDS produce no change in current and the current saturation occur.

The drain and transfer characteristics of n-channel enhancement-type MOSFET is shown in Fig. 8.7. From Fig. 8.7 it is clear that for the values of VGS less than the threshold level the drain current of an enhancement-type MOSFET is 0 mA. For levels of VGS > VT the drain current is related to the applied gate-to-source voltage by the following non-linear relationship : ID = K (VGS VT)2 where

... (8.1)

VGS = Applied gate-to-source voltage VT = Threshold voltage ID = Drain current K = Constant that is a function of the construction of the device.

310

BASIC ELECTRONICS ENGINEERING & DEVICES

ID (mA)

ID (mA)

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

1

2 3 VT

4

5

6

7

8

0

VGS

VGS = + 8 V

VGS = + 7 V

VGS = + 6 V VGS = + 5 V VGS = + 4 V VGS = + 3 V 5

10

15

20

25

VDS

VGS = VT = 2 V

(a) Transfer characteristics

(b) Drain characteristics

Fig. 8.7. Transfer and drain characteristics of n-channel enhancement-type MOSFET.

The value of K can be determined from the following equation (derived from eqn. 8.1) where ID(on) and VGS(on) are the values for each at a particular point on the characteristics of the device. K=

I D (on)

cV

GS (on)

– VT

h

2

... (8.2)

It may be noted that for all the practical purpose the value of threshold voltage (VT) should be as low as possible, because a low value of threshold voltage allows : —

the use of low power supply voltage

—

smaller switching time due to the smaller voltage swing during switching.

—

higher packing densities.

Methods which are generally used to lower the magnitude of VT are given below : (1)

The silicon nitride approach makes use of a layer Si3N4 and SiO2, whose dielectric constant is about the twice that of SiO2 alone.

(2)

Polycrystalline silicon doped with boron is used as the gate electrode instead of aluminium.

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)

D

G

311

D

G

S n-channel FET

S p-channel FET

D

D

G

G

S n-channel enhancement MOSFET

S p-channel enhancement MOSFET

D

D

G

G

S n-channel depletion MOSFET

S p-channel depletion MOSFET

Fig. 8.8. Symbols for JFET and MOSFET.

JFETs and MOSFETs are quite similar in their operating principles and in their electrical characteristics. However, they differ in some aspects, as discussed below : 1. JFETs can only be operated in the depletion mode whereas MOSFETs can be operated in either depletion or in enhancement mode. In a JFET, if the gate is forward biased, excess carrier junction occurs and the gate current is substantial. Thus channel conductance is enhanced to some degree due to excess carriers but the device is never operated with gate forward biased because gate current is undesirable. 2. MOSFETs have input impedance much higher than that of FET. This is due to negligibly small leakage current.

312

BASIC ELECTRONICS ENGINEERING & DEVICES

3. JFETs have characteristics curves more flatter than those of MOSFETs indicating a higher drain-resistance. 4. When JFET is operated with a reverse bias on the junction, the gate current IG is larger than it would be in a comparable MOSFET. The current caused by minority carrier extraction across a reverse biased junction is greater, (per unit area) than the leakage current that is supported by the oxide layer in a MOSFET. Thus MOSFET devices are more useful in electrometer applications than the JFETs. For the above reason and also because MOSFETS are somewhat easier to manufacture, they are more widely used than the JFETs.

? 1. Explain the basic construction of a n-channel depletion type MOSFET. Draw and explain its characteristics. 2. What is the significant difference between the construction of an enhancement-type MOSFET and a depletion-type MOSFET ? 3. What are the advantages of MOSFET over JFETs ? 4. What do you mean by threshold voltage VT in the case of MOSFET ? 5. List the methods used to reduce the threshold voltage (VT ). 6. Explain the basic operation and characteristics of enhancement-type MOSFET. 7. Draw the symbol of enhancement and depletion type MOSFET. 8. What are the similarities and dissimilarities between the JFET and MOSFET.

Example 1. Sketch the transfer characteristics for an n-channel depletion-type MOSFET with IDSS = 10 mA and VP = 4 V.

ID (mA) IDSS 10

Solution : At VGS = 0 V, ID = IDSS = 10 mA VGS = VP = 4 V, ID = 0 mA VGS = ID = At

VP 2

=

9 8

4 = 2 V, 2

7

I DSS 10 = = 2.5 mA. 4 4

All these values are shown in Fig. P (8.1).

5 4 3

IDSS 4

I DSS ID = , VGS = 0.3 2 VP = 0.3 ( 4) = 1.2 V.

6

IDSS 2

2 1

VGS

4

2

1.2

Fig. P (8.1).

0

VGS

313

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) 20 V

Example 2. Determine the VDS for the network of Fig. P (8.2). Solution : From the Fig. P (8.2).

1.5 k

VGS = 0 V. Therefore IP = IDSS = 10 mA. so

VDS = VDD IDRD

or

VDS = 20 10 ×

or

VDS = 20 15

or

VDS = 5 V.

103

× 1.5 ×

G

109

Ans.

S

IDSS = 10 mA VP = 4 V

Fig. P (8.2).

Example 3. An n-channel E-MOSFET has the following parameters ID

(ON)

= 5 mA at VGS = 8 V and VGST = 4 V

Determine the drain current when VGS = 6 V. Solution : As per the equation : K =

K = Now, drain current,

I D ( ON )

cV

GS ( ON )

V GST

5 mA ( 8 4)2

h

2

= 0.3125 mA/V2

ID = k (VGS VST)2 = 0.3125 (6 4)2 = 1.25 mA.

Ans.

Example 4. The data sheet for a certain enhancement-type MOSFET reveals that ID(on) = 10 mA at VGS = 12 V and VT(on) = 3 V. Is this device P-channel or N-channel ? Find the value of ID when VGS = 6 V. Solution : Given

ID(on) = 10 mA VGS = 6 V VT(on) = 3 V

Since the value of VGS is negative for the enhancement-type MOSFET, this indicated that the device is P-channel. We know that the drain current, ID = K [VGS VT(on)]2 and

or

K =

K =

I D ( on )

cV

GS

VT ( on )

h

2

10 10 3 { – 12 – (– 3)} 2

... (1)

314

BASIC ELECTRONICS ENGINEERING & DEVICES

or

10 = .12 mA/V. 81

K =

Substituting this value of K and VGS = 6 V in eqn. (1), we have ID = 0.12 × 103 { 6 ( 3)}2 or

ID = 1.08 mA.

Ans.

Example 5. Find for the Network shown in Fig. P (8.3)

VPD = 9 V

(i) IDQ RD = 1.2 k

(ii) VDS. Solution : (i) We know that, K = or

K =

VT = 4 V

I D ( ON ) (V GS ( ON ) VT )2 5mA ( 7 4 )2

R

= 0.55 × 10–3 A/V2

ID = K(VGS – VT)2 = 0.55 × 10–3 (7 – 4)2

VGS(ON) = 7 V ID(ON) = 5 mA

RS = 0.5 k

= 0.55 × 10–3 × 9 = 4.95 × 10–3 Amp = 4.95 mA. (ii)

VDS = VDD – IDRD – IDRS

or

VDS = 9 – ID (RD + RS)

or

VDS = 9 – 4.95 × 10–3(1.2 + 0.5) × 103

or

VDS = 9 – 4.95 × 1.7

or

VDS = 9 – 8.415

or

VDS = 0.585 V Ans.

Fig. P (8.3)

9 Digital electronics began in 1946 with an electronic digital computer called ENIAC, which was implemented with vacuum-tube circuits. The first digital computer was built in 1944 at Harvard University, but it was electromechanical, not electronic. Generally there are two types of signal namely analog signal and digital signal. A continuously varying signal (voltage or current) is called an analog signal. For example, a sinusoidal signal is analog signal. However, a signal (voltage or current) which can have only two discrete values, is called a digital signal. For example, a square wave is a digital signal. An electronic circuit that is designed for two-state operation is called a digital circuit. The term digital is derived from the way in which computers perform operation by counting digits. For years, applications of digital electronics were confined to computer systems. Today, digital techniques are applied in many diverse areas, such as telephony, data processing, medical instruments, process control and consumer products. Digital technology has progressed from vacuum-tube circuits to integrated circuits and microprocessors. It is very interesting to know that in digital systems, the two states are used to represent numbers, symbols, alphabetic characters, and other types of information. In the two state number system, called binary, the two digits are 0 and 1. These binary digits are called bits.

In digital systems two logic levels represent the two binary digits, 1 and 0. Usually there are two logic systems are most widely used namely positive logic system and negative logic system. If the higher of the two voltages represents a 1 and the lower voltage represents a 0, the system is called a positive logic system. On the other hand, if the lower voltage represents a 1 and the higher voltage represents a 0, we have a negative logic system. i.e., for positive logic and, for negative logic

R| S| T R| S| T

HIGH = 1 LOW = 0 HIGH = 0 LOW = 1 315

Comp-1/Laxmi-5/Computer/Revision/Belec-9—10.5.07

316

BASIC ELECTRONICS ENGINEERING & DEVICES

It may be noted that both positive logic and negative logic are used in digital systems, but positive logic is the more common. Pulses are very important in the operation of digital circuits and systems because voltage levels are normally changing back and forth between the the HIGH and LOW states. Fig. 9.1 shows the pulse waveform for positive pulse and negative pulse. HIGH

HIGH Trailing edge

Leading edge

Leading edge

LOW

Trailing edge

LOW

(a) Positive pulse

(b) Negative pulse

Fig. 9.1. Pulse waveform.

A number system is simply a way to count. Number system is broadly divided into four system namely : (1) Binary number system. (2) Decimal number system. (3) Octal number system. (4) Hexadecimal number system. Table 9.1 illustrates several bases and the numerals (set of characters) used in their respective number system. Table 9.1 Radix (base)

Character set

2 (binary)

(0, 1)

3

(0, 1, 2)

4

(0, 1, 2, 3)

5

(0, 1, 2, 3, 4)

.

.

.

.

8 (octal)

(0, 1, 2, 3, 4, 5, 6, 7)

9

(0, 1, 2, 3, 4, 5, 6, 7, 8)

10 (decimal)

(0, 1, 2, 3, 4, 5, 6, 7, 8, 9)

.

.

.

.

.

.

.

.

.

.

16 (hexadecimal)

(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)

NUMBER SYSTEMS AND LOGIC GATES

317

In the binary number system, only two digits (0 and 1) are used. Therefore the base of this system is 2. In a binary number, each position has a value that is 2 times the value of the next position to its immediate right. In other words, every position can be expressed by 2 raised to some power, each binary digit (0 or 1) is referred to as a bit. A string of four bits is called a nibble and eight bits make a byte. Thus, 1011 is a nibble and 10010111 is a binary byte. For example, the binary number 1001 is equal to the decimal number 9. This can be readily shown as under : 1001 = 1 × 23 + 0 × 22 + 0 × 21 + 1 × 20 = 9. It may be always remember that for binary numbers, the digit at the extreme left is referred to as least significant bit (LSB). However the digit at the extreme right is referred to as most significant bit (MSB). For example, binary number 1010, 1 is MSB while 0 is LSB. The binary number system is less complicated than the digital system because it is composed of only two digits.

In the decimal number system, the ten digits (0, 1, 2 .............. 9) are used. Therefore the base of this system is 10. In this system the count starts as 0, 1, 2 .............. 9. After 9, we are to write the next number. To do so, we use the second digit of the decimal system (i.e., 1) followed by the first digit (i.e., 0). So after 9, the next number is 10. The count again continues as 10, 11, 12 .............. 19. After 19, we use the third digit of the system (i.e., 2) followed by the first digit (i.e., 0) and the count continues as 20, 21 .............. etc. In this way we get the number upto 99.

In the octal number system, the system is composed of eight digits, which are 0, 1, 2, 3, 4, 5, 6, 7. Counting in octal is the same as counting in decimal, except any number with as 8 or 9 is omitted. Therefore the base of the octal number system is 8. To distinguish octal numbers from decimal numbers, we will use the subscript 8 to indicate the octal number. For example, (15) 8 is a representation of octal number while (15)10 is a representation of decimal number. The hexadecimal number system has a base of 16. That is, it is composed of 16 digits and characters. Many digital systems process binary data in groups that are multiplies of four bits, making the hexadecimal number very convenient because each hexadecimal digit represents a four-bit binary number. Ten digits and six alphabetic characters make up this number system. We will use subscript 16 to indicate the hexadecimal number.

318

BASIC ELECTRONICS ENGINEERING & DEVICES

Table 9.2 shows the representation of a hexadecimal numbers : Table 9.2 Decimal

Binary

Hexadecimal

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110

0 1 2 3 4 5 6 7 8 9 A B C D E

15

1111

F

Conversion of bases means one number system is converted into another. For example, a binary system converted into decimal number system, here the base 2 is converted into base 10. There are many conversion may possible namely : Decimal to binary conversion. Binary to decimal conversion. Octal to binary conversion. Binary to octal conversion. Binary to hexadecimal conversion. Hexadecimal to binary conversion. Decimal to hexadecimal conversion. Before starting the conversion it is very necessary to know that any number (N), in any base or radix (r) would be represented as : (N)r = dn1 dn2 dn3 ....... d1d0 integer part

.

d1 d2 d3 ........ dm

radix point

fractional part

or in positional notation as : (N)r = dn1 r n1 + dn2 r n2 + ...... di r i + ...... d1r + d0 + d1 r 1 + d2 r 2 + ...... dm r m. n 1

or

(N)r =

d

K m

k

rk

319

NUMBER SYSTEMS AND LOGIC GATES

where,

r d N n m K

= = = = = =

radix or base of a number system character from the character set of the radix or digit number to be represented in radix r number of digits in the integer portion of N number of digits in the fractional portion of N any digit position of number.

The method used for decimal to binary conversion is called double-dubble because it requires successive division by 2. As the conversion from decimal to binary or to any other base-r system is more convenient if the number is separated into an integer part and a fraction part and the conversion of each part done separately. Double Dabble Method. This is the most popular method to convert the decimal numbers into binary numbers. In this method, we follow the following steps : Step 1 : Divide the decimal number by 2. Step 2 : Note the quotient and remainder. Step 3 : Again divide the quotient by 2 and note the next quotient and remainder. Step 4 : Follow the step-1 to step-3 upto the quotient is 1. This is also the last remainder. Step 5 : Reading of remainder from bottom to top gives the binary equivalent of decimal number. The conversion from decimal to binary is best explained by example as given below : For example, convert decimal 41 to binary. First, 41 is divided by 2 to give an integer quotient of 20 and a remainder of 1, the quotient is again divided by 2 to give a new quotient and remainder. This process is continued until the integer quotient becomes 0. The coefficients of the desired binary number are obtained from the remainders as follows : Remainder

Coefficient

41 = 20 2

1

1

20 = 10 2

0

0

10 = 5 2

0

0

5 = 2 2

1

1

2 = 1 2

0

0

1 = 0 2

1

1

Read out bottom to top

Integer quotient

320

BASIC ELECTRONICS ENGINEERING & DEVICES

Thus,

(41)10 = (101001)2

This is the required conversion of decimal to binary number. NOTE :

The above explained method, i.e., divide by 2 can’t be applied for the fractional part. To find the binary equivalent of a number having both integer and fractional parts, the convert both separately and write together. To convert the fractional part, we multiply the fractional number by 2 and register the integer obtained reading the integer carry’s obtained from top to bottom we obtain the binary equivalent of the fractional number.

Example. Convert (0.825)10 into binary. Solution : To convert the number into binary we multiply it by 2 and register the integer part, i.e., Product

Integer part

0.825

× 2

1.650

MSB 1

0.650

× 2

1.300

1

0.3

× 2

0.6

0

0.6

× 2

1.2

1

0.2

× 2

0.4

0

0.4

× 2

0.8

0

0.8

× 2

1.6

and so on

.

.

LSB

1 .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Reading top to bottom

Fractional part

Now reading the registered integer parts, resulting from each product we obtain the binary equivalent of given fractional decimal number, i.e., (0.825)10 = (0.1101001........)2.

Ans.

Binary number can be converted to equivalent decimal numbers quite easily. The conversion of binary number to decimal number can better understand with the help of example given below : Given binary number is 110011. Its conversion to equivalent decimal number involves the following two steps : (i) Place the decimal value of each position of the binary number. (ii) Add all the decimal values to get the decimal number. 1

1

0

0

1

1

25

24

23

22

21

20

321

NUMBER SYSTEMS AND LOGIC GATES

(110011)2 = 1 × 25 + 1 × 24 + 0 × 23 + 0 × 22 + 1 × 21 + 1 × 20

Thus,

= 51

(110011)2 = (51)10

This is the required conversion of binary number to decimal number. Streamlined Method. This method is almost similar to the positional notation or weight multiplication method discussed above but having easy steps. The following steps are used in this conversion method. Step 1 : Write the binary number. Step 2 : Write the weights of each bit just below it i.e., 1, 2, 4, ........., 2n, working from the right. Step 3 : If a zero appears in a bit position, struck out the decimal weight for that position. Step 4 : Add the remaining weights to obtain the decimal equivalent. The example given below better describes the operation of binary-to-decimal conversion by using streamlined method. Example. Convert the following binary numbers into decimal equivalent : (a) (11011001)2

(b) (11001101101)2

(c) (100110)2 .

Solution : (a) To perform the conversion using streamlined method, we use the following steps : Given :

(N)2 = (11011001)2

Step 1

1

1

0

1

1

0

0

1

Step 2

128

64

32

16

8

4

2

1

Step 3

128

64

32

16

8

4

2

1

Step 4

128 +

64

+

16 +

8

+

1

(N)10 = 217

Therefore,

(11011001)2 = (217)10 .

Ans.

(b) Given binary number : (N)2 = (110011.1101)2 Using streamlined method, we have, Step 1

1

1

0

0

1

1

.

Step 2

32

16

8

4

2

1

binary point

Step 3

32

16

8

4

2

1

Step 4

32 + 16

+

2 +

1

+

1

1

0

1

1 2

1 4

1 8

1 16

1 2

1 4

1 8

1 16

1 + 2

1 4

+

1 16

322

BASIC ELECTRONICS ENGINEERING & DEVICES

or Therefore,

(N)10 = (51.8125)10 (110011.1101)2 = (51.8125)10.

Ans.

(c) Given the binary number, (N)2 = (100110)2 Using streamlined method for base conversion, we have, Step 1

1

0

0

1

1

0

Step 2

32

16

8

4

2

1

Step 3

32

16

8

4

2

1

Step 4

32

+

4

Therefore, or

+

2

(N)10 = (38)10 (100110)2 = (38)10.

Ans.

Since the octal number system has a base of eight, each successive digit position in an increasing power of eight, beginning in the right-most column with 8. The conversion of octal number into a decimal number can better understand by the example given below. Here multiplying each digit by its weight and summing the product. Example. Convert (2374)8 into decimal. Solution :

(2374)8 = 2 × 83 + 3 × 82 + 7 × 81 + 4 × 80 = 2 × 512 + 3 × 64 + 7 × 8 + 4 × 1 = (1276)10

(2374)8 = (1276)10

This is required octal-to-decimal conversion. For example, let us consider the conversion of 543.2610 to octal number. Consider the integer part (Nf) 543 8

543

8

67

8

8

3

8

1

0

0

1 MSB

Remainders 7 LSB

Reading the remainders from the bottom to the top we have 543 10 = 10378. Now consider the fractional part (Nf) 0.2610 and multiply repeatedly as follows :

323

NUMBER SYSTEMS AND LOGIC GATES

Base

Fractional number

Product

Fractional part of the product

Overflow or carry

8

×

0.26

2.08

0.08

2 MSB

8

×

0.08

0.64

0.64

0

8

×

0.64

5.12

0.12

5

8

×

0.12

0.96

0.96

0 LSB

Terminating the product after 4th place we have 0.2610 = 0.2058. Hence 543.2610 is equivalent to 1037.2058. The primary requirement of conversion of octal number into binary number is in the representation of binary number. Since it takes only one octal digit to represent three bits, octal numbers are much easier to “read” than binary numbers. Because all three-bit binary numbers are required to represent the eight octal digits, it is very easy to convert from octal to binary and from binary to octal. Table 9.3 Octal digit

Binary

0

000

1

001

2

010

3

011

4

100

5

101

6

110

7

111

To convert an octal number to a binary number, simply replace each octal digit by the appropriate three bits. This is illustrated in the following example : Convert (14)8 into binary (14)8 = ( 001 . 100 )2

{from Table 9.3}

This is the required conversion of octal-to decimal.

Converting a binary number to hexadecimal is a straight forward procedure. Simply break the binary number into four-bit groups starting at the binary point, and replace each group with the equivalent hexadecimal symbol. For example, convert (1100101001011101)2 into hexadecimal number 1100 1010 0101 1101 C

A

5

D

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BASIC ELECTRONICS ENGINEERING & DEVICES

Thus,

(1100101001011101)2 = (C A 5 D)16

This is the required conversion of binary to hexadecimal.

To convert from a hexadecimal number to a binary number, reverse the process and replace each hexadecimal symbol with appropriate four bits. For example, convert (10 A 4)16 into binary number

Thus,

1

=

0001

0

=

0000

A

=

1010

4

=

0100

(10A4)16 = (0001 0000 1010 D100)16

This is required conversion of hexadecimal-to-binary number.

In order to convert hexadecimal number into decimal number the following two methods are generally used. 1. First convert the hexadecimal number to binary and then convert from binary to decimal. 2. Another way to convert a hexadecimal number to its decimal equivalent is multiplying each hexadecimal digit by its weight and then taking the sum of these products. For example, convert (1C)16 into decimal. Method 1. Now,

(IC)16 = ( 0001 1100 )2 (00011100)2 = 1 × 24 + 1 × 23 + 1 × 22 = 16 + 8 + 4 (00011100)2 = (28)10

(1C)16 = (28)10

This is the required conversion of hexadecimal-to-decimal number. Method 2.

(1C)16 = 1 × 161 + C × 160 = 1 × 16 + 12 × 1 = 16 + 12 = (28)10

(1C)16 = (28)10

Ans.

Decimal-to-hexadecimal number conversion can be obtained by using repeated division of a decimal number by 16 will produce the equivalent hexadecimal number

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NUMBER SYSTEMS AND LOGIC GATES

formed by the remainders of each division. This is similar to the repeated division-by2 for decimal to binary conversion and repeated division-by-8 for decimal-to-octal conversion. The following example illustrates this procedure : Convert (650)10 to hexadecimal number. (650)10 16

650

Hexadecimal number 40

640 10 16

40

A (LSB)

8

2 (MSB)

2

32 8 16

2

0

0 2 Therefore

(650)10 = (28A)16

This is the required conversion of decimal-to-hexadecimal number. NOTE 1. In order to convert very large decimal number into binary number, it will be very simple to convert first of all the decimal number into hexadecimal and then into binary. NOTE 2. The binary number we have seen so far have been whole numbers. Fractional numbers can also be represented in binary by placing bits to the right of the binary point. Just as fractional decimal digits one placed to the right of the decimal point. The column weight of a binary number are : 2n ..... 2423222120 . 212223 ..... 2n Binary point This indicates that all the bits to the left of the binary point have weights that are positive powers of two, as previously discussed. All bits to the right of the binary point have weights that are negative powers of two, or fractional weights (2 1, 22 ..... etc.). For example, convert binary number .1011 into decimal number. (.1011)2 = 1 × 21 + 0 × 22 + 1 × 23 + 1 × 24 1 1 1 + 0 + + 2 8 16 = .5 + 0 + .125 + .0625 =

= (.6875)10 NOTE 3. This procedure can also be apply for the fractional numbers of bases other than the binary. For example, convert (.325)8 into decimal.

326

BASIC ELECTRONICS ENGINEERING & DEVICES (.375)8 = 3 × 81 + 2 × 82 + 5 × 83 =3 ×

1 1 1 + 2 × + 5 × 8 64 512

= 3 × (.125) + 2 × (.015623) + 5 × (.001953) = (.416015)10

Thus,

(.325)8 = (.41605)10

Hexadecimal number system (i) It is more convenient when the word length is divisible by 4 bit and not by 3 bit. For example, a 4, 8, 16, 32 or 64 bit word divides evenly into hexadecimal digits but not so for octal digits of these bit. (ii) Hexadecimal system is significantly shorter, especially for long computer word lengths, such as 48 or 64 bits. Octal number system 1. As it uses only numeric digit and not alphabets one cannot be confused with names of words. 2. It is easy to derive octal from a binary number. 3. It is simpler to convert octal numbers to decimal number. 4. As in octal we have all digits same as in decimal digits whereas in hexadecimal we have letters as well. 5. Octal arithmetic is simple and less confusing.

As you have learned, decimal, octal and hexadecimal numbers can be represented by binary digits. Not only numbers, but letters and other symbols, can represented by 1s and 0s. In fact, any entity expressible as numbers, letters other symbols can be represented by binary digits, and can be processed by digital logic circuits. Combination of binary digits that represent numbers, letters or symbols are digital codes. In many applications, special codes are used for such auxillary functions as error detection.

The 8421 code is a type of binary coded decimal (BCD) code and is composed of four bits representing the decimal digits 0 through 9. The designation 8421 indicates the binary weights of the four bits (23, 22, 21, 20). Binary coded decimal means that each decimal digit is represented by a binary code of four bits. You should realize that with four bits, sixteen numbers (24) can be represented, and that in the 8421 code only ten of these are used. The six code combinations that are not used : 1010, 1011, 1100, 1101, 1110, and 1111 we invalid in the 8421 BCD code.

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NUMBER SYSTEMS AND LOGIC GATES

Table 9.4. The 8421 BCD code 8421 (BCD)

Decimal

0000

0

0001

1

0010

2

0011

3

0100

4

0101

5

0110

6

0111

7

1000

8

1001

9

For example, write BCD number for the decimal number 246. From above Table 9.4 Decimal number

Corresponding BCD

2

0010

4

0100

6

0110

Therefore

In Gray is changed. incremented only one bit

(246)BCD = (0010 0100 0110)2

Codes, we assume as one advances from one number to next, only one bit Not only change in one bit takes place every time decimal number is by one from 0 through 9 but even for the change from 9 to 0 also has change. Table 9.5 shows gray codes for decimal numbers from 0 to 12. Table 9.5. Gray codes Decimal digit

Binary

Gray codes

0 1 2 3 4 5 6 7 8 9 10 11 12

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100

0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010

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The binary numbers can be converted into gray code equivalent by the following method : 1. Record the most significant bit. 2. Add this bit to the next position, neglecting carry if any record the sum. 3. Continue recording sums until completed and LSB is reached. The gray code number will always have the same number of bits as the binary number. Example. Convert (1100 1010)2 into gray code. Solution. First record the most significant bit. Then add this most significant bit to the next most significant bit (1 + 1 = 1) and ignoring the carry generated record the sum, as 0 bit. Now add the second most significant bit to the third significant bit (1 + 0 = 1). Record it then add the third significant bit to the fourth significant bit (0 + 0 = 0). Record it. In this way continue upto the LSB (1 + 0 = 1) as shown in Fig. 9.2. Binary number

1

1

0

0

1

0

1

0

GRAY CODE

1

0

1

0

1

1

1

1

Fig. 9.2.

Example. Convert binary 10010113 into gray code. Solution. The conversion is shown in Fig. 9.3. Binary number

1

0

0

1

0

1

1

GRAY CODE

1

1

0

1

1

1

0

Fig. 9.3.

The gray code numbers can be converted into equivalent binary number as follows : (i) Record the MSB. (ii) Add the binary MSB to the next significant bit of the gray code. (iii) Ignoring carries record the result. (iv) Continue this process until you reach LSB. Example. Convert a gray code 1001 1011 to binary. Solution. First record the MSB of gray code. This will be the MSB of equivalent binary. Then add this MSB to the next most significant bit of the gray code number (1 + 0 = 1). Record it as the second most significant bit of equivalent binary. Add this second most significant bit of binary to the third most significant bit of equivalent binary. Add this third most significant bit of the gray code (1 + 0 = 1). Record sum as

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NUMBER SYSTEMS AND LOGIC GATES

third most significant bit of equivalent binary. Add this third most significant bit of binary so obtained to the fourth most significant bit of the gray code (1 + 1 = 0) and ignoring the carry generated record it as the fourth most significant bit of the equivalent binary (0 in this case). Continue this process till the last between bit of equivalent binary is added to the LSB of the gray code as shown in Fig. 9.4. GRAY CODE

Binary Number

MSB 1

0

0

1

1

0

1

LSB 1

1

1

1

0

1

1

0

1

Fig. 9.4.

Example. Convert a gray code 11100111 into binary. Solution. The conversion is shown in Fig. 9.5. GRAY CODE

1

Binary Number

1

1

1

0

0

1

1

1

0

1

1

1

0

1

0

Fig. 9.5.

In this code, there is no positional weighted, i.e., each position within the binary number is not assigned a prefixed value. There are two types of codes in non-weighted codes.

There is another important BCD code. For converting decimal number in excess3 code (also called XS-3). We add three to the each decimal digit before converting it into equivalent binary. The XS-3 code is related to the 8421 BCD code because of its binary coded decimal nature i.e., each 4 bit group in XS-3 code is equal to a specific decimal digit. This will be clear from the following examples. Table 9.6 shows XS-3 code along with their complements and decimal number. Table 9.6. Excess-3 code for decimal numbers Excess-3 code

Complement of excess-3 code (9’s complement)

Decimal

8421 BCD

0011

1100

0

0000

0100

1011

1

0001

0101

1010

2

0010

0110

1001

3

0011

0111

1000

4

0100

1000

0111

5

0101

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BASIC ELECTRONICS ENGINEERING & DEVICES 1001

0110

6

0110

1010

0101

7

0111

1011

0100

8

1000

1100

0011

9

1001

0100 0011

1011 1100

10

0001 0000

0100 0100

1011 1011

11

0001 0001

Example. Express 129 to an excess-3 number. Solution. Before converting each group into binary, add 3, i.e., 1

2

9

+ 3

+ 3

+ 3

4

5

12

0100

0101

1100

Hence the code for 12910 in the excess-3 code is 0100 0101 1100. The main problem in BCD (8421) was addition of the numbers whose sum exceeds 9. This excess-3 code has very interesting properties when used in addition. For adding in excess-3 binary number are added as usual and if there is a carry out, add 0011 and if there is no carry out from the four bit group, subtract 0011. Following examples will illustrate both these cases. Example. Add 610 and 310 in XS-3 code. Solution.

Excess 3 for 6 =

1001

Excess 3 for 3 =

0110

Sum =

1111

Since we are getting no 0011

carry subtract. Excess-3 for sum (12)

=

1100

Example. Add 36 and 39 in XS-3 form. Solution.

A

B

XS-3 for 36

=

0110

1001

36

XS-3 for 39

=

+ 0110

1100

+ 39

1101

0101

75

0011

+ 0011

1010

1000

Subtract and add 3 as per rule stated above XS-3 for 75

NUMBER SYSTEMS AND LOGIC GATES

331

In the above example in column B we add 1001 and 1100 and get 0101 with a carry of 1 for column A. In column A we add 0110 and 0110 and the carry we got from column B and get 1101 with no carry. As there is carry the result in column B is back in 8421 code. The result in column A is still in excess-6 form as this column does not produce any carry. To get the result in XS-3 we should add 3 to the sum obtained in column B as there is a carry and subtract 3 from the sum obtained in column A as there is no carry. The final answer is 1010 1000 which is XS-3 number for 75. When carry is generated, the sum is expressed automatically in 8421 code. NOTE :

This type of codes are self complementary which means if we change all the 1’s to zeros and all the zeros to 1 in the number, the resulting number is 9’s complement of the original number. For example, the decimal number 7 has the XS-3 code version as 1010. Its complement (1010 = 0101) in XS-3 code 0101 represents 2 which is the 9’s complement of 7. XS-3 codes are very useful in digital systems as this requires very simple electronic circuit for performing subtraction operation for such codes. The XS-3 code is very useful in arithmetic circuit as it is very easy to complement.

Need of Complements ? Complements in digital systems are used for simplifying the subtraction operation and for logical manipulation. There are two types of complements for each base-r (i.e., 2, 8, 10, 16 etc.) system namely : (1) Radix complement (2) Diminished radix complement. The radix complement is referred to as the r’s complement and the diminished radix complement is referred to as (r 1)’s complement. For example, if we put base r = 2 (i.e., binary system), the two types are referred to as the 2’s complement and 1’s complement for binary number. On the other hand, if we put r = 10 (i.e., decimal number system), the two types are referred to as the 10’s complement and the 9’s complement for decimal number system. (1) Radix Complement. The r’s complement of an n-digit number N in base r is defined as rn N for N = 0 and 0 for N = 0. Comparing with the (r 1)’s complement, we note that the r’s complement is obtained by adding 1 to the (r 1)’s complement since rn N = [(rn 1) N] + 1 Thus, the 10’s complement of decimal 4389 is 5610 + 1 = 5611 and is obtained by adding 1 to the 9’s complement value. The 2’s complement of binary 101100 is 010011 + 1 = 010100 and is obtained by adding 1 to the 1’s complement value. Since 10n is a number represented by a 1 followed by n 0’s, 10n N, which is the 10’s complement of N, can be formed also by leaving all least significant 0’s unchanged, subtracting the first non-zero least significant digit from 10, and subtracting all higher significant digits from 9.

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BASIC ELECTRONICS ENGINEERING & DEVICES

For example : (i) The 10’s complement of 023495 is 97.6505 (ii) The 10’s complement of 2345 is 7655 (iii) The 10’s complement of 12345 is 87655. The 10’s complement of the first number is obtained by subtracting 5 from 10 in the least significant position and subtracting all other digits from 9. The example (2) and (3) follow the same rule. Similarly, the 2’s complement can be formed by leaving all least significant 0’s and the first is unchanged, and replacing 1’s with 0’s and 0’s with 1’s in all other higher significant digits. For example : (i) The 2’s complement of 11010100 is 00101100 (ii) The 2’s complement of 01100111 is 10011001 The 2’s complement of the first number is obtained by leaving the two least significant 0’s and the first 1 is unchanged, and then replacing 1’s with 0’s and 0’s with 1’s in the other 5 most significant digits. The 2’s complement of the second number is obtained by leaving the least significant 1 unchanged and complementing all other digits. (2) Diminished Radix Complement. The (r 1)’s complement of N (i.e., a given number) in base r having n digits is defined as (rn 1) N. For decimal numbers r = 10 and r 1 = 9, so the 9’s complement of N is (10n 1) N. Now, 10n represents a number that consists of a single 1 followed by n 0’s. 10n 1 is the number represented by n 9’s. For example, if n = 3 we have 103 = 1000 and 103 1 = 999. It follows that the 9’s complement of a decimal number is obtained by subtracting each digits from 9. For example : The 9’s complement of 347800 is : 999999 347800 = 652199 However, for binary numbers, r = 2 and r 1 = 1, so the 1’s complement of N is (2n 1) N. Again, 2n is represented by a binary number that consists of a 1 followed by n 0’s . 2n 1 is a binary number represented by n 1’s. For example, if n = 4 we have 24 = (10000)2 and 24 1 = (1111)2. Thus the 1’s complement of a binary number is obtained by subtracting each digit from 1. However, when subtracting binary digits from 1, we can have either 1 0 = 1 or 1 1 = 0, which causes the bit to change from 0 to 1 or from 1 to 0. Therefore, the 1’s complement of a binary number is obtained by changing 1’s to 0’s and 0’s to 1’s. For example : The 1’s complement of 1011000 is 0100111. NOTE :

The (r 1)’s complement of octal or hexadecimal numbers is obtained by subtracting each digit from 7 or F, respectively.

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NUMBER SYSTEMS AND LOGIC GATES

So far in all the discussions we have considered all the numbers as positive numbers. However, in all the number system both positive and negative values are possible. The normal procedure to represent a positive or negative number is to use a + (plus) for positive and (minus) for negative number before the number. However, in digital systems or computers we work in binary system and use only 0’s and 1’s and every number is represented as a combination of 0’s and 1’s. Hence for representing negative numbers in binary we should use 0 or 1 only. There are following three important signed number systems :

One method of representing a signed number is to use an extra bit at the left most end or before the most significant bit. This additional bit is usually known as sign bit and placed at the most significant end to represent the sign. A 0 is by convention used to represent the + sign and 1 is used as sign for representing the sign. For example, + 7 can be represented as 0, 111 and 6 as 1,110. For separating sign bit from the actual number a comma is used. In this simple signed system the MSB (most significant bit) represents the sign of the number and this notation is called signed binary. In an n bit number the first i.e., MSB represents the sign of the number and the remaining n 1 bits express the magnitude of the number in binary. For example, Sign bit 2510 = 1,110012

1 ()

+ 1310 = 0,11012

0 (+)

2010 = 1,101002

1 ()

1410 = 0,11102

0 (+)

In Table 9.7 few 4 bit signed binary numbers along with their equivalent decimal numbers are shown. Table 9.7. 4 bit signed binary numbers and their decimal equivalent Decimal

Binary

Decimal

Binary

+ 0

0,000

0

1,000

+ 1

0,001

1

1,001

+ 2

0,010

2

1,010

+ 3

0,011

3

1,011

+ 4

0,100

4

1,100

+ 5

0,101

5

1,101

+ 6

0,110

6

1,110

+ 7

0,111

7

1,111

This signed binary system makes the arithmetic difficult because the sum of the positive and negative of a number is not zero. The advantage of this representation is that we can use a single basic electronic circuit for addition and subtraction.

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The 1’s complement of a binary number is obtained by changing each 0 to a 1, and each 1 to a 0. This complemented value represents the negative of the original number. In hardware or digital systems it is very easy to obtain the 1’s complement by simply feeding all bits through invertors. In 1’s complement system the positive numbers are represented in a similar way as in sign magnitude representation. However the negative numbers in 1’s complement representation are expressed in a different way. For example, the number 6 is represented as 1,001. The MSB (the bit appearing before the comma) is the sign bit. To obtain this representation, as stated above, replace every 1 by a 0 and every 0 by a 1 in the binary representation of the number + 6 (0,110). This process of replacing 0 bit by a 1 and 1 bit by a 0 is called bit complementing. In general for a binary number of n bits (excluding the sign bit) its 1’s complement can be obtained by the following relation. 1’ complement of a binary number 0, X = 1, (2n 1 X ) For example, the complement of number (+ 12), 0,1100 can be obtained by substituting n = 4 (number of bits excluding sign bit) in the above relation i.e., 1’ complement of binary number 0,1100 = 1, (24 1 1100) = 1, (10000 1 1100) = 1, (1111 1100) = 1,0011 The same result is obtained by bit complementing 0,1100 i.e., changing 0’s to 1 and 1’s to zero. Addition and Subtraction in 1’s Complement Notation First we shall discuss the addition rules for binary numbers represented in the notation of 1’s complement assuming the numbers to be 4-bit. For adding two positive numbers we add the binary numbers including their sign bit. For example, we have for the sum of + 4 and + 9 + 4 = 0,0100 + 9 = 0,1001 + 13 = 0,1101 However, if we add two numbers whose sum exceeds 15 we find this addition gives incorrect answer as is clear from the addition of + 9 and + 10 + 9 = 0,1001 + 10 = 0,1010 = 1,0011

which is not equal to 19.

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NUMBER SYSTEMS AND LOGIC GATES

For adding + 9 and + 10 if we use 8-bits we have + 9 =

0,0001001

+ 10 =

0,0001010

=

1,0010011

which is equal to 19.

For adding eight bit number the sum should not exceed 255. In general for adding positive numbers of n bit this rule will apply only if the sum does not exceeds 2n 1. The main advantage of 1’s complementary representation is that the subtraction can be done as addition of the 1’s complement of the number. For example, the subtraction of 7 from 21 can be carried out as follows : 2110 710 = 21 + ( 7) In 1’s complement eight-bit form we have 00010101 = + 21 + 11111000 = Sum neglecting carry

7

00001101 = + 13 + 1 End around carry 00001110 =

14

In the above example the subtraction of 7 from 21 is done as the addition of 21 and ( 7). We find on adding + 21 and 7 we get 13 which is one short than the actual answer + 14, if we neglect the carry generated. To get the correct answer we add the carry generated to the binary sum which we have got by neglecting the carry generated in the addition and this carry generated in the addition, would be added to the least significant place of the sum obtained neglecting the carry. When we add a positive number with a negative number there are two possibilities either the answer will be positive or negative. If the sum of the two numbers including sign bits results in an over flow i.e., there is end around carry beyond the sign bit the answer is positive and the result is obtained by adding carry to the sum obtained by adding carry, to the sum obtained and is the right answer with the right sign as was the case in the above example. However, if on adding a positive and a negative number there is no over flow i.e., if no carry is generated the result is negative and result obtained is correct as it is. This will be clear from the following example : Example. Add 9 and + 4 using 1’s complement notation. Solution. In 1’s complement notation we have + 9 = 1,0110 + 4 = 0,0100 Sum

5 = 1,1010

To check the result find the 1’s complement from the sum (as it is negative number) which is 00101 or + 5 hence 1,1010 is 5 and is correct answer.

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BASIC ELECTRONICS ENGINEERING & DEVICES

If we add two negative numbers and there is a carry generated, this carry is added to the LSB and the result so obtained is the right answer with the right sign. Example. Add 9 and 5 using 1’s complement. Solution.

9 = 1,0110 5 = 1,1010 1 1,0000

Add carry generated

1

14

1,0001

Again as stated earlier this rule holds good only if the sum of the two numbers does not exceeds 15 for 4 bit operand an 255 for 8 bit operand. Consider the addition of 8 and 8 8 = 1,0111 + 8 = 0,1000 0 = 1,1111 From this we find that the one’s complement of zero, is not zero. Hence there are two possible representation for zero in one’s complement representation system i.e., + 0 is 0,0000 and 0 is 1,1111. Because of dual representation for zero and the necessity of the end around carry, 1’s complement arithmetic is not used for performing subtraction in digital systems. For this we use 2’s complement representation.

The 2’s complement of a binary number is a binary number which is obtained by adding 1 to the 1’s complement of the number i.e., 2’s complement = 1’s complement + 1 For example, the 2’s complement of 1010 can be obtained by first finding its 1’s complement which is 0101 and then adding 1 to it i.e., 0101 + 1 (= 0110) hence the 2’s complement of 1010 is 0110. In another method for a number of n bits say x, the 2’s complement is given by the following relation 2’s complement of x = (2n x) There is another method of obtaining 2’s complement of a number in which we scan the number from right to left and complement all the bits appearing after the first appearance of a 1 i.e., starting from LSB and moving from right to left, copy each bit including first 1 bit encountered, then complement the remaining bits.

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NUMBER SYSTEMS AND LOGIC GATES

The concept of 2’s complement can be better understand by the examples given below : Example. Express 6 in 2’s complement form. Solution. First method Binary equivalent of the positive number i.e., 6

= 00000110

1’s complement of the number

11111001

Add 1

=

2’s complement of the number

+

1

11111010

2nd method Considering the word length 8 (= n) 2n = 28 =

100000000

Subtract 6

00000110

Result

11111010

3rd method Original number

=

00000110

Copy upto first 1

=

10

Complementing remaining bits

=

11111010

If we compare the results obtained by all the three methods we find the result is same in every case. Example. Express 18 in 2’s complement form. Solution. First method Positive of the number in binary =

00010010

1’s complement of the number

=

11101101

Add 1

=

+ 1

2’s complement of the number

=

11101110

2nd method Considering word length = 8 (= n) 2n = 28 = Subtracting 18

100000000 00010010 11101110

3rd method Original number

=

00010010

Copying upto first 1

=

10

Complementing remaining bit

=

11101110

Again we see by all the three methods we get the same result.

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BASIC ELECTRONICS ENGINEERING & DEVICES

For adding two positive numbers the situation is identical to the one described for 1’s complement notation. However when we add two numbers out of which one is positive and other negative, the result can be positive or negative. The addition of such numbers is carried out ignoring overflow if any or by ignoring the carry generated if any. As in earlier case, the sign bit is treated as the part of the number. After performing addition the bit in the sign bit position represents the correct sign bit. Example. Add + 9 and 8 using 2’s complement using 8 bits. Solution.

+ 9 =

0

0001001

8 =

1 1111000

Sum =

1 0000001 ignore this carry

or =

0 0000001

Hence the addition of + 9 and 8 gives us 1 which is correct. Example. Add 18 and + 17 using 2’s complement. Solution. + 17 = 00010001 18 = 11101110 Sum

= 11111111

To check the result take 2’s complement of 1111 1111 (as this is negative number) which is 0000 0001 which shows 1111 1111 is equal to 1. Hence the result obtained is correct. Example. Add + 128 and 130. Solution.

+ 128 =

1000 0000

130 =

0111 1110

Sum = 2 =

11111110

To check the result convert this negative number obtained by summing, into a positive number. For this find 2’s complement of 1111 1110 which is 0000 0010 which is 2. Thus 1111 1110 is equal to 2 and is the correct answer. When we add two negative numbers in 2’s complements notation an overflow bit will result and this bit or carry generated is ignored. The sign bit represents the correct sign. However, one should be careful that the sum is within the allowed range of the answer. For example, for 4-bit numbers the answer should not exceed 15. In case the sum is beyond the permitted range the sign bit will become zero indicating an error in the answer. The ease with which the addition and subtraction can be performed in 2’s complement notation has made this representation most common for most of the digital system.

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NUMBER SYSTEMS AND LOGIC GATES

Example. Add 15 and 20 by using 2’s complement. Solution.

15 =

1111 0001

20 =

1110 1100

35 =

1 1101 1101 ignoring carry

=

1101 1101

To check the result find the 2’s complement of this negative result which is 00100011 which is 35. Hence the result 1101 1101 (= 35) is correct answer.

A digital circuit with one or more input signals but only one output signal is called a logic gate. Since a logic gate is a switching circuit (i.e., a switching circuit) its output can have only one of the two possible states i.e., either a high voltage (1) or a low voltage (0), or in other words we can say that it is either ON or OFF. Whether the output voltage of a logic gate is high (1) or low (0) will depend upon the conditions at its input. Fig. 9.6 shows the basic ideal of logic gates using switches. S1

V

S2

+

Bulb

–

S1

S2

Bulb

open

open

OFF

open

closed

OFF

closed

open

OFF

closed closed (a)

ON

(b) Truth table S1

S2

Output

0

0

0

0

1

0

1

0

0

1

1

1

(c) Fig. 9.6. Basic idea of logic gates.

Thus, from Fig. 9.6 it is clear that :

When S1 and S2 are open, the bulb is OFF.

When S1 is open and S2 is closed, the bulb is OFF.

When S2 is open and S1 is closed, the bulb is OFF.

When both S1 and S2 are closed, the bulb is ON.

Finally we conclude that the output (OFF or ON) depends upon the conditions at the input. In usual practice to show the conditions at the input and output of a logic gate in the binary form as shown in the table, such a table is called truth table.

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The term “logic” is usually used to refer to a decision-making process. A logic gate makes logical decision regarding the existence of output depending upon the nature of the input. Hence, such circuits are called logic circuits.

As we have discussed earlier that a logic gate is a circuit that has one or more input signals but only one output signal. All logic gates can be analysed by constructing a truth table. A truth table list all input possibilities and the corresponding output for each input. The three basic logic gates that make up all digital circuits are namely : (i) OR-gate (ii) AND-gate (iii) NOT-gate. NOTE :

Generally a binary 0 represent 0 V and binary 1 represents + 5 V. It is common to refer to binary 0 as LOW input or output and binary 1 as HIGH input or output. The operation of logic gate may be described either by truth table or Boolean Algebra.

An inverter or NOT gate has only a single input and always a single output signal. Output logic is the complement of the input logic i.e., output is NOT same as input, due to which it is called NOT gate. + 5 V (VCC)

C Vi

VO

B

Vi

VO

E

(a) Inverter circuit

(b) Logic symbol of inverter or NOT gate

Fig. 9.7.

The circuit in Fig. 9.7(a) shows a CE amplifier, which switches between cut off and saturation. When Vi is low (say OV), then transistor gets cut off and is unable to conduct, thus full voltage of VCC i.e., + 5 V is available at the output terminal. Thus when V1 is low, V0 is high. Whereas when V1 is high (say + 5 V), it will saturate the transistor, giving a low V0. Fig. 9.7(b) shows the logic symbol of inverter NOT gate. Table 9.8 V1

V0

0

1

1

0

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An OR gate has two or more inputs and only one output, which is equal to the OR sum of all inputs. Fig. 9.8(a) shows the circuit of a two input OR gate and Fig. 9.8(b) shows its standard symbol. The circuit consists of two inputs A, B and two diodes A

D1

A

Y B

Y

R

B

D2

(a)

(b)

Fig. 9.8.

D1 and D2 and a resistance R. In digital circuits ‘0’ is assigned to voltages from 0 to 0.75 V, and it is assigned to voltages in the range + 2 V to + 5 V, whereas voltages between 0.75 V to 2 V are not defined and in normal condition should be avoided. The diode has a property of conducting if positive voltage is applied and it does not conduct if a negative or nearly 0 V is applied to it. If both the inputs are low (0), then diode D1 and D2 do not conduct, giving low (0) output at Y. If any input A or B is high, the diode with that high input conducts, giving high (1) output. If both the inputs are high, both diodes conduct, giving high (1) output. Thus we see that one OR move high inputs give high output, and that is the reason the name OR gate is given to it. Table 9.9 shows the truth table of OR gate. Table 9.9 A

B

Y = A + B

0

0

0

0

1

1

1

0

1

1

1

1

An AND gate has two or more inputs and only one output which is equal to AND product of all inputs. Fig. 9.9(a) shows the circuit and Fig. 9.9(b) shows the standard symbol of a two input AND gate. A

D1

+ 5V R

A Y

B

Y B

D2

(a)

(b)

Fig. 9.9.

The circuit consists of two diodes D1 and D2 and a resistance R, connected as shown. If both inputs A and B are low, then anodes of D1 and D2 are connected to

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+ 5 V. As such both diodes D1 and D2 are forward biased and conduct pulling down the output to low value. If one of the inputs is low, the other being high, the diode with low input conducts and pulls down the output to low value. The diode with the high input being reversed biased, gets cut-off. If both inputs are high, both diodes being reverse biased get cut-off and supply voltage, high, appears at output. Thus we see that inputs A AND B high give a high output and that is why the name AND gate is given to it. Table 9.10 shows the truth table of a two input AND gate. The last entries in the table show that inputs A and B both must be 1 to get 1 output. Table 9.10 A

B

Y = A . B

0

0

0

0

1

0

1

0

0

1

1

1

The OR, AND and NOT gates are the three basic gates are called fundamental or basic gates. Now, we shall discuss a few combinations of these basic gates.

NOR gate actually means NOT-OR. It has two or more inputs, but only one output which is the complement (Inverter or NOT) of the OR sum of the two or more inputs. Fig. 9.10(a) shows standard symbol of NOR gate and Fig. 9.10(b) shows its equivalent circuit standard symbol of NOR gate is the same as OR gate symbol followed by a small circle or bubble on the output side; the bubble actually represents the inversion A

A Y=A+B

Y= A+B B

B

(a)

(b)

Fig. 9.10.

operation. First the OR operation is done, which is then followed by inversion (NOT gate) as explained in Fig. 9.7(b). The truth table of NOR gate is shown in Table 9.11, which can be easily obtained from truth table of OR gate and then simply inverting or negating it to obtain the final output of the NOR gate. Thus we see that the final output Y of the NOR gate is high only if both the inputs are low. If any of the inputs is high or if both inputs are high, then output of NOR gate is low. Table 9.11 A

B

Y = A + B (OR)

Y = A + B (NOR)

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

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NUMBER SYSTEMS AND LOGIC GATES

NOR Gate as a Universal Gate The NOR gate is called an universal gate as all functions, OR, AND and NOT can be realised from it. Fig. 9.11 shows the realisation of NOT, OR and AND gates by using NOR gate. A OY

NOT :

OR :

A

A + A = A A =Y

A+B

Y=A+B=A+B

B

A

A+A=A A

AND :

A + B = A . B = AB B B+B=B B

Fig. 9.11. Realisation of NOT, OR and AND gates using NOR gate.

NAND gate actually means NOT-AND. It has two or more inputs, but only one output which is complement (Inverter or NOT) of the AND product of all inputs. Fig. 9.12(a) shows standard symbol of NAND gate and Fig. 9.12(b) shows its equivalent A

A Y=A.B

B

Y=A.B B

(a)

(b)

Fig. 9.12.

circuit or logical meaning. Standard symbol of NAND gate is the same as AND gate symbol followed by a small circle or bubble on the output side, the bubble actually represents the inversion operation. First the AND operation is done, which is then followed by inversion (NOT gate) as explained in Fig. 9.7(b). The truth table of NAND gate is shown in Table 9.11, which can be easily obtained from truth table of AND gate and then simply inverting or negating it to obtain the final output of the NAND gate. Thus we see that the final output Y of the NAND gate is high if any of the inputs is low or all inputs are low. If all inputs are high, then only the output of NAND gate is low.

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Table 9.12 A

B

Y = A . B (AND)

Y = A . B (NAND)

0 0 1 1

0 1 0 1

0 0 0 1

1 1 1 0

NAND Gate as a Universal Gate The NAND gate can also be work as a universal gate as all functions, OR, AND and NOT can be realised by using NAND gate. Fig. 9.13 shows the realisation of NOT, AND and OR gate by using NAND gate. A

NOT :

AND :

Y=A.A= A=A

A

A.B Y=A.B= A.B

B

A

A

OR :

Y=A.B= A+B =A+ B B

B

Fig. 9.13. Realisation by using NAND gate only.

Exclusive OR gate is abbreviated as XOR gate. Fig. 9.14(a) shows the logic diagram and Fig. 9.14(b) shows its standard symbol. AND gate A

OR gate

1 AB

Y = AB + BA

BA 2

B

AND gate

(a) A

Y

B

(b)

Fig. 9.14.

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NUMBER SYSTEMS AND LOGIC GATES —

—

Two inverters (i.e., NOT gate) give outputs of A and B . Then two AND gates are — — used. The AND gate 1 gives the product A B and AND gate 2 gives the product B A as — — shown in Fig. 9.14(a). Finally A B and B A are given as input to an OR gate and the resulting output is : Y = AB + BA The operator symbol for XOR gate is Thus

Y = A XOR B

or

Y=A B

Truth table of XOR gate is shown below in Table 9.13. Table 9.13 A

B

Y = A B

0

0

0

0

1

1

1

0

1

1

1

0

From the Table 9.12 it is clear that the output from the exclusive OR (XOR) gate will be high only when the input are different to each other, or in other words if one input is high then for the output to be high other input must be LOW. That is why it is called exclusive OR gate.

Exclusive NOR is abbreviated as XNOR gate. Fig. 9.15(a) shows the logic diagram of XNOR gate and Fig. 9.15(b) shows its standard symbol. The logical symbol of exclusive NOR gate is XOR gate followed by NOT gate. A

Y= A

B

B

(a)

A

Y= A

B

B

(b)

Fig. 9.15.

Due to the NOT gate (i.e., inverter) on the output side in Fig. 9.15(a), the truth table of XNOR gate is the complement of truth table of XOR gate. The output of XNOR gate is high only when all the inputs are same i.e., either all inputs are low or all the inputs are high. Table 9.14 shows the truth table of the XNOR gate.

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Table 9.14 B = A . B + AB

A

B

Y = A

0

0

1

0

1

0

1

0

0

1

1

1

Output of XNOR gate can be easily obtained by applying De-Morgan’s theorem : Y= A B or

Y = AB + BA

or

Y = AB . BA

or

Y= A + B

or

Y= A + B

or

Y = A B B B A A AB

or or

Y = A B + AB Y=A B

e

j eB + A j

e

j dB + A i |UV |W

RS B B T AA

= 0 = 0

UV W

Fig. 9.16 shows the realisation of NOR, XOR and XNOR gates using NAND gate only. A

A AB

NOR : B

Y = AB = A + B

B

A

A A.B

XOR :

Y = AB + AB = A B B

B

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NUMBER SYSTEMS AND LOGIC GATES A

A

XNOR :

A.B Y=A B

B

B

Fig. 9.16. Realisation of NOR, XOR and XNOR gate using NAND gate only.

As we know that digital circuits perform the binary arithmetic operations with binary digits 1 and 0. These operation are called logic functions or logical operations. The algebra used to symbolically describe logic functions is called Boolean Algebra. There are four connecting symbols used in Boolean Algebra are given below : (i) equal sign (=) (ii) multiply sign (.) (iii) plus sign (+) (iv) bar sign ()

The theorems that are useful in manipulating and simplifying Boolean expressions. For better understanding, we divide the boolean theorems into the following two groups : (i) Single variable theorems (ii) Multivariable theorem. (i) Single variable theorem. Single variable theorems refer to the condition when only one input to the logic gate is variable. Theorem 1 :

A + 0 = A

Theorem 2 :

A . 1 = A

Theorem 3 :

A + A = 1

Theorem 4 :

A + A = A

Theorem 5 :

A . A = A

Theorem 6 :

A + 1 = 1

Theorem 7 :

A . 0 = 0

Theorem 8 :

A = A.

Duality Principle Before describing to the multivariable theorems, this would be the right place to mention an important property of Boolean algebra called duality principle. It is stated below : Statement. A Boolean expression remains valid if operators OR and AND are interchanged and 1’s and 0’s in the expression are also interchanged.

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In order to understand this duality principle, consider the Boolean theorem 1 : A + 0=A According to the duality principle, this Boolean expression remains valid if OR function is replaced by AND function and 0 by 1. In that case the boolean expression becomes : A.1 = A From theorems mentioned above we see that this is a Boolean theorem no. 2. Therefore boolean theorem 2 is a dual of the boolean theorem 1 and vice-versa. Applying duality principle, theorem 4 is dual of theorem 3 and vice-versa, theorem 6 is dual of theorem 5 and vice-versa. To apply duality principle to a Boolean expression, we simply interchange OR and AND operator and replace 1’s by 0’s and 0’s by 1’s. (ii) Multivariable theorems. These theorem refers to the condition when more than one input to the logic gate are variable. The theorems given below are also known as Boolean postulates. Theorem 9 : Associative laws (A + B) + C = A + (B + C); (AB)C = A(BC) Theorem 10 : Commutative laws A + B = B + A; AB = BA Theorem 11 : Distributive laws A(B + C) = AB + AC; A + (B . C) = (A + B) . (A + C); A + ( A . B)= (A + A ) . (A + B) = A + B Theorem 12 : De-Morgan’s laws. De-Morgan’s theorems are extremely useful in simplifying expressions in which a product or sum of variables is inverted. The two theorems are : (i) ABC.... = A + B + C + ..... (ii) A + B + C.... = A B C ..... Theorem 13 : Absorption laws A + AB = A, A + AB = A + B (negative absorption law), AB + A B = A A. (A + B) = A, (A + B) (A + B ) = A

Some More Important Theorems (i) Redundancy Theorem The absorption laws are also known as Redundancy theorem. Statement. In a Boolean expression in SOP form, if the same factor is present in more than one term, the other terms are redundant. Example. A + AB = A as the factor A is present in the 2nd term also.

Comp-1/Laxmi-5/Computer/Revision/Elec-9b—10.5.07

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NUMBER SYSTEMS AND LOGIC GATES

AB + ABC + A B = AB + A B = A. The same factor AB is present in 1st and 2nd terms and so AB. AD + A B D + ACD = AD as the factor AD is present in all the 3 terms. (ii) Consensus Theorem Statement. If in a Boolean expression, one term contains a variable and the second its complement a third term can be formed with the remaining two variables with the value of the expression remaining the same. Example. f = AC + B C ; C and its complement C is present in the two terms. A third term AB can be formed and the value of the Boolean expression remains the same. SOP

f = AC + B C + AB = AC + B C + AB (C + C ) = AC + B C + ABC + AB C = AC (B + 1) + B C (A + 1) = AC + B C

POS NOTE :

(A + B) ( A + C) = (A + B) ( A + C) (B + C) Consensus theorem is sometimes useful in simplifying the original equation.

Logic circuit is defined as a circuit constructed from various inputs by means of OR gate, AND gate, inverters and possibly other devices for performing truth functional operation. A logic statement is a sentence which can be classified as true or false but not both. The truth value of the logic statement the Sun rises in the east is Truth, and the truth value of statement the Sun rises in the west is False. In Boolean algebra 0 + 0 = 0, 0 + 1 = 1, 1 + 1 = 1 and 0 . 0 = 0, 0 . 1 = 0, 1 . 1 = 1.

OR

AND

NOT

A + 0 = A

A . 0 = 0

0 = 1, 1 = 0

A + 1 = 1

A . 1 = A

If A = 0, A = 1; if A = 1, A = 0

A + A = A

AA = A

A = A

A + A = 1 A B

AA = 0 A B

To arrive at the final true output it may be necessary to combine different logic functions. The starting point for most logic function is the truth table. The truth table is converted into a Boolean expression and finally the assembly of logic gates accordingly.

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Any Boolean expression representing a switching function can be obtained from the truth table by writing sum of all the terms, which correspond to all those combinations (arrows) for which the function attains high value (i.e., 1). Conversion from Truth Table to Boolean Expression. The following is a truth table for 3 variable inputs, single output Input Output A B C Y 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 As the output can be either 1 or 0 for the 3 inputs, there can be 23 = 8 outputs. A perusal of the truth table shows that the output is true with a logical 1 only in rows, — — — 1, 3, 6. A 1 input is A, B or C and 0 input its complement A , B or C . So the Boolean expression is Y = ABC + A B C + A B C ... (9.1) As we know that AND operation is a product while OR operation is sum. So eqn. 9.1 is a ‘Sum of Products’ (SOP) form is called a minterm expression. The switching function expressed as the sum of all the minterms is called the canonical sum of products (SOP) or disjunctive normal expression. Finally, an AND-OR Logic circuit is drawn for the Boolean expression shown below in Fig. 9.17. A

A B

A.B.C

C

B

A B

A.B.C

C

A B C

A.B.C

C

Fig. 9.17.

Y=ABC+ABC+ABC

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NUMBER SYSTEMS AND LOGIC GATES

Product of Sums Boolean expression. Similar to SOP, we can have a Product of Sums (POS) Boolean expression. This will be an OR-AND circuit. For example, Y = (A + B + C) (A + B + C) (A + B + C) is a Product of Sums Boolean expression. A POS expression is called maxterm form of Boolean expression. Writing a truth table for a maxterm is different from minterm. Before that let us look into the truth table of AND and OR for two variables A, B. AND Input

OR Output

Input

Output

A

B

Y

A

B

Y

0

0

0

0

0

0

0

1

0

0

1

1

1

0

0

1

0

1

1

1

1

1

1

1

By comparing each column, we note the truth table of OR is the inverse of AND. That is one is the dual of the other and so AND can be derived from OR and vice versa. For conversion, 1. Change each OR sign to an AND sign 2. Change each AND sign to an OR sign 3. Complement each 0 and 1 A (B + C) = AB + AC = (A + B) (A + C) So the maxterm form of Boolean expression is developed from the 0’s of the truth table output. The minterms and maxterms of a three variable are given below in Table 9.15. Table 9.15 Row No.

ABC

Minterms

Maxterms

0

0 0 0

A BC = m0

A + B + C = M0

1

0 0 1

A B C = m1

A + B + C = M1

2

0 1 0

A BC = m2

A + B + C = M2

3

0 1 1

ABC = m3

A + B + C = M3

4

1 0 0

A BC = m4

5

1 0 1

A BC = m5

6

1 1 0

ABC = m6

7

1 1 1

ABC = m7

—

—

—

—

—

A + B + C = M4

—

—

A + B + C = M5 —

—

—

—

A + B + C = M6 —

A + B + C = M7

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BASIC ELECTRONICS ENGINEERING & DEVICES

If in a standard form of Boolean expression, the number of minterms is equal to the number of maxterms, the function is called neutral function. Converting from maxterm to minterm and vice versa This can be done by using the two De Morgan’s theorems. The procedure is as follows : 1. Convert all ANDs to ORs and ORs to ANDs. 2. Complement or invert each variable (place a bar). 3. Complement the entire function (put a bar over the entire function). 4. Eliminate groups of double overbars. For example, to SOP to POS Consider a function : Y = ABCD + A BCD Applying steps listed above : Y = (A . B . C . D) + (A . B . C . D) = (A + B + C + D) . (A + B + C + D) —

Conversion to minterms. Every variable say, A, B, C is called a literal. An AND function like A. B. C. D is a product term and an OR function like A + B + C + D is a sum term. We have also seen that if there are 2 variables, the truth table will have 2 2 = 4 rows and 4 outputs. So for n variables there will be 2n possible combinations. Each output can have a 0 or 1 so that there can be 2 2n different output functions. Supposing we have a four variable function, f (A, B, C, D) = A B + AC + B CD + ABC We note that each product term does not contain all the 4 variables. As we have already discussed that a Boolean expression which contains all the variables in each product term is called a standard sum of products form or SOP canonical form or disjunctive normal form. Each term in the standard SOP form is called a minterm. The standard forms are unique and if 2 or more Boolean expressions in standard form are identical, then the two functions are identical. Another feature is that each minterm value is 1. If there is a 3 variable function f (A, B, C) = A B C + ABC + AB C , then each minterm A B C output is 1 (true). i.e., A = 1, B = 1, C = 1 then f = 1 or same as saying A = 1, B = 0, C = 1, f = 1. In order to better understand the concept of canonical sum of products (SOP) form and product of sum (POS) form, see the examples carefully, given as follows :

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NUMBER SYSTEMS AND LOGIC GATES

Example. (i) Find the canonical Sum of Products (SOP) form for the expression given below : f (A, B, C) = AB + A B + AC + AC . (ii) Also find product of sums expression for the above expression. Solution. (i) f (A, B, C) = AB + A B + AC + A C —

= AB (C + C ) + A B (C + C ) + AC (B + B ) + A C (B + B ) = ABC + AB C + A B C + ABC + AC B + AC B + A C B + A C B —

—

= ABC + AB C + A B C + A BC + ABC + A B C + A BC + A BC Eliminating ABC and ABC once as they are repeated twice, we get f (A, B, C) = ABC + AB C + A B C + ABC + ABC + ABC = 111 + 110 + 001 + 000 + 101 + 010 = (7, 6, 1, 0, 5, 2) = (0, 1, 2, 5, 6, 7) (ii) The product of sums expression will be given by POS form = Complement of (3, 4) = Complement of (011, 100) = (ABC + ABC) = ( ABC + A B C ) = ( ABC . A B C ) = ( A + B + C) (A + B + C ) = (A + B + C) (A + B + C) NOTE :

When any switching expression is to be expressed in canonical POS form, then each term of the expression should be examined and if it is a maxterm, then it should be kept as it is. Thus if any term contains all the variables in either complemented or uncomplemented form, then it should be retained. If any particular variable does not occur in any sum term, then for each variable A, B or C which do not occur, add AA , BB or CC as the case may be. Then convert the sum terms into product of sums and eliminate the repeated terms.

Example. Find the canonical product of sums (POS) form and sum of products (SOP) form of the switching functions given below : f (A, B, C) = ( A ) . ( B + C ) Solution. f (A, B, C) = (A) . (B + C)

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In the first factor (A) , the variable B and C are absent and in the second factor (B + C) , the variable A is absent. Therefore adding BB and CC to the first factor and

adding AA to the second factor, we get : f (A, B, C) = ( A + BB + CC ) ( B + C + AA ) = [(A + B) (A + B) + CC] . [(B + C + A) (B + C + A)] = [{(A + B)(A + B) + C}{(A + B) (A + B) + C}][(A + B + C)(A + B + C)] = [C + (A + B) . (A + B)] [C + (A + B) . (A + B)] [(A + B + C) (A + B + C)] = (C + A + B) . (C + A + B) . (C + A + B) . (C + A + B) . (A + B + C) . (A + B + C)

= (A + B + C)(A + B + C)(A + B + C)(A + B + C)(A + B + C)(A + B + C) Since the third and last factors are repeated, therefore deleting them once i.e., retaining one of them, we get the Product of Sums form as : = (A + B + C) (A + B + C)(A + B + C)(A + B + C)(A + B + C) = (100) (110) (101) (111) (001) = II (4, 6, 5, 7, 1) or

f (A, B, C) = II (1, 4, 5, 6, 7) is the required POS form. To find the SOP form

of f (A, B, C) we multiply each factor by the absent variables (C + C ) and (B + B ) respectively. Thus f (A, B, C) = A (B + C ) = AB + A C = A B (C + C ) + A C (B + B ) = A BC + A B C + A B C + ABC (delete A B C once as it is repeated twice) = A BC + A B C + ABC = 011 + 010 + 000 = (3, 2, 0) or

f (A, B, C) = (0, 2, 3) is the required SOP form.

Upto now we have studied simplification of logic circuits by applying different Boolean identities (i.e., theorems). In 1953, Maurice Karnaugh devised a graphical technique to simplify Boolean expression. As the simplification of Boolean switching functions by using postulated of Boolean algebra and De Morgan’s theorem has been found to be awkward as it does not follow any specific set of rules, but uses a hit and trial manipulative method as discussed. However, Karnaugh map method, provides a simple set procedure for minimizing the switching function. The Karnaugh map is normally used for representing and minimizing two-variable, three variable or four-variable switching function expression.

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NUMBER SYSTEMS AND LOGIC GATES

For two variables : The starting point, as usual, is the truth table which for a two variables OR-gate is given below : Block number

Inputs

Output

A

B

Y

0

0

0

0

1

0

1

1

2

1

0

1

3

1

1

1

The Karnaugh map called K map is a block of squares, each square representing a row of the truth table. Thus there will be as many squares as there are rows. We know for a 3 variable, there will be 23 = 8 rows corresponding to eight outputs. So there will be 8 squares.

A

1. A block of 4 squares is drawn for the 2 variables. 2. A tail is extended from the left corner to divide the blocks into A and B. A blocks are columnwise from top to bottom and B blocks rowwise across. It can be the other way also. 3. Each square in the block represents the output corresponding to the input variables 0 or 1. 4. We write the minterm expression of

B

(1)

A

B

B=0

(2)

B=1

A

A=0

B

B

B

A

A=1

the truth table in which A = 1, A = 0, B =

0

1

2

3

A

(3)

0

1

2

3

(4)

1, B = 0. A . B + A . B + A . B = Y = 1 5. Corresponding to each row of the truth table we place a 0 or 1 in each square.

AB = 0, A B = 1, A B = 1, AB = 1 Normally 0 is not written and the square is left blank. Sometimes, in one corner of each square a decimal number corresponding to the row number is written which we have seen in m0, m1, m2, m3, e.g., the intersection A = 1 and B B = 0 is equal to binary 1 and decimal 2.

A

B

B=0

B=1

A=1

B

0

1

1

0 A=0

A

1

0 1

1 2

(5)

3

0 0 1

1

1

1

1 2

(6)

3

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6. Until now, the K map is a representation of the truth table. The final step is simplified by forming loops or groups. If two adjacent squares either horizontally or vertically have the same literal or output, they are grouped or looped. Looping is done in groups of 2, 4, 8, etc. A group of 2 yields a single variable. The common to both the A column and B row is A = 1, B = 1 and these are the remaining variables. This is now ORed to get the simplified expression A + B=Y We write the minterm expression of the truth table and draw the K map. The K map can be drawn with reference to the maxterm expression also. For this, the procedure of locating 1’s is reversed. Instead, the 0’s are located on the K map corresponding to the maxterms. For our example, the Boolean expression is A + B = 0 = Y as there is only one 0. NOTE :

To summarise the procedure for simplification of Boolean expressions by K map. 1. Write a minterm Boolean expression from the truth table. 2. Place the 1’s on the appropriate squares of the K map. 3. Circle the isolated 1’s which do not form adjacencies. 4. Loop pairs of adjacencies. 5. Loop any octet. 6. Loop any quad that contains one or more 1’s which have not already been looped. 7. Simplify by dropping terms that contain a variable and its complement within the loop. 8. OR the remaining terms (one term per loop) and write the simplified minterm Boolean expression.

K map for three variables. A 3 variable expression will be 23 = 8 squares. In this, 2 variables will be on one side of the tail and one below. It can be drawn horizontally or vertically.

C AB

C 0

C 1

A B 00

AB

00

01

0

ABC

ABC

ABC

ABC

1

ABC

ABC

ABC

ABC

C

AB

A B 01

10

11

A

A

C

A B 11

or

A B 10

ABC

ABC

ABC

ABC

C

ABC

ABC

ABC

ABC

C

B

Fig. 9.18.

B B

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NUMBER SYSTEMS AND LOGIC GATES

Consider output is given

AB

Y = A B C + A BC + AB C + ABC

C

0

1

00

Karnaugh map for the above output is shown in Fig. 9.19.

01

1

1

11

1

1

We can make either 3 loops in 2’s or one loop of 4. A group of 4 yields a single variable. In this case, it can be either A or B. However, we see that against the loops are A B and AB. When there is a variable and its complement, it is eliminated so that simplified Boolean expression is B = Y = 1.

10

Fig. 9.19

We can cross check by two loop method. In 3 loops, all 1’s are covered. 1. A B C and A BC When there is a variable and its complement, that variable is eliminated. A B. 2. ABC, AB C AB 3. A BC, ABC BC (eliminating A, A ) Y = A B + AB + BC = B (A + A ) + BC = B + BC = B (C + 1) = B. It may also be seen that among the 8 minterms only B is uncomplemented. In a 3 variable map, 1. A group of four adjacent squares yields a single variable; 2. A group of two adjacent squares yields a two variable term; 3. An uncombined single square gives a 3 variable term. K-map four variable map. A four variable Boolean function is f (A, B, C, D). Its K-map will be with 16 squares. C

C

AB

B A

00 B

01

or A

11

B

CD

00

01

11

10

0

1

3

2

4

5

7

6

12

13

15

14

8 0

9

11

10

10 D

D D

Fig. 9.20.

In 4 variable map : 1. 8 adjacent squares yield a single variable; 2. 4 adjacent squares yield a two variable term;

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BASIC ELECTRONICS ENGINEERING & DEVICES

3. 2 adjacent squares yield a three variable term; 4. individual cells yield a four variable term. Five and six variables will have 2 blocks and 4 blocks of 16 squares, each block of 16 squares representing a 0 or 1. From the foregoing, we see that a pair (group of two) reduces to one variable, a quad eliminates 2 variables, an octet eliminates 3 variables and 2 n (a group of n squares) eliminates n variables. If there are 5 variables A, B, C, D, E, we use two 16 cell squares one for E and another for E, one above other. NOTE :

Another point of interest, is that any pair of adjoining minterms can be combined into a single term with one variable less than the minterm themselves. For instance, if we have a four variable A, B, C, D and adjoining minterms are ABCD and ABC D , the reduced minterm is ABC as D is eliminated. So now, there are only 3 variables ABC.

Some unusual looping combinations : 1. Rolling. In this, a 3 and above variable K map may be considered as a cylinder which can be rolled over. AB

C

0

AB

01

11

11 1

10

Fig. 9.21 (a). ——

—

(a) Simplification A B C + A B C —

—

1

1

1

1

10

AB

CD

00

01

11

10

00

Y = A BC + AB C —

11

Fig. 9.21 (b).

From Fig. 9.21, ——

01

00

01

10

00

1 1

00

CD

—

= B C (A + A) = B C From Fig. 9.21 (b) and (c), It is a 4 variable map

01

1

1

11

1

1

(b) Y = A B C D + A B CD + A B C D + A B CD Y = AB D + AB D = B D

10

(c) Y = A B C D + AB C D + A BC D + ABC D Y = B C D + BC D = B D

Fig. 9.21 (c).

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NUMBER SYSTEMS AND LOGIC GATES

NOTE :

To indicate rolling, half circles are drawn.

From Fig. 9.21 (d),

CD 00

The four 1’s may be considered as a single group of 4 thereby eliminating 2 variables. ABC D + AB CD + ABC D + AB CD = Y

or

Y = ABD + ABD

or

Y = B D ( A + A) = B D

Don’t care conditions. When the output for inputs is immaterial whether a 1 or 0, we put an X or d in the K map and call it a don’t care condition. Such functions are incompletely specified functions. Outputs may be specified for only a combination of inputs leaving the rest undecided. For instance, in a four variable input, outputs may be specified for some say upto m10 leaving the rest unspecified either 0 or 1. Such an expression is expressed as : f (A, B, C, D) = Y mi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8 9, 10) + dj (j = 11, 12, 13, 14, 15)

10

1

01 11 10

1

1

Fig. 9.21 (d). AB CD

00

00

1

01

1

11

1

01

1 1

d

1 1

1 9

15

d 11

14

1 10

d 6

8

13 d

7

2

1 12

5

1

10

d 4

3 10

11

1 0

The K map of such a function is shown in the Fig. 9.22. NOTE :

11

1

00

This is a corner location of 1’s in the K map. For simplification, the map may be visualised as wrapped around a sphere.

01

AB

Fig. 9.22.

A d square can combine with either a 1 or 0. For instance, square of decimal 11 with d can be looped with square of decimal 3, m2.

Using maps with maxterm expressions. The rules are : 1. Write the maxterm Boolean expression from the truth table. 2. For each 0 output write a 1 on the map. The number of 0’s in the truth table will equal the number of 1’s on the map. 3. Loop around consecutive 1’s in 2’s, 4’s, 8’s on the map. 4. Eliminate the variable(s) with its complement(s) within the loop. 5. Logically AND the remaining groups to form the simplified maxterm expression.

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+D C B + A

A+B

C

11 00 10 01 (C + D) (C + D) (C + D) (C + D)

C(0)

C(1) 00 (A + B)

00 (A + B) 01 (A + B)

01 (A + B)

11 (A + B)

11 (A + B)

10 (A + B)

10 (A + B)

3 variable maxterm map

4 variable maxterm map Fig. 9.23.

Compare the maxterm map with the minterm map to note that each column and row of minterm map is ORed.

? 1. State Boolean postulates. 2. What are universal gates and why are called so ? Explain. 3. What is boolean algebra ? 4. What is the importance of De Morgan’s theorems in boolean algebra ? 5. Give two differences between decimal and binary number system. 6. What’s are the advantages of hexadecimal number and octal number over binary and decimal number ? 7. What’s are the advantages of 2’s complement ? 8. What are the advantages of Boolean theorems ? 9. What is the importance of NAND and NOR gates ? 10. List the basic logic gates. 11. What is the basic difference between OR and XOR gates ? 12. What’s are the application of Boolean algebra ? 13. Make the truth table of EX-OR and EX-NOR gates ? 14. List three important signed number system. 15. What is the need of complement ? 16. What do you mean by BCD code. 17. What do you mean by non-weighted codes ? 18. Explain, why excess-3 codes are called self-complementary ? 19. What is the difference between canonical form and standard form ? Also write the De Morgan’s theorem ?

361

NUMBER SYSTEMS AND LOGIC GATES 20. What is BCD ? Where it is used ?

21. Why is digital electronics considered important ? State the advantages and disadvantages of using binary numbers.

Example 1. Find the 9’s complement of each of the following numbers : (a) 12

(b) 28

(c) 56

(d) 562

Solution : To get the 9’s complement of a decimal number, we subtract each digit in the number from 9. (a)

99 12 87

(b)

9’s complement of 28.

Ans.

9’s complement of 56.

Ans.

99 56 43

(d)

Ans.

99 28 71

(c)

9’s complement of 12.

999 562 437

9’s complement of 562.

Ans.

Example 2. Convert the following decimal numbers to their 10’s complement form : (a) 52

(b) 428.

Solution : First we will find the 9’s complement, and then add 1 in order to get 10’s complement of the given (a)

99 52 47 + 1 48

(b)

9’s complement of 52. 10’s complement of 52.

999 428 571 + 1

9’s complement of 428.

572

10’s complement of 428.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Example 3. Convert binary numbers 1101101 to decimal. (1101101)2 = 1 × 26 + 1 × 25 + 0 × 24 + 1 × 23 + 1 × 22 + 0 × 21

Solution :

+ 1 × 20 = 64 + 32 + 0 + 8 + 4 + 0 + 1 Ans.

= (109)10

Example 4. Determine the decimal value of number 11101.011. Solution :

(11101.011)2 = (1 × 24 + 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20) . (0 × 21 + 1 × 22 + 1 × 23) = (16 + 8 + 4 + 0 + 1) . (0.25 + 0.125) Ans.

= (29.375)10

Example 5. Determine the decimal value of the fractional binary number 0.1011. (.1011)2 = .(1 × 21 + 0 × 22 + 1 × 23 + 1 × 24)

Solution :

= .(.5 + 0 + .125 + .0625) Ans.

= (.6875)10

Example 6. Convert 101111010110.1101100112 into octal equivalent. Solution : Dividing the number into groups of three 101

111

010

110 .

110

110

011

6

6

3

Express each group in octal 5

7

2

6

.

MSD

LSD

Therefore, 101111010110.1101100112 = 5726.6638. Ans. Example 7. Convert 111011000110101.00111012 into octal. Solution : Divide into groups of three 111

011

000

110

101 . 001

110

100

6

4

Express each group in octal 7

3

0

6

5

.

1

MSD

LSD

Therefore, 111011000110101.00111012 = 73065.1648. Ans.

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NUMBER SYSTEMS AND LOGIC GATES

Example 8. Convert the decimal number (749.25)10 to binary, octal and hexadecimal numbers. Solution : In

( 749 . 25 )10

Integer part

Fraction part

(a) Into Binary Integer

Remainder

Fraction

2

749

1 (LSB)

.25 × 2 = 0/.50

2

374

0

.50 × 2 = 1/.00

2

187

1

(0.25)10 = (.01)2

2

93

1

2

46

0

2

23

1

2

11

1

2

5

1

2

2

0

2

1

1 (MSB)

0 So

749 = (1011101101)2

Therefore,

(749.25)10 = (1011101101.01)2

Ans.

(b) Into Octal 001

011

101

1

3

5

Therefore,

101 . 010 5

2

(749.25)10 = (1355.2)8

Ans.

(c) Into Hexadecimal Additional zeros can be added in MSB if required Therefore,

0010 2

1110 E

1101 D

(749.25)10 = (2ED.4)16

.

0100 4

Additional zeros can be added in LSB if required.

Ans.

Example 9. Prove each of the following using simplification theorems for boolean variables. (i) AB + A B = A

(ii) A + A B = A + B

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BASIC ELECTRONICS ENGINEERING & DEVICES

Solution :

(i)

LHS = AB + A B = A (B + B ) = A Ans.

= RHS. (ii)

LHS = A + A B = (A + A ) (A + B) = 1. (A + B) = A + B = RHS. Ans.

= RHS.

R| S| T

Distributive law as A + A = 1 as 1 . A = A

Example 10. Convert 132658 into binary. Solution : Octal number 1

3

2

6

5

Binary equivalent of each octal digit 001

011

010

110

101

Therefore, 132658 = 10110101101012. Ans. Example 11. Convert 76438 to binary. Solution : Octal number 7

6

4

3

Binary equivalent of each octal digit 111

110

100

011

Therefore, 76438 = 1111101000112. Ans. Example 12. Convert the hexadecimal number (ICD . 2A)16 to Binary and Decimal numbers. Solution : Into binary :

Therefore, Into decimal :

Hexa bit

Binary string

1

0001

C

1100

D

1101

2

0010

A

1010

(1CD.2A)16 = (0001 1100 1101.0010 1010)2

Ans.

(1CD.2A)16 = 1 × 162 + C × 161 + D × 160 + 2 × 161 + A × 162 = 1 × 256 + 12 × 16 + 13 × 1 + 2 × = (461.1640625)10.

Ans.

1 1 + 10 × 16 256

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NUMBER SYSTEMS AND LOGIC GATES

Example 13. Add and subtract without converting the following two number (7571)8 and (4176)8 into decimal. Solution : Addition :

carry from previous addition

0 1 0 7571 + 4176 13767

(13767)8

Ans.

(borrow) Subtraction : 7 5 7 1 4 1 7 6 3 3 7 3

(3373)8

Ans.

Example 14. Prove the identities, using Boolean algebra. (a) A . B + C . D = (A + C) (A + D) (B + C) (B + D). (b) (A + B C + C) C = AB C + A BC + A B C . (c) A ( A + C) ( A B + C ) = 0 Solution : (a)

AB + CD = (A + C) (A + D) (B + C) (B + D) L.H.S. = AB + CD = (AB) + C . D = (AB + C) . (AB + D) = (C + A . B) . (D + A . B) = (C + A) . (C + B) . (D + A) . (D + B) = (A + C) (A + D) (B + C) (B + D) = R.H.S.

(b) (A + B C + C) C = AB C + A BC + A B C L.H.S. = (A + B C + C) C = AC + BC C + CC = AC + BC + 0 = A (B + B ) . C + (A + A ) B C = AB C + A B C + AB C + A B C = AB C + AB C + A B C + A B C = AB C + A B C + A B C = R.H.S. (c) A ( A + C) ( A B + C ) = 0 L.H.S. = A ( A + C) . ( A B + C ) = (A A + AC) . ( A B + C ) = 0 + AC . ( A B + C ) = AC A B + AC C

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BASIC ELECTRONICS ENGINEERING & DEVICES

= A A BC + A . C C = 0 . BC + A . 0 = 0 + 0 = 0 = R.H.S. Example 15. Simplify the following Boolean expression A = XY + XYZ + X Y + X Y Z Solution :

A = XY + XYZ + X Y + X Y Z = (XY + X Y) + XYZ + X Y Z = Y + XYZ + X Y Z (As XY + X Y = Y) = Y (1 + XZ) + X Y Z = Y + XYZ — ( A + A B = A + B, here, B = XZ, A = Y) = Y + XZ. Ans.

Example 16. Solve the following Boolean expression

XY + XYZ X (Y X .Y ) Solution : XY + XYZ X (Y X. Y) = X (Y + YZ) X (Y XY) = X (Y + Z) X (Y X) = XY + XZ XX XY = XY + XZ X = (X + Y) (X + Z) + X = XX + XZ + XY + Y . Z + X = X (1 + Z + Y) + YZ + X = X + XZ + XY + YZ + X = X + YZ + X = ( X . X) ( YZ ) = 0

Ans.

Example 17. Convert 562.310 into octal. Solution : Consider the integer part 56210 and using successive division. 8

562

Remainders

8

70

2 LSB

8

8

6

8

1

0

0

1 MSB

Hence 56210 is equivalent to 10628. Now consider fractional part 0.310 and performing repeated multiplication as explained above and terminating product at 4th place we have

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NUMBER SYSTEMS AND LOGIC GATES

Base

Fractional number

Product

Fractional part of the product

Overflow or carry

8

×

0.3

2.4

0.4

2 MSB

8

×

0.4

3.2

0.2

3

8

×

0.2

1.6

0.6

1

8

×

0.6

4.8

0.8

4 LSB

0.310 = 0.23148 (upto 4th place only) Hence the equivalent of 562.310 in octal is 1062.23148. Ans. Example 18. Add and subtract following two numbers without converting to decimal numbers (4F3A)16 and (23C1)16. Solution : Addition : 1

carry

4 F 3 A + 2 3 C 1 7 2 F B

Ans.

Subtraction : 4 F 3 A 2 3 C 1 2 B 7 9

Ans.

Example 19. State and prove De Morgan’s theorem. Solution : Try yourself. Example 20. Simplify the following expressions : (a) X + X . Y + X . Z

(b) ( X + Y ) . XYZ

Solution : (a) X + X . Y + X . Z = X + X . (Y + Z) = X + (Y + Z) = X + Y + Z. (b)

Ans.

(X + Y) . X . Y . Z = X . X . YZ + Y . X . Y . Z = 0 + 0 = 0. Ans. —

—

Example 21. Obtain the complement of (1 + X ) (Y + Z ) . 1. Solution : For obtaining the complement, change all ‘+’ into ‘.’ and complement 0 and 1 or each literal. The complement of the given expression is i.e.,

b1 X g bY Z g.1 = 1 X Y Z 1 = 1.X X .Z 0 = 0 Y Z 0 = Y Z .

Ans.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Example 22. Simplify the following logic expressions ( X + Y + Z ) ( X + Y + U + V) (Z + U) Solution : ( X + Y + Z ) ( X + Y + U + V) (Z + U) = ( X + Y + Z ) (Z + U) ( X + Y + U + V) (X + Y) ( X + Z ) = (X + Y) ( X + Z) ( Y + Z) Consider the following term and using above theorem, we have ( X + Y + Z ) (Z + U) = (Z + U) ( Z + X + Y) = (Z + U) ( Z + X + Y) (U + X + Y) Hence we have for the expression ( X + Y + Z ) (Z + U) ( X + Y + U + V) = (Z + U) ( Z + X + Y) (U + X + Y) ( X + Y + U + V) ( X + Y + Z ) ( X + Y + U) ( X + Y + U + V) (Z + U) Now using absorption law, we have for the term = ( X + Y + Z) (Z + U) = ( X + Y) Z + ZU.

Ans.

Example 23. What are the Boolean postulates ? State them. Solution : Try yourself. Example 24. Add and subtract the following two numbers without converting to decimal numbers. (432)5 and (013)5. Solution :

Addition : 1 1

Subtraction : carry

4 3 2

4 3 2

+ 0 1 3

0 1 3

1 0 0 0

4 1 4

Therefore (432)5 + (013)5 = (1000)4

Ans.

borrow

Therefore (432)5 (013)5 = (414)5 Ans.

Example 25. Prove the following identities using Boolean algebra and De Morgan’s theorems : (a) AB BC CA = AB BC AC (b) AB + A + AB 0 (c) AB + AC + ABC ( AB + C ) = 1 Solution : (a) AB BC CA = A B B C A C L.H.S. = AB BC CA = AB + (BC + CA) = AB . (BC + CA)

(Applying De Morgan’s first theorem)

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NUMBER SYSTEMS AND LOGIC GATES

= A . B . {C (B + A )} = (A + B) . {C + (B + A )}

(Applying De Morgan’s second theorem)

= (A + B) . (C + B . A) = AC + ABA + BC + BBA = AC + AA B + BC + BBA = AC + AB + BC + BA

= AC + AB + BC + AB

= A C + (A B + A B) + B C = A C + A B + B C = A B + B C + A C = R.H.S. (b) AB + A + AB 0 L.H.S. = AB + A + AB = A + B + A + AB = (A + A) + B + AB = (A + B) + AB = AB + AB = 1 = 0 = R.H.S. (c) AB + AC + ABC ( AB + C ) = 1 L.H.S. = AB + AC + A B CAB + A B CC = AB + ( A + C ) + AAB B C + A B C = AB + A + C + 0 + A B C = AB + A B C + A + C = A (B + B C) + A + C = A {B (1 + C) + B C} + A + C = A (B + BC + B C) + AC = A {B + C (B + B )} + AC = A (B + C . 1) + AC = AB + AC + AC = AB + (AC + AC ) = AB + 1 = 1 = R.H.S. Example 26. Convert the following numbers as indicated. (i) (62.7)8 = ( (iii) (0.342)6 = (

)16

(ii) (10.10001)2 = (

)10

Solution : (i) (62.7)8 first converting into binary (6)8 (110)2 (2)8 (010)2 (7)8 (111)2 So,

(62.7)8 = (110010.111)2

To convert binary number into hexadecimal. additional zeros

So,

0011

0010

3

2

. 1110

(62.7)8 = (32.E)16.

E Ans.

)8

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BASIC ELECTRONICS ENGINEERING & DEVICES

(ii) (10.10001)2 to convert it into octal, combination of three bits from decimal point is replaced by its octal equivalent.

So,

010

100

010

2

4

2 Ans.

(10.10001)2 = (2.42)8

(iii)

61

(0.342)6 = 3 ×

+ 4 × 62 + 2 × 63 Ans.

= (.62)10 Example 27. Solve the following : (a) X

Y

Y

Z

Z

Z

(b) X + X + Y + Y + Y (c) X

X

Y

+ X

(d) X

X

Y

Y + X

Solution : (a) X

Y

Y + Y

Y

Y Y

Z Z

(b) X + X + Y + Y + Y

X

Y

X

Z Z

Z

= X

(Y

Y)

= X

Y

Z

Z

(Z

Z = X

Z) Y

Z

= (X + X) + Y + (Y + Y) = X + Y + Y = X + (Y + Y) = X + Y

(c) X

X

Y + X

Y

—

Y + Y

Y

= (X = X (d) X

X

Y

Y + X

Y

Z

X X)

X Y + X

Y + X

(Y

Y) + (Y

Y + 0 = X

—

Y)

(X

Y

Z

= X

X

Y

= X

Y + X

= Y

(X + X

Y + X Y

Y

Z

Z

Z

Z) = Y (X + Z)

Example 28. Prove the following identity using Boolean algebra. AB C + A BC + AB = A C + AB

Solution :

L.H.S. = A BC + ABC + AB = AC (B + B) + AB = AC + AB = R.H.S.

Example 29. Prove the following identities using Boolean algebra. (i) ABC + ABC + ABC + ABC = C (ii) AB + ABC + AB + ABC = B + AC

X)

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NUMBER SYSTEMS AND LOGIC GATES

Solution : (i)

L.H.S. = A B C + ABC + AB C + ABC = A B C + AB C + ABC + ABC = (A + A) BC + (A + A) BC = BC + BC = C (B + B) = C . 1 = C = R.H.S.

(ii)

L.H.S. = AB + ABC + AB + ABC = AB + ABC + A B + A B C + ABC = AB (1 + C) + A B + AC ( B + B) —

= AB + A B + AC = B (A + A ) + AC = B 1 + AC = B + AC = R.H.S. Example 30. Prove the following using Boolean algebra ABC + ABC + ABC + ABC + ABC + ABC = A + BC

Solution : ABC + ABC + ABC + AB C + AB C + A B C = A + BC L.H.S. = ABC + AB C + ABC + AB C + ABC + A B C = AB (C + C) + AB (C + C) + BC (A + A) —

—

( C + C = 1, A + A = 1) = AB + AB + BC = A (B + B) + BC = A + BC = R.H.S. Example 31. Prove the following Boolean identity, ABC + A BC + ABC + ABC + A B C A B + B ( A C )

Solution : ABC + A BC + ABC + ABC + A B C A B + B (A C) L.H.S. = ABC + A B C + ABC + A B C + ABC = ABC + ABC + A BC + A BC + AB C + A B C = ABC + ABC + ABC + A B C + A B C + A B C = BC (A + A) + AB (C + C) + A B (C + C) = BC + AB + A B = A B + AB + BC = A B + B (A + C) = R.H.S. Example 32. Simplify the following Boolean expressions. (a) AB + ABC ( B C C ) AC (b) ABC ABC AB C ABC

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BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : (a) AB + ABC (B C C) AC = AB + AB B C C + A BCC + AC = AB + 0 + ABC + A + C = C + AB + A + A . BC = C + AB + (A + A) . (A + BC) = C + AB + 1 . (A + BC) = A + A. B + C + B. C = (A + A) . (A + B) + (C + B) . (C + C) = 1 . (A + B) + (C + B) . 1 = A + B + C + B = (B + B) + A + C = 1 + AC = 1

Ans.

(b) ABC ABC AB C ABC = ABC + ABC + ABC + AB C + ABC = AB (C + C) + ABC + ABC + AB C = AB . 1 + BC (A + A) + AB C = A . B + BC . 1 + AB C = A . B + BC + AB C = B . (A + C) + AB C

Ans.

Example 33. Reduce the following Boolean expressions ABCD + ABCD + ABCD + ABCD .

Solution : ABCD + ABCD + ABCD + ABCD = BC (AD + AD + AD + A D) = BC {A (D + D) + A (D + D)} = BC (A . 1 + A . 1) = BC (A + A) = BC

1 = BC.

Ans.

Example 34. Implement the following Boolean expression using NAND gates only Y = A + B C + AC. Solution : Here

Y = A + B C + AC

Y = A BC AC = A + B C + AC = A + B C + AC

—

Y = Y = A + BC + AC

(using De Morgan’s theorem)

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NUMBER SYSTEMS AND LOGIC GATES

Thus it can be easily realised using NAND gates as shown below in Fig. P (9.1). A

B

C A

B

BC

Y

AC

Fig. P (9.1).

Example 35. Simplify the following Boolean expressions, (a) ABC D + ABC D + ABCD + ABCD (b) AB ABC ABC ABC (c) AB ( ABC AB C ABC ) . Solution : (a) ABC D + ABCD + ABCD + ABCD = ABC (D + D) + ABC (D + D) = ABC . 1 + ABC . 1 = ABC + ABC = AB (C + C) = AB . 1 = AB Ans. (b) AB AB C ABC ABC = AB + ABC + ABC + ABC + ABC = AB + ABC + ABC + ABC + ABC = AB + AB (C + C) + BC (A + A) = AB + AB

1 + BC

1

= AB + AB + BC = AB + BC = B

(A + C).

Ans.

(c) AB (ABC AB C ABC) = ABABC + ABAB C + ABABC = AA . BC + AB . BC + AA . BC = 0 . BC + A . 0 . C + 0 . BC = 0 + 0 + 0 = 0

Ans.

374

BASIC ELECTRONICS ENGINEERING & DEVICES

Example 36. Show that using Boolean algebra and De Morgan’s theorems : Y Z + W X Z + W XYZ + WYZ = Z .

Solution :

L.H.S. = Y Z + W X Z + WXYZ + WYZ = Y Z + W X Z (1 + Y) + WXYZ + WYZ = Y Z + W X Z + W XYZ + WXYZ + WYZ = Y Z + W X Z + WYZ (X + X) + WYZ = Y Z + W X Z + WYZ + WYZ = Y Z + W X Z + YZ (W + W) = Y Z + W X Z + YZ = (Y + Y) Z + W X Z = Z + W X Z = Z (1 + W X) = Z (1) = Z = R.H.S.

Example 37. Prove the Boolean identity. A. B + A . B + B. C = A. B +A B + A C.

Solution :

L.H.S. = A B + AB + BC = AB (C + C) + A B (C + C) + (A + A) BC = ABC + ABC + A BC + A B C + ABC + ABC = ABC + ABC + A BC + A B C + ABC (Since ABC is repeated, so writing it only once) R.H.S. = AB + A B + AC = AB (C + C) + A B (C + C) + A (B + B) C = ABC + ABC + A B C + A B C + ABC + A BC = ABC + ABC + A BC + A B C + ABC (Since A B C is repeated, so writing it only once)

Thus we see that L.H.S. = R.H.S. Example 38. Why is a two input NAND gate called universal gate. Solution : Try yourself. Example 39. Convert the following number as indicated (i) (1BE)16 = (

)8

(ii) (676)8 = (

)2

(iii) (321)4 = (

)10.

375

NUMBER SYSTEMS AND LOGIC GATES

Solution : (i) (1BE)16 To convert the hexadecimal number into octal first convert it into binary. (1)16 (0001)2 (B)16 (1011)2 (E)16 (1110)2 So,

(1BE)16 = (0001 1011 1110)2

Now this binary number is converted into octal by converting 3 bit binary string into its octal equivalent.

So,

000

110

111

110

0

6

7

6

(000 110 111 110)2 = (0676)8

Thus

Ans.

(1BE)16 = (676)8

(ii) (676)8 (6)8 (110)2 (7)8 (111)2 So,

(676)8 = (110 111 110)2

(iii)

(321)4 = (3 ×

42

+ 2 ×

41

= (48 + 8 + 1)10 = (57)10

Ans.

Example 40. State Boolean postulates. Solution : Try yourself. Example 41. Solve without changing the base. (i) (734)8 + (444)8 (ii) (432)5 (124)5 (iii) (A1D)16 + (99F)16. Solution : (i) (734)8 + (444)8 1 1 1

carry

734 + 444 1400 Therefore,

(734)8 + (444)8 = (1400)8

Ans.

Ans. + 1 × 40)10

376

BASIC ELECTRONICS ENGINEERING & DEVICES

(ii) (432)5 (124)5 borrow 4 3 2 1 2 4 3 0 3 (432)5 (124)5 = (303)5

Therefore,

Ans.

(iii) (A1D)16 + (99F)16 1

1 1

carry

A 1 D + 9 9 F 1 3 B C Therefore, (A1D)16 + (99F)16 = (13BC)16

Ans.

Example 42. Construct AND gate, NAND gate and OR gate with the help of NOR gate. Solution : Try yourself. Example 43. Obtain the following conversion : (i) (397.75)10 to hexadecimal (ii) (101010.10)4 to octal. (iii) (23.AB)16 to binary. Solution : (i)

(397 . 75)10 Integer part

Hexadecimal 16

397

16

24

16

1

Fraction part

Remainder 13 or D (LSB) 8 1 (MSB)

0 (397)10 = (18D)16 .75 × 16 12 .00 or C

(.75)10 = (.C)16 Therefore,

(397.75)10 = (18D.C)16

Ans.

377

NUMBER SYSTEMS AND LOGIC GATES

(ii) (101010.10)4 In order to convert the number (101010.10)4 into octal, first converted into binary by replacing its each digit by 2 bit binary equivalent i.e., 0 by 00 and 1 by 01 So,

(101010.10)4 = (0100011000100.0100)2

Now this binary number is converted into octal by making combination of 3 bits from decimal point towards left and towards right and replacing each combination by its octal equivalent

So,

010

001

000

100

.

100

2

1

0

4

.

2

(101010.10)4 = (2104.2)8

0 left

Ans.

(iii) (23.AB)16 to binary. Hexadecimal number is first converted into binary by replacing each hexa digit by its 4 bit Binary equivalent. (2)16 0010 (3)16 0011 (A)16 1010 (B)16 1011 So,

(23.AB)16 = (0010 0011.10101011)2

Ans.

Example 44. Write the sum of (23.53)10 and (23.53)8 in decimal. (U.P. Tech. 2002-2003) Solution : First we convert (23.53)8 into decimal (23.53)8 = (2 × 81 + 3 × 80 + 5 × 81 + 3 × 82)10 = (19.671875)10 Now,

(23.53)10 + (23.53)8 = (23.53)10 + (19.671875)10 = (43.201875)10.

Ans.

Example 45. Simplify the following logic expression and realize it using NAND gates. F AB ABC ABCD ABCD

Solution :

F = AB + ABC + ABCD + ABCD = AB + ABC + ABC (D + D) = AB + ABC + ABC = AB + AB (C + C) = AB + AB = A (B + B) = A

378

BASIC ELECTRONICS ENGINEERING & DEVICES A

A Y=A=A

Fig. P (9.2).

Example 46. Simplify the following Boolean equation and realize the same using a combination of AND, OR, NOR gates Y (A B ) ( A C ) (B C )

Solution :

Y = (A + B) (A + C) (B + C) = (A C + AB + BC) (B + C), since AA = 0 = A B C + A C + ABC + BC, since further C C = C; BB = 0 Y = A C + BC, since B + 1 = 1

... (1)

Y = C (A + B)

... (2)

Realisation in the form (1) is as shown A

A

AC

C

C

Y=AC+BC B.C

B

Fig. P (9.3).

Realisation in the form (2) is as shown in Fig. P (9.4).

A

A

B

C

A+B C

Y = C (A + B)

C

Fig. P (9.4).

Example 47. For the combinational logic circuit shown in Fig. P (9.5), obtain simplified Boolean expressions for the output variables V, W, X, Y, Z in terms of the input variables.

379

NUMBER SYSTEMS AND LOGIC GATES

A

Y

V

B Z

X

C

W

Fig. P (9.5).

Solution :

V = (A . B) = A + B = A + B Y = A . (A + B) = A + (A + B) = A + A . B = A + A. B = A + B ( A + AB = A + B) = A. B W = A + B + C + (A + B) = 1 —

W = 1 = 1 X = V + W = 1 + A + B = 1 Z = X + Y = 1 + A . B = 1 . (A . B) = AB

Ans.

Example 48. Add the following Hex numbers. (i) 93 + DE (U.P. Tech. 2001-2002)

(ii) ABCD + EF12 Solution : Try yourself.

Example 49. Realise or implement the following Boolean expressions using basic gates. (a) Y = A

B + C

D + E

(b) Y = (A + B)

(C + D)

(c) Y = (A + B)

C + AB

Solution : (a) Y = A

F (E + F)

B + C

D + E

F

The above boolean expression can be realised by using diagram of Fig. P (9.6a).

380

BASIC ELECTRONICS ENGINEERING & DEVICES

A B C Y=A B+C D+E F D E F

Fig. P (9.6 a).

(b) Y = (A + B)

(C + D)

(E + F)

The above Boolean expression can be realised by the logic diagram of Fig. P (9.6 b). A B C Y = (A + B) . (C + D) . (E + F) D E F

Fig. P (9.6 b).

(c) Y = (A + B)

C + AB = AB + BC + CA.

The above Boolean expression can be implemented by the logic diagram of Fig. P (9.6 c) shown below : A

A+B (A + B) C

B

C Y = (A + B) C + A B

A B

C

Fig. P (9.6 c).

381

NUMBER SYSTEMS AND LOGIC GATES

Example 50. Implement the following Boolean expression using NAND gates only Y = ABC + DEF Solution : Try yourself. Example 51. Convert the following numbers into desired bases. (i) (3451)10 = (?)2 (U.P. Tech. 2003-2004)

(ii) (1745.246)8 = (?)16 Solution : (i) (3451)10 = (?)2. Decimal number

Remainder

2 3451 2 1725

1 (LSB)

2

862

1

2

431

0

2

215

1

2

107

1

2

53

1

2

26

1

2

13

0

2

6

1

2

3

0

2

1

1

0

1 (MSB)

So,

(3451)10 = (110101111011)2

(ii) (1745.246)8 = (?)16 First of all octal number is converted into binary by replacing each octal digit into equivalent 3 bit binary string. Then binary number is converted into hexadecimal by converting 4 bit binary string into hexa equivalent. 1 001

7 111 3

Therefore,

4 100 E

5 . 2 101 . 010 5

.

(1745.246)8 = (3E5.53)16

Comp-1/Laxmi-5/Computer/Revision/Belec-9b—10.5.07

4 100 5

Ans.

6 110 3

left

382

BASIC ELECTRONICS ENGINEERING & DEVICES

Example 52. Add (10111010)2 and (101001)2 without converting base. Solution : 1 0 1 1 1 0 1 0 +

1 0 1 0 0 1 1 1 1 0 0 0 1 1

So,

(10111010)2 + (101001)2 = (11100011)2.

Ans.

Example 53. Find the Boolean function for P and Q in terms of A and B as shown in the circuit of the Fig. P (9.7) below. Also identify the function of the circuit. A B

P

Q

Fig. P (9.7).

Solution : A

A B

B

AB AB

NAND

AB A A

NAND

A.A

NAND

B B

XY

AB

A

B

P

AB = AB

NAND (1)

A B =A+B

B NAND

Fig. P (9.8).

NAND (2)

Q NAND (3)

383

NUMBER SYSTEMS AND LOGIC GATES

Output of NAND 1 Output of NAND 2

P = A. B = A. B = A. B = A + B = A + B = (A + B) . AB = (A + B) . (A + B) = AB + AB ( AA = 0, BB = 0)

Output of NAND 3

= AB AB = AB AB Ans.

Example 54. (a) Simplify the Boolean expression Z = (X + Y) (X + Y ) ( X + Y) (b) Realize this function using the minimum number of two-input NAND gates. Solution : (a) (X + Y) (X + Y) (X + Y) (X + Y) (XX + XY + X Y + YY) X (XY + X Y) + Y (XY + X Y)

X X = 0, Y Y = 0

XY + 0 + XY + 0 XY (

X X Y = 0; XXY = XY; XY + XY = XY)

(b) Realization of two-input NAND gate is given below in Fig. P (9.9). X

XY

XY

Z

Y NAND

NAND

Fig. P (9.9).

Example 55. Realize the following using NAND gates only without minimization. (i) ABC + ABC + ABC

(ii) (1 B ) (ABC)

Solution : (i) ABC + ABC + ABC

A

B

ABC

ABC

C ABC

Fig. P (9.10).

Y = ABC + ABC + ABC

384

BASIC ELECTRONICS ENGINEERING & DEVICES

(ii) ( 1 B) (ABC) A

B

C

1

1·B (ABC)·(1·B)

Y = (1 + B) (ABC)

A·B·C

ABC

Fig. P (9.11).

Example 56. Determine the maxterms canonical product of sums (POS) form and minterm or canonical sum of products (SOP) form of the switching functions : f (A, B, C) — = B . C —

Solution : f (A, B, C) = B . C —

The function has three-variables A, B, C. In the first factor (B), the variables A and C are absent and in the second factor (C), the variables A and B are absent. Therefore, — — — — adding AA + CC to the first factor and adding AA + BB to the second factor, we get : f (A, B, C) = (B + AA + CC) . (C + AA + BB) = [(B + A) . (B + A) + CC] [(C + A) (C + A) + BB] (using distributive property] = [(B + A) (B + A) + C] [(B + A) (B + A) + C]

[(C + A) (C + A) + B][(C + A) (C + A) + B] (again using distributive property] = [C + (B + A) (B + A)] [(C + (B + A) (B + A)] [B + (C + A) (C + A)][B + (C + A) + (C + A)]

Again by applying distributive property, we get = (C + B + A) (C + B + A) (C + B + A) (C + B + A) (B + C + A)(B + C + A) (B + C + A) (B + C + A)

= (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)

Retaining the repeated factors only once, i.e., by deleting the last two factors, we get, = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)

385

NUMBER SYSTEMS AND LOGIC GATES

which is the required POS form, and further it can be written as f (A, B, C) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C) = (010) (110) (011) (111) (000) (100) = II (2, 6, 3, 7, 0, 4) = II (0, 2, 3, 4, 6, 7) in POS form. Ans. To obtain the SOP form of the above function f (A, B, C) = B . C, we multiply this factor by A + A as the variable A is missing

f (A, B, C) = B . C = (A + A ) . B C = ABC + A BC = 101 + 001 = (5, 1) f (A, B, C) = (1, 5). Ans.

ABC + A BC or (1, 5) is the required SOP form of the given function. Example 57. Using Karnaugh’s map simplify the Boolean function

ABCD + ABCD + ABCD + ABCD + ABC D + ABCD Solution : The location of minterms and a four-variable K-map for the given switching function are shown in Fig. P (9.12). f (A, B, C, D) = (ABCD ABCD) ABCD ABCD ABC D ABCD f (A, B, C, D) = ABCD ABCD ABCD ABC D ABCD CD Eliminate B ACD Eliminate C ABD

AB

00

01

00 01

1

1

11

10

1

CD

1

CD

1

11

Eliminate D ABC Eliminate A BCD

CD

10

CD AB

AB

AB

AB

Fig. P (9.12).

Y = ABC + A CD + ABD + BCD Example 58. Simplify (a) f (x1, x2, x3, x4) = (0, 1, 3, 4, 5, 6, 7, 9, 12, 13, 14) (b)

f (ABC) = [A + B + AB] [A + C + AC]

386

BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : (a) The location of minterms and a four-variable K-map for the given switching function shown in Fig. P (9.13). x1 x2 00

x3x4 00

1

01

1

01 1 0

12

1

1

10

1 4

1 11

11

1

8 1

5

13

9

7

15

11

14

10

1 3

10 2

1

1 6

Fig. P (9.13).

There are 5 groups of 4 minterms (quad) and one doublet. — —

—

—

—

—

—

f (x1, x2, x3, x4) = x 1x 3 + x2x 3 + x 3x4 + x 1x4 + x 1x2 + x2x3x 4 (b) A + B + AB Put A + B = X X + AB = X AB + XAB

... (1)

X = AB + AB AB AB = (A + B ) ( A + B)

= (A + B) (A + B) Putting in (1) (AB + AB) (A + B) (A + B) (A + B) AB

= AB + AB + (AA + A B + AB + BB) AB = AB + AB + AB = B (A + A) + AB = B + BA . Ans. Similarly,

A + C + AC = A + C f (ABC) = (A + B) (A + C) = A + AC + AB + BC = A (C + 1) + AB + BC = A + AB + BC = A + BC

Example 59. f (A, B, C, D) = m (2, 3, 8, 10, 11, 12, 14, 15). Using the K-map minimize the function in the sum-of-products form. Also, give the realization using only two-input NAND gates.

387

NUMBER SYSTEMS AND LOGIC GATES

Solution : The location of minterms and a four-variable K-map for the given switching function shown in Fig. P (9.14).

CD

AB

00

01

11

10

1

00

3 DA

1

0

4

12

8

1

5

13

9

3

7

2

6

01 11 10

1

1

1 AB

1 15

11 1

1 14

AB

AB

10

CD CD 2 BC CD 1 = AC CD

AB

Fig. P (9.14).

Y = 1 + 2 + 3

Y = AC + BC + AD = A (C + D) + BC

Example 60. Simplify f (a, b, c) = ab + b c + ca using K-map. Solution : The location of minterms and a three-variable K-map for the given switching function is shown in Fig. P (9.15). f(a, b, c) = ab(c c ) bc (a a ) a (b b ) = abc abc b ca b ca cab cab C

ab

ab

ab

ab

1

1

C C

1

ab

2

1

1

1

1 3

Fig. P (9.15).

Simplified output

Y = 1

+

2

+

3

(i.e., SOP form)

Y = ab + bc + ca

Ans.

Example 61. Find POS canonical form of the function of above example. Solution : K-map is as follows : To get POS canonical form combination of 0’s are seen. – – – f (a, b, c) = (a + b + c) . (a + b + c)

388

BASIC ELECTRONICS ENGINEERING & DEVICES

ab

C

ab

ab

ab

ab

C

0

1

1

1

C

1

1

0

1

Fig. P (9.16).

Example 62. Simplify f (A, B, C, D) = ABC + BC D + ACD + AB + A using Kmap. Solution : The location of minterms and a four variable K-map for the given switching function shown in Fig. P (9.17). f (A, B, C, D) = ABC + BCD + ACD + AB + A Output of the function Ans.

AB

Y = 1

+ 2

or Y = A + B

AB

AB

AB

CD

1

1

1

CD

1

1

1

CD

1

1

1

CD

1

1

1

CD

AB

1

2

Fig. P (9.17).

Example 63. Determine the POS canonical form of the following function : f = ABC + ABD + ACD + D + B Solution : The location of minterms and a four-variable K-map for the given switching function shown in Fig. P (9.18). f = ABC + ABD + ACD + D + B To get POS canonical form combination of ‘O’ is formed. So,

—

f

—

f

= 1 +

2

= ABCD + ABCD

f = ABCD + ABCD

389

NUMBER SYSTEMS AND LOGIC GATES AB AB

AB

AB

AB

CD

1

1

1

1

CD

1

0

1

1

1

CD

1

1

0

1

2

CD

1

1

1

1

CD

Fig. P (9.18).

f = ( ABCD)( ABCD) f = (A + B + C + D) (A + B + C + D) This is the required POS form for the function given above.

Ans.

Example 64. Minimise the following using K map. f (A, B, C, D) = m (0, 2, 4, 6, 8, 10, 12, 14) (U.P. Tech. 2001-2002) Solution : The location of minterms and a four-variable K-map for the given switching function shown in Fig. P (9.19). The output of the function will be : Y = 1

+

2

or

Y = C D + CD

or

Y = D (C + C) Y = D

Ans.

Alternative method Y = Pair of eight = D

Fig. P (9.19).

Example 65. Simplify the following Boolean function in product of sums. F (A, B, C, D) = m (0, 1, 2 5, 8, 9, 10) Solution : Try yourself. Example 66. Obtain a reduced expression for the following multiple output system, given as : F1 (A, B, C, D) = m (0, 1, 2, 5, 7, 8, 9, 10, 13, 15) F2 (A, B, C, D) = m (0, 1, 2, 8, 10, 11, 14, 15) and realize the minimised function using NOR gates only. Solution : Try yourself.

390

BASIC ELECTRONICS ENGINEERING & DEVICES

Example 67. Reduce the following function using K-map : f (A, B, C, D) = m (0, 1, 2, 11, 12, 14, 15) + d (3, 5, 6, 13) (U.P. Tech. 2002-2003) Solution : The location of minterms, don’t care and a four variable K-map for the given switching function shown in Fig. P (9.20). f (A, B, C, D) = m (0, 1, 2, 11, 12, 14, 15) + d ( 3, 5, 6, 13) AB CD

AB

CD

1

CD

1

CD

d

CD

1

AB

AB

AB

1 0

4 d

12

8

13

9

d 5 1

3

7 d

2

1

1 15

11

14

10

3

1 6

2

Fig. P (9.20).

The output Y is given as : Y = 1

+ 2

+

3

Y = A B + AB + ACD

Ans.

Example 68. Minimize the following Boolean expression using K-map. f (x, y, z, w) = M (0, 2, 5, 7, 8, 10, 13, 15) (U.P. Tech. 2003-2004) Solution : Try yourself. Example 69. Convert (i) (47.25) into Binary (ii) (2715)8 into Hex (iii) (1E7B)H into Octal.

(U.P. Tech. 2004-2005)

391

NUMBER SYSTEMS AND LOGIC GATES

Solution : (i) (47.25) into binary is obtained as 2 2 2 2 2 2

47 23 11 5 2 1 0

1 1 1 1 0 1

101111

and .25 may be obtained as follows: Integer 0.25 × 2 = .50

0

.50 × 2 = .00

1

Thus we obtained binary as (47.25) in binary as 101111.01 Ans. (ii) (2715)8 into Hex we get as follows:

2715 010 111 001 101 and converting this to Hex

0101 1100 1101

So,

5 C (2715)8 = (5CD)16 Ans.

D

(iii) (1E7B)H into octal as follows: . Now converting this into octal as follows: 000 001 111 001 111 011 017173 So,

(1E7B)H = (017173)8 Ans.

Example 70. Minimize the K-map. CD AB

00

01

11

10

1

00

1

01

1

1

1

1

11 10

1

1

Fig. P (9.21).

392

BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : We get BD + ABCD + ABCD + ABCD + ABCD BD + BD(AC + AC) + BD(AC + AC) BD + BD(A

C) + BD(A C).

Ans.

4 1 2

3

5

Fig. P (9.22).

Y = 1 + 2 + 3 + 4 +

5

= BD + ABC + ACD + A CD + ABC . Ans. Example 71. F = (A + C)(A + D)(B + C)(B + D) Simplify using Boolean algebra. Solution :

F = (A + C)(A + D)(B + C)(B + D) =

(A + C) A D B + C B D

=

ACADBCBD

=

A(C D) B(C D)

=

(A B)(C D)

F = AB + CD. Example 72. Realize the function, Y = ABC + ABC ABC ABC by using minimum number of gates. Solution :

Y = ABC + AB C ABC ABC = ABC + ABC AB C ABC = AB (C C) + AB(C C)

Y = AB + AB

Y = A (B B) = A

[

C + C = 1]

393

NUMBER SYSTEMS AND LOGIC GATES

Circuit Realization is shown below in Fig. P (9.23) A

Y

Fig. P (9.23).

Example 73. Realize 3-bit adder circuit using basic gates. Solution : The truth table of 3-bit adder is shown is table below : A

B

C

Sum

Carry

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Sum =

A BC ABC AB C ABC

=

A(BC BC) A(B C BC)

=

A(B C) A(BC BC)

Sum = (A B + C) Carry = =

ABC ABC ABC + ABC BC(A + A) A(BC + BC)

Carry = BC + A(B C) C B Sum A

Carry

Fig. P (9.24).

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BASIC ELECTRONICS ENGINEERING & DEVICES

Example 74. For the truth table given below, draw the K-map and simplify the K-map. A

B

C

F

0

0

0

1

=

m0

0

0

1

0

=

m1

0

1

0

1

=

m2

0

1

1

1

=

m3

1

0

0

0

=

m4

1

0

1

0

=

m5

1

1

0

0

=

m6

1

1

1

1

=

m7

Solution : The K-map for the truth table shown above can be drawn as shown in below Fig. P (9.25a) F

BC

A

1

BC 0 0

A

BC

0

1 1

1 3

0 4

BC

1 5

BC

BC

BC

BC

A

1

0

1

1

A

0

0

1

0

2

0 7

F

6

(a)

(b) Fig. P (9.25)

Here the above K-map shows the plotting of the function ( f ) as per the truth table. Now encircling the group of the 1’ element as shown is Fig. P (9.25b), we obtain three overlapped pairs of bodean equation i.e., F =

AB + BC + A C

Example 75. Draw the K-map for the below given truth table and then simply it. A

B

C

D

F

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 1 1 0 1 1 1 1 1 0 0 1 1 0 0

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NUMBER SYSTEMS AND LOGIC GATES

Solution : The K-map for the given truth table is given below i.e. Fig. P(9.26a) F

CD

AB

0

CD 0 0

AB

0

1

1

AB

1

1

1

1

0

0

0

CD

CD

CD

CD

AB

0

0

1

1

AB

0

1

1

1

AB

1

1

0

0

AB

1

1

0

0

6

15

14

0

9

F

2

7

13

1 8

1 3

5

12

CD

1 1

4

AB

CD

11

10

(a)

(b) F

CD

CD

CD

CD

AB

0

0

1

1

AB

0

1

1

1

AB

1

1

0

0

AB

1

1

0

0

F = AC + AC + ABD

F = AC + AC + BCD

(c)

Fig. P (9.26)

It means that one can obtain K-map of the given truth table by two different approach of encircling the elements as shown in above Fig. P(9.26b) and (9.26c). The two Boolean equation obtained below are correct and valid due to their logical equivalence. Example 76. Obtain the simplified Boolean equation for the K-map shown below in Fig. P(9.27) F

CD

CD

CD

CD

AB

0

0

0

0

AB

1

0

0

0

AB

1

1

1

1

AB

1

1

1

0

Fig. P (9.27)

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BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : In order to obtain the simplified equation of the K-map, one has to encircle the valid group of the proper elements as shown in below Fig. P(9.28) F

CD

CD

CD

CD

1

AB AB

1

AB

1

1

1

AB

1

1

1

Fig. P (9.28)

F = AB + AC + AD + BC D Example 77. A four variable function can be expressed as F = (0, 1, 3, 6, 9, 13, 15) Use K-map to minimize the above function. Solution : The K-map of the given function can be plotted as shown below is Fig. P(9.29a). And in order to simplify and minimize the function, we have to choose the valid group of the elements and encircle them as shown in Fig. P(9.29b) i.e.,

Fig. P (9.29)

F = (0, 1, 3, 6, 9, 13, 15) F =

A B C + A BD + ABD + ACD + ABCD .

Example 78. Convert following functions in other canonical forms (a) f (x, y, z) = (1, 3, 7)

(b) f (x, y, z) = (0, 3, 6, 7)

Solution : (a) f (x, y, z) = (1, 3, 7) or,

f (x, y, z) = m1 + m3 + m7 = x yz + xyz + xyz

Minimizing f (x, y, z), (Sum of minterms form)

397

NUMBER SYSTEMS AND LOGIC GATES

f (x, y, z) = =

f (x, y, z) =

xz (y + y ) + xyz = xz (1) + xyz

y + y = 1)

(

(x xy ) z = (x y ) z

x + xy = x + y)

(

xz yz

Converting f(x, y, z) to product of maxterms form, f (x, y, z) =

or,

xz yz zz = 0, yy = 0)

=

(x y ) z = (x y zz )(y .y z )

=

(x y z )(x y z )(y z )(y z )

=

(x y z )(x y z )(xx y z )(xx y z )

f (x, y, z) = =

(

xx = 0)

(

(x y z )(x y z )(x y z )(x y z )(x y z )(x y z ) (x y z )(x y z )(x y z )(x y z )(x y z )

= M4.M5.M0.M2.M6 = M0.M2.M4.M5.M6 = (0, 2, 4, 5, 6) Thus,

f (x, y, z) = (1, 3, 7) = (0, 2, 4, 5, 6) Ans.

(b)

f (x, y, z) = (0, 3, 6, 7) = (x + y + z) (x y z )(x y z )(x y z ) [Product of Maxterms form] = (x + y + z) (x y z )(x y z )(x y z ).(x y z ) [

A . A = A]

= (x + y + z) ( x . x y z )( x y z . z ) [

(A + B + C )(A + B + C ) = (A + B + C . C )]

= (x + y + z) (y z )(x y ) [Minimized Product of Maxterms form] Converting to sum of minterms form, f (x, y, z) = (x + y + z) (y z )(x y ) = [xy xz yy yz zy zz ](x y ) =

(xy xz yz yz )(x y )

=

x . x .y x .x .z xyz x yz xy .y xz .y yz .y yz .y

= 0 + 0 + xyz x yz xy xy z 0 yz . =

xyz x yz xy z xy yz

[

A . A = 0]

398

BASIC ELECTRONICS ENGINEERING & DEVICES

=

xyz x yz xy z xy ( z z ) ( x x )yz

=

xyz x yz xy z xyz xy z xyz x yz

=

xyz x yz xy z xyz

A + A = 1)

( (

A + A = A)

= m2 + m1 + m4 + m5 = m1 + m2 + m4 + m5 = (1, 2, 4, 5) Ans. Example 79. Obtain the simplified expression in sum of products for the following Boolean function using K-map. = xyz xy z xyz xyz

(i) f

(ii) f(x, y, z) = (0, 2, 4, 5, 6) Solution : (i) f = xyz xy z xyz xyz = m3 + m4 + m5 + m6 Using K-map as shown in Fig. P(9.30) Encircling the pairs and encircling the isolated 1’s, we get, f = xy xz xyz Ans. (ii) f(x, y, z) = (0, 2, 4, 5, 6) Fig. P(9.31) shows the K-map for the above function. yz

f

yz

yz

x

yz

f (x, y, z)

1 0

x

1

x 3

1

1 4

yz

1

x

1

Fig. P (9.30)

yz

0

1

1 3

1

4

6

yz

0 0

2

1 7

5

yz

0 5

2

1 7

6

Fig. P (9.31)

The minterms m0, m2, m4 and m6 form a quad while minterms m4 and m5 form a pair. Thus, the result follows as :

z xy Ans.

f (x, y, z) =

Example 80. Given the following truth table x

y

z

f1

f2

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

399

NUMBER SYSTEMS AND LOGIC GATES

(a) Express f 1 and f 2 in product of maxterms. (b) Obtain the simplified function in SOP form using K-map. (c) Obtain the simplified function is POS form using K-map. Solution : (a) From table, f 1 =

(x y z )(x y z )(x y z )(x y z )

and,

(x y z )(x y z )(x y z )(x y z ) Ans.

f2 =

(b) First, for f 1, the K-map is shown in Fig. P(9.32) Encircling 1’s, we get f1 =

x y z xyz xy z xyz

(SOP form)

= x y z Secondary, for f 2, the K-map is shown in Fig. P(9.32) Total three pairs are formed and seen through encirclements done in K-map of Fig. P(9.32). Thus, we get f1 x x

yz

f2 yz

yz

0 1

0

1

yz

7

yz

0

yz

x

0

Fig. P (9.32)

0 3

1

1 4

6

yz

1

0 0

2

0

1 5

yz

x

3

1

4

x

yz

0

1 0

x

yz

2

1

1 7

5

6

Fig. P (9.33)

f 2 = xz + yz + xy

(SOP form) Ans.

(c) First, for f 1, the K-map is shown in Fig. P(9.34) From the K-map of Fig. P(9.34), encirclings 0’s, we get complement of f 1 i.e.,

f1

=

x y z xyz xyz xyz

Taking complement of f 1 , we can have f 1, so — –

f 1 = (f 1) = x y z xyz xyz xyz = (x + y + z) (x y z )(x y z )(x y z ) (POS form) Similarly, f 2 can be evaluated from K-map of Fig. P(9.35) Encirclements of 0’s leads to the result, f1

f1 yz

x

yz

0 1

Fig. P (9.34)

x

7

yz

0

0 3

1

1 4

yz

1

0 0

x 6

yz

0

2

0

1 5

yz

1 3

1

0 4

yz

0

1 0

x

yz

1

1 5

2

7

Fig. P (9.35)

6

400

BASIC ELECTRONICS ENGINEERING & DEVICES

f2 = x z x y y z Complement of f 2 will be, therefore, f 2 = x z x y y z = (x + z)(x + y)(y + z)

(POS form) Ans.

Example 81. Simplify each of the following Boolean function (f) using the don’t care condition (d) in (i) Sum of products and (ii) Product of sums. (a) f = A B D ACD ABC ;d = ABCD ACD AB D Solution : (a) The function f is a four variable function. Directly feeding the values of function in the K-map as shown in Fig. P(9.36), we get

AC B D

f =

(sum of products form)

f

AB AB

CD

CD

CD

1

0

1

0

0

AB

0 X

1 3

X 4

AB

1

1

0 0

8

2

1

5

12

CD

7

13

X

0 15

X

9

X don’t care condition

6

14

X 11

10

Fig. P (9.36)

Instead of 1’s, if we encircle 0’s as shown in K-map of Fig. P(9.37), we get f CD AB

CD

1

0 0

AB

0

X

0

AB

1

0

X

1

X

6

X don’t care condition

0 15

X 9

2

7

13

0 8

1 3

5

12

CD

1 1

4

AB

CD

14

X 11

10

Fig. P (9.37)

401

NUMBER SYSTEMS AND LOGIC GATES

=

f

BC CD A

Complement of f is, — –

( f ) = f = BC C D A =

(BC )(C D )( A )

=

(B C )(C D )A [Product of sums form] Ans.

Example 82. A four variable function is expressed as F = (0, 4, 5, 6, 7, 13, 14, 15) Use K-map minimization technique to obtain simplified Boolean equation in product of sums form. Solution : Fig. P(9.38) shows the K-map and the entries of 0’s at the respective maxterm numbers is also shown. Fig. P (9.39) shows the valid encirclements of 0’s. The sum of products (SOP) form of equation will be =

F

A C D BD BC

F CD AB

CD

CD

0 0

AB

CD

0

1

0 4

AB

3

0 5

0

CD

AB

0

AB

0

CD

CD

CD

0

0

0

0

0

0

2

0 7

0

F

6

AB

0

12

13

15

14

8

9

11

10

AB

AB

Fig. P (9.38)

Fig. P (9.39)

The function for SOP form is represented as F and not F because the resultant equation is due to encirclement of 0’s and not 1’s. Complementing F will yield F and also in product of sums (POS) form. — –

F = (F ) = AC D BD BC = ( A C D )(B D )(B C ) = (A + C + D) (B D )(B C ) Example 83. Use a K-map to simplify the following function : f(A, B, C, D) = (0, 6, 9, 10, 13) + d(1, 3, 8) Solution : K-map of Fig. P(9.40) shows the entries of 1’s and don’t cares (crosses) at the minterm places as expressed in the function. Fig. P(9.41) shows the valid

402

BASIC ELECTRONICS ENGINEERING & DEVICES

encirclements, considering don’t cares of m1 and m8 as ‘1’ while m3 as ‘0’. The Boolean equation, hence, can be expressed as

BC ACD AB D ABCD Ans.

f(A, B, C, D) =

f

f

AB

CD

CD

CD

1

X

X

0

1

CD AB 3

AB AB

7

X

X

X 1

AB 13

15

9

11

1

14

1 8

1

CD

6

1 12

CD

AB

1 5

CD

2

AB 4

CD

AB

1

X

1

1

10

Fig. P (9.40)

Fig. P (9.41)

Example 84. Simplify the Boolean function (f) in sum of products using the don’t care conditions (d) (a) f = y x z d = yz + xy (b) f 2 = BC D BCD ABCD d = BCD ABCD Solution : (a)

y xz

f =

d = yz + xy Ans. Directly expressing function f and don’t care conditions, d in K-map as shown in Fig. P (9.42) and encircling them, we get, f = 1 f x

yz

yz

1

1 0

x

yz

1

X 1

1 4

yz 1 3

X 5

2

X don’t care condition

X 7

6

Fig. P (9.42)

(b) f = BC D BCD ABCD d = BCD ABCD

403

NUMBER SYSTEMS AND LOGIC GATES

Feeding the values of function f and don’t care condition d in K-map directly, we get the map as shown in Fig. P(9.43) F1

AB AB

CD

CD

CD

1

0

0

0

0

X 4

AB AB

0 1

1

12

8

0

X 3

0 5

0

CD

13

9

2

1 7

0

6

X don’t care conditions

1 15

0

14

X 11

10

Fig. P (9.43)

Encircling 1’s, the K-map of Fig. P (9.43) results in a function f as follows : f = B D CD = (B C )D Ans.

10 Analog systems (both linear and non-linear) can be constructed with the op-amp or differential amplifier as the basic building block. In their early stages, these opamps were constructed from discrete components (vacuum tubes and then transistors and resistors) and their cost was prohibitively high. In 1960’s, with the development of IC’s, set the stage for a first IC op-amp (µA702) developed by Fairchild semiconductors in 1963. In 1965, Fairchild introduced the µA709, regarded as first generation op-amp, which was the improved version of µA702. Fairchild, in 1968, came with the most popular IC op-amp µA741, also regarded as the second generation op-amp. One of the reasons for the popularity of op-amp is its versatility and, in fact, the IC op-amp has characteristics that closely approach assumed ideal op-amp.

An operational-amplifier (op-amp), which is the basic building block for many analog system itself, consists of a very high gain, direct-coupled amplifier with feedback, having high input impedance, a low output impedance and acting as differential amplifier. The op-amp is basically a multistage amplifiers (since it consists many amplifier stages, directly coupled to previous one), so it can be represented as a block diagram as shown in Fig. 10.1.

vin

Diff. AMP

More Stages of Gain

Output Stage

v0

Fig. 10.1. Block diagram of operational amplifier.

The first block of the Fig. 10.1 is the input stage, consisting of Dual Input Balanced Output (DIBO) differential amplifier, providing most of the voltage gain and also establishes the input resistance of the op-amp. The second block, consists of many stages of direct coupled (DC) Dual Input Unbalanced Output (DIUO, single ended) differential amplifiers, which provides additional gain. 404

Comp-1/Laxmi-5/Computer/Revision/Elec-10—13.4.07

30.4.07

405

OPERATIONAL AMPLIFIERS

The last block consists of two stages, one for DC level shifting (usually emitter follower) and the second is Class B power amplifier output stage. The well designed output stage provides low output resistance and also increases the output voltage swing (peak-to-peak variation) and raising the current supplying capability. Fig. 10.2 (a), shows the schematic symbol of an op-amp and Fig. 10.2 (b), the equivalent circuit of op-amp. +vCC

Non-Inverting Input

R0

v1

+

v0

(v1) OP-AMP

Inverting Input

Output (v0)

Rin

A(v1 – v2)

– (v2) v2

–VEE

(a) Schematic symbol of op-amp

(b) Equivalent circuit of op-amp

Fig. 10.2.

From the signal point of view, the op-amp has three terminals, two input terminals and one output terminal. The two input terminals are non-inverting and inverting terminals. The amplifiers require dc supply for biasing purpose. The two dc sources, named as + VCC and VEE, are required for the biasing of op-amps, these two are equal in magnitude with opposite polarities. The reference grounding point in op-amp circuit is just the common point of two dc supplies, i.e., no terminals of op-amp package is physically connected to ground. The equivalent circuit of an op-amp, includes important values, A, R0 and Rin. The A (v1 v2) is an equivalent Thevenin’s voltage source and R0 is the Thevenin’s equivalent resistance, looking back into the output terminals of an op-amp. The equivalent circuit is useful in analysing the basic operating principle and the effects of feedback arrangement. The output voltage can be written as : v0 = A (v1 v2) = A vid where,

A = Large signal voltage gain or open loop voltage gain vid = (v1 v2) = The difference input voltage v1 = Voltage at the non-inverting input terminal

and

v2 = Voltage at the inverting input terminal.

Note that v1 and v2 are taken with respect to ground.

... (10.1)

406

BASIC ELECTRONICS ENGINEERING & DEVICES

Thus from the eqn. (10.1), we deduce that, the op-amp only amplies the difference of the input signals, applied at the two input terminals. Another important point to be kept in mind is that the ideal op-amp does not suppose to draw any input current on both terminals (i.e., i1 = i2 = 0 Amp or Rin ). In eqn. (10.1), if v1 > v2, the v0 is positive and if condition is reversed, i.e., v2 > v1, v0 is a negative quantity, thus acting as non-inverting and inverting amplifiers, respectively. The last case, results in zero output voltage, i.e., v0 = 0, when v1 = v2 and this is known as common mode input configuration.

The ideal op-amp, are those op-amps, which have these characteristics, given below : 1. Infinite voltage gain A (A = ). 2. Infinite input resistance (Rin = ). 3. Zero output resistance (R0 = 0). 4. Infinite bandwidth (BW = ). 5. Infinite common mode rejection ratio (CMRR = ). 6. Infinite slew rate (SR = ). 7. Zero output voltage where input difference voltage, vid, is zero. The properties mentioned above makes, the ideal op-amp, a perfect voltage amplifier and often referred to as a voltage controlled voltage source (VCVS), as shown in Fig. 10.2 (b). The practical op-amps can be made to behave nearly in unison with the ideal one by using the proper feedback circuitry. CMRR (Common Mode Rejection Ratio) is defined as the ratio of differential voltage gain (Ad) to the common mode voltage gain (ACM), i.e., CMRR =

Ad ACM

... (10.2)

where ACM is common mode voltage gain and is given by, ACM =

VOCM VCM

... (10.3)

VOCM = Output common mode voltage and

VCM = Input common mode voltage.

CMRR is often expressed in desibel’s (dBs). In practical case ACM is very small (not exactly zero), and Ad is very large (as it is large signal gain, i.e., A), therefore, CMRR is very large, but not exactly infinite, such as 90 dB for 741 IC op-amp. ACM is determined from the common mode configuration of op-amp, as shown in Fig. 10.3.

407

OPERATIONAL AMPLIFIERS

v1

+ OP-AMP

v2

vCM + –

v0CM

–

Fig. 10.3. Common mode configuration.

Slew Rate (SR) is the maximum rate of change of output voltage with respect to time, i.e., SR =

dv 0 dt

... (10.4) max

The unit of the Slew Rate is V/µs (volts per microsecond). It is the cause of nonlinear distortion at the output.Table 10.1

Initially the application areas of op-amp were analog computation and instrumentation, so named “op-amp”, i.e., the amplifier which performs many operations. Originally, it was used to perform mathematical functions such as addition, multiplication by a constant, subtraction, differentiation, integration, etc., one now put to a variety of other uses, for e.g., as comparator, pulse generator, wave generator, schimitt trigger, multivibrations, etc. We can use the op-amps also as, logarithmic and antilogarithmic modules, linear differential eqn. solver and to solve other mathematical functions.

? 1. Define op-amp. 2. What are the minimum number of terminals required in single op-amp ? 3. Which differential amplifier configurations are used in op-amp ? 4. Can op-amp amplify dc voltage ? 5. Which type of coupling is used between the various stages of op-amp and why ? 6. What are the main characteristics of an op-amp ? 7. Define CMRR and its significance. 8. Define Slew Rate.

408

BASIC ELECTRONICS ENGINEERING & DEVICES 9. Whether op-amp amplifies a large signal, small signal or both. Give the satisfactory conclusion. 10. What are the different application areas of op-amp ? 11. State the ideal characteristics of an operational amplifier and also the important mathematical operations of an OP-AMP can performs. (U.P. Tech. 2001-2002)

Example 1. For an op-amp, CMRR = 105 and differential gain Ad = 105. Determine the common mode gain ACM of the op-amp. Solution : Given for an op-amp : CMRR = 105 Ad = 105

and Since, we know that,

CMRR =

ACM =

Ad ACM

105 Ad = CMRR 105 Ans.

ACM = 1.

Example 2. The output voltage of an op-amp circuit changes by 20 V in 4 µs. What is the slew rate ? Solution : Given : Change in voltage, V = 20 V Change in time, t = 4 µs from the definition, slew rate SR =

V t

= max

SR = 5 V/µs.

20 V 4 s Ans.

Example 3. The input voltage to an op-amp is a large voltage step. The output is an exponential waveform that changes 0.75 V in 50 ns. What is the slew rate of the op-amp ? Solution : Given : V = 0.75 V t = 50 ns

409

OPERATIONAL AMPLIFIERS

From definition : Slew rate (SR) =

=

V t

max

0.75 V 0.75 V = 50 ns 50 10 3 s

SR = 15 V/µs.

Ans.

As we know, op-amp amplifies only the difference of the two signals, applied at the non-inverting and inverting terminals, but the range of signals is very small due to the very large open loop (differential, large signal) voltage gain Ad (of the order of 105), because the maximum amplitude of the output signal cannot exceed to the maximum value of biasing voltage. Beyond this range op-amp is said to be in saturation with constant evelop of voltage signal. For example, if the maximum value of output voltage for an op-amp circuit is 20 V and the large signal voltage gain is 2 × 105, then the maximum value of signal, which can be amplified by op-amp is vid =

v0 Ad

20

or

vid =

or

vid = 104 volt

2 105

which is a very small quantity. Such small signals are very susceptible to noise (unwanted and random electrical signals) and almost impossible to obtain in laboratory. Besides, being large, the open loop voltage gain of the op-amp is not a constant, but varies with temperature, power supply as well as device to device. It makes the open loop op-amp unsuitable for many linear applications. Also the bandwidth of most open loop op-amps is negligible small — almost zero. Therefore, the open loop configurations are impractical in AC applications. Due to above mentioned disadvantages of open loop op-amps, these are generally not used in linear applications. We cannot only select, but also control the gain of the op-amp, simply by introducing the feedback (combining a portion of output signal with input signal either directly or indirectly) in the circuit. When the phase of input and feedback signals are same (i.e., phase difference is 0°), the feedback is said to be positive or regenerative feedback. When the feedback signal is of opposite polarity (i.e., out of phase by 180°) with respect to the input signal, the feedback is called negative or degenerative feedback. Since the discussion of “feedback” is beyond the scope of this book, so we will enlist only the advantages of negative feedback here.

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BASIC ELECTRONICS ENGINEERING & DEVICES

In amplifiers, negative feedback have following characteristics : stabilizes the gain. increases bandwidth.

Advantages of Negative Feedback

changes input and output impedances. decreases the effect of distortion and noise.

reduces the voltage gain (this is only disadvantage of negative feedback).

The inverting amplifier is most basic constant gain amplifier. It is also known as the voltage-shunt feedback amplifier. The basic circuit diagram is shown in Fig. 10.4. Here biasing power supplies are not shown for simplicity. RF

vin

Iin

R1

t

IF

t

v2 + vid IB2

– 0 OP-AMP

vin

v1

v0

–

v0

+ IB1

0

Fig. 10.4. Inverting amplifier.

An input voltage vin drives the inverting input through resistor R1. This results an inverting input vid, which is amplified by the open-loop voltage gain to produce an inverted output voltage v0. The output voltage is feedback to the input through the feedback resistor RF. This arrangement forms a negative feedback, because the output is 180 out of phase with the input. Note that non-inverting terminal is grounded.

Concept of Virtual Ground A point is any circuit is said to be grounded if the potential at that point is equal to the ground potential. If that point is connected to the ground with the help of any conducting (metallic) wire, then all the current from that point (node) flows towards the ground, and the point is said to be physically or mechanically grounded. In case of virtual ground, only the condition for potential is satisfied, i.e., potential at that point becomes same as ground potential, but there is no path for current from that point to ground. The concept of virtual ground is a widely used shortcut for analysing an inverting amplifier.

411

OPERATIONAL AMPLIFIERS

The concept of virtual ground is based on an ideal op-amp, i.e., the voltage gain of an ideal op-amp is infinite and input impedance is infinite. We can deduce the RF

IF

Iin vin

R1

v2

0 IB2

– 0 OP-AMP

I =0 Virtual ground

v1

v0

+ IB1

0

Fig. 10.5. Concept of virtual ground.

following ideal properties for inverting amplifier from the above discussion : (1) since, i.e.,

Rin Iin

, therefore, IB 2 = IB1

0,

IF .

(2) since, Ad is infinite (in ideal case),

Ad =

v0 v id

vid =

v0 Ad

vid = (v1 v2)

v0

0 0 volt

... (10.5)

From Fig. 10.5 and eqn. (10.5), we see that, v2

0 volt = v1

due to virtual ground. Virtual ground is very unusual and just like half of a ground, because it is a short for voltage but an open for current.

Voltage Gain Here, voltage gain means to the closed loop or overall voltage gain of inverting amplifier. It can be determined by two methods, either by feedback method or by virtual ground concept.

1. Virtual Ground Method (Ideal op-amp) Consider the inverting amplifier configuration shown in Fig. 10.5. We have from virtual ground concept,

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BASIC ELECTRONICS ENGINEERING & DEVICES

Here,

RSas T

Iin

IF

... (10.6)

Iin =

v in v 2 R1

... (10.7)

potential difference resistance

current =

and

v2 v0 RF

IF =

v in v 2 R1

Therefore, but from eqn. (10.5),

v in R1

0 =

v0 =

... (10.8)

v2 v0 RF

=

v2

so,

UV W

v0 RF

RF v R1 in

... (10.9)

or overall or closed loop voltage gain,

v0 RF = v in R1

A0 =

... (10.10)

2. Feedback Method (Practical op-amp) In previous derivation, we assumed about ideal op-amp, but here we will consider the finite differential voltage gain Aid, which is very large (almost, but not exactly, infinite). Consider the Fig. 10.6, RF

IF

vin

R1

Iin

v2 a + vid

– IB

0 OP-AMP

v1

–

+

Fig. 10.6.

Applying KCL at node (a), Iin = IF + IB

v0

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OPERATIONAL AMPLIFIERS

Since, Rin is very high (of the order of 2 M), IB is negligibly small, therefore, Iin

IF

... (10.11)

v2 v0 RF

... (10.12)

Now from eqns. (10.7) and (10.8),

v in v 2 R1

=

However, v1 v2 = Since,

v0 Ad

v1 = 0 V vid = v2 =

v0 Ad

... (10.13)

substituting the value of v2 from eqn. (10.13) into eqn. (10.12), we get,

v in

v0 Aid

R1 Solving,

A0 =

v0 v in

v0 v0 Ad RF

=

=

Ad R F R1 R F Ad R1

... (10.14)

since, internal differential gain Aid of the op-amp is very large (ideally infinite), therefore, Ad R1 >> R1 + RF , hence eqn. (10.14) reduces to A0 =

v0 v in

RF R1

... (10.15)

which is same as eqn. (10.10) for ideal op-amp, or obtained using virtual ground concept. Eqns. (10.10) and (10.14) also indicates that the closed loop voltage gain does not depend on the internal differential gain of the op-amp and desired gain or multiplier can be obtained by simply adjusting the appropriate value of the external resistors R1 and RF .

Input Impedance Input impedance is defined as the ratio of input voltage to input current, i.e., Ri =

v in I in

... (10.16)

Now from eqn. (10.7), where v2 = 0 V, Ri = R1

... (10.17)

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BASIC ELECTRONICS ENGINEERING & DEVICES

? 1. Why an open-loop op-amp is not suitable for linear applications ? 2. What is feedback ? 3. What are the advantages of negative feedback ? 4. Which type of feedback is suitable for oscillators and non-linear applications ? 5. What is virtual ground ? 6. What are the properties of virtual ground ? 7. Which type of feedback is used in inverting amplifier configurations ? 8. What will happen to closed loop gain A0 if load resistor RL is connected at the output terminal and why ? 9. Suppose, a voltage source of 2 V is connected at the non-inverting terminal. Is the concept of virtual ground is still valid ? 10. What is the formula for the gain of inverting amplifier ?

Example 1. Consider the circuit of Fig. 10.6. Determine the value of closed loop voltage gain and input impedance if R1 = 1 k and RF = 4.7 k. Solution : Given for the inverting amplifier, R1 = 1 k and

RF = 4.7 k We know that,

closed loop voltage gain,

A0 =

v0 RF = v in R1

=

4.7 k 1 k

A0 = 4.7. and input impedance,

Ans.

Ri = R1 Ri = 1 k.

Ans.

Example 2. Consider the circuit in Fig. 10.6. Determine the values for R1 and R2 such that the closed loop gain is 20 and the input impedance is 5 k. Solution : Given for inverting amplifier configuration : A0 = 20 Ri = 5 k R1 = ? RF = ?

415

OPERATIONAL AMPLIFIERS

We know that, Ri = R1 R1 = 5 k. Ans. Also, closed loop voltage gain for inverting amplifier is given as : A0 = Substituting the values,

RF R1

RF 5 k = 20 × 5 k = 100 k. Ans.

20 = RF RF

Example 3. What output voltage results for an input of 1.25 V in the circuit of Fig. P (10.1). 300 k

20 k vin

– v0

OP-AMP +

Fig. P (10.1).

Solution : Given in Fig. P (10.1), R1 = RF = and vin = v0 = We know that, A0 =

20 k 300 k 1.25 V ?

v0 v in

v0 = A0 vin =

v0 =

RF v R1 in

300 1.25 20

v0 = 18.75 volt. NOTE :

Ans.

This output voltage can be achieved only when the maximum voltage swing is greater than or equal to 19 V.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Example 4. Determine the values of R1 and RF for an inverting amplifier configuration for which gain is 4 V/V and the total resistance used is 100 k. Solution : Given for an inverting amplifier circuit, A0 = 4 V/V R1 + RF = 100 k

... (1)

R1 = ? RF = ? We have,

A0 =

RF R1

4 =

RF R1

RF = 4R1

... (2)

Substituting the value of RF from eqn. (2) into eqn. (1). R1 + 4R1 = 100

R1 = 20 k.

and

Ans.

RF = 4 × 20 k RF = 80 k.

Ans.

The non-inverting amplifier is another basic op-amp circuit uses negative voltageseries feedback to stabilize the overall voltage gain. It is also known as voltage series feedback amplifier. The circuit configuration of non-inverting op-amp is shown in Fig. 10.7. v1

vin t

+

V0 +

vid vin

– v2

OP-AMP

V0

– RF

+ vf –

Fig. 10.7. Non-inverting amplifier.

R1

t

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OPERATIONAL AMPLIFIERS

Here, an input voltage source is connected at the non-inverting terminal of the op-amp. This input voltage is amplified to produce the in phase output voltage, as shown. Part of v0, i.e., vf , is feedback to the input through a voltage divider network at the inverting terminal. Note here, that feedback voltage vf is almost equal to the input voltage vin , as v1 v2 0 V for op-amp. It can be easily verified by applying KVL at the input section. Since, the feedback voltage vf , opposes the input voltage vin, feedback is known as negative feedback. Almost zero voltage difference between the two terminals, i.e., v1 v2 0, is due to almost infinite input resistance and almost infinite differential voltage gain of the operational amplifiers and known here as the virtual short. Because of the virtual short, the inverting input voltage follows the non-inverting input voltage. If the non-inverting voltage changes, the inverting input voltage immediately changes to the same value. This follow-to-leader action is called Bootstrapping. In other words, the inverting input is bootstrapped to the non-inverting input.

Voltage Gain Consider the circuit of Fig. 10.8. If we apply KVL at the input side, we get, vin = vid + vf

... (10.18)

vid = v1 v2

where,

v1 = vin and

v f = vz =

R1 v0 R1 R F

v0 = Ad (v1 v2)

However,

... (10.19)

= Ad vid Therefore,

FG v H

v 0 = Ad

LM A R N aR R

v0 1

or

(by voltage divider rule)

d

1

1 F

O f PQ

in

R1v 0 R1 R F

IJ K

= Ad vin

or the closed loop voltage gain is A0 =

v0 = v in

A0 =

Ad R1 R F R1 R F Ad R1

Ad Ad R1 1 R1 R F

a

a

f

f

Generally, Ad is very large quantity (of the order of 105), therefore, Ad R1 >> (R1 + RF) Thus,

A0

aR

1

RF R1

f

... (10.20)

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BASIC ELECTRONICS ENGINEERING & DEVICES

or

A0 =

FG1 R IJ H R K F

=

1

v0 v in

... (10.21)

The same result, as in eqn. (10.21), can be obtained by virtual short concept as follows : Rewriting eqn. (10.18) here, vin = vid + vf vid = v1 v2

as

vin but

0 V, we have,

vf

R1 R1 R F

v0

vin

R1 R1 R F

v0

A0 =

v0 v in

vf = Substituting this value, we get,

or closed loop voltage gain,

=

R1 R F R1

A0 = 1

or

RF R1

... (10.22)

Input Impedance Input impedance for this type of circuit is given as, Ri = Rin (1 + Ad )

... (10.23)

Where is feedback circuit gain and given by : =

R1 R1 R F

... (10.24)

? 1. Which type of feedback is used in non-inverting amplifier configuration ? 2. At which terminal, a part of output is feedback ? 3. What is bootstrapping ? How is it comes into non-inverting amplifier ? 4. What is virtual short ? 5. What is the significance of virtual short in non-inverting configuration ? 6. What is the basic difference between inverting and non-inverting amplifiers ?

419

OPERATIONAL AMPLIFIERS 7. Sketch the properties of an ideal OP-AMP.

(U.P. Tech. 2003-2004)

8. With a neat circuit diagram, explain the operation of an adder using an ideal OP-AMP. 9. Draw the circuit of an OP-AMP voltage follower and find an expression for

v0 . vi

10. Explain the following terms in connection with an OP-AMP : (i ) Input offset voltage. (ii ) Bias current. (iii ) Slew rate. 11. What will happen if RF is made zero in non-inverting amplifier ? 12. What is the effect of feedback at the input impedance of non-inverting amplifier ? 13. Give the formula for voltage gain of non-inverting amplifier. 14. What is the phase relationship between the input, output and feedback voltages in noninverting amplifier configuration ?

Example 1. Consider the circuit of Fig. 10.8. What output voltage results in the circuit for an input voltage of 0.25 V, if R1 = 15 k and RF = 450 k ? Solution : Given for a non-inverting amplifier : R1 = 15 k RF = 450 k vin = 0.25 V

and

v0 = ? We have, v0 = A0 vin where,

A0 = 1

so,

v0 =

RF R1

FG1 H

RF R1

IJ v K

FH1

450 15

in

Substituting the values, we get, v0 =

v0 = 7.75 volts.

IK

( 0.25) Ans.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Example 2. Design a circuit based on the topology of the non-inverting amplifier to obtain a gain of + 1.5 V/V, using only 10 k resistors. Solution : Given for a non-inverting amplifier, Desired closed loop gain, Available value of resistors,

A0 = + 1.5 V/V R = 10 k R1 = ? RF = ?

We have,

A0 =

FG1 H

1.5 = 1

RF R1

RF R1

IJ K

RF R1

= 0.5

This relation of R1 and RF can be implemented in two ways, these are described below. (i)

RF = 0.5 R1

If

R1 = R = 10 k.

Then,

RF = 0.5 R1 RF = 5 k. RF = R

i.e.,

Ans.

Ans.

R

The circuit diagram for this configuration is shown in Fig. P (10.2). vin

v1

+

OP-AMP v2

v0

– 10 k

10 k RF

R1

Fig. P (10.2).

10 k

421

OPERATIONAL AMPLIFIERS

(ii)

R1 = 2 RF

Now, If

RF = 10 k.

Then,

R1 = 2 RF

Ans.

= 2R = R + R

Ans.

R1 = 20 k.

The circuit diagram for this configuration is shown in Fig. P (10.3). vin

+

v1

OP-AMP v2

v0

–

RF

10 k

10 k R1 10 k

Fig. P (10.3).

Example 3. Design a non-inverting amplifier circuit that is capable of providing a voltage gain of 10. Assume an ideal op-amp. (Resistor should not exceed 30 k ) Solution : Desired closed loop gain of non-inverting amplifier, A0 = 10 R1 = ? RF = ?

or or

FG1 H

We know that,

A0 =

10 = 1

RF R1

= 9

RF = 9 R1

RF R1

RF R1

IJ K

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BASIC ELECTRONICS ENGINEERING & DEVICES

Now, according to the given condition, maximum value of resistor should not exceed 30 k. According to above relation between RF and R1, we can select 27 k resistor for RF , i.e., Ans.

RF = 27 k.

27 9

and

R1 =

or

R1 = 3 k.

Ans.

Circuit diagram is shown in Fig. P (10.4). vin

v1

+ OP-AMP

v0

v2 –

RF = 27 k R1 = 3 k

Fig. P (10.4).

From the analysis of non-inverting amplifier, with feedback, we can conclude that non-inverting amplifier is perfect voltage amplifier, because it has stable and controllable voltage gain, very high input resistance, very low output resistance and large bandwidth. Consider, here, the gain formula for non-inverting amplifier from eqn. (10.22), i.e., A0 = 1

RF R1

From this eqn., we see that minimum constant gain that can be obtained using non-inverting configuration is unity, which can be obtained, simply by making RF = 0 and R1 = in Fig. 10.8, i.e., For

RF = 0 and R1 = A0 = 1

... (10.25)

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OPERATIONAL AMPLIFIERS

The circuit diagram of unity gain amplifier configuration is drawn in Fig. 10.8. v1

vin

+ OP-AMP

v0

v2 –

Fig. 10.8. Unity gain amplifier.

From eqn. (10.25) and Fig. 10.8, it reveals that in this circuit, output voltage is equal to input voltage and both are in phase, therefore, this configuration is often called as op-amp voltage follower amplifier. Here all voltage is feedback to the inverting input, therefore, negative feedback is maximum and the circuit is very close to ideal. The main application of this configuration is as a non-inverting buffer. When it is placed between two networks, it removes the loading on the first network, as it has very high input impedance and very low output impedance, just like a emitter follower, but better than that.

This configuration is an inverting amplifier but gain of the circuit is made unity RF = R1

R1 vin

– OP-AMP

v0

+

Fig. 10.9. Inverter or sign changer.

by selecting precisely equal resistors R1 and RF = R1. This selection makes gain unity which produces output voltage, equal in magnitude but 180 out of phase with respect to input voltage, i.e., the closed loop gain of inverter circuit is, A0 = 1

... (10.26)

Both the configurations of op-amp, i.e., inverting and non-inverting with feedback, can be used as scale changer or constant gain multiplier. In this configuration, when

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BASIC ELECTRONICS ENGINEERING & DEVICES

we apply an input voltage to the amplifier, we get scaled voltage at the output. For this purpose, we select the values of R1 and RF such that the ratio of these two, i.e.,

RF , R1

is an integer constant, say, ‘n’. When we take,

RF R1

= n

We have, for inverting amplifier, A0 =

RF R1

= n

v0 = n vin

i.e.,

... (10.27)

and for non-inverting amplifier,

RF = (n + 1) R1

A0 = 1

v0 = (n + 1) vin

i.e.,

... (10.28)

In this application, R1 and RF are selected as precision resistors. Whenever, we need to combine two or more analog signals into a single output, we use summing amplifier or adder.

Inverting Configuration The inverting configuration of a summing amplifier or adder is shown in Fig. 10.10. Only three input voltages are shown here for simplicity, but we can have as many inputs as needed for the application. In Fig. 10.10, three input voltages va, vb and vc are connected at the inverting terminal through the resistors R1, R2 and R3 respectively. The operation of circuit can be verified by the mathematical expression of v0. The expression of v0 can be obtained from Kirchhoff’s current law, written at inverting node and applying virtual ground concept, we get, ia + ib + ic as iB

0 Amp and v1 = v2

... (10.29)

iF

0 V.

Therefore,

va vb R1 R2 or

vc R3

=

v0 RF

v0 =

FG R HR

F 1

va

RF R v F v R2 b R3 c

IJ K

... (10.30)

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OPERATIONAL AMPLIFIERS

i1

R1

i2

R2

i3

R3

va vb vc

iF

v2

RF

– OP-AMP

v1

v0

+

Fig. 10.10. Summing amplifier (adder).

This expression can also be verified using superposition theorem. If we take, R1 = R2 = R3 = R, then eqn. (10.30) reduces to, v0 =

RF va vb vc R

... (10.31)

Note that, in eqn. (10.31) output voltage is proportional to the sum of input voltage. Obviously, when gain of circuit is 1, i.e., R = RF , the output voltage v0 is equal to the negative sum of input voltages, i.e., v0 = (va + vb + vc )

... (10.32)

Non-Inverting Configuration The non-inverting configuration can also be used as the summing amplifier if the input voltages to be added and corresponding resistors are connected at the noninverting input terminals and selecting appropriate value of RF and R1 as shown in Fig. 10.11. Here, all the resistors connected with input voltages are taken equal, i.e., Ra = Rb = Rc = R. Since, virtual ground concept is not applicable in non-inverting configuration due to the feedback at the inverting terminal, the expression for output voltage v0 can be obtained using superposition theorem, i.e., by adding the output voltages, produced by the individual voltage when others are grounded.

426

BASIC ELECTRONICS ENGINEERING & DEVICES R va R

v1

vb

+

R vc

v0

OP-AMP v2

– RF

R1

Fig. 10.11. Non-inverting summer.

First, consider only the voltage va, applied at the non-inverting input terminal and making vb = vc = 0, then the equivalent circuit can be redrawn as shown in Fig. 10.12. Here, the resistances which were connected with vb and vc and now in parallel and making the voltage divider network with the resistance connected with va. R

v1

va

+ v0a

OP-AMP R

R

v2

– RF

vb = 0

vc = 0 R1

Fig. 10.12.

From Fig. 10.12, the voltage at non-inverting terminal is, v1 = v a

v1 =

R R R R R

R 2 va RR 2

... (10.33)

427

OPERATIONAL AMPLIFIERS

Now, from eqn. (10.22), v0

a

=

FG1 H

RF R1

IJ FG R 2 IJ v K H R R 2K

... (10.33a)

a

Similarly, we can obtain the expression for the output voltage, v0 and v0 for the b c inputs vb and vc respectively, i.e., v0

and

b

=

v0 = c

FG1 H FG1 H

RF R1

RF R1

IJ K IJ K

FG R 2 IJ v H R R 2K FG R 2 IJ v H R R 2K

b

... (10.34)

c

... (10.35)

By superposition principle, we can write, v0 = v0 + v0 + v0 a

=

v0 =

if the gain, i.e.,

FG1 H

RF R1

IJ K

FG1 H FG1 H

b

RF R1

RF R1

IJ K IJ K

c

FG R 2 IJ av H R R 2K FH 1 IK av 3

a

a

vb vc

vb vc

f

f ... (10.36)

is made unity, the amplifier of Fig. 10.11 can be used as

an averaging circuit, i.e., eqn. (10.36) reduces to, v0 =

Fv H

a

vb vc 3

I K

... (10.37)

and if the value of the gain of non-inverting amplifier is made equal to the number of inputs, then the circuit works as the summer or adder circuit, i.e.,

FG1 H

if,

RF R1

IJ K

= n = 3 (Here)

We get,

v0 = va + vb + vc

... (10.38)

Note that no sign change or phase reversal occurs between inputs and output.

The subtractor circuit can be implemented by using op-amp differential configuration, i.e., by applying the voltages, to be subtracted, at the both (inverting and non-inverting) terminals simultaneously. Such a simple configuration is shown in Fig. 10.13.

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BASIC ELECTRONICS ENGINEERING & DEVICES R

R va

– OP-AMP

v0 = (vb – va)

R vb

+

R

Fig. 10.13. Subtractor.

It can be shown easily by superposition principle, for the circuit of Fig. 10.13, that v0 = vb va

... (10.39)

If we place a capacitor C in the feedback path and a resistor R1 in the input path, the circuit realizes the mathematical operation of integration and hence known as integrator circuit. This is also known as Miller integrator, after its inventor and shown in Fig. 10.14. The integrator circuit is a non-linear application of op-amp. iF

R1

+

v2

vin (t)

vc – C

–

i1

OP-AMP v1

v0 (t)

+

Virtual ground

Fig. 10.14. Integrator circuit.

The function of integration using the circuit of Fig. 10.14 can be proved mathematically. Suppose that a time varying voltage vin (t) is applied at the input of circuit. Since, circuit is inverting type, we can use the concept of virtual ground to find the expression of output voltage. We can write, i1

iF

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OPERATIONAL AMPLIFIERS

That is, voltage vin (t) appears in effect across R1 and thus a time varying current i1 flows through the capacitor C, causing charge to accumulate on C. If we assume that the input is applied just at the time instant t = 0, then at an arbitrary time t current i1 will have deposited a charge equal to

z

t i 0 1

dt on capacitor C. If the initial voltage on

C (i.e., at t = 0, before applying the input) is vc (0), then voltage across C can be given as,

1 C

vC (t) = vC (0) + v0 (t) = vC (t)

but, and

i1 =

v in t R1

We have from eqn. (10.40), v0 (t) =

1 R1C

z

t

0

i1 dt

... (10.40)

(From the concept of virtual ground)

z z

t

0

v in t dt v C 0

... (10.41)

Here, vC (0) may be any constant value. If vC (0) = 0 V, then, v0 (t) =

1 R1C

t

0

v in t dt

... (10.42)

It is revealed from eqn. (10.42) that output is proportional to the integration of the input, where

1 is scale multiplier. R1C is known as time constant of the RC circuit, R1C

and hence of the integrator. Suppose a voltage of constant magnitude is applied to the circuit of Fig. 10.14, then the value of output can be calculated from eqn. (10.43) as,

vin (t) = K (constant)

From eqn. (10.43),

z

t

v0 =

1 R1C

v0 =

K t R1C

0

... (10.43)

k dt

... (10.44)

Therefore, output voltage is directly proportional to the time t, with scaling factor of

K , i.e., v0 linearly varies with time. Such an output is shown in Fig. 10.15 for R1C

a constant input voltage, K = 1 and R1C = 1 unit time. The output voltage is a ramp of slope

K which is 1 v/s here. It is an ideal case that if an input of constant R1C

magnitude (DC) is applied for infinite duration, output will tend to infinity, but such

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BASIC ELECTRONICS ENGINEERING & DEVICES

2 1

0

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

t

t

–1 –2 –3

–Kt R1C

–4 –5 –6

Fig. 10.15.

a case not possible practically. As described earlier too, the voltage can vary linearly only upto a certain permissible value, after that op-amp goes into saturation and a voltage of constant magnitude is appeared at the output terminal. It should be noted here that the product of R1C controlles the slope of the output, i.e., lower the product R1C, steeper will be the ramp voltage. For a sinusoidal input, output can be calculated as,

vin (t) = Vm sin (t)

v0 (t) =

1 R1C

=

Vm R1C

v0 (t) =

z

t

0

V m sin t

LM cos t OP N Q

t 0

Vm (cos t 1) R1C .

We clearly see here that output is 90 phase shifted to the input and integrated version of input.

431

OPERATIONAL AMPLIFIERS

If more than one inputs are applied at the input of integrator, Fig. 10.16, the output can be calculated by the superposition principle and given by eqn. (10.45), as, C Ra

va (t)

Rb

vb (t)

–

Rc

vc (t)

v0 (t)

OP-AMP +

Fig. 10.16.

v0 (t) =

LM 1 NR C a

z

v a t dt

z

1 Rb C

v b t dt

z

1 v c t dt Rc C

OP Q

... (10.45)

The main application of integrator circuit is in analog computers to solve the linear differential eqn.s with constant coefficients. This circuit is also used in Cathode Ray Oscilloscopes (CROs) as a sweep generator and known there as Miller sweep generator.

If the position of resistor and capacitor is interchanged in the circuit of Fig. 10.14 circuit performs another interesting mathematical function, i.e., differentiation and known as differentiator circuit. This is also a non-linear amplifier and shown in Fig. 10.17. RF

iF

C vin (t)

v2

–

i1 OP-AMP v1

+

Fig. 10.17.

Using the concept of virtual ground we can write, i1 where,

iF

i1 = Current through the capacitor = C

d v t dt in

v0 (t)

432

BASIC ELECTRONICS ENGINEERING & DEVICES

iF =

and

v 0 t RF

Now, substituting these values we have,

v 0 t d v t = C RF dt in v0 = R F C

i.e.,

d v in t dt

... (10.46)

Where, RFC is the time constant of differentiator circuit and RFC is known as scale factor. If a periodic square wave is applied, then to differentiate it RFC should be much less than the full cycle time, i.e., RFC > RL, if a load RL is connected, rce can be neglected. (g) Controlled current source (gm Vbe) : It represents the coupling between the junctions. Its value is proportional to the base current (I b) . gm is the transconductance of the transistor. The transconductance represents the small change in collector current about the operating point produced by the small changes in base emitter voltage. Hybrid- Parameter Values : The typical magnitudes for the elements of the hybrid- model at room temperature and for IC = 1.3 mA are given below : (i)

gm = 50 mA/V

(ii)

rbb = 100

(iii)

rbe = 1 K

(iv)

rbc = 4 M

(v)

rce = 80 K

(vi) Cbc = 3 pF (vii) Cbe = 100 pF Note : Relationship Between Low Frequency h-Parameters and High Frequency Parameters : (i)

where

gm =

VT =

IC VT

T with T in °K. 11,600

At room temperature (300°K), VT = 0.026 V so, we have gm =

b

I C in m A 26 m V

b g

g

479

HIGH FREQUENCY TRANSISTOR

h fe

(ii)

rbe =

(iii)

rbb = hie – rbe

(iv)

rbc =

1 r = be gb c hre

(v)

gce =

1 = hoe – (1 + hfe) gbc. rce

gm

T-model is a alternative of small-signal hybrid- model. Although the hybrid- model can be used to carry out small signal analysis of all transistor circuits, but there are some situations in which an alternative model shown in Fig. 11.14 is much more convenient. The model of Fig. 11.14 represents the BJT as a voltage controlled current source with the control voltage vbe. ib = ie – ic or

ib =

or

ib =

be

re be

re

C ic gm vbe B ib

+ vbe re –

ie

E

Fig. 11.14

– gm vbe (1 – gm re)

...(11.26)

From equation (11.26), we see clearly that the model yields the correct expressions for ic and ie.

In this article, let us demonstrate that all the resistive components in the hybrid- model can be obtained from the h-parameters in the CE configuration. (i) Transistor transconductance gm : Fig. 11.15 shows a p-n-p transistor in the CE configuration with the collector shorted to the emitter for time-varying signals. In the active region, the collector current is given by IC = ICO – 0 IE Now, since the short-circuit current gain given in Fig. 11.13 is gmVbe the transconductance gm is defined by : Ic rbb

Q

– +

Vcc

Fig. 11.15 Circuit diagram for evaluation of gm.

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BASIC ELECTRONICS ENGINEERING & DEVICES

gm = or

IC Vb e

gm = 0

= – 0 VCE constant

IE Vb e

I E VE

...(11.27)

In the above expression, we have assumed that 0 is independent of VE. If the emitter diode resistance is re, then re =

VE I E

...(11.27a)

Thus, using equation 11.27 (a), we have gm =

0 re

...(11.28)

Recall that the dynamic resistance of a forward-biased diode is given by re = where,

i.e.,

VT =

k.T q

re =

k.T IE . q

VT , IE

...(11.29)

Now, using equations, (11.27) and (11.28) we obtain gm =

0 IE . q I = 0 E k.T VT

In the above expression replacing 0 IE by ICO – IC, we get gm =

I CO I C VT

...(11.30)

Further, for a p-n-p transistor, IC is negative. For an n-p-n transistor, IC is positive, but the foregoing analysis (with VE = Vbe) leads to gm = (IC – ICO)/VT. This means that for either type of transistor, gm is positive. Since | IC | >> | ICO |, then gm is given by gm where

VT =

IC VT

...(11.31)

T . 11,600

It may be noted that gm is directly proportional to current and inversely proportional to temperature. At room temperature, we have gm = For

IC

amAf

26 mV

IC = 1.3 mA, gm = 0.05 mho = 50 mA/V.

481

HIGH FREQUENCY TRANSISTOR

IC = 10 mA, gm 384.6 mA/V.

For

These values are much larger than the transconductances obtained with FETs. (ii) The input conductance gbe : Fig. 11.16 (a) shows the hybrid- model valid at low frequencies, where all the capacitances are negligible. However, Fig. 11.16 (b) represents the same transistor, using the h-parameter equivalent circuit. lb

rbb

B

Vbe

rbe

E

C gmVbe

rce E

(a) lb

B

lc

rbc

B

lc

hie

C +

hreVce –

hfelb

E

(b)

hoe E

Fig. 11.16. (a) The hybrid model at low frequencies. (b) The h-parameter model at low frequencies.

As we have already observed that rbc >> rbe Hence, Ib flows into rbe and so Vbe Ib rbe The short-circuit collector current is given by IC = gm Vbe or

IC gm Ib rbe

...(11.32)

We know that the short-circuit current gain hfe is defined as hfe =

or

rbe =

IC Ib

= gm rbe VCE

h fe gm

Substituting the value of gm, we get rbe = or

gbe =

h fe VT IC

gm h fe

It may be noted that over the range of currents for which hfe remains fairly constant, rbe is directly proportional to temperature and inversely proportional to current.

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BASIC ELECTRONICS ENGINEERING & DEVICES

(iii) The feedback conductance gbc : With the input open-circuited, hre is defined as the reverse voltage gain, or from Fig. 11.16 (a) with Ib = 0, we have hfe = = or

Vb e Vce rbe rb e rb c

rbe (1 – hre) = hre rbc

Now, hre >|, the above equation may be put in the following form (Using equation (11.33)) gce hoe – gm hre

...(11.39)

483

HIGH FREQUENCY TRANSISTOR

Summary As a matter of fact, if the CE h-parameters at low frequencies are known at a given collector current IC, the conductances or resistances in the hybrid- circuit are calculable from the following five equations in the order given : (i) gm =

IC

(ii) rbe =

VT

(iii) rbb = hie – rbe

(iv) rbc =

(v) gce = hoe – (1 + hfe) gbc =

h fe gm

=

h fe VT IC

or gbe =

gm h fe

h rb e or gbc = re hre rb e

1 rce

The hybrid- model for a transistor shown in Fig. 11.13 (a) includes two capacitances. The collector junction capacitance Cbc is the measured CB output capacitance with the input open (IE = 0), and is usually specified by manufactures as Cbb. Since in the active region, the collector junction is reversed biased, then Cbc is the transition capacitance and varies as VCB–n, where n is 1/2 or 1/3 for an abrupt or graded junction, respectively. The capacitance Cbe represents the sum of the emitter diffusion capacitance CDe and the emitter junction capacitance CTe. For a forward biased emitter junction, CDe is usually much larger than CTe, and therefore, we have Cbe = CDe + CTe CDe

...(11.40)

We can show that Cbe

gm 2 fT

...(11.41)

Experimentaly, Cbe is determined from a measurement of f T, the frequency at which the CE short-circuit current gain drops to unity, which we will discuss later. Example 6. A BJT has following low frequency h-parameter as Ic = 5 mA, hie = 1k, hre = 10–4, hfe = 100, hoe = 4 10–5 mho. Calculate the resistive parameters of the hybrid– equivalent model. Solution : We know that (i) Substituting all the values, we get gm =

I c in mA 26

5 = 0.192 mho 26 (ii) Substituting all the values, we get gm =

rbe = rbe =

h fe gm 100 = 520.8 0.912

484

BASIC ELECTRONICS ENGINEERING & DEVICES

(iii) Substituting all the values, we get rbb = hie – rbe = 1000 – 520.8 = 479.17 (iv) Substituting all the values, we get rbc =

rb e hre

479.17 = 5.17 M. 10 4 (v) Substituting all the values, we get rbc =

gce = hoe – (1 + hfe) gbc

a

f

gce = 4 10 5 1 100

1 4.79 10 6

Solving, we get gce = 1.89 10–5 mho Therefore, rce = 1/gce =

1 = 52.87 k 1.89 10 5

Example 7. A BJT has hie = 6 k and hfe = 224 at Ic = 1 mA, with f T = 80 MHz and Cbc = 12 pF. Determine : (i) gm, (ii) rbe, (iii) rbb and (iv) Cbe at room temperature given that collector current is 1 mA. Solution :

gm =

a f

I c mA 26

Substituting all the values, we get = rbe =

1 = 38.46 mmho 26

h fe gm

Substituting all the values, we get rbe =

224 = 5.824 k = hie – rbe 38.46 10 3

Substituting all the values, we get = 6000 – 5824 = 176 Cbe =

gm – Cbc 2 fT

Substituting all the values, we get

38.46 10 3 12 10 12 76.5 10 12 12 10 12 2 80 10 6

or

Cbe =

Solving, we get

Cbe = 64.5 pF.

485

HIGH FREQUENCY TRANSISTOR

If the input voltage of an amplifier is kept constant but its frequency is varied, it is found that the amplifier gain : (i) remains practically constant over a sizeable range of mid-frequencies. (ii) decreases at low as well as at high frequencies. A typical frequency versus gain curve (frequency response) of an RC coupled amplifier is shown in Fig. 11.17. AV AVm 0.707 AVm

3dB

A

B

Gain

Passband

0

f1

Frequency

f

f2

Fig. 11.17. Variations in amplifier gain with frequency.

Thus, in frequency response curve, three values of frequency are important : (i) mid-frequency range. (ii) lower cut-off frequency, f 1. (iii) upper cut-off frequency, f 2.

Let us consider a single-stage CE transistor amplifier, or the last stage of a cascade. The load resistor RL on this stage is the collector-circuit resistor, so that R C = RL In this section, let us assume that RL = 0, whereas the circuit with RL = 0 is analyzed in the next article. To obtain the frequency response of the transistor amplifier, we shall use the hybrid- model as shown in Fig. 11.18.

+

B

rbb

B

gbc

C IL

Cbe Vbe –

E

gbe

Cbe

gce

g 1/rbe m Vbe

RL

+

Vce

E

–

Fig. 11.18. The hybrid- circuit for a single transistor with a resistive load RL.

The approximate equivalent circuit from which to calculate the short-circuit current gain has been shown in Fig. 11.19. Here, a current source furnishes a sinusoidal input current of magnitude Ii, and the load current is IL.

486

gbe.

BASIC ELECTRONICS ENGINEERING & DEVICES

We have neglected gbc, which should appear across terminals BC, because gbc >>

Further, gce disappears, because it is in shunt with a short-circuit. An additional approximation is also involved, in that we have neglected the current delivered directly to the output through gbc and Cbc. Ii

gbe

B

C

gm hfe

Cbe + Cbc

gmVbe

E

IL

E

Fig. 11.19. Approximate equivalent circuit for the calculation of the short-circuit CE current gain.

From Fig. 11.19 we observe that the load current is given by IL = – gm Vbe where

Vbe =

...(11.42)

Ii gb e j C b e C b c

b

g

...(11.43)

The current amplification under short-circuited conditions is given by

or,

Ai =

IL Ii

Ai =

gm gb e j C b e C b c

b

g

...(11.44)

Now, using the result given in ‘summary’, we have Ai =

or

| Ai | =

h fe

d

i j f f

i

h fe

LM1 d f f i OP N Q

2 1/ 2

where,

f =

gb e 2 C b e C b c

or

f =

1 gm . h fe 2 C be C b c

or

f =

b

g

...(11.45)

b

2rb e

Note : At f = f , | Ai | is equal to

b

1 C b e C b c

g

g ...(11.46)

1 = 0.707 of its low-frequency value hfe. The frequency 2

487

HIGH FREQUENCY TRANSISTOR

range upto f is referred to as the bandwidth of the circuit. f is the frequency at which a transistor’s CE short-circuit current gain drops 3-dB from its value at lower (mid) frequencies. Further, f represents the maximum attainable bandwidth for the current gain of a CE amplifier with a given transistor.

A CB amplifier has much higher 3-dB frequency than a CE amplifier. The shortcircuit current gain for CB amplifier which can be derived from the approximate high frequency circuit of the CB amplifier with output shorted is given by : | Ai | =

h fb

IL = Ii

FfI 1 j G J Hf K

...(11.47)

where,

f =

2 rb e

h fe 1 2 rb e C b e 1 h fb C b e

d

...(11.48)

i

Now, substituting equation (11.46) in equation (11.48), we get f =

b

h fe f C b e C bc

g

...(11.49)

C b e

f is the (alpha) cut-off frequency at which the CB short-circuit small signal forward-current transfer ratio (Ai) drops 3-dB from its value at low frequencies ( 1 kHz). Fig. 11.20 shows the variation of Ai with frequency for CE and CB amplifiers and f and f . A 100

(Common-emitter)

hfe 0.707 hfe 10 hfb1 0.707 hfb

Gain-bandwidth product

Cut off

Cut-off (Common-base)

0.1 10

2

3

10

4

5

10

6

10 10 f

7

fT

Frequency in Hz

8

10

10 f

Fig. 11.20. Variations of Ai with frequency for CE and CB amplifiers.

We know that f T which is defined as the frequency at which the short-circuit common-emitter current gain attains unit magnitude. We know that the magnitude of CE short-circuit current gain is given by | Ai | =

h fe

LM1 d f / f i OP N Q g = 2 bC C g

...(11.50)

2 1/ 2

where,

f

b e

b e

bc

=

1 gm . h fe 2 C be C b c

b

g

...(11.51)

488

BASIC ELECTRONICS ENGINEERING & DEVICES

Here, let us substitute at

f = f T, | Ai | = 1 in equation (11.50) then, 1 =

h fe

LM1 e f / f j OP N Q

2 1/ 2

2

T

>> 1

h 2fe

therefore,

h 2fe = 1 + (f T / f )2

T

Ff I GH f JK

or

Ff I G J Hf K

2

T

f T hfe f

or

...(11.52)

Now, using equation (11.52), we get f T hfe .

fT

or

b

1 gm . h fe 2 C be C b c

b

gm

2 C b e C b c

g ...(11.53)

g

Further, since Cbe >> Cbc, therefore, we shall have

gm f T 2C b e Hence, from expression, Ai =

Ai

we get

...(11.54)

h fe

d i

1 j f / f h fe

b

1 jh fe f / fT

...(11.55)

g

This equation shows the dependence of transistor’s short-circuit gain on the transistor’s gain at low frequencies “hfe” and the high frequency characteristics “f T”. fTMHz 400

VCE = 5V T = 25ºC

300

Ai (dB) = 20 log |Ai| 3 dB = 20 log hfe

200

6 dB/octava = 20 dB/decade

100 10 100 Ic (log scale), mA

Fig. 11.21

Log f

Fig. 11.22

Log fT log f

489

HIGH FREQUENCY TRANSISTOR

Now, let us note few points from the above Figs. 11.21 and 11.22. (i) The parameter f T is an important high frequency characteristic of a transistor. Like other transistor parameters, its value depends, upon the operating conditions of the device. Typically, the dependence of f T on collector current is as shown in Fig. 11.21. (ii) Since f T hfe . f , this parameter may be given a second interpretation. It represents the short-circuit current-gain-bandwidth product. This means that for the CE configuration with the output shorted, f T is the product of the low-frequency current gain and the upper 3-dB frequency. (iii) From equation 11.54, it may be noted that there is a sense in which gain may be sacrificed for bandwidth and vice-versa. Thus, if two transistors are available with equal f T, the transistor with lower hfe will have a corresponding larger bandwidth. (iv) In Fig. 11.22 Ai expressed in decibels (i.e., 20 log | Ai |) is plotted against frequency on a logarithmic frequency scale. When f > f , | Ai | hfe f / f = f T / f.

So that

Ai (dB) = 20 log f T – 20 log f

Accordingly,

Ai (dB) = 0 dB at f = f T

Also for

f >> f

the plot approaches as an asymptote a straight line passing through the point (f T, 0) and having a slope which causes a decrease in Ai (dB) of 6-dB per octave (f is multiplied by a factor of 2, and 20 log2 = 6-dB), or 20-dB per decade. Further, the intersection of the two asymptotes occurs at the “corner” frequency f = f , where Ai is down by 3-dB. Hence, f is also known as the 3-dB frequency. Example 8. A BJT has gm = 38 mmhos, rbe = 5.9 k, hie = 6 k, rbb = 100 , Cbc = 12 pF, Cbe = 63 pF and hfe = 224 at 1 kHz. Calculate and cut-off frequencies and f T. Solution : We know that f

h fe 2 rb e C b e

Substituting all the values, we get f =

Again, we have

f =

224 = 95.9 MHz 2 5.9 10 3 63 10 12

2rb e

b

1 C b e C b c

g

490

BASIC ELECTRONICS ENGINEERING & DEVICES

We know that

f =

Further, we know that f T =

1 2 5.9 10 63 10 12 12 10 12

d

3

gm 2 C b e C b c

b

i = 0.359 MHz

g

Substituting all the values, we get fT =

38 10 3 2 63 10 12 12 10 12

d

i = 80.63 MHz

With a resistive load connected in the output, the high frequency equivalent circuit of a CE transistor amplifier has been shown in Fig. 11.23. By using Miller’s theorem the circuit of Fig. 11.24 can be modified as described below : rbb

Cbc

B

B

C

+ rbe

Vbe

Cbe gm Vbe

RL VCE

–

E

E

Fig. 11.23. High frequency equivalent circuit with resistive load.

Miller’s Theorem Miller’s theorem states that if an impedance Z is connected between the input and output terminals of a network which provides a voltage gain. A i an equivalent circuit that gives the same effect can be drawn by removing Z and connecting as impedance Zi =

Z ZA across the input and Zo = across the output as shown in 1 A A 1

Fig. 11.24. Z +

+

+

V1

V2

V1

–

–

–

+ Z 1– A

Fig. 11.24. Miller’s theorem.

From Fig. 11.23, the voltage gain will be A=

gm Vb e R L VCE = Vb e Vb e

ZA A –1

V2 –

491

HIGH FREQUENCY TRANSISTOR

A = – gm RL

or or

1 – A = 1 – (– gm RL) = 1 + gm RL

Since the impedance at the input gets decreased by a factor of (1 – A), therefore, the capacitance will be increased by a factor of (1 – A) or 1 + gm RL. The capacitance that is to be included in the output circuit will not make any significant change in the performance and may be neglected. This results in the modified equivalent circuit of Fig. 11.25. The total input capacitance between B and E is rbb

Cbc

B + rbe

Vbe

Cbe

–

E

C Cbc (1 + gm.R.)

B

gmVbe

RLVCE

E

Fig. 11.25. Modified equivalent circuit.

C = Cbe + (1 + gm RL) Cbc

...(11.56)

If the effect of source resistance Rs is also taken into account, the upper 3-dB frequency f 2 is given by f2 = where R = (Rs + rbb) || rbe =

1 2R C

bR

s

...(11.57)

g

rbb rb e

R s rbb rb e

=

bR

s

g

rbb rb e

R s hie

and C is the total input capacitance given by C = Cbe + (1 + gm RL) Cbc If the effect of biasing resistors R1 and R2 are also taken into account, then R =

bR r g r s

bb

be

R s hie

where

R s = Rs || RB

and

RB = R1 || R2.

Thus, the source and biasing resistors have a strong influence in determining the upper 3-dB frequency f 2. Example 9. A BJT has the following parameters at an operating. Current of Ic = 2.6 mA f T = 500 MHz, rbe = 1 k, rbb = 100 , Cc = 3F. Find the values of gm . Ce ; and for the BJT.

492

BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : We know that, (i)

gm =

I c in mA mho 26

Substituting all the values, we get = (ii) Also,

2.6 = 0.1 mho 26

hfe = gm rbe = 0.1 1 103 = 100.

(iii) Again, We know that Cbe =

gm – Cbc 2 fT

Substituting all the values, we get =

0.1 3 10 12 Farad 2 500 10 6

FG 0.1 10 H 2 500 10 12

IJ K

3

or

Cbe =

or

Cbe = 31.82 – 3 = 28.82 pF. Ans.

6

pF

Example 10. A BJT has the following CE h-parameters hie = 1100 , hre = 2.5 10–4, hfe = 50, hoe = 2.5 10–5 mho (i) Determine the h-parameters for the CC and CB configurations. (ii) Assuming base-spreading resistance value as 100 estimate the resistance hybrid- parameters. Solution : (i) From table, we have the CC h-parameters of the BJT expressed as under : hic = hie = 1100 hrc = 1 – hre = 1 – 2.5 10–4 1. hfc = – (1 + hf e) = – (1 + 50) = – 51, and hoc = hoe = 2.5 105 mho. Similarly, the CB h-parameters of the BJT are expressed the following relations : hIb =

Also, hrb =

hie 1100 = = 21.57 1 h fe 1 50 hie hoe – hre 1 h fe

Substituting all the values, we get hrb =

1100 2.5 10 5 2.5 10 4 1 50

493

HIGH FREQUENCY TRANSISTOR

hrb = 53.92 10–5 – 2.5 10–5

Simplifying, we get

hrb = 28.92 10–5 = 2.9 10–4 Again,

hob =

hoe 2.5 10 5 = 1 h fe 1 50

= 0.5 10–6 mho. (ii) The hybrid- parameters of the BJT can be obtained by using following formula of conversion i.e., rbe = hie – rbb = 1100 – 100 = 1000 = 1 k rbe =

hie rbb 1100 100 = (400 104) = 4 M hre 2.5 10 4

h fe

50 = 0.05 mho 1100 100

We know that

gm =

Also,

h fe hre 1 = hoe – rce hie rbb

hie rbb

Substituting all the values, we get

1 50 2.5 10 4 = 2.5 10 5 rce 1100 100 or

1 = 2.5 10–5 – 1.25 10–5 = 1.25 10–5 mho rce

or

1 1 = = 0.8 105 =80 k. Ans. rce 1.25 10 5

Example 11. For a BJT, hie = 500 , hfe = 100 mA, VCE = 10 V, and room temperature of 27°C. The BJT has f T = 50 MHz and Cbc = 3F. Calculate all the parameters of the hybrid- model of the BJT. (Given Ic = 10 mA) Solution : We know that (i)

gm =

I c in mA , mho 26

Substituting all the values, we get gm = (ii) and

rbe =

(iii) Also,

rbc =

10 = 0.385 mho. 26

h fe gm

=

100 = 260 0.385

hie rbb r = be hre hre

494

BASIC ELECTRONICS ENGINEERING & DEVICES

Substituting all the values, we get = (iv)

1 ro

= hoe –

h fe hre hie rbb

260 = 2.6 M 10 4 = 4 10 5

100 10 4 260

Solving, we get

1 = 0.154 10–5 mho ro

or

ro = 6.5 105 = 650 k.

(v) Now Cbc = measured CB output capacitance with the input open (I E = O), specified by the manufacturer = 3pF. (vi) Again,

Cbe =

FG g H 2 f m

T

Cbc

IJ K

Substituting all the values, we get Cbe =

0.385 ‘– 3’ = 1224 pF – 3pF 2 50 10 6

Solving, we get Cbe = 1221 pF. Example 12. Given the following parameters for a given transistor at Ic = 10 mA, VCE = 10 V and the room temperature : hfe = 100 ; hie = 500 ; | Ai | = 10 at 10 MHz, and Cc = 3pF. Find F , FT, Ce, rbe and rbb. Solution : We know that, gm =

h fe

100 = 260 . Ans. 384.6 10 3

Also,

rbe =

We know that

rbb = hie – rbe = 500 – 260 = 240 . Ans.

gm

=

IC 10 m A = = 384.6 mS VT 0.026

FT = | Ai | f = 10 10 = 100 MHz. Ans. We know that,

f =

Cbe =

fT f 100 = T = = 1 MHz. Ans. hie 100 gm 384.6 10 3 3 10 12 = 609 pF. Ans. C b c = 2 fT 2 100 10 6

Example 13. A BJT is found to have fT = 500 MHz, hfe = 100, rbb = 100 , rbe = 900 and Cbc = 5 pF. It is used as a CE amplifier with Rs = 1 k and RL = 500 . Determine for the amplifier.

(i) Mid band voltage gain AVs =

Vo and (ii) The upper 3-db cut-off frequency f . Vs

495

HIGH FREQUENCY TRANSISTOR

Solution : We know that Since

gm =

h fe rb e

Substituting all the values, we get

100 1 S 900 9 Midband voltage gain will be given by gm =

AV =

g V R Vce 1 = m b e L = – gm RL = 500 = – 55.55 Vb e Vb e 9

(i) Midband voltage gain taking RS into account AVs =

A V rb e 55.55 900 = = – 25. Ans. R s rbb rb e 1000 100 900

(ii) Upper 3-db cut-off frequency, fB =

fT 500 = = 5 MHz. Ans. h fe 100

The model discussed up to were hybrid- and T model excluding capacitive effects. Now we will discuss the hybrid- model of BJT, including capacitive effects, as shown in Fig. 11.26 specifically, there are two capacitances namely. (i) the emitter-base capacitance, C = Cde + Cje and (ii) the collector-base capacitance, C. Typically, C is in the range of a fraction of Pf (picofarad) to a few Pf, and C is in the range of a few Pf to a few tenth of Pf. It may be noted from the Fig. 11.26 that we have omitted the resistance r because, even at moderate frequencies, the reactance C is much smaller than r, we have, however, added a resistor rx to model. C

B

rx

r

+ V

C

C

gmV

ro

–

Fig. 11.26

The resistance of the silicon material of the base region between the base terminal B and a fictitious internal, or intrinsic, base terminal B. Typically, rx is a few tenth of ohms, and its value depends on the current level in a rather complicated manner. Since r >> rx, so effect of rx is negligible at low frequencies. However at high frequencies effect of rx can’t be neglected, because rx play an important role in determining the frequency

496

BASIC ELECTRONICS ENGINEERING & DEVICES

response of transistor circuit. It follows that an accurate determination of rx should be made from a high frequency measurement.

The transistor data sheets do not usually specify the value of C . Rather, the behaviour of or hfe versus frequency is normally given. In order to C determine and C we shall derive an expression for hfe as a function of frequency in terms of the hybrid- components. For this purpose consider the circuit shown in Fig. 11.27 in which the collector is shorted to the emitter, the short-circuit collector current I c is Ic = (gm – sC) V Ib

Vb

+ V

Ic = (gm – sC)V

sCV

B r

...(11.58)

C r

C

C

gmV

ro

– E

E

Fig. 11.27

A relationship between V and Ib can be established by multiplying I b by the impedance seen between B and E : V = Ib (r || C || C)

...(11.59)

Thus, hfe can be obtained by combining equations (11.58) and (11.59) hfe =

gm s C Ic = 1 Ib s C C r

d

i

At the frequencies for which this model is valid, gm >> C, resulting in hfe

Thus,

hfe

gm . r

d

i

1 s C C r 0

d

i

1 s C C r

( gm r = 0)

...(11.60)

where 0 is the low-frequency value of . Thus hfe has a single pole response with a 3-dB frequency at = , where =

dC

1

i

C r

...(11.61)

Fig. 11.28 shows a Bode plot for [hfe] from the – 6dB/octave slope it follows that the frequency at which | hfe | drops to unity, which is called the unity-gain bandwidth T is given by T = 0

497

HIGH FREQUENCY TRANSISTOR

T =

Thus, and

fT =

gm C C

d

gm

2 C C

...(11.62)

i

The unity-gain bandwidth f T is usually specified on the data sheets of the transistor. In some cases f T is given as a function of IC and VCE. To see how f T changes with IC, recall that gm is directly proportional to ic but only part of C (the diffusion capacitance Cde) is directly proportional to IC. It follows that f T decreases at low currents as shown in Fig. 11.28. However, the decrease in f T at high currents, also shown in Fig. 11.29 cannot be explained by this argument ; rather it due to the same phenomenon that 0 causes to decrease at high currents. In the region where f T is almost constant, C is dominated by the diffusion part. |hfe| (dB)

fT 3-dB

o

-6 dB/octave

0 dB

w

wT

Ic

w(loq scale)

Fig. 11.28. Bode plot for |hfe|.

Fig. 11.29. Variation of f T with IC.

Typically, f T is in the range of 100 MHz. The value of f T can be used in equation (11.62) to determine C + C. The capacitance C is usually determined separately by measuring the capacitance between base and collector at the desired reverse-bias voltage.

Summary 1. General H–Parameter equations. V1 = h11i1 + h12 V2 i2 = h21i1 + h22V2 2. S. No.

h-Parameter

Meaning

Condition

In general

CE

CB

CC

h-Parameter 1.

h11 =

Vi i1

2.

h21 =

3. 4.

Input impedance

Output short Circuited

hi

hie

hib

hic

V1 V2

Forward current gain

Output short Circuited

hf

hfe

hfb

hfe

h12 =

i2 i1

Input open circuited

hr

hre

hrb

hre

h22 =

i2 V2

Reverse voltage gain Output admittance

Input open circuited

ho

hoe

hob

hoe

498

BASIC ELECTRONICS ENGINEERING & DEVICES 3. Transistor Amplifier using h-Parameters (i) Current gain : Ai =

hf 1 h0 R L

(ii) Input Resistance : Ri = hi

(iii) Voltage gain : Av =

hr h f

bY

hf RL

+

b

g

where hiho – hrhf = h

hi hR L

(iv) Power gain : Ap =

h0

L

h 2f R L hi hR L 1 h0 R L

gb

bR

g

hi h h0 R s

(v) Output Resistance : Ro =

s

FG Z IJ HZ R K F R IJ = – A G HR Z K i

(vi) Overall voltage gain : Avs = Av

i

(vii) Overall current gain : Ais

g

s

s

i

s

i

4. T-Model : T-Model is a alternative of small signal hybrid- model. ib =

Vbe (1 – gmre) re

5. hybrid- conductances. (i) Transistor trans-conductance gm gm =

I co I c VT

(ii) gm is directly proportional to current and inversely proportional to temperature. (iii) At room temperature. gm =

amAf

Ic

26

(iv) The i/P conductance (gbe) gbe =

gm h fe

(v) The feed back conductance (gbc) gbc = hre gbe (vi) The base-spreading resistance (rbb) rbb = hie – rbe

499

HIGH FREQUENCY TRANSISTOR (vii) The output conductance (gce) gce = hoe – gmhre 6. The Hybrid- copacitancesCbe = CDe + CTe CDe Cbe

or

gm 2fT

7. When the input voltage of an amplifier is kept constant but it’s frequency is varied. The amplifier gain(i) Remains practically constant over a sizeable range of mid-frequencies. (ii) Decreases at low as well as at high frequencies. 8. The maximum attainable band width for the current gain of a CE Amp r. f =

c

1

2rb e Cb e Cb c

h

9. -cut off frequency f = 10.

c

h fe f Cb e Cb c

h

Cb e

f T hfe f

11. Unity gain band width fT =

d

gm

2 C C

i

? 1. Define hybrid Parameter’s and calculate the h-parameters for the given two-part system. + V1 –

I1

I2 Linear Circuit

+ V2 –

2. Draw the hybrid equivalent ckt of CB, CC and CE configuration and write their h-parameter equation. 3. Why the name hybrid parameter was given to a set of parameters of BJT. Find out the expression of current gain and voltage gain using h-parameter of a transistor amplifier. 4. Explain the high frequency parameters of hybrid- model. 5. Draw the small signal hybrid model at high frequency. Explain the complete mode prove that hfe = gmrbe. 6.

(a) Explain hybrid capacitances. (b) Define f , f T and derive the relationship between f and f T.

500

BASIC ELECTRONICS ENGINEERING & DEVICES 7. Explain the miller’s theorem. 8. Explain the frequency response of an amplifier

Example 1. Find Ic and VcE for the following Fig. of Si transistor. 9V 200 K

1K hic = 2K, hfe = 100 hoe = 0, hre = 0

100 K

1K

Fig. P (11.1)

Solution : (i)

R =

200 100 = 66.6 K 300

V =

9 100 = 3V 300 9V 1K R V

1K

Fig. P (11.2)

V = Rib + VBE + 1 k ib (hfe + 1) 3 – 0.7 = ib (66.67 + 101) ib =

2.3 = 13 Amp. 167.67

ic = ib 100 = 1.3 mA Ans. (ii)

Vcc = icRc + VCE + Reib (hfe + 1) 9 = 1.3 + VCE + 1.301 VCE = (9 – 2.6) = 6.4 V Ans.

Example 2. A CE amplifier has RL = 10 k ohms. Given hie = 1 k ohm, hfe = 50, hre = 0, 1/hoe = 40 k. The voltage gain AV is. Solution : We know that voltage gain in the case of CE amplifier

501

HIGH FREQUENCY TRANSISTOR

Av = A i

ZL Zi

Where Ai = current gain

ZL = RL = 10 k Zi = input impedance Ai = or

h fe 1 hoe Z L

Ai = –

Ai =

50 10 10 3 1 40 10 3

50 = – 40 1 2.5

Zi = hie or

h fe. hre YL hoe

Zi = 1 103

where YL =

10

4

1 1 = = 1 10–4 ZL 10 10 3

50 0 1 10 3 40

Zi = (10)3 = 103 Now,

Av =

40 10 10 3 10 3

Av = – 400 Ans. Example 3. In the common emitter amplifier with RL = 4000, given hfe = 100, hoe =

1 , hie = 1000, the current gain |Ai|, is given by 36 10 3 Solution : |Ai| =

h fe 1 hoe .R L

=

100 100 = 400 1 1 1 36 10 3 9

|Ai| = 90 Ans. Example 4. In an emitter follower with RL = 10 k, given hfe = 99, hoe = hie = 1 k the values of current gain and input resistance are given by. Solution :

Ai = |Ai| =

h fe 1 hoe .R L 99 1 1 10 3 10 10 3 40

F 1 I 10 H 40 K

–3,

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BASIC ELECTRONICS ENGINEERING & DEVICES

=

99 10 1 40

|Ai| = 79.2 |Ai| 80 Ri = hie + Ai hre RL Ri = 1 k + 80 1 10 k Ri 800 k Ans. Example 5. The transistor in the amplifier shown has following parameters : hfe = 100, hie = 2 k, hre = 0, hoe= 0.05 m mhos, C is very large. The output impedance is 9 VCC 58 K

5K

C 10 K

1K

C

Fig. P (11.3)

h fe . hre

Solution :

Y0 = hoc –

where

Rs = source Resistance

hie R s

Y0 = 0.05 10–3

100 0 2 10 3 R s

Y0 = 0.05 10–3 Z0 =

1 1 = Yo 0.05 10 3

Z0 = 20 k Example 6. For the emitter follower with Rs = 0.5 k and RL = 5 k . Calculate Ai, Ri, Av. Assume hfe = 51, hie = 1 k , hoe = 25 micro amp/volt. Solution : (i) The current gain

Ai =

1 h fe 1 hoe .R L

=

1 51 1 25 10 6 5 10 3

Ai = 46.222 Ans. (ii) Input resistance Ri = hie + hre AiRL Ri = hie + 1 Ai RL = hie + AiRL Ri = 1 103 + 46.22 5 103 = (1 + 231.11)103 Ri = 232.11 103

503

HIGH FREQUENCY TRANSISTOR

Ri = 232.11 k (iii)

Av =

Vo A .R = i L Vi Ri

Av =

46.22 5 232.11

Av = 0.9956 Ans. Example 7. A BJT is found to have f T = 500 MHz. hfe = 100, rbb = 100 , rbe = 900 and Cbc = 5 PF. It is used as a CE amplifier with Rs = 1 k and RL = 500 . Determine for the amplifier (i) mid-band voltage gain Avs =

Vo Vs

(ii) The upper 3-db cut-off frequency f . Solution : Since

gm =

h fe rb e

substituting values,

100 900 1 gm = s 9 mid-band voltage gain will be gm =

Av =

Vce Vb e

Av =

gm Vb e R L Vb e

Av = – gm RL

1 9 Av = – 55.55 Av =

(i)

Avs =

A v rb e R s rbb rb e

Avs =

55.55 900 1000 100 900

Avs = – 25 Ans. (ii) upper 3-db cut-off frequency f =

fT 500 = = 5 MHz Ans. h fe 100

504

BASIC ELECTRONICS ENGINEERING & DEVICES

Example 8. A BJT has the following Parameters at an operating current of Ic = 2.3 mA, f T = 500 MHz, rbe = 1.5 k, rbb = 100 , Cc = 3F, Find the values of gm, Ce, and for the BJT. Solution : (i)

(ii)

a f

I c mA mhos 26 2.3 = = 0.088 mho. 26

gm =

= hfe = gm rbe = 0.088 1.5 103 = 132

(iii)

Cbe =

gm C be 2 f T

Cbe =

0.088 – 3 10–12 farad 2 500 10 6

Cbe =

FG 0.088 10 H 2 500 10 12

6

IJ K

3 PF

Cbe = 28.011 – 3 Cbe = 25.01 PF Ans. Example 9. Given the following parameters for a given transistor at Ic = 10 mA, VcE = 10 v and the room temperature : hfe = 100, hie = 500 , |Ai| = 10 at 10 MHz and Cc = 3 PF. Find f , f T, Ce, rbe Solution :

gm = rbe =

Ic 10 mA = = 384.6 ms VT 0.026

h fe gm

=

100 384.6 10 3

rbe = 260 Ans. rbb = hie – rbe rbb = 500 – 260 rbb = 240 f T = |Ai| f f T = 10 10 f T = 100 MHz. Ans. f =

fT f = T hie

f =

100 = 1 MHz Ans. 100

505

HIGH FREQUENCY TRANSISTOR

Ce =

gm – Cbe 2 f T

Ce =

384.6 10 3 – 3 10–12 2 100 10 3

Ce = 609 PF Ans.

1. Given hie = 2.4 k, hfe = 100, hre = 4 10–4 and hoe = 25 s sketch the (a) Common – emitter hybrid equivalent model. (b) Common – base hybrid equivalent model. 2. A CB transistor amplifier uses a voltage source of its internal resistance R s = 1100 and the load Resistance RL = 1300 . The h-parameter’s hib = 21 , hrb = 3.0 10– 4, h fb = – 0.99 and hob = 0.45 A/v. Calculate the following. (i ) Input impedance (ii ) Overall voltage gain. (iii ) Overall current gain. 3. Given the h-parameter’s for common emitter hie = 1000 ohms, hfe = 49, hoc =

1 1 . 3 and hre = 0, the values of hib and 40 10 hob

(Ans. – 20 ohms and 2M ohms)

4. A BJT has following low frequency h-parameter as Ic = 6 mA, hie = k, hre = 10–4, hfe = 102, hoe = 4.5 10–5 mho, calculate the resistive parameters of the hybrid- equivalent model. 5. A BJT has the following CE h-parameters hie = 1100 , hre = 2.5 10–4, hfe = 50, hoe = 2.5 10–5 mho (i ) Find the h-parameter for CB and CC configuration. (ii ) If base spreading resistance = 100 the find the resistance hybrid parameter. (Ans. (i) hie = 1100 , hrc = 1, hfc = – 51, hoe = 2.5 10–5 mho, hib = 21.57 , hrb = 2.9 10–4, hob = 0.5 10–6 mho (iii) rcc = 80 ohm) 6. For a BJT operated at Ic = 1 mA, determine f T and C if C = 2 PF and |hfe| = 10 at 50 MHz. [Ans. 500 MHz, 10.7 PF] 7. If C = 10.7 PF of the BJT includes a relatively constant depletion-layer capacitance of 2 PF, find f T of the BJT when operated at Ic = 0.1 mA. (Ans. = 130.7 MHz)

12 At the end of this unit you will be able to learn about the Introduction to feedback Basic concept behind feedback Types of feedback Classification of negative feedback Effects of the feedback circuits Analysis of different feedback circuits

The important characteristics of an amplifier are its voltage gain, bandwidth, input and output impedances. The parameters are more or less constant for an amplifier. The value of these parameters are required to change. The designer’s does not control the value of these parameters. This problem can be solved with number of ways. For example, if the gain could be reduced by voltage divider circuit in the input or in the ouptut circuit of an amplifier, the input impedance of an amplifier could be increased if required by connecting a series resistance in the circuit. But these methods results in the loss of useful signals. A new technique is introduced called as feedback in the amplifiers. The feedback is a process of injecting some energy (i.e., the form of voltage or current) from the output and then return it back to the input when the fraction or a part of output is feedback to the input, the process is known as Feedback. When amplifier circuit uses the feedback, then it is called feedback amplifier.

As Fig. 12.1 (a) shows a block diagram of a basis amplifier. Here, Vi is the input signal and Vo is the output signal. If A is the voltage gain of the amplifier, the output Vo is related to the input Vi by, A =

Vo Vi

In this amplifier, the input does not know what is happening at the output. If due to some reason, the output changes the net input remains unaffected. Such a system is called open-loop or non-feedback system. 506

Comp-1/Laxmi-5/Computer/Revision/Belec-12—26.4.07

10.5.07

507

FEEDBACK IN AMPLIFIER

However, Fig. 12.1 (b) shows a block diagram of feedback amplifier network. This feedback network is called a network or a feedback network. A fraction Vo of output voltage is going back to the input. This changes the net input voltage to the amplifier. The input knows at every instant what the output is. Such a system is called a closedloop or feedback system.

+

+ Vin

Amplifier (A)

+

+

Vs

Vi

–

– – V + f +

Vo

–

–

V o –

(a) Block diagram of basic amplifier.

+ V0 –

A

Feedback network ()

(b) Feedback introduced in the amplifier. Fig. 12.1

The voltage gain of the feedback amplifier is then Af =

Vo Vs

...(12.1)

The more general structure of the feedback amplifier is given below in Fig. 12.1 (c). Here this is a signal flow diagram, and the quantities x represent either voltage or currency signal. Source

xs

xi

xo A

Load

–

xf

Fig. 12.1 (c). General structure of the feedback amplifier.

x0 = Axi

(i)

These are general equation of a feedback amplifier xf = xo

(ii)

xi = xs – xf

(iii)

Af =

xo A = xs 1 +A

(iv)

But from Fig. 12.1 (b) (i.e., on applying KVL), we get Vs = V i + V f

...(12.2)

where Vf = feedback voltage. The output voltage (Vo) and feedback voltage (Vf) are related with feedback network () as

508

BASIC ELECTRONICS ENGINEERING & DEVICES

=

Vf Vo

Vf = Vo

or

...(12.2 (a))

For the basic amplifier, the input is Vi and the output Vo. Hence its voltage gain A (called internal gain) is given as A =

Vo Vi

...(12.3)

We shall now derive the expression of the gain Ai in term of A (internal gain) and (feedback network) Now,

or

Af = Af =

or

Af

=

Af =

Vo Vs

Vo Vi V f

...(12.4)

Vo (from equations (12.3) and (12.4)) Vo Vo A

A 1 +A

...(12.5)

Thus, it is clear from the equation (12.5) that the gain of amplifier decreases when we apply negative feedback. However, gain of an amplifier when we apply positive feedback is given by the relation. Af =

A 1 – A

...(12.6)

Thus, positive feedback increases the gain. Thus, and

finally Af =

A 1 +A

– for Negative feedback

Af =

A 1 – A

– for Positive feedback

The term ‘’ is called ‘feedback factor’. Whereas is known as feedback ratio. The expression (1 ± A) is called loop gain). Amplifiers are not the only things where the feedback is used. We use the idea of feedback in our daily life too. You may not have realised it, but even we use feedback in the process of learning. When a child is asked to write a letter A, he will probably write it as shown in Fig. 12.2 (a). When he finds that the stroke is not going in the correct direction, the information goes to his brain through the eyes. The brain immediately orders the hand to correct the direction of the stroke. With much effort and with constant feedback, the child writes the letter ‘A’ as shown in Fig. 12.2 (b).

509

FEEDBACK IN AMPLIFIER

Fig. 12.2 (a)

Fig. 12.2 (b)

From the equations (12.5) and (12.6), we have the following three cases : (i) Af > A ; for positive feedback. (ii) Af < A ; for negative feedback. (iii) In the case of positive feedback, if A = 1 and Af = . It is possible only in the case : when input is zero. But the amplifier is capable of producing output at input zero. This stage of an amplifier works as an oscillator (Discuss later in chapter 5 in detail). Example 1. Calculate the gain of a negative feedback amplifier with gain A = 200 and the feedback factor =

1 . 10

Solution : Given gain,

A = 200

Feedback factor,

=

From equation (12.5),

Af =

=

1 10

A 200 = 1 1 +A 1 200 10

F I H K

200 200 = = 9.52 1 20 21

Gain of the amplifier with feedback is 9.52. Conclusion : (i) With the negative feedback, the gain of the amplifier decreases. (ii) The value of the feedback factor () of the circuit lies between 0 to 1. Example 2. An amplifier with negative feedback has a voltage gain of 1000. It is found that without feedback, an input signal of 50 mV is required to produce a given output whereas, with feedback the input signal must be 0.5 V for the same output. Calculate the value of A and . Solution : Given : Af = 1000 Vi = 50 mV = 0.05 V Vs = 0.5 V

510

BASIC ELECTRONICS ENGINEERING & DEVICES

Af =

Vo Vs

Vo= Vs Af = 0.5 V 1000 = 500 V Gain without feedback, A =

Vo 500 V = = 10000 Vi 0.05 V

Af =

A 10000 = 1 +A 1 10000

Gain with feedback,

1000 =

10000 1 10000

1000 + 107 = 10000 =

10000 1000 = 0.0009 10 7

= 0.09%.

As we have discussed a feedback amplifier is consist of two parts namely amplifier circuits and feedback circuit. Depending upon whether the feedback signal increase or decreases the input signal there are two types of feedback in amplifier. (a) Positive Feedback. If the feedback signal (voltage or current) is applied in such a way that it is in phase with the input signal and thus increases it. Then it is called positive feedback. It is also known as regenerative feedback or direct feedback. Advantages : (i) It increases the gain of the amplifier (ii) If positive feedback is sufficiently large it leads to oscillations. So it used in oscillators. Disadvantages : It increases the distortion and instability. (b) Negative feedback. If the feedback signal (i.e., voltages or current) is applied in such a way that it is out of phase with the input signal and thus decrease it. Then it is called negative feedback. It is also known as degenerative feedback. Advantages : (i) It stabilize the gain of the amplifier. (ii) It reduces the distortion and noise. (iii) It reduces the output impedance.

511

FEEDBACK IN AMPLIFIER

(iv) It increase the input impedance. (v) It increase the range of uniform amplification or bandwidth. Disadvantages : It reduces the gain of amplifier. But due to the large number of advantages of negative feedback is frequently employed in the amplifiers. So lets discuss the negative feedback in more detail.

Negative feedback

Negative voltage feedback

Voltage series

Negative current feedback

Voltage shunt

Current series

Current shunt

Fig. 12.2. Classification of –ve feedback.

There are two types of negative feedback circuits i.e., (i) Negative voltage feedback. The voltage is fedback to the input of amplifier is proportional to the output voltage irrespective to the load. It is further classified into two categories i.e., (a) Voltage series feedback (b) Voltage shunt feedback (ii) Negative current feedback. The voltage is fedback to the input of the amplifier is proportional to the output current, irrespective to the load. It is further classified into two catagories : (a) Current-series feedback (b) Current-shunt feedback Let us discuss and analyze the effect of these four types of Negative feedback on the input and output impedance. +

R2

VO

R1

VO

–

Fig. 12.4. General representation of feedback circuit with resistors.

Vo = or

=

R1 . Vo R1 R 2 R1 R1 R 2

(By applying potential divider rule)

512

BASIC ELECTRONICS ENGINEERING & DEVICES

(a) Voltage series feedback : In the voltage series feedback circuit there is amplified

amplification of voltage into a voltage (i.e., voltage voltage) and a fraction of output voltage is fedback in series with the input voltage through the feedback network. The Basic circuit or a block diagram representation of voltage series feedback is shown in Fig. 12.5. +

+

VS

Vi

–

–

+

Vf

–

+

Feedback network

Vo

+ VO

Basic amplifier (AV)

–

+ Vo –

Fig. 12.5. Voltage series feedback circuit.

Derivation for input impedance with feedback From the circuit shown input impedance with feedback is given as : Zif = Zif = Zif =

Vs Vi

V f Vi

( Vs = Vi + Vf)

Ii Vo Vi Ii Basic amplifier

+

+

VS –

Vi –

Vf

+

+

–

–

A v Vi

RLVO –

+

+ –

Vo

Fig. 12.6 Note : During the calculation of input impedance for any circuit output is open circuited

or

Zif =

. A . Vi Vi Zi

or

Zif =

aA 1f VI

i

i

{ Vo = Av Vi then output is open}.

RS V T I

i

1

Zi , input impedance of the amplifier

UV W

513

FEEDBACK IN AMPLIFIER

Zif = Zi (1 + A) Thus, the impedance increases in voltage series feedback. Derivation of output impedance with feedback Note : To calculate the output impedance for any circuit all the independent sources are replaced by the internal resistance (i.e., voltage source will be treated as short circuited and current source as open circuited). Take imaginary voltage source (V) at the output of the terminal and also assume that current (I) is flowing through this source then output impedance with feedback will be equal to the ratio of imaginary voltage source (V) to the current (I) i.e.,

Zof =

V I

This procedure will apply in all the feedback circuits. The circuit diagram of voltage series configuration for calculating the output impedance is shown here. Source voltage Vs is the independent source replaced by short-circuit (S.C.) Basic amplifier circuit Zo Vi

RL

±

+ V – O

AvVi

VS = 0 S.C. –+ V1

Vo = V

+ Vo –

Fig. 12.7

Now, Applying KVL at the output V = I Zo + Av Vi

( Vs = Vi + Vf

V = I Zo + Av (– Vf)

0 = Vi + V f

V = I Zo – Av . Vo

or Vi = – Vf)

V = I Z o – Av . V

( Vo = V here)

V + V Av = IZo or

Zo V = I 1 Av

or

Zof =

Zo 1 Av

Thus, we see that in voltage series feedback output impedance decreases. (b) Voltage shunt feedback : In the voltage shunt feedback there is amplification of current into a voltage (i.e., current amplified voltage) and a fraction of output voltage is fedback in shunt with the input current through a fedback network. Basic circuit for voltage shunt feedback is shown in Fig. 12.8.

514

BASIC ELECTRONICS ENGINEERING & DEVICES

IS

+

Basic amplifier Rm

If

Vo –

Feedback network

= If / Vo

Fig. 12.8. Voltage shunt feedback circuit.

Derivation for input impedance From Fig. 12.9, Basic amplifier circuit Ii IS

Zo Vi

RL

± Rmli

+ R L Vo –

If If = Vo

Fig. 12.9

Zif =

Vi Is

or

Zif =

Vi I f Ii

or

Zif =

Vi Vo I i

or

Zif =

Vi . R m Ii Ii

or

Zif =

Vi Ii R m 1

or

Zif =

Zi 1 Rm

b

( Is = Ii + If) ( If = Vo) ( Vo = Rm Ii)

g

Thus, input impedance in the case of voltage shunt feedback is decreases. Derivation for output impedance According to the procedure for calculating output impedance the circuit diagram shown as in Fig. 12.10.

515

FEEDBACK IN AMPLIFIER Basic amplifier circuit Ii Zo If Ri

O.S.

l V Vo

± RMIi

Feedback network ()

+ Vo = V –

Fig. 12.10

V I V = I Zo + Rm I i

Zof = Now, or

V = I Zo + Rm (– If)

Is = Ii + If)

or

V = I Zo – Rm . V

o = Ii + If I i = – If

or

V (1 + Rm ) = I Zo

{If = Vo} V = Vo

or

Zo V = I 1 Rm

or

Zof =

Zo 1 Rm

Thus we see that in voltage shunt feedback output impedance decreases with feedback. (a) Current series feedback : In the current series feedback circuit there is amplification of voltage into current (voltage

Vo current) and a fraction of output Vi V f

current is fedback in series with the voltage through a feedback network. Basic circuit for current series feedback is as shown in Fig. 12.11). + VS –

–

+

+ Vi –

Basic amplifier Gm

RL

Vf

= Vf/Io

Feedback network

Fig. 12.11. Current series feedback circuit.

+ VO –

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BASIC ELECTRONICS ENGINEERING & DEVICES

Derivation for input and output impedance It is an exercise for students. In this circuit both input and output impedance after feedback are : Zif = (1 + Gm ) Zi Zof = (1 + Gm ) Zo

and

(b) Current shunt feedback : In the current shunt feedback circuit there is amplified

amplification of current into a current (i.e., current current) and a fraction of output current is fedback in shunt with the input current, through a feedback network. Basic circuit for current shunt feedback is shown in Fig. 12.12. Ii Is

Basic amplifier AI

RL

Feedback network

Io

If

= If/Io

+ VO –

Fig. 12.12. Current shunt feedback circuit.

Derivation for input impedance Is = I + If = Ii + Io = Io (1 + A) Zif =

=

Vi VI = Is Ii 1 A

a

f

Zi VI I i = 1 A 1 A

So, the input impedance of amplifier by a factor (1 + A). Derivation for output impedance To calculate the change in output impedance, the output resistance RL is disconnected and Vo is set to zero. External voltage Vo is applied across the output terminals and output current is measured. Zif =

Vo Io

(Io + AIo) =

Vo Zo

Zo (1 + A) Io = Vo Zif =

Vo = Zo (1 + A) Io

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FEEDBACK IN AMPLIFIER

Now, Table 12.1 shows the effects of feedback connection on input and output impedance after feedback. Table 12.1 Type/Parameter

Voltage series

Current series

Voltage shunt

Current shunt

Zif

Zi (1 + A)

Zi (1 + A)

Zi 1 A

Zi 1 A

increases

increases

decreases

decreases

Zo 1 A

Zo (1 + A)

Zo 1 A

Zo (1 + A)

decreases

increases

decreases

increases

Zof

Table 12.2 shows some parameters and their relationship under different feedback circuits. Table 12.2 Type/Parameter

Voltage series

Gain without feedback (A)

A =

Feedback ratio ()

=

Gain with feedback (Af )

Af =

Vo Vi

Vf Vo Vo Vs

Voltage shunt Current series Current shunt A =

=

Af =

Vo Ii

If Vo Vo Is

A =

=

Af =

Io Vi

Vf Io Io Vs

A =

=

Af =

Io Ii

If Io Io Is

Before proceeding with the concept of feedback, it is very necessary to study the classification of amplifiers. Generally amplifiers can be broadly classified in four categories, as given below : (i) Voltage amplifier (ii) Current amplifier (iii) Transconductance amplifier (iv) Transresistance amplifier This classification is based on the magnitudes of the input and output impedances of an amplifier relative to source and load impedance respectively. (i) Voltage amplifier : The general representation of voltage amplifier is shown in Fig. 12.13(a). If the amplifier input resistance Ri is large compared with the source resistance Rs then Vi = Vs. If the external load source resistance RL is large compared with the output resistance Ro of the amplifier will provide a output voltage proportional to input voltage and the proportionality factor is independent of the magnitudes of the source and load resistance. Such a circuit is called a voltage amplifier.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Ri >> Rs Ro > RL Rs > Rs Ro > Ri RL > Ri and RL >> Ro; when both input and output resistance of a amplifier are lower as compared to source and load resistance respectively. Since if R i > Ro, Vo Rm Ii Rm Is. This type of amplifier is called transresistance amplifier. Now, Table 12.3 shows the ideal requirement of amplifier characteristics like input and output resistance.

519

FEEDBACK IN AMPLIFIER Table 12.3 Amplifier Type Parameter

Voltage

Current

Transconductance

Transresistance

Ri

0

0

Ro

0

0

Transfer characteristics

V o = Av V s

I L = Ai I s

IL = Gm Vs

Vo = Rm Is

Now for better understanding we will draw a schematic representation of a single loop feedback amplifier. The transfer gain A may be Av, Ai, Gm, Rm as the case may be. I O = IL Comparator + V or Mixer – i

Signal Source

Basic Amplifier Forward transfer gain (A)

+ –V

Sampling network

RL Load Resistance

If + Vf –

Feedback network Reverse transmission ()

Fig. 12.16. Simple loop feedback amplifier.

The function of each block is given below : (a) Signal Source : This block is either a signal voltage Vs in series with resistance (Rs) or a current source (Is) in parallel with a resistance Rs. (b) Feedback Network : This block is usually a passive two part network which may contain resistors, capacitors and inductors. Most often it is simply a resistive configuration. Voltage amplifier Basic amplifier (A)

Feedback network () (a) voltage

+ Vi –

Basic amplifier (A)

Current amplifier Ic RLVo

Feedback network ( ) (b) current.

Fig. 12.17. Feedback connection of the output of basic amplifier, sampling the output.

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BASIC ELECTRONICS ENGINEERING & DEVICES

(c) Sampling Network : In the sampling network the output voltage is sampled by connecting the feedback network in shunt across the output. Another feedback connection which samples the output current where the feedback network is connected in series with the output. This type of connection is referred to as current or loop sampling. (d) Comparator or mixer network : Two mixing blocks are very common, series (loop) input and shunt (node) input connection respectively. A differential amplifier is often used as a mixer. Such an amplifier has two inputs and gives an output proportional to the difference between the signal at the two inputs. Now, we will discuss the feedback connections at the input of a basic amplifier as shown in Fig. 12.18. Source

Series mixer

Rs

Shunt mixer

Source + Basic amplifier A

V1

+ Vs –

Is

Ii

Basic amplifier A

Rs

–

Vf

If

(a)

(b)

Fig. 12.18. Schematic diagram of feedback connections at the input of a basic amplifier (a) series mixer (b) shunt mixing.

Transfer ratio or gain : Transfer ratio or gain of amplifier is the ratio of output

Vo is the voltage amplification or voltage Vi I gain. In the same fashion on transfer ratio o represents current amplification or Ii I current gain. However, the transfer function o represents the transconductance gm of Vi V amplifier and the transfer ratio o represents transresistance RM. From the above Ii discussions it is clear that the symbol gm and RM does not represent an amplification in the usual sense. Nevertheless, it is convenient to refer to each of the four quantities Av, Ai, gm and RM as a transfer gain of basic amplifier without feedback and to use the symbol A to represent any one of these quantities. signal to the input signal. The transfer ratio

The symbol Af is defined as the ratio of the output signal to the input signal of the amplifier configuration and is called the transfer gain of the amplifier with feedback. V I I Hence Af is used to represent any one of the four ratios o Avf, o = Iif, o = gmf, Is Is Vs Vo and = RMf Is

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FEEDBACK IN AMPLIFIER

Fig. 12.19 as shown below shows the schematic representation of a single loop feedback amplifier. Comparator or mixer Input signal (Xi)

(xe) Difference signal

+ ±

Output signal Xo = AXe Basic amplifier A RL

Feedback signal Xf = Xo

Feedback network

Load external

Fig. 12.19

As we have already seen that feedback circuits effects the many parameters of the amplifier. These effects may be in positive or negative side for various parameters like Bandwidth, gain, stability, distortion, frequency respnose etc. Now, we are going to discuss the effects of negative feedback on these parameters one by one.

The gain of an amplifier may change due to change in power supply voltage or change in parameter of active device. This adversely affects the performance of the amplifier. The gain of amplifier with negative feedback is : Af =

A 1 +A

(From equation 12.5)

If we assume that A >> 1, then the above equation may be written as : Af =

A 1 A

Thus, the gain Af of the feedback amplifier is made independent of the internal gain. It depends only on , which in turn depends upon passive elements such as resistors, inductors or capacitors. Since the values of passive elements remain constant, and hence the gain is stabilized. The only condition for the stabilization is that A >> 1. However, if this condition is not fully met some improvement occurs in the stability of the gain. Suppose a certain change in the internal gain of the amplifier takes place. We can find the corresponding percentage change in the overall gain of the feedback amplifier. This can be done by differentiating equation (12.5) with respect to A.

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BASIC ELECTRONICS ENGINEERING & DEVICES

dA f dA dA f dA or

=

=

dAf =

dA f Af dA f Af

=

=

a1 Af .1 A a1 Af 2

1

a1 Af

2

RS A T

dA

a1 +Af d A a1 Af . A a1 Af 2

f

A 1 +A

UV W

2

1 dA . 1 A A

a

f

...(12.7)

Thus, from equation (12.7) it is clear that as (1 + A) > 1, the percentage change in Af is seen to be much less than percentage change in A. Another desirable characteristics of negative feedback is the reduction of harmonic distortion. A non-linear or harmonic distortion is usually introduced in the output of a large signal amplifiers. However, when a negative feedback is used in such amplifier the distortion and noise is reduced. To determine the amount of reduction in distortion caused by negative feedback, refer the block diagram of the feedback amplifier as shown in Fig. 12.20. Input signal

+

Amplifier A

Df

Output

–

Feedback network

Df

Fig. 12.20

Consider the amplifier with gain A producing a distortion D without feedback. Whenever feedback is applied then gain becomes Af and the distortion in the output becomes Df. Let us see how the distortion in the output changes from D to D f. A part Df of distortion Df is feedback to input. This gets amplifier A times by the basic amplifier and becomes Df. This gets added up (in reverse polarity because of negative feedback) to the original distortion D to make the net distortion D f . Thus, or

Df = D – ADf Df =

D 1 +A

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FEEDBACK IN AMPLIFIER

Note that the distortion after feedback is reduced by a factor (1 + A) times. Noise (i.e., electrical noise) may appear due to many reasons, if a noise voltage appears just at the input of the amplifier, it is amplified by the same amount as the signal voltage. If negative feedback is applied the net noise in the output is reduced by (1 + A) and the performance of the amplifier is much improved.

For all the amplifiers the most basic requirement is the high input impedance. Then it will not load the preceeding stage or the input voltage source. This type of characteristic can be achieved with the help of negative voltage series feedback. To derive the input impedance of a negative feedback, consider a voltage series feedback circuit as shown below in Fig. 12.21. Let Zif is the input impedance of the amplifier circuit after feedback. Ii + Vs –

–

+

+ Vi – +

A

Vo

–

Vf = Vo

Fig. 12.21. Block diagram of a negative feedback amplifier.

Now,

Zif =

Vs Ii

V f Vi

or

Zif =

or

Zif =

Vo Vi Ii

or

Zif =

. AVi Vi Ii

or

Zif = (A + 1)

FG V =Z HI i

i

or

{ Vs = Vi + Vf}

Ii

i

Vi Ii

FG V HV

f

o

IJ K

IJ K

input impedance of the amplifier

Zif = Zi (1 + A) Thus, we see that the input impedance is increased by a factor of (1 + A)

Just as a high input impedance is advantegeous to an amplifier in the similar fashion a low output impedance is also advantegeous. Because an amplifier having low

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BASIC ELECTRONICS ENGINEERING & DEVICES

output impedance is capable of delivering power (voltage or current) to the load without much loss. Such a desirable characteristic is achieved by employing negative voltage series feedback. To derive the expression of output impedance of an amplifier after the feedback, first of all we will draw the block diagram of voltage series amplifier as shown in Fig. 12.22. Note that the output impedance of any circuit is determined by deactivating all the independent sources i.e., replaced by their internal resistance (i.e., voltage source as short circuited and current source is open circuited). Since here V s (source voltage) is independent source so replaced by the short circuit, we get Zof =

Vo Io Zo

+

+ Vi –

Vs –

IL + AV o –

RL

+ Vo –

+ Vf –

Fig. 12.22

Vo + AVo = Io Zo Vo (1 + A) = Io Zo

Vo Zo = Io 1 A or

Zof =

Zo 1 A

...(12.8)

Thus, we see that output impedance is reduced by a factor (1 + A).

We have seen that the overall gain of an amplifier decreases when a negative feedback is applied. i.e.,

Af =

A where A is the gain of basic amplifier 1 +A

We know that when negative feedback is employed, the lower cut of frequency decreases by this factor (1 + A) and the upper cut of frequency increases by the same

525

FEEDBACK IN AMPLIFIER

factor (1 + A). Hence there is improvement in the bandwidth i.e., difference between the upper and lower cut-off frequency increases (BW = Fu – Fl). This is based upon the fact that for a given amplifier the product of gain and bandwidth remains constant and known as gain bandwidth product (GBW) i.e.,Gain Bandwidth before feedback = Gain Bandwidth after feedback. A BW = Af . BWf A BW = or

A . BW f 1 +A

BWf = (1 + A). BW

...(12.9)

Thus, there is increase in bandwidth by factor (1 +A).

Linear analysis of a transistor circuit. There are many transistor circuits which do not consist of CE, CB or CC configuration as discussed earlier. Before applying feedback between input and output, we must follow some steps as given below : 1. Draw the actual wiring diagram of the circuit neatly. 2. Mark the point B (base), C (collector) and E (Emitter) on the circuit diagram. Locate these points during the starting of the equivalent circuit. Maintain the same relative positions as in original circuit. 3. Replace each transistor by its h-parameters as discussed earlier. 4. Replace each independent dc source by its internal resistance (i.e., the ideal voltage source is replaced by a short circuit, and the ideal current source by an open circuit). 5. Solve the resultant linear circuit for mesh or branch current and node voltages by applying KVL and KCL. Miller’s theorem is the best solution for the problem (or difficulty) discussed earlier. When there is a voltage feedback we apply Miller’s theorem or in other words we can say that generally Miller’s theorem is used to isolate the input and output, because feedback creates a problem when we apply KVL and KCL. According to the Miller’s theorem, if the feedback impedance (Z f ) is connected between input and output can be replaced by a circuit as shown Fig. 12.23. Zi

+ Vi Input –

1 + –

V1

2

Network 1 2

V2

+ –

+ Vo –

Fig. 12.23. Network with feedback.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Fig. 12.23 shows the network with feedback. The effect of feedback on impedance (Zf) in input side is as : 1

+ Vin

2

+ Vo

Network

–

–

1 2

Zf 1 – Av

Zf 1–

1 Av

Fig. 12.24. Isolated network after applying the Miller’s theorem.

Zin = where

Zf 1 Av

Av = Voltage gain =

V2 V1

However, the effect of feedback on impedance in the output side is as shown in Fig. 12.24. Zo =

Zf 1

1 Av

However, Dual Miller’s theorem is also applicable when there is a current feedback. According to the Dual Miller’s theorem for the circuit as shown in Fig. 12.25 and Fig. 12.26. The impedance Zf in input side as well as in output side is connected in series given by the relation. 1

2

I1

Z

I2

1

2

Fig. 12.25. General circuit with current feedback.

I1

1

1

Z 1–

Z(1 – AI )

Z

1 AI 2

I2

2

Fig. 12.26. Isolated circuit i.e., often applying Dual Miller’s theorem.

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FEEDBACK IN AMPLIFIER

Zin = Z (1 – AI)

FG H

Zout = Z 1

FG H

Where AI is the current gain A I

I2 I1

1 AI

IJ K

IJ K

Example of Miller and its dual theorem : To understand the above theorem and its dual more clearly consider the transistor (CE) configuration where there is a voltage feedback. To calculate the parameters like Av, Zi, Zo etc., we should first apply the Miller’s theorem because there is a voltage series feedback. Now we applying the Miller’s theorem the above circuit can be replaced as shown in Fig. 12.27. VCC RL Rf +

C +

Rs Vo

B

Vs

E –

–

Fig. 12.27. Voltage shunt feedback. VCC RL C Rs

I1 B

Vs ±

Rf 1 – Av

Rf E

1–

1 Av

Fig. 12.28. Circuit after applying Miller’s theorem or the amplifier without feedback.

Now, the circuit shown in Fig. 12.29 employs a current feedback. In this circuit we should apply a dual Miller’s theorem.

528

BASIC ELECTRONICS ENGINEERING & DEVICES VCC RL C

+

Rs B E

Vo

Vs ± RE –

Fig. 12.29. Amplifier with feedback. VCC RL 11 RERE 1 1–– AAji

+ Rs

RE (1 – Ai) Vo

± Vs –

Fig. 12.30. Example of dual Miller’s theorem or circuit without feedback.

Summary 1. A feedback amplifier may be defined as the amplifier in which a fraction of output energy voltage or current is feedback to their input. 2. There are two types of feedback namely positive feedback and negative feedback. 3. When a feedback energy is in phase with the input signal and thus aids to it, it is known as positive or regenerative or direct feedback. 4. When a feedback energy is not in phase with the input signal i.e., the input and output differ by 180° such type of feedback is known as negative, degenerative or reverse feedback. 5. On the basis of energy feedback there are two types of feedback circuit i.e., voltage feedback and current feedback circuit. 6. Gain of amplifier without feedback.

A =

Vo Vin

FEEDBACK IN AMPLIFIER

529

7. Gain of amplifier with feedback. Af =

A Where is called feedback ratio or fraction. 1 +A

8. Negative feedback is more advantageous than disadvantage. 9. Negative voltage feedback decreases distortion and increases bandwidth therefore it is used in public address system, transistor radio receivers etc. 10. Negative feedback provides perfect impedance matching therefore generally used at the output stage. 11. Feedback circuits may be classified into four categories namely voltage-series feedback, voltage shunt, current-series, current-shunt feedback. 12. In voltage series feedback input impedance increases while output impedance decreases with feedback. 13. In voltage-shunt feedback both input and output impedances with feedback increases. 14. In current-series feedback both input and output decreases with feedback. 15. In current-shunt feedback input impedance decreases while output impedance increases with feedback. 16. Miller’s and Dual Miller theorem is used to isolate the input and output. 17. Negative feedback is employed to make the amplifier gain less sensitive to components variations, to control input and output impedances, to extend bandwidth ; to reduce non-linear distortion and to enhance signal to-noise-ratio. 18. The key feedback parameters are the loop gain (A). 19. Since A and are in general frequency dependent, the poles of the feedback amplifier are obtained by solving the characteristic equation 1 + A (s) (s) = 0. 20. For the feedback amplifier to be stable, its poles must all be in the left half of the Splane. 21. To make a given amplifier stable for a given feedback factor , the open-loop frequency response is suitably modified by a process known as frequency compensation.

? 1. What does you mean by feedback. What do you understand by negative and positive feedback ? Why is negative feedback applied in the high gain amplifier. 2. Distinguish current feedback and voltage feedback with appropriate circuit block diagram. 3. Drive the formula for negative feedback amplifier gain in terms of A f : A and B. 4. Explain, how is bandwidth increased by Negative feedback. 5. Draw the circuit of a transister amplifier with negative voltage feedback circuit. How to explained it ? Explain how in Negative voltage feedback to the input. 6. What is an oscillator ? How does it differ from an amplifier ? What are the essential parts of an oscillator circuit ? Explain the function of each part. 7. Explain why : (i) A Negative feedback is always employed in high gain amplifiers.

530

BASIC ELECTRONICS ENGINEERING & DEVICES (ii) Emitter-follower circuit is also called common-collector amplifier circuit. (iii) A common emitter circuit without by pass capacitor is called a negative current feedback circuit. 8. State the merits and demerits of negative feedback in amplifiers. 9. Derive an expression to illustrate that the voltage gain in an amplifier circuit with negative feedback is some what stable even if the of transistor changes due to its ageing or due to its replacement. 10. What do you mean by Miller’s theorem ? 11. State Miller’s dual theorem. 12. List the fire main advantages of Negative feedback amplifier. 13. Explain why the input impedance and output impedance of a transconductance amplifier should be high. 14. Explain different basic feedback topologies. 15. What do you mean by loop gain ? 16. How feedback effects stability ? Explain in detail.

Example 1. Calculate the gain of a negative-feedback amplifier with an internal gain A = 125 and feedback factor =

1 . 10

Solution : Given that A = 125

1 10 We know that gain of negative feedback is given by =

Af =

A 1 +A

125 = 9.259. Ans. 13.5 Example 2. An amplifier with negative feedback has a voltage gain of 100. It is found that without feedback, an input signal of 50 mV is required to produce a given output, whereas with feedback, the input signal must be 0.6 for the same output. Calculate the value of A and B. =

Solution : Given that Af = 100. The input voltage required to produce the same output voltage as for the amplifier without feedback is 0.6 V. Thus the output will be. Vo = Af Vi = 100 0.6 = 60 According to question If no feedback is employed, the required input to produce 60 V output is 50 mV.

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FEEDBACK IN AMPLIFIER

Hence the internal gain of the amplifier is A = Now, from

Af = 1 = =

Vo 60 = = 1200 Vi 50 10 3

A 1 +A 12 1200 1 = 1200 = 11 1 1200 . 1 1200 11 Ans. 1200

Example 3. To an amplifier of 60 dB gain, a feedback of = 0.005 is applied. What would be the change in overall gain of the feedback amplifier if the internal amplifier is subjected to a gain reduction of 12%. Solution : Given :

A = 60 dB = 1000

{

gain in dB = 20 log10

= 0.005

FG V IJ HV K 2 1

60 = 20 log10 (A)

3

or

A = 10 = 1000

dA f dA = – 12% = – 0.12, = ? A Af We know that

dA f Af dA f

or

Af dA f Af

=

1 dA 1 A A

=

1 0.12 1 1000 0.005

a

f

= – 0.02 or – 2%. Ans.

Therefore, the overall gain of the feedback amplifier will be reduced by 2%. Example 4. An amplifier has gain A = 60 dB and output impedance Zo = 12.6 k. It is required to modify its output impedance to 500 by applying negative feedback determine. (i) The value of feedback factor (ii) The percentage change in overall gain for 20% change in the gain of the basic amplifier. Solution : Given gain in dB = 60. We know that gain in

dB = 20 log10

FG V IJ HV K

60 = 20 log10 (A) So,

A = 103 = 1000

2 1

= 20 log10 (A)

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BASIC ELECTRONICS ENGINEERING & DEVICES

Zo = 12.6 k Zof = 500 We know that,

Zof = 500 =

Zo 1 A

12600 1 1000

5 + 5000 = 126 =

121 5000

= 0.0242 Now,

dA f Af

=

1 dA 1 = = 0.083%. Ans. 1 A A 1 1000 0.0242

Example 5. An amplifier without feedback gives a fundamental output of 36 V with 7% second harmonic distortion when the input is 0.028 V. (a) If 1.2% of the output is feedback into the input in a negative voltage series feedback circuit, what is the output voltage ? (b) If the fundamental output is maintained at 36 V but the second-harmonic distortion is reduced to 1 percent, what is the input voltage. Solution : Given that Vo = 36 V Vi = 0.028 V A = =

Vo 36 = = 1285 Vi 0.028

Vf Vo

=

1.2 = 0.012 100

(a) Gain with the feedback is given by,

Also

Af =

A 1285 = = 78.2 1 +A 1 1285 0.012

Af =

Vo Vs

Vo = Af Vs = 78.2 0.028 = 2.19 V. Ans. (b) If the output is maintained constant at 36 V then the distortion generated by the device is unchanged. The reduction of the total distortion is caused by feedback. Df =

D 1 +A

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FEEDBACK IN AMPLIFIER

or

1 + A =

D 7 = 1 Df

RS D T D f

UV W

1% = 7%

A = 7 – 1 = 6 Now, from equation,

Af =

A 1285 = = 183.57 1 +A 7

Vs =

Vo 36 = = 0.196. Ans. Af 183.57

Example 6. An amplifier with open loop voltage gain of 1000 ± 10% is available. However we desire to build an amplifier whose gain does not vary by more than 0.1%. Find the required feedback ratio and the corresponding closed loop voltage gain. Solution : Given, we know that

dA f Af

=

0.1 =

dA 1 . A 1 A 10 1 A

1 + A = 100 Given,

A = 1000 =

So, closed loop gain

Af =

100 1 = 0.099 1000

A 1000 = = 10. Ans. 1 +A 100

Example 7. An amplifier has open loop voltage gain of 1000 and delivers 10 watts output with 10% second harmonic distortion when the input is 10 mV. If 40 dB of negative feedback is applied, what will be the distortion ? How much input voltage should be applied to 10 watts output power ? Solution : The term 40 dB of feedback means 20 log10 (1 + A) = 40 dB.

40 20 1 + A = (10)2

or

log10 (1 + A) =

or or

1 + A = 100

Af =

...(i)

A 1000 = 1 +A 100

= 10 {Given A =1000,and 1+A = 100 from equation (i)} New value of second harmonic distortion Df =

Do 10 = = 0.1% 1 A 100

Now value of input required = 10 mV 100 = 1 V { Vs = Vi (1 + A)}. Ans.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Example 8. An amplifier has an input of 10 mV and a gain of 200 without feedback. The distortion produced at the output of the amplifier is 10%. It is desired to reduce the distortion to 1% by using negative feedback. Calculate the gain, input voltage and output voltage with feedback. Solution : Given :

D = 10% = 0.1 Df = 1% = 0.01 A = 200 Vs = 10 mV

We know that,

Df =

0.01 =

D 1 +A 0.1 1 200 .

= 0.045 or 4.5%

A 200 = = 20 1 +A 1 0.045 200

Gain with feedback,

Af =

Now output voltage,

Vo = Af Vs = 20 10 mV = 0.2 V

Now input voltage,

Vin = 0.01 V + (– 0.045 0.2) = 0.001 V. Ans.

Example 9. An amplifier has an input impedance of 1 k and output impedance of 10 k and a voltage of 10,000. If a negative feedback of = 0.02 is applied to it, determine the input and output impedance of the amplifier with feedback. Solution : Given :

A = 10,000 = 0.02 Zi = 1 k Zo = 10 k Zif = ? Zof = ?

Consider a voltage series feedback case in which feedback input impedance increases, while output impedance decreases and given by the relation. Zif = Zi (1 + A) or

Zif = 1 k (1 + 10000 0.02) = 1 k (201) = 201 k. Ans.

and

Zof =

Zo 1 A

or

Zof =

a1 10,000 0.02f

10 k

=

10 = 0.4975 k. Ans. 201

535

FEEDBACK IN AMPLIFIER

Example 10. An RC coupled amplifier has a mid-frequency gain of 400 and a frequency response from 200 Hz to 40 kHz. Determine the gain and frequency response when negative feedback with feedback ratio of 0.01 is introduced in the amplifier circuit. Solution : Given :

A = 400, = 0.01

We know that gain with feedback, Af =

A 1 + A

= 400 Lower cut-off frequency with feedback fLF = =

fL 1 A

200 Hz = 40 Hz. 1 +400 0.01

Upper cut-off frequency with feedback fHF = f H (1 + A) = 40 kHz (1 + 400 0.01) = 40 5 = 200 kHz.

Ans.

Example 11. A negative feedback amplifier is shown in Fig. P (12.1) if the gain of the amplifier without feedback is 4000, find : (i) Feedback fraction or feedback ratio. (ii) Overall voltage gain with feedback. (iii) Output voltage if input voltage is 2 mV. +

op-amplifier +

–

Vin = 2mV

RL = 10k Vo R2 = 9k R1 = 1k –

Fig. P (12.1)

Solution : Given

A = 4000 R1 = 1 k R2 = 9 k

(i) Feedback fraction,

=

R1 1 = = 0.1. Ans. R1 R 2 19

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BASIC ELECTRONICS ENGINEERING & DEVICES

(ii) Overall voltage gain with feedback Af = =

A 1 +A

4000 4000 = 1 4000 0.1 1 400

= 9.975. Ans. (iii) We know that,

Af =

Vo (here Vs = 2 mV) Vs

Vo = Af . Vs = 9.975 2 mV = 19.95 mV. Ans. Example 12. An amplifier has a gain of 54.8 dB without feedback. Find the change 1 in gain if of the output voltage is feedback at the input. Determine the percentage 50 reduction in harmonic distortion in the output due to feedback. Solution : Given : A in dB = 54.8 We know that gain in dB = 20 log10 (A)

54.8 = log10 (A) 20 or

A = 102.74

or

A = 549.5 550 =

Feedback factor,

1 = 0.02 50

Now, gain with feedback, Af =

A 550 = 1 +A 1 550 0.02

Df =

D D = 1 +A 1 550 0.02

Distortion with feedback,

Percentage change in distortion

Df D

100 =

1 100 12

= 8.33%. Ans. Example 13. (i) Find

V f Vo

for the network shown below :

(ii) Sketch the circuit of a phase shift FET oscillator using this feedback network. (iii) Find the minimum gain required for the oscillation.

537

FEEDBACK IN AMPLIFIER C

R

+

+ Vo

I1

R Vf

C I2

–

–

Fig. P (12.2)

Solution : (i) Applying KVL in the loop (1) and (2), we get Vo = I 1

O = I2

FG R + 2 IJ H j C K FG R + 1 IJ H j C K

– I2

1 jC

– I1

1 jC

From equations (A) and (B) eliminating current I 1

FG H

I2 R + Vo =

Vo = jC I2 or

1 jC

1 jC

IJ K FG R + 2 IJ I H jC K

2

1 jC

FG R + 1 IJ FG R + 2 IJ 1 H j C K H j C K j C

Vo 2 2 Rj C RjC – R 2 2 C2 1 = jC V f

( Vf = I2R.)

R or

or

or

V f Vo V f Vo V f Vo

=

=

=

j CR 1 +3 j CR – R 2 2 C 2 1 1 RC 3 j CR j 1

F 1 I 3 j G RC – J RC K H

Ans.

(ii) Circuit of phase-shift FET oscillator using the feedback network is shown in Fig. P (12.3).

538

BASIC ELECTRONICS ENGINEERING & DEVICES

+ VDD Rc

R1

C

R C

R2

R

Rs

Fig. P (12.3) (iii) We know that =

V f Vo

the frequency at which is purely real. In other word imaginary part must be zero.

1 to 3 i.e.,

When in the expression

V f Vo

imaginary part equal to zero, then

V f Vo

becomes equal

1 3 A 1 =

Also

A

1

A 3 Amin = 3 Ans. Example 14. Determine the stability of an amplifier, given the loop gain function. T (f) =

a f

100

F1 j f I H 10 K

3

5

Determine the stability of the amplifier for = 0.20 and = 0.02. Solution : The loop gain can be written in terms of its magnitude and phase, as T (f) =

LM MN

a f f I 1 F H 10 K 100

5

2

OP PQ

3

– 3 tan–1

FfI H 10 K 5

539

FEEDBACK IN AMPLIFIER

The frequency f 180 at which the phase becomes – 180 degree is – 3 tan–1

Ff I H 10 K 180 5

= – 180°, we get,

f 180 = 1.73 105 Hz The magnitude of the loop gain at this frequency, for = 0.20, is then

b g

T f180

=

a0.20f a100f

= 2.5

8

For = 0.02, the magnitude is

b g

T f180

=

a0.020f a100f

= 0.25

8

Note : The loop gain magnitude at the frequency at which the phase is – 180 degree is 2.5 when = 0.20 and 0.25 when 0.02. The system is therefore unstable for = 0.20 and stable for = 0.02, since at = 0.20 gain is 2.5 which is greater than 1. Hence, the system is unstable for = 0.20.

Example 15. Determine the required feedback transfer function which gives a phase margin of 45 degrees. Given that :

T (f) =

F1 J f H 10

3

a100f F I G1 J f K H 5 10

4

IJ F 1 J f I K H 10 K 6

Solution : A phase margin of 45 degree implies that the phase of the loop gain is – 135 degree at the frequency at which the magnitude of the loop gain is unity. The phase of the loop gain is = –

LMtan F f I tan FG f IJ tan F f I OP H 10 K Q H 5 10 K N H 10 K 1

1

3

1

4

6

Since the three poles are far apart the frequency at which the phase is – 135 degree is approximately equal to the frequency of the second pole. So in this example, f 135 5 104 Hz, so we have that = –

LMtan F 5 10 I tan F 5 10 I tan F 5 10 I OP GH 5 10 JK GH 10 JK PQ MN GH 10 JK 4

1

3

4

1

4

4

1

6

= – [88.9° + 45° + 2.86°] – 135°

or

Since we want the loop gain magnitude to be unity at this frequency, we have

af

T f

= 1 =

F 5 10 IJ 1 G H 10 K a100f a50f a1.41f a1f 4

3

or

1

a f

100

2

F 5 10 IJ 1 G H 5 10 K 4 4

2

F 5 10 IJ 1 G H 10 K 4

6

2

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BASIC ELECTRONICS ENGINEERING & DEVICES

1. An amplifier has a gain of 2000. If the feedback ratio is 0.04, then find the voltage gain of the amplifier with negative feedback. [Ans. 24.7] 2. An amplifier has a gain of 4000. With negative feedback, the gain reduces to 25. Calculate the fraction of the output that is feedback to the input. [Ans. 0.04] 3. An amplifier with negative feedback has a gain of 50. It is found that without feedback, an input signal of 0.1 V is required to produce a given output, whereas with feedback, the input signal must be 0.8 V for the same output. Calculate the amount of voltage gain and feedback ratio. [Ans. Av = 400, = 0.018] 4. An amplifier has a voltage gain of 500. A technician decides that 10% negative feedback should be employed to reduce distortion. (a) What will be the voltage gain with feedback ? (b) What should be the feedback in order to double the gain that existed in (a). [Ans. (a) 9.8 ; (b) 4.9%] 5. The midband voltage gain of a certain amplifier is 500. Its upper half-power frequency (f 2) is 20 kHz and the lower half-power frequency (f 2) is 20 Hz. What will be the upper and lower half power frequencies and voltage gain, if 2% negative feedback is introduced ? [Ans. f 2 = 200 kHz ; f 2 = 1.8 Hz, Av = 45.5] 6. An amplifier with 2.5 k input resistance and 50 k output resistance has a voltage gain of 100. The amplifier is now modified to provide 5% negative voltage feedback in series with the input. Calculate (a) the voltage gain, (b) the input resistance, and (c) the output resistance with feed back. [Ans. (a) 16.67, (b) 15 kW and (c) 8.3 kW] 7. A feedback amplifier has an internal gain A = 40 dB and feedback factor = 0.05. If the input impedance of this circuit is 12 k. What would have been the input impedance of the amplifier if feedback not present. [Ans. 2 k] 8. What should be the feedback factor of negative feedback applied to an amplifier of internal gain A = 180, and Z = 250 , in order to increase the input impedance to 1 k. [Ans. 0.0389] 9. A certain amplifier has an internal gain of 80 and the harmonic distortion in the output is 12%. To improve the performance of the amplifier from the point of view of harmonic distortion. Negative feedback is introduced in the circuit. This reduces the distortion within a tolerable limit of 3%. Calculate the feedback factor in the amplifier. [Ans. = 0.0375 = 3.75%] 10. A negative feedback amplifier has a closed-loop gain Af = 100 and the open-loop gain A = 105. What is the feedback factor ? If a manufacturing error results in a reduction of A to 103. What closed-loop gain results ? What is the percentage change Af corresponding to this factor of 100 reduction in A ?

13

At the end of this unit you will be able to learn about the Cascade amplifier Amplifier coupling Different coupling used in multistage amplifier RC coupled amplifier and analysis Transformer coupled amplifier Direct coupled amplifier Emitter follower Darlington amplifier analysis Bootstrapping Tuned amplifier basics Tuned (Resonant) circuits Single tuned voltage amplifier Double tuned voltage amplifier Stagged-tuned voltage amplifier

As we have discussed earlier that voltage or current or power gain obtained from a single-stage amplifier is limited. It is inadequate to drive the output devices like speaker, indicating instruments etc. So in order to achieve high voltage gain, current or power, we need more than one stage i.e., multistage. As we know that an amplifier is the basic building block of most electronics system. Just as one brick does not make a house, a single-stage amplifier is not sufficient to build a practical electronics system. Thus, we can say that when a number of amplifier stages are used in succession (one after the other) it is called a multistage amplifier or cascaded amplifier. It may be noted that much higher gain can be obtained from the multistage amplifiers. In the multistage or cascaded amplifier, more than two amplifier are arranged in a manner that output of one stage (amplifier) act as input of the other stage (amplifier). Much higher gains (thousands and millions times) can be obtained from a multistage amplifier. 541

Comp-1/Laxmi-5/Computer/Revision/Belec-13—26.4.07

10.5.07

542

BASIC ELECTRONICS ENGINEERING & DEVICES

A cascaded (multistage) amplifier (n-stages) can be represented by the block diagram as shown in Fig. 13.1. You may note that the output of the first stage makes the input of the second stage, the output of the second stage makes the input of third stage and so on. The signal voltage VS is applied to the input of the first stage. The final output V0 is then available at the output terminals of the last stage. The output of the first stage or the input to the second stage is

v1 = A1 vs where A1 is the voltage gain of the first stage. Then the output of the second stage (or the input to the third stage) is

v2 = A2 v1 Similarly, the final output v0 is given as

v 0 = v n = An V n

– 1

where An is the gain of the nth stage. Now, overall gain A of the amplifier is then given as A =

0

1

s

s

2

n 1

1

VS = Vin

A1

A2

V1

0 n 1

n–2

A = A1 A2 ... An

VS

– 1

An

V3 Vn–1

A3

V2

An

Vn = V0

Fig. 13.1. Block diagram of a multistage amplifier having n stages.

For example, the three stages (cascaded) common emitter amplifier are shown in Fig. 13.2. + VCC R1

RC

CC

1

RS + VS –

R1

RC

CC

2

RE

VO

Q2 CE

1

RC

3

Q1 R2

R1 CC

R2

RE

Q3 CE

2

R2

RE

CE

3

Fig. 13.2. Three stage cascaded common emitter amplifier. Note. The gain of a multistage amplifier can be easily computed if the gains of the individual stages are known in dB. If we take logarithm (to the base 10) then from equation (13.1) and then multiply each term by 20, we get

20 log10 A = 20 log10 A1 + 20 log10 A2 + ... + 20 log10 An

...(13.1)

543

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

In the above equation, the term on the left is the overall gain of the multistage amplifier expressed in d B. The terms on to the right denote the gains of the individual stages expressed in d B. Thus, the overall voltage gain in dB of a multistage amplifier is the sum of the decibel voltage gains of the individual stages i.e., Ad B = Ad B1 + Ad B2 + Ad B3 + ... + Ad Bn

...(13.2)

Bandpass of Cascaded Stages The high 3-d B frequency for n-cascaded stages is f H and equal to the frequency

1 (which we will discuss, in more 2

for which the overall voltage gain falls 3d B i.e.,

detail latter) of its mid band value. To obtain the overall transfer function of noninteracting stages, the transfer gain of individual stages are multiplied together. Hence, if each stages has a dominant pole and if the high 3-dB frequency of its stage is f Hi, where i = 1, 2, 3, ..., n, then f H* can be calculated from the product.

1

Ff*I 1 G H f JK

2

1

Ff*I 1 G H f JK

H

2

H

H1

Hi

1

1

FG f * IJ HI K

2

=

H

1 2

n

for n stages with identical upper 3-dB frequencies, we have

fH1 = fH 2 = fH3 = .......... fH i = fHn fH thus f H* is calculated from

LM MM N

or

OP F f*I P 1G H f JK PQ 1

2

2

=

H

1 2

H

f H* = f H .

21/n 1

...(13.3)

where f H* = higher cut-off or upper 3-dB upper 3-dB frequency after n stage. f H = cut-off or upper 3-dB frequencies of each stage. Thus, from equation (13.3) it is clear that as the number of cascaded stages increases the upper 3-dB frequency decreases. For example, for n = 2,

fH* = 0.64. fH

Hence, two cascaded stages, each with a bandwidth, f H = 10 kHz, have an overall bandwidth of 6.4 kHz. However, if the lower 3-dB frequency for n identical non-interacting cascaded stages is f L* then corresponding to equation (13.3) we find f L* =

2

fL 1/ n

1

...(13.4)

where f L* = Lower cut-off or lower 3-dB-frequency after n-stage f L = Cut-off or lower 3-dB frequency of each stage.

544

BASIC ELECTRONICS ENGINEERING & DEVICES

Thus, from equation (13.4) it is clear that as the number of cascaded stages increases the lower 3-dB frequency increases. Now, if we combine these two results we see that a cascade of stages has a lower fH and a higher fL than a single stage, resulting in a shrinkage (decrease) in bandwidth. Example 1. A multistage amplifier consists of three stages. The voltage gains of the stages are : 80, 50, 30, find the average (overall) voltage gain in dB. Solution : We know that the overall voltage gain in dB of three stage amplifier is given by Ad B = Ad B1 + Ad B2 + Ad B3 First we calculate the gains of individual stages in dB. Thus, Ad B1 = 20 log10 80 = 38.06 d B Ad B2 = 20 log10 50 = 33.99 d B Ad B3 = 20 log10 30 = 29.54 d B Overall voltage gain is Ad B = 38.06 + 33.99 + 29.54 d B 101.59 d B. Example 2. Find the overall voltage gain of the 3-stage (multistage) amplifier. If each stage has Rin = 1 k ; = 60 and RC = 2.4 k. Solution : Voltage gain of single stage, G1 =

RC 2.4 = 60 = 144. R in 1

Voltage gain of one stage in dB = 20 log10 G1 = 20 log10 144 = 20 2.158 = 43.17 dB. Overall gain of the multistage amplifier (similar stages) G = 3 G1 = 3 43.17 = 129.4 d B. Ans.

Earlier it was stated that almost every electronic devices contains at least one stage of amplification. Many devices contain several stages of amplification and therefore several amplifiers. Stages of amplification are added when a singlestage will not provide the required amount of amplification. For example, if a single stage of amplification will provide a maximum gain of 100 and desired gain is 1000, two stage amplification will be required. The two stage might have gains of 10 and 100, 20 and 50 or 25 and 40. (The overall gain is the product of individual stages : 10 100 = 20 50 = 25 40 = 1000). Fig. 13.3 shows the effect of adding stages of amplification. As stages of amplification are added, the signal increases the final output (from the speaker) is increased.

545

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

Amplifier

Turntable

Speaker

Input

Output

Fig. 13.3 (a). Single stage amplifier.

Amplifier 1

Turntable

Amplifier 2

Input

Speaker

Coupling

Output

Fig. 13.3 (b). Two stage amplifier.

Turntable

Amplifier 1

Input

Amplifier 2 Coupling

Amplifier 3 Coupling

Speaker Output

Fig. 13.3 (c). Three stage amplifier.

Whether an amplifier is one of a series in a device or a single stage connected between other devices (as in Figs. 13.3(a) and (b)) there must be some way for the signal to enter and leave the amplifier. The process of transferring energy between circuits is known as coupling. There are various ways of coupling signals into and out of amplifier circuits. The following is a description of some of the more common method of amplifier coupling.

It should be always remembered that, all amplifier need some kind of coupling network. Even a single stage amplifier needs coupling to the input source and output level. Following types of interstage coupling are given below : 1. Resistance-capacitor (RC) coupling. 2. Impedance coupling. 3. Transformer coupling. 4. Direct coupling.

Fig. 13.4 shows a two-stage RC coupled transistor amplifier. The given circuit consists of two singlestage C-E transistor amplifiers. The resistors R 1, R2, RB and capacitor CC form the coupling network. The capacitor C1 is used to couple the input signal to the base of Q1, while the capacitor C2 is used to couple the output signal from the collector of Q2 to the load. The capacitor CE connected at the emitters of Q1 and Q2, are needed because they bypass the emitter current to the ground. without these capacitors, the voltage gain of each stage will be lost.

546

BASIC ELECTRONICS ENGINEERING & DEVICES VCC

R1

RL

RC

R1

CC

Cout

C1 Vin

R2

R2 RE

RE

CE

Input signal

CE

Coupling network

Fig. 13.4. RC coupled amplifier.

Operation : When the ac signal (i.e., input signal) is applied to the input of first stage, it is amplified by a transistor and appears across the first stage output. This signal is given to the input of second stage through a coupling capacitor C C. The second stage does further amplification of the input signal. Thus, we can say that the cascaded stages amplify the signal and the overall gain is equal to the product of the individual stage gains. It will be interesting to know that the output signal of two stage RC coupled amplifier is in phase with the input signal. It is because of the fact that its phase has been reversed twice by the amplifier. Analysis : Some assumption is to be made for the analysis of RC coupled amplifier. These assumptions are : (a) hre is so small so that voltage source hre Vo can be neglected. (b) The bias resistors (R1 and R2) value are usually large as compared to hie. (c)

1 h oe

is very large so it can be considered as open circuit.

(d) The reactance of CE is so small for any input frequency so the parallel combination of RE and CE can be effectively considered as short circuit. From the above assumptions, we simplified the equivalent circuit diagram as shown in Fig. 13.5. Ib

Vin

CC

Ic

hie

hfeIb

RL

hie

Vo

Fig. 13.5. Equivalent circuit (simplified) of RC-coupled amplifier.

For the purpose of analysis the entire frequency range may be divided into the following three categories : (i) Low frequency range (i.e., below 100 Hz)

547

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

(ii) Mid frequency range (i.e., above 20 KHz) (iii) High frequency range (i.e., between 100 Hz to 20 KHz). Let us discuss and analysis of low frequency ranges. (i) Low Frequency Range Analysis : For the low frequency range, the impedance offered by coupling capacitor is comparable with load resistance and it largely affect current amplification. Therefore, it is included in its equivalent circuit (in Fig. 13.6). After this apply the Thevenin theorem on the circuit and the equivalent Thevenin circuit become (as shown in Fig. 13.6). I

hie

Vin

CC

RL

+

hfeibRL

hie

Vo –

Fig. 13.6. Thevenin equivalent circuit.

From the above Figure,

h fe I b R L

...(13.5)

hie R L j / C C So the current gain for low frequencies is given by AiL =

h fe . R L I = Ib hie R L j / C C

...(13.6)

Output voltage Vo Vo = hie Current (I) =

h fe hie I b R L hie R L j / C C

Vin = hie Ib

Input voltage is

Voltage gain = AVL

...(13.7) ...(13.8)

h fe R L Vo = – Vin hie R L j / C C

...(13.9)

From the equation (13.9) we can see that in low frequency range voltage gain decreases with the decrease in frequency. (ii) Mid-frequency range Analysis : At mid-frequencies, the impedance offered by coupling capacitor CC is so small. So it can be effectively considered as short circuit. So capacitor CC can be neglected. So the equivalent circuit for the mid-range frequencies is shown in Fig. 13.7. Ib

Vin

hie

hfeIb

RL

hie

Jo

Fig. 13.7. Equivalent circuit for mid-range frequency.

548

BASIC ELECTRONICS ENGINEERING & DEVICES

and the Thevenin equivalent circuit as shown in Fig. 13.8. Ib

hie

Vin

RL

I

hfeIbRL

hie

Vo

Fig. 13.8. Thevenin equivalent.

Current (I) =

Current gain Aim =

h fe I b R L

...(13.10)

hie R L h fe R L I = Ib R L hie

...(13.11)

Input voltage Vin = hie Ib Output voltage Vo = hie I =

So voltage gain, AVm =

hie . h fe I b R L

...(13.12)

R L hie

b

hie h fe I b R L / R L hie Vo = Vin hie I b

g

h fe R L

...(13.13)

R L hie

The –ve sign means a phase changes of 180°. As from the above equation of current and voltage gains are equal. (Aim = AVm). (iii) High Frequency Range Analysis : In high frequency range, the reactance offered by coupling capacitor CC is very small and it may be considered as a shortcircuit. One most important factor that comes into picture at high frequencies is their capacitances. In the BJT, there are two depletion regions across the two P-N-junctions as shown in the Fig. 13.9. + VCC

RL CB

CC Vo

C

CC

Vin

E

Cw

2

Cw

1

CB

E

RE

CE

Fig. 13.9. BJT transistor capacitances.

549

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

Here, we consider three main inter capacitance as shown in Fig. 13.9. These intercapacitance and their effects are explained below as : CBC – Capacitance between the base and collector connects output with input. It makes the –ve feedback path. Due to this gain is reduced. This effect increase with increase in frequency because with increase in frequency reactive impedance of capacitor decreases. CBE – Capacitance between the base and emitter. It offers a low impedance path at the side of input at high frequencies. This reduces the input impedance of the device, so the input signal reduces and gain also reduced. CCE – Capacitance between collector and emitter, it produces a shunting effect at high frequencies on the output side. It is worthnoting point that C bc is most important capacitance because feedback takes place from output to input circuit through this capacitance. This is called miller effect. Cw , Cw – Capacitances of wiring which connects between connecting wires of 1 2 circuit and ground. The CBE and CBC is replaced with Cd across the input resistance hie of the transistor. The value of shunt capacitance (Cd) in the input circuit of the first stage is very small. But in the output circuit (Cd) is increased by the stray capacitance of wires. The reactance

1 will have sufficient shunting effect on R2 and hie. The C d

equivalent circuit at high frequencies shown in Fig. 13.10 and their Thevenin equivalent circuit in Fig. 13.11. Ib

Ic

Vin

hie

hfeIb

RL

hie

Cd

Vo

Fig. 13.10. Equivalent circuit at high frequencies.

Ic

Vin

hie

hfe .ib .

RLhie RL + hie RLhie RL hie

Cd

Vo

Fig. 13.11. Thevenin’s equivalent circuit.

R L hie h fe . I b . R L . hie R L hie (I) = = 1 R L hie 1 R L . hie R L hie j Cd R L hie jCd h fe . I b .

Current

Current gain, Ai

b

h

=

h fe . hie . R L I 1 Ib R L hie R L hie jCd

b

g

g

...(13.14)

...(13.15)

550

BASIC ELECTRONICS ENGINEERING & DEVICES

Input voltage

(Vin) = Ib hie

Output voltage

(Vo) = I . Vo =

1 j C d

b g 1 LMcbR . h g/bR h gh 1 OP j C j C Q N h fe . I b . R L . hie / R L hie L

Vo =

Voltage gain

A vh = Avh =

...(13.16)

ie

L

ie

d

h fe . I b . R L . hie

b

R L . hie . j C d R L hie

d

d

g

...(13.17)

Vo Vin

h fe . R L

...(13.18)

hie R L j C d . R L . hie

It is clear from above equation if frequency of input voltage increases, the voltage gain decreases. Lower cut-off frequency (f1) : The frequency at which the magnitude of the voltage gain in the low frequency range falls off to

1 or 0.707 times the maximum gain in 2

the mid frequency range is called lower cut-off frequency. Thus, | Avi | =

1 | Vvm | 2

...(13.19)

From the above equation, the magnitude of Av become 1

| Av l | =

h fe R L

b

hie R L

g FGH 21f C IJK 2

2

h fe . R L

L F bh R g MM1 G 2 f C bh1 R N H F h . R IJ | =G Hh R K ie

L

ie

and

| Avm

A A

L m

fe

ie

=

I OP g JK PQ

1 2

2

L

L

L

1

LM F 1 MN1 GH 2 f C bh

ie

RL

I g JK

2

OP PQ

...(13.20)

551

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

f 1 is the lower cut-off frequency. So equation become

1

1 = 2

LM L OP OP 1 1 M MN MN 2 f C bh R g PQ PQ L OP = 2 1 =1 + M MN 2 f C bh R g PQ 2

1

ie

L

2

1

1 2 f1 C hie R L

b

g

ie

L

=1

f1 =

1 2 C hie R L

b

...(13.21)

g

We get (from equation 13.20)

A

| Av L | =

m

b1 f / f g

2

=

1

where

tan l =

f1 or i = tan–1 f

A

b FG f IJ H fK

m

1 tan 1

g

...(13.22)

2

1

...(13.23)

So that total phase shift of the AvL is given by L = 180 + l 180 + tan 1

f1 f

...(13.24)

From equation (13.24), it is obvious that with the decrease in frequency l increases and f = f1 l = 180 + 45° = 225° So L increases above 225°, if f is further decrease. Upper cut-off Frequency ( f2) : The frequency at which the magnitude of the voltage gain in the high frequency range falls to

1 or 0.707 of the magnitude of the 2

gain in the mid-frequency range is called upper cut-off frequency. Thus, | Avh | =

A

m

...(13.25)

2

From the equation, the magnitude of Avh become | Avh | =

h fe R L

bh

ie

RL

g LMM1 FGH 2 f .hC .Rh N d

ie

ie L

. RL

IJ OP K PQ

1 2

552

BASIC ELECTRONICS ENGINEERING & DEVICES

and

| Avm | =

A vh

=

A vm

h fe . R L hie R L 1

LM1 F 2 f . C . h MN GH h R

. RL

ie

d

ie

L

IJ OP K PQ

...(13.26)

1

2 2

F2 is the upper cut-off frequency, so equation become

1 = 2

1

LM1 F 2 f . C . h . R I OP MN GH h R JK PQ L 2 f . C . h . R OP = 2 1 + M N h R Q 1

2 2

2

ie

d

ie

L

L

2

2

or

d

ie

ie

L

L

2 f2 . C d . hie . R L =1 hie R L f2 =

LM N

1 1 1 . 2 C d hie R L

OP Q

...(13.27)

From equation (13.26),

A A

h

1

=

m

LM1 F f I MN GH f JK FfI = tan G J Hf K 2

h

2

OP PQ

1

=

e1 btan g j 2

...(13.28)

h

–1

...(13.29)

2

H = 180° – h = 180° – tan–1

FG f IJ Hf K

...(13.30)

2

At

f = f 2, H = 180° – 45° = 135°

So H decrease below 135°. If f is further increase. Frequency response of RC coupled amplifier : The frequency response of an amplifier is nothing but a graph, which indicates the relationship between the voltage gain as a function of frequency. Generally, the voltage gain (in decibels) is plotted along the vertical axis and frequency along the horizontal axis of the frequency response graph.

553

Voltage gain (dB)

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER Low frequency Roll off

High frequency Roll off Flat Response

100 Hz 20 kHz Frequency (Hz)

Fig. 13.12. Frequency response of RC coupled amplifier.

It is evident from Fig. 13.12 that voltage gain drops off (or rolls off) at low frequencies and at high frequencies, while it remains constant in the mid-frequency range. The behaviour is discussed in more detail follows : (a) At low frequencies (i.e., below 100 Hz) : We know that the capacitive reactance (XC) is inversely proportional to the frequency. Thus, at low frequencies, the reactance of the capacitor CC is quite large. Therefore it will allow only a small part of the signal to pass from one stage to the next stage. Besides, this the emitter bypass capacitor (C E) cannot shunt the emitter resistor effectively, because of its large reactance at low frequencies. As a result of these two factors, the voltage gain rolls of at low frequencies. (b) At high frequencies (i.e., above 20 KHz) : In this frequency range, the reactance of CC becomes quite small, therefore it behaves like a short-circuit. As a result of this, the loading effect of next stage increases, which reduces the voltage gain. In addition to this, the capacitance of the emitter diode plays an important role at high frequencies. It increases the base current of the transistor due to which the current gain () reduces. Hence the voltage gain rolls off at high frequencies. (c) At mid-frequencies (i.e., between 100 Hz to 20 KHz) : The effect of coupling capacitor, in this frequency range is such that it maintains a constant voltage gain. Thus, as the frequency increases the reactance of CC decreases, which tends to increase the gain. However, at the same time, the lower capacitive reactance increases the loading effect of next stage due to which the gain reduces. These two factors almost cancel each other. Thus, a constant gain is maintained throughout this frequency range. Advantages of RC coupled amplifier It is the most convenient and least expensive multistage amplifier. It has a wide frequency response. It provides less frequency distortion.

Disadvantages of RC coupled amplifier Following are the disadvantages of RC coupled amplifier The overall gain of the amplifier is comparatively small because of loading effect

of successive stages. It has a tendency to become noisy with age, especially in moist climates. It provides poor resistance (or temperature) matching between the stages.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Note. RC coupled amplifier has an excellent frequency response from 100 Hz to 20 kHz. This property makes it very useful in the initial stages of all public address systems. However, it may be noted that a coupled amplifier can not be used as a final stage of amplifier because of its poor impedance matching characteristics.

Example 3. A two stage amplifier uses transistors of which the transistor-parameters are hie = 4.5 k and hfe = 330. If the load resistance, RL = 5.5 k, find the required value of the coupling capacitor C, so that the lower cut-off frequency is 50 Hz. Solution : Given : hie = 4.5 k ; RL = 5.5 k hfe = 330 ; f = 50 Hz We know that lower cut-off frequency f 1 is given by f1 =

1 2 C hie R L

g

C =

1 2 f1 hie R L

g

b

b

Put the given values in above expression, then we get C =

10 5 1 = F 3 2 3.14 5 2 314 . 50 4.5 5.5 10

a

f

–5

= 0.0319 10

F = 0.319 F. Ans.

Example 4. In two stage RC coupled amplifier the values for R1 = 2 k ; B = 80 and RC = 1.5 k . Calculate the voltage gain for first stage and overall voltage gain in dB. Solution : Given

R1 = 2 k RC = 1.5 k = 80.

As we know that there is loading effect on the first stage first we calculate effective load of first stage RAC = RC || R1 = =

R C R1 1500 2000 R C R1 1500 2000

3000000 = 857.15 . 3500

Voltage gain of first stage, G1 =

R AC R1

857.15 = 34.28 2000 G = G1 G2 ( Two stages) = 80

Overall gain (voltage)

Let us calculate G2, as there is no load effect on second stage ;

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MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

Voltage gain of second stage,

RC Ri

G2 =

1.5 = 60 2 Overall voltage gain = G1 G2 = 80

G = 34.28 60 = 2056.8 Overall voltage gain in dB = 20 log10 G = 20 log 2056.8 G = 66.28. Ans.

The circuit shown in Fig. 13.13 (a) is a two stage impedance-coupled amplifier using NPN transistor amplifier circuits. The impedance is coupling is different from RC coupling is that collector resistance RC of first transistor has been replaced by an inductor L. The inductor turns are wound on a iron core and shielded to avoid the interference of magnetic field with the signal + VCC

CC

R1

RC CC

R1

+

Cin

VS

R2

RE

CE

R2

RE

Vout

CE –

Fig. 13.13 (a). Two Stage Impedance-Coupled Transistor Amplifier.

The equivalent circuit of two-stage impedance coupled transistor amplifier is shown in Fig. 13.13 (b). B

Vin

R1

R2

C

1 1

B

L

B 1r e

E

R1

R2

C

1 2

B1r e

R1

R2 Vout

E

Fig. 13.13 (b). Equivalent Circuits.

All the capacitance have been considered as short circuit so voltage gain (first stage).

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BASIC ELECTRONICS ENGINEERING & DEVICES

Av = i

R ac1

= XL|| R1||R2||B2r 1e2

r1e1

...(i)

XL >> R1||R2||Br 2e2

For

Av = R1||R2||B2r 1e2 1

Voltage gain (second stage) Av =

R ac2

2

=

re1 2

R c ||R L r1e2

Advantage of Impedance Coupling (i) This type of coupling results in more efficient amplification because no signal power is wasted in inductor. Disadvantage of Impedance Coupling (i) It is heavier, costlier and larger than the RC coupling.

The circuit shown in Fig. 13.14 (a) is a two-stage transformer coupled amplifier. The circuit consists of two single stage common emitter transistor amplifiers. The Resistor RC is replaced by the primary winding of the transformer. Note that in this circuit there is no coupling capacitor. The dc isolation between the two stages is provided by the transformer itself. There is no existence of the dc path between the primary and secondary windings of a transformer. However, the ac voltage across the primary winding is transformed to the secondary winding. The main advantage of the transformer coupling over RC coupling is that all the dc voltage supplied by VCC is available at the collector. There is no voltage drop across the collector resistor RC. The dc resistance of primary winding is very low. Operation : When the input is applied to the base of transistor Q1, its amplified output is appears across the primary winding of transformer T 1, due to the sufficient magnetic induction, it is passed to the secondary. After this the output of secondary T 1 is applied to the base of transistor Q2. The amplified output appears across the primary of the transformer T2. + VCC T2

T1 R1

R1

VO Q1 VS R2

RE

Q2 CE

R2 RE

CE

Fig. 13.14 (a). Two stages using CE transistors, are coupled by a transformer.

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MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

Analysis : For the analysis of transformer coupling the equivalent circuit of the above Fig. is shown in Fig. 13.14 (b). Ic

1

Ib

1

2

(hfe )ib

1

Ib

hoe

1

(hie)

1

hie

1

First stage

2

Second stage

Fig. 13.14 (b). Equivalent circuit of transformer coupled amplifier.

Let k be the transformer ratio of the transformer, then k =

I1 N2 = I2 N1

...(13.31)

d i to the first stage. The

Let us consider the input impedance of second stage hie2

transformer with turn ratio k reflects a load impedance Z to the primary equal to a

Z . By considering this fact, let us again draw the simplified equivalent circuit k2 diagram becomes (as shown in Fig. 13.15). value

Ic

1

1

1

(hie )(Ib )

Ib

1

hie 2

hoe

1

hie

1

K2

Fig. 13.15. Equivalent circuit (simplified).

The impedance (output) of first stage hoe1 and effective load transferred from second stage is

hie2 k2

.

For maximum power transfer, these two should be equal, so equation is

hie 1 = 22 k hoe1

hie2

FG N IJ HN K

2

2

=

FG N IJ HN K 1 2

2

hie2

...(13.32)

1

N1 = N2

1 hoe1 . hie2

So we can calculate the current gain at mid-frequency range. K =

I b2 =

Ic I1 = 1 I2 I b2

I c1 K

N1 Ic N2 1

d i

...(13.33)

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BASIC ELECTRONICS ENGINEERING & DEVICES

The current I c1 through the primary will be Hence,

I b2 =

N1 N2

FG h H

. I b1

fe1

2

h fe1 . I b1

IJ K

2

(for matched conditions)

So current gain is given by

I b2 I b1

=

N1 h fe1 N2 2

...(13.34)

The current gain is several times as large as the gain of RC coupled amplifier. Example 5. A load of 20 is to be matched with a source that has an output impedance of 10 k. Calculate (i) the transformer turn ratio so as to transfer maximum power to the load. (ii) the load voltage if source voltage is 8 V Solution : Load impedance, ZL = 20 Source impedance,

ZS = 10 k = 10,000 ZS = K2 ZL

where K is ratio of primary to secondary turns K2 =

ZS 10000 = = 500 20 ZL

K =

500

K = 23 Load voltage

VL = V2 =

V1 VS 8 = 0.348 V. Ans. K K 23

Advantages of Transformer Coupled Amplifier Following are the advantages of transformer coupled amplifier : No signal power is lost in the collector or base resistors, because of the low

winding resistance of the transformer. It provides a higher voltage gain than the RC coupled amplifier. It provides an excellent resistance (or impedance) matching between the stages.

The resistance matching is desirable for maximum power transfer. Disadvantages of Transformer Coupled Amplifier Following are the disadvantages of transformer coupled amplifier : The most obvious disadvantage is the increased size of the system. The transformer

is very bulky as compared to a resistor or a capacitor. It is also relatively costlier. At radio frequencies, the winding inductance and distributed capacitance produces

reverse frequency distortion. It tends to produce “hum” in the circuit.

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MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

Frequency response of transformer coupled amplifier Fig. 13.16 shows the frequency response for a transformer coupled transistor amplifier. From Fig. 13.16, it is clear that voltage gain (in d B) drops off at low as well as at high frequencies, whereas it remains constant in mid-frequency range. Another noticeable feature is that at one particular frequency (f 0) the voltage gain increases and then rolls off continuously. Resonant rise Flat response

High frequency Roll off

Voltage gain (dB)

Low frequency Roll off

Frequency (Hz)

Fig. 13.16. Frequency response of a transformer coupled amplifier.

Now, we will discuss this typical behaviour – as we know that output voltage of a transformer coupled amplifier is equal to the product of the collector current and the reactance of the primary winding of coupling transformer. At low frequencies, the reactance of primary winding (XL = 2f L) begins to decreases and hence the voltage gain reduces. At high frequencies, the effect of leakage inductance and distributed capacitance becomes significant and hence the voltage gain reduces. The peak gain results due to resonance (or turning) effect of inductance and distributed capacitance, which forms a resonant circuit. The frequency at which the peak, occurs is called resonant frequency ( f 0 ). It has been found that the flat part of frequency response curve of transformer coupled amplifiers is small as compared to that of RC coupled amplifier. As a result of this, these amplifier, cannot be used over a wide range of frequencies. Besides, this if they are used, they produce frequency distortion, which means that all the frequency components in a complete input signal are not equally amplified.

The amplifier used for amplification of very slowly varying signal makes use of direct coupling. The range lies below 10 Hz. In this case it is to be noted that the capacitors, inductors and transformers cannot be used as a coupling network at very low frequencies because the electrical size of these devices, at low frequencies becomes very large. Fig. 13.17 shows a two stage direct coupled amplifier. It is to be noted that the output of the first stage is directly connected to base of the next transistor. Moreover, there are no input or output coupling capacitors. R 1, R2, RC and RE form biasing network.

560

BASIC ELECTRONICS ENGINEERING & DEVICES + VCC R1

RC

R1

RC VO

Q1 Input signal

R2

RE

Q2 R2

RE

Fig. 13.17. Two stage direct coupled amplifier.

The signal to be amplified is applied directly to the input of the first stage. Due to the transistor action, it appears as the amplified form across the collector resistor or transistor Q1. This voltage then drives the base of second transistor Q2 and the amplified output is obtained across the collector resistor of transistor Q 2. Frequency response of direct coupled amplifier : Fig. 13.18 shows the frequency response of a direct coupled amplifier. It is evident from Fig. that the gain is uniform up to a certain frequency denoted by f 2. Beyond this frequency, gain rolls off at high frequencies due to increased emitter diode capacitance and stray wiring capacitance. Flat response Voltage gain (dB)

High frequency roll off

0

f2 Frequency

Fig. 13.18. Frequency response of direct coupled amplifier.

Advantages of Direct Coupled Amplifier Following are the advantages of direct coupled amplifier : The circuit arrangement is very simple because it uses a minimum number of

resistors. The circuit cost is low because of the absence of coupling devices. It can amplify very low frequency signals down to zero frequency.

Disadvantages of Direct Coupled Amplifier Following are the disadvantages of direct coupled amplifier : It cannot amplify high frequency signals. It has a poor temperature stability because of this Q-point shifts. In a multistage

direct coupled amplifier, the Q-point is amplified in succeeding stages. Thus, a small dc shift in the first stage can cause the final stage to be either saturated or cut-off. All integrated circuit amplifiers are direct coupled because of the difficulty of fabricating large integrated capacitors. It leads to special problems in their design.

561

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER Comparison of different types of couplings S.No.

Type of couplings/ Particular

RC coupling

1.

Size and weight

Small

2.

Cost

3.

Transformer coupling

Impedance coupling

Direct coupling

Large and bulky

Larger and heavier than RC coupling

Very small

Small

Costlier

Costlier than RC coupling

Very small

Frequency response

Excellent in the audio frequency range

Poor

Good

Best

4.

Impedance matching

Not good

Excellent

Not good Unsuitable

Good

5.

Uses

For voltage amplification

For power amplification

For frequencies beyond audio range

For amplification of extremely low frequency signals

The circuit diagram of common emitter is shown in Fig. 13.19. Where R1, R2 are the biasing parameter. C C is the coupling capacitance. Now, here we are interested to know what is the effect of coupling capacitor on low frequency. We know that, XC =

1 thus, it is 2 f C

clear that on low frequency the voltage drop across the coupling capacitor increases which results decrease in the magnitude of the input signal. Also we know that V0 = A Vin means output voltage decreases.

+ VCC RC C C

R1 CC RS VS

B R2

VO

C E RE

CE

Fig. 13.19. Common emitter amplifier given with coupling capacitor CC.

The circuit diagram of a common-collector transistor amplifier is shown in Fig. 13.20. This configuration is also called the emitter follower because its voltage gain is close to unity, and hence change in base voltage appears as an equal change across the load. In other words, we can say that emitter follows the input signal. It is shown that input impedance Ri of an emitter follower is very high (approximately hundred of kilo ohms) and the output resistance R0 is very low (approximately tenth of ohm). Hence the most common use for the common collector (CC) or emitter follower circuit is as a buffer stage (or in impedance matching) which performs the function of

562

BASIC ELECTRONICS ENGINEERING & DEVICES

resistance transformation (i.e., from high to low resistance) over a wide range of frequencies, with voltage gain close to unity. In addition emitter follower increases the power level of the signal. IC

RS

C

IB

VCC

B E VS

+

+

Vi

IL = I E

–

RL

Ri

Vo

Ro

Fig. 13.20. A common collector, or emitter follower configuration.

Main Characteristics of Emitter Follower : (i) It has a voltage gain value close to unity (i.e.,

1)

(ii) It has high input impedance ( 10 – 30 k) (iii) It has low output impedance ( 5 – 20 ) (iv) There is no phase shift between output and input in either voltage or current. (v) It increases the power level of the signal. Expression for current gain, input resistance, voltage gain and output resistance of emitter follower : (i) Current gain : AI =

– h fc 1 h fe IE = IB 1 hoc R L 1 hoc R L

...(13.35)

Vi = hie + hrc AI RL hie + AI RL IB

...(13.36)

(ii) Input resistance Ri =

( hrc ~ — 1) (iii) Voltage gain Av =

V0 Ai R L R hie h = = i = 1 – ie Vi Ri Ri Ri

...(13.37)

(iv) Output resistance Z0 =

d

i

1 h fe h fc hrc 1 where Y0 = hoc – = hoc Y0 hie R S hie R S

b

g

...(13.38)

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MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

As emitter follower does in BJT (Bipolar Junction Transistor) source follower in FET (Field Effect Transistor). Source follower is also called a common drain amplifier. The output voltage of a source follower (or common drain) amplifier is approximately equal to and in phase with the input voltage. Because of this fact, the source follows the input signal. The circuit arrangement for source follower are shown in Fig. 13.21. VDD D CC

G

S VS

VO

RG RS

Fig. 13.21. Common drain or source follower configuration.

It is also called high-input resistance transmitter circuit. In some applications we require an amplifier with a high input impedance. For input resistances smaller than 500 k, the emitter follower is taken into consideration. However, to achieve larger input impedances, the circuit shown in Fig. 13.22 called the Darlington connection is used. Darlington pair is nothing but a cascade connection of two common collector transistors. Basically a Darlington pair is a three terminal device namely Base (B), Emitter (E) and Collector (C). It acts like a transistor, with an extremely high current gain in which both the collectors are coupled to the VCC supply. The Darlington pairs are available for both npn and pnp transistors.

+ VCC

B1

C1

C2

Q 1 E1 B2

Q 2 E2

Fig. 13.22. npn transistor darlington.

The Darlington composite emitter follower will be analysed by referring to Fig. 13.23. Derivation for input impedance, output impedance, current gain and voltage gain for a Darlington connection before starting the derivations, we assume hoe RE < 0.1

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BASIC ELECTRONICS ENGINEERING & DEVICES + VCC

Ii = I b

C1

B1

C2

I2 = (1 + hfc)Ib E1

Rs

B2 Q2 E2

Vi VS

V0

V2

+

RE

–

Ri

R0

Fig. 13.23. Darlington emitter follower.

Derivation for Current Gain Here it is interesting to note that to calculate the current gain of any cascaded amplifier. First of all we must analyse the last stage (i.e., here second stage, which will be discussed, in more detail latter) Current gain of second stage :

A i2 =

h fc 1 hoc R L

d1 h i fc

1 hoc R E

{ RL = RE ; hfc = – (1 + hfc)}

d1 h i fc

or

A i2

or

A i2 (1 + hfc) Now,

=

[ hoc RE < 0.1]

1

R i2 = hic + A i2 hrc RL

{we can neglect hic since the current gain of C-C is very high} or,

R i2 (1 + hfc) . RE

so,

A i1 =

or

A i1 =

h fc

{RL = RE}

1 hoc R i2

d1 h i 1 h d1 h i R d1 h i 1 h R d1 h i fc

oc

or

A i1

{hrc 1 A i2 = 1 + hfc

E

fc

fc

oc

E

fc

565

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

Current gain of Darlington pair : AI = A i1 A i2 or

AI =

d1 h i d1 h i 1 h R d1 h i d1 h i fc

fc

oc

E

fc

2

or

AI =

AI =

fc

1 hoc R E hoc R E h fc

d1 h i

2

fc

...(13.39)

1 hoc R E h fc

{neglecting hoc RE < 0.1}

Equation (13.39) represents the current gain of a Darlington pair. For the standard values of hybrid parameter. Ai for this configuration is found 427, and for the single stage common collector configuration it is about 50. It means Darlington pair has more current gain compared to the single stage emitter follower. Derivation for Input Impedance of Darlington Pair Input impedance, Ri = hic + A i1 + R i2 hrc or

Ri = hic +

or

d1 h i . d1 h i R 1 h h R fc

oc

fc

d1 h i

2

fc

Ri = hic +

d1 h h d1 h i . R oc

fc

fc

E

. RE . RE

E

.1

i

2

Ri

fc

E

1 hoc h fc R E

...(13.40)

From equation (13.40), it is clear that input impedance of Darlington pair is very high. Derivation for Voltage Gain

A 2= 1 – A But,

1

= 1 –

hie2 R i2 hie1 R i1

Ri = hie + hrc . A i1 . R i2 hrc + A i1 . R i2 .

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BASIC ELECTRONICS ENGINEERING & DEVICES

R i1

d

i

1 1 h fc . R i2

d1 h

i

h fe R E

oc

From figure since the transistor is CC so input voltage must be equal to output voltage. Ib . hie1 = (1 + hfc) hie2 Ib

i.e.,

hie1 = (1 + hfc) hie2

or Now,

Avi =

hie1

d1 h i R fc

i2

d1 h h R i d1 h i h d1 h h 1 – d1 h i R h d1 h . h . R i 1 – oc

E

fc

ie2

fc

oc

fc

ie2

oc

fe

RE

i

i2

fe

E

R i2

So, overall voltage gain, Av = A 1 A or

Av =

R| h d1 h S|1 R T

Av = 1 –

ie2

hic2 R i2

oc

2

h fc . R E

i2

i U|V |RS1 h |W |T R

[2 + hoc hfc RE]

ie2

i2

|UV |W ...(13.41)

Derivation for Output Impedance Output admittance is given by relation.

h fc . hrc

YO 2 = hoc –

YO 2 = hoc

or

where

But,

hie2 R S

d1 h i . 1 fc

hie2 R S

RS = R O1 =

YO1 = hoc YO1 = hoc

1 YO1 h fc hrc

hic R S

d1 h i . 1 fc

hic R S

...(13.41(a))

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MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

YO1

d1 h i fc

hic R S

RS = R O1 =

h RS 1 = ie YO1 1 h fc

d

i

Now, on putting the value of RS in equation (13.41(a)), we have

hie2 or

YO 2

d1 +h i d1 h i h fc

YO 2

fc

ie1

RS

1 h fc

b1 +h g fc

RS 1 h fc

hie2 hie2

d1 +h i 2 h d1 h i R d1 h i 2

or

YO1

fc

ie2

fc

S

2

or

YO1

so,

R O2 =

fc

{ hie1 = (1 + hfc) hie2 }

2 hie1 R S

d

i

2 1 +h fc R S

d1 h i

...(13.42)

2

fc

We conclude from equation (13.42) that the Darlington emitter follower has a higher input resistance and a voltage gain less closer to unity than a single stage emitter follower. The output impedance of the Darlington circuit may be greater or smaller than that of a single transistor emitter follower, depending upon the value of RS relative to hie . If RS = 0, then RO for the Darlington combination is twice R O for a 2 single stage emitter follower. + VCC

R1 C B E VS R2

RE

+ VO –

Ri

Ri

Fig. 13.24

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BASIC ELECTRONICS ENGINEERING & DEVICES

Advantages of Darlington Pair Following are the advantage of Darlington Pair : It provides very high value of current gain () approximately 400. The circuit arrangement is very simple as very few components are used. It posses excellent impedance transformation capability i.e., it can transform a

high impedance source to low impedance load. Hence, it is used in a high gain operational amplifier which depends on very high input impedance for its operation as an integrator or summing amplifier. Disadvantages of Darlington Pair The major disadvantage of Darlington transistor pair is that the leakage current of first transistor is amplified by the second. Hence, the overall leakage current may be high and hence a Darlington connection of three or more transistor is usually impractical.

We have just discussed the analysis of different parameters for Darlington pair connection, and seen that input impedance of Darlington pair was very high. However, biasing problem, results in decrement in the input impedance of Darlington connection. This difficulty can be overcome by using a bootstrapping circuit. Thus, in reference to the Darlington pair Bootstrapping is nothing but an improvement of input impedance in the Darlington pair. The circuit which provides this facility is called Bootstrapping circuit. Fig. 13.24 shows the typical biasing network of resistors R1, R2 and RE. The input resistance R i of this stage (procedure will be discussed latter) is Ri || R, where R = R1 || R2. i.e.,

R 1 = R1 || R

or

R i = Ri || R1 || R2

...(13.43)

From equation (13.43), it is clear that since Biasing resistors are in order of k, therefore the resultant input impedance decreases, or in other words we can say biasing create a problem that reduces the input impedance. We get resultant input impedance of the order of k. To overcome the decrease in the input resistance due to the biasing network, the input circuit of Fig. 13.25 is modified by the addition of C between the emitter and the junction of R1 and R2. The capacitance C is chosen large enough to act as a shortcircuit at the lowest frequency under consideration. The bottom of R 3 is effectively connected to the output (the emitter), whereas the top of R 3 is at the input (the base). Since the input voltage is Vi and output to voltage is V0 = Av Vi, by using A.C. equivalent model of Fig. 13.15 and applying Miller theorem (which will be discussed in detail). The biasing arrangement R1, R2 and R3 represents an effective input resistance of : Reff =

R3 1 Av

...(13.44)

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MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER + VCC

R1 C B + Vi

E

C

R3

+

R2

RE

–

VO –

Ri

Ri

Fig. 13.25

since, for the emitter follower, Av approaches unity, Reff becomes extremely large. For example, with Av = 0.995 and R3 = 100 k, we find Reff 20 M. The above effect, when Av + 1, is called Bootstrapping. The term arises from the fact that, find one end of the resistor R3 changes in voltage, the other end of R3 moves through the same potential difference ; it is as if R3 were “pulling itself up by its bootstraps”. The input resistance of the CC amplifier is Ri =

hic i.e., increased input resistance of the common 1 Av

collector (CC) configuration.

Why we need a tuned amplifier : As we know that audio amplifier which operate between (20 Hz to 20 kHz) and radio frequency amplifiers which operate between (a few kHz to hundred of MHz). We can operate audio amplifiers at radio frequencies. But there are some drawbacks in it. They are : They become less efficient at audio frequencies. Their gain is dependent of signal frequency over a large bandwidth because of

resistive load. These amplifiers are not capable of selecting a particular frequency while rejecting all other frequencies. Sometimes, we need to select a particular frequencies and their amplification for a special application. When radio frequency signals from different broadcasting stations reach the receiving antenna, a weak signal is induced in it. To extract the original audio signal from the receiver, it is necessary to amplify it. This is achieved by tuned amplifier. So tuned amplifier can be defined as “The amplifiers which amplify a narrow band of frequencies signal are called tuned amplifiers”. Such amplifiers are widely used in radio and TV circuits where radio frequency signals are to be handle. So we need to employs a tuned circuit in a tuned amplifier (as shown in Fig. 13.26). The tuned circuit is capable of selecting a particular or relatively narrow band of

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BASIC ELECTRONICS ENGINEERING & DEVICES

frequencies with the phenomenon called resonance. The centre of the frequency band is the resonant frequency of the tuned circuit.

L

C

Fig. 13.26. Tuned circuit.

So before the discussion of tuned amplifiers let us discuss tuned (resonant) circuits and their analysis in more detail. Tuned (Resonant) Circuits There are two types of tuned (resonant) circuits : (i) Series tuned circuits (ii) Parallel tuned circuits Both types of circuits consists of resistance, an inductance L and capacitance C with two elements connected in parallel or in series to form parallel tuned circuits and series tuned circuits respectively. Analysis of series tuned circuits Consider a series RLC circuit shown in Fig. 13.27. R + + –

VR

L –

+

VL

C –

+ – VC

VS

Fig. 13.27. RLC Series Circuit

The total impedance for series RLC circuits is ZS = R + j (XL – XC) = R + j I =

FG L – 1 IJ H CK

VS ZS

The circuit is said to be resonance if the current is in phase with applied voltage of if XL = XC (for series). The frequency at which the resonance occurs is called the resonant frequency. At the resonance xL = XC i.e., L =

1 C

571

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

At resonant frequency, the voltage across capacitance and inductance are equal in magnitude, but they are 180° out of phase with each other. They cancel each other, and so the zero voltage appears across the LC combination. If we solve the above equation, we get XL = XC L = or

1 C

2f r L =

1 2 fr C

fr2 =

1 4 LC

fr =

1 2 LC

2

In RLC series circuit, the resonance effect can be obtained by varing the frequency and kept L and C constant. Resonance curves : The resonance curve shows the variation of impedance and current with frequency in Fig. 13.28.

Z impedance

Current fr

Fig. 13.28. Resonance Curve.

At resonant frequency, the capacitive reactance is equal to inductive reactance, and impedance is minimum. The maximum current flows through the circuit. At the zero frequency, the capacitor acts as an open circuit and block current. The complete sources voltage appears across the capacitor. If we start to increase the frequency, the XC decreases and XL increases, causing total reactance (X C – XL) to decreases. Due to decrease in impedance the current increases, VR also increases, and both VC and VL increases. If the frequency reaches its resonant frequency value f r, the impedance is equal to R, hence the current reaches its maximum value, and V R is at its maximum value. If the frequency is increased above resonance, X L increases continuously and XC decreases continuously. It causes the total reactance X L – XC to increases. As a result there is increase impedance and a decrease in current if the current decreases, V R decreases and VC and VL also decreases. As the frequency becomes very high, the current reaches to zero, both VR and VC also reaches zero, VL approaches VS.

572

BASIC ELECTRONICS ENGINEERING & DEVICES

Bandwidth of RLC (Tuned Series Circuits) The bandwidth of the system is defined as the range of frequencies for which the current or output voltage is equal to 70.7% of its value at resonant frequency.

I

·707

f1

fr

f2

f

Band width

Fig. 13.29. Bandwidth of Tunned Series Circuit.

As Fig. 13.29 shows a typical tuned (resonant) circuit. The circuit current is equal to or greater than 70.7% of maximum current

FI H

r

V R

I K

between frequency f 1 to f 2.

Example 6. A circuit contain a coil of inductance 10 H and resistance 18.2 and connected in series with a capacitor of 2530.3pF. Calculate (a) resonant frequency ( f r ). (b) Voltage across resistance (VR), inductor (VL ) and capacitor (VC ) at resonance. (c) Q factor. Assume the impressed voltage to be 0.182 volts. Solution :

Given

L = 10 H, 10 10–6 H R = 18.2 C = 2530.3pF = 2530.3 10–12

(a) Resonant frequency for the series circuit is given by fr =

1 1 = = 1 MHz. 6 2 LC 2 10 10 2530 10 12

(b) Current at resonant frequency Ir =

V 0.182 = = 0.01 Ampare. R 18.2

VR = Ir R = 0.01 18.2 = 0.182 V VL = Ir XL = Ir 2f r L = 0.01 2 106 10 10–6 = 0.6283 V VC = I r X C = I r .

1 2 fr C

573

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

=

Q-factor Q =

0.01 = 60.283 V 2 10 2530.3 10 2 6

XL 2 10 6 10 10 6 = = 3.45. (Approx). R 18.2

The quality factor (Q) and its effect on band width (B.W) The quality factor, Q is the ratio of the reactive power in the inductor or capacitor to the true power in the resistance (series) with a inductor or capacitor. Qfactor = 2 Q =

Maximum energy stored Energy dissipated per cycle

L 1 = (for series circuits) CR R fr BW

The relation between band width and Q factor is given as Q = Hence, higher the value of Q, the smaller is the B.W. Parallel tuned circuit

In a parallel resonance or tuned circuit consist of an inductor (coil) and capacitor are connected in parallel across an ac source as shown in Fig. 13.30. The parallel resonant circuit is generally known as tank circuit. Because the circuit stores energy in the magnetic field of the coil and in the electric field of the capacitor. C

RL

IL

Fig. 13.30. Parallel Tunned Circuit.

The circuit is said to be resonant condition, if the susceptance part of admittance is zero. The total admittance (Y) of circuits is given : Y =

1 1 RL j X L j XC

Simplified form of above equation is Y =

RL j XL j R = 2 L 2 + j 2 2 RL XL XC RL XL

LM 1 NX

C

R 2L

XL X 2L

OP Q

574

BASIC ELECTRONICS ENGINEERING & DEVICES

The susceptance part is zero to satisfy the condition of resonance :

1 X = 2 L 2 XC RL XL C =

R 2L

L 2 L2

From the above equation,

R 2L 2 L2 = 2L2 = 2 = =

L C L R 2L C

1 R2 2L LC L

1 R2 2L LC L

The resonant frequency for the tank circuit is fr =

1 R2 2L LC L

1 2

Usually, the resistance of inductor is very small so we can neglect the value 2

R , we get L2

Resonant

fr =

1 2 LC

.

Resonance Curve : The impedance of a parallel tuned (resonant) circuit is maximum of f r and decreases at lower and higher frequencies as shown in Fig. 13.31. L Zr = RC

X L > XC

X L = XC XL < XC

fr

f

Fig. 13.31. Resonance Curve

Sharpness of resonance The resonance curve, of a resonant circuit, is required to be a sharp as possible in order to provide a high selectivity. The sharp resonance curve means that the impedance falls off rapidly as the frequency is varied above and below the resonant

575

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

circuit frequency. Mathematically, the sharpness of a resonance curve is defined as the ratio of the bandwidth of the circuit to its resonant frequency i.e., sharpness of resonance. Sharpness =

BW f2 f1 1 fO fO QO

Band width = Resonant frequency

where QO is called the quality factor or simply Q-factor of the circuit at resonance. Mathematically,

XL . L 2 fO . L = O R R R L = Value of circuit inductance

QO = where

R = Value of circuit resistance or coil resistance. Small R Medium R

Impedance

Large R

Frequency

Fig. 13.32. Effect of coil resistance (R) on the sharpness of resonant curves.

Thus, we conclude that a higher value of quality factor provides a higher frequency selectivity, but a smaller bandwidth, whereas a lower value of quality factor provides a poor selectivity but a larger bandwidth. Example 7. A tank circuit (parallel) has an inductor of 15 H and capacitor of 1000 pF and the resistance of inductor is 50 . Calculate (a) Resonant frequency ; (b) Impedance at resonance ; (c) Q-factor and (d) Band width (BW). Solution : Given :

L = 15 H = 15 10–6 H R = 50 C = 1000 pF = 10 10–12 F

(a)

fr =

1 2 LC

1 2 5 10

6

1000 1012

= 1299.5 kHz (b)

Zr =

(c)

Q =

(d)

BW =

15 10 – 6 L = = 300 CR 1000 10 12 50

2 fr L 2 1299.5 10 3 15 10 6 = R 50 = 2.452.

fr 1299.5 10 3 = = 519 kHz. Ans. Q 2.5

576

BASIC ELECTRONICS ENGINEERING & DEVICES

Fig. 13.33 shows the circuit of single tuned voltage amplifier using BJT for low frequency applications. For microwave range we should go for FET or vacuum tubes like pentodes etc. Fig. 13.33 (a) is called capacitively coupled tuned amplifier because the output is taken through a coupling capacitor CC. Similarly, the circuit shown in Fig. 13.33 (b) is called inductively coupled tuned amplifier because the output is taken across an inductor. + VCC

+ VCC

R1 C

L

CB

VS

R1 C CB

CC VO

R2

R2

VS

CE

RE

VO

RE

CE

(b) Inductively coupled

(a) Capacitively coupled

Fig. 13.33. Single tuned voltage amplifier.

Both these circuits consist of transistor amplifier and tuned circuit is load. The values of capacitance (C) and inductance (L) of the tuned circuit are selected in such a way that the resonant frequency of the circuit is equal to the frequency to be selected and amplified. The resistors R1, R2 and RE are called biasing resistors. They provide necessary biasing voltage from VCC to the transistor. The resonant frequency of the circuit of the amplifier is made equal to the frequency of the input signal to be amplified. BW A

B

Voltage gain (Av) f1

f0

f2

Frequency (Hz)

Fig. 13.34. Bw Curve for Single Tuned Voltage Amp.

The voltage gain

AV =

rL Ri

r L = ZP =

L CR

577

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

L CR Ri

AV =

and

bandwidth, BW = f = f 2 – f 1 =

fO QO

Fig. 13.35 shows the circuit of a double tuned voltage amplifier. It consists of a transistor amplifier with two tuned circuits. + VCC

R1

C1

L1

L2

+ VO

C2

–

CC

VS

R2

CE

RE

Fig. 13.35. Double tuned voltage amplifier.

One of the tuned circuits (L1, C1) is shown as the collector load and other (L 2, C2) as the output. The resistors R1, R2 and RE are used to set-up Q-point for the transistor operation. The signal to be amplified is applied at the input terminal through the coupling capacitor CC. The resonant frequency of the L1 C1 is made equal to that of the signal by adjusting L1 or C1. Under these conditions, the tuned circuit offers a very high impedance to the input signal. As a result of this, large output appears across the tuned circuit L1 C1. The output from this tuned circuit is inductively coupled to the L 2 C2 tuned circuit. The frequency response of double tuned circuit depends upon its degree of coupling. The degree of coupling gives an idea of the amount of energy transferred between two tuned circuits.

Av

Av

fo

fo

fo

Av

fo

fo

Frequency

Frequency

Frequency

(a) Tight coupling

(b) Critical coupling

(c) Loose coupling

Fig. 13.36. Frequency response of double tuned circuit with different degrees of coupling.

578

BASIC ELECTRONICS ENGINEERING & DEVICES

It has been observed that if two or more tuned circuits, which are synchronously tuned are cascaded, the overall bandwidth decreases. However, if the different tuned circuits, which are cascaded, are tuned to slightly different frequencies, it is possible to obtain an increased bandwidth with a flat passband with steep sides. This technique is used in stagger-tuning. + VCC

R1

+ VCC

C1

L1

C1

L2

CC

CC

VS

R1

R2

CC

R2 RE

RE

VO

CE

Fig. 13.37. Staggered tuned voltage amplifier circuit.

At very low frequencies, XC become very small and XL is very large so total impedance is inductive in nature. As frequency (f) increases impedance (z) also increases. After that XL = XC, the impedance is max at this point. So current is very less at this point which satisfying the resonance. As the frequency further increases the capacitive reactance dominate and impedance starts decreasing.

Summary 1. There are different types of coupling namely Resistance Capacitor Coupling, impedance coupling, transformer coupling and direct coupling. 2. Cascaded arrangement is one in which output of one stage is coupled with the input of the next stage. 3. A transistor in which a number of amplifier stages are in succession is called a multistage amplifier. 4. R-C coupled amplifier has a wide range of frequency response. 5. R-C coupled amplifier provides less frequency distortion. 6. Transformer coupling is the best coupling because there is no power is lost in the collector base resistors, because of the low winding resistance of the transformer. 7. The main functions of a coupling device is to transfer only ac output of one stage to the input of the next stage and to block dc components and isolate the dc conditions of one stage from the other stage. 8. Direct coupled amplifier usually used to amplify very low frequency signal. 9. Transfer coupled amplifier usually used to amplify very high frequency signal. 10. Overall gain of a multistage amplifier is equal to the product of gains of individual stages. i.e.,

A = A1 A2 A3 An.

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

579

11. Decibel is the common logarithm (log to the base 10) of power gain is known as bel power gain i.e.,

Pout bel. Pin

A = log10 12. Number of bels = log10 13. In d B,

Pout Pin

power gain = 10 log10

Pout dB Pin

voltage gain = 20 log10

Vout dB Vin

current gain = 20 log10

I out d B. I in

14. Gain of multistage amplifier in d B is equal to the sum of decibel gains of the individual stages. A (dB) = A1 d B + A2 d B + A3 d B + ... An d B. 15. Frequency response, the curve drawn between voltage gain and signal frequency of an amplifier is known as its frequency response. 16. Bandwidth may be defined as the range of frequency over which the gain of an amplifier is equal or greater than 70.7% of its maximum gain is known as band width. 17. Higher or upper - 3d B frequency of n-stage amplifier is given as

21/n 1

fH* = f H where

f H = initial frequency

fH* = frequency after n-stages n = number of stages 18. Lower - 3d B frequency of n-stage amplifier is given as

fL* = where

fL 1/ n

2

1

f L = lower initial frequency

fL* = lower initial frequency after n-stages n = number of stages. 19. There is a shrinkage (decrease) of a bandwidth by using a cascaded amplifier. 20. A common collector configuration is also called emitter follower because its voltage gain is close to unity. In other words we can say that emitter follows the input signal. 21. Common drain amplifier is called source follower. 22. Emitter follower (C-C configuration) has very high input resistance and low output resistance. 23. Darlington pair is nothing but a cascade connections of two common collector transistor, which passes very high input impedance and very high current gain.

580

BASIC ELECTRONICS ENGINEERING & DEVICES 24. The major disadvantage of darlington transistor pair is that the leakage of current of first transistor is amplified by the second. Hence, the overall leakage current may be high a Darlington connection of three or more transistor is usually impractical. 25. The final stage of an audio or multi-stage amplifier is power amplifier. 26. The range of audio frequency is lies between 20 Hz to 20 kHz. 27. Small signal transistor tured amplifiers amplify small signals at radio frequencies. Power involved is small. They are operated under class-A condition so that distortion is negligibly small. 28. Large signal transistor tuned amplifiers are meant for amplifying large signals at radio frequencies. Power involved is large. Hence, they are operated under class AB, B or C conditions providing large collector circuit efficiency. 29. Staggered tuned amplifier uses a number of single tuned stages in cascade. The successive tuned circuits are tuned to slightly different frequencies. 30. An LC circuit is called a tuned circuit. 31. At resonant frequency, inductive reactance and capacitive reactance become equal. 32. For series resonance ; fr =

1 2 LC

circuit impedance Zr = R circuit current

I =

V R

33. Quality factor Q = 34. BW =

XL R

fr Q

35. For parallel resonance circuit,

1 1 R2 2 2 LC L

fr =

1 2

Zr =

L CR

I =

V . Zr

1 LC

36. High selectivity of the tuned amplifiers depend on the sharpness of the frequency response curve. 37. For cascaded stages : 1

2n 1

fH* = f H .

fL* =

fL 1 n

2 1

.

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

581

? 1. What do you mean by a multistage amplifier ? Explain it briefly. 2. State the various method of cascading transitor amplifier. 3. With the help of a suitable circuit diagram, explain the working of a RC coupled amplifier. Derive the expression for voltage gain of the amplifier. 4. Draw the circuits diagram of a RC coupled amplifier using PNP transistor. 5. Explain with suitable circuit diagram, the operation of transformer coupled transistorized amplifier. 6. Explain the essential difference between the RC coupled and direct coupled amplifier. 7. Draw the circuit diagram of a darlington emitter follower and derive the expressions for its voltage gain and input resistance. 8. Draw the circuit diagram of a direct coupled amplifier. Explain its working. Discuss its applications ? 9. What is the necessity of impedance matching in amplifier ? 10. Draw a circuit diagram for a transformer coupled amplifier and explain its working. 11. How will you obtain impedance matching with transformer coupling ? 12. In a multi-stage amplifier, the input impedance of a amplifier stage should be very high and output impedance must be very low. Justify this statement ? 13. Explain why 3-d B frequencies for current gain is not the same as for voltage gain. 14. Define bandwidth, selectivity and quality factor. 15. What are wide band amplifiers ? Why they are preferred over general audio amplifier ? 16. What is a tuned circuit ? What is its function with reference to a tuned amplifier ? 17. What are various tunning circuits ? 18. Explain how a large gain can be achieved by simply increasing the number of transistors in the distributed amplifier. 19. What is the advantage of stagger tunning ? 20. What is a tank circuit ? 21. Differentiate between single tuned and double tuned amplifiers. 22. What are the advantages of double tuned over single tuned amplifiers ?

Example 1. A multistage amplifier consists of three stages. The voltage gains of the stages are 30, 60 and 90. Calculate the overall voltage gain in dB. Solution : We know that overall voltage gain in dB of the three-stage amplifier is given as AdB = A d B1 A d B2 A d B3 But, we are given the voltage gains of the individual stages as ratios, so, we should first find the gains of the individual stages in decibels. Thus,

582

BASIC ELECTRONICS ENGINEERING & DEVICES

A d B1 = 20 log10 30 = 29.54 dB A d B2 = 20 log10 60 = 35.56 dB A d B3 = 20 log10 90 = 39.08 dB AdB = 29.54 + 35.56 + 39.8 = 103.16 dB. Ans. Alternatively, the overall voltage gain is A = A 1 A2 A3 = 30 60 90 = 162000 Therefore, the overall voltage gain in dB will be, Ad B = 20 log10 162000 or

Ad B = 104.19 dB. Ans.

Example 2. An RC-coupled amplifier has a voltage gain of 100 in the frequency range of 40 Hz to 25 kHz. On either side of these frequencies, the gain fall so that it is reduced by 3dB at 80 Hz. Calculate gain in dB at cut-off frequencies and also construct a plot of frequency response curve. Solution : The gain in dB is :

40 37

AdB

80

400

25 10

3

40 10

Frequency (Hz)

Fig. P (13.1)

AdB = 20 log10 A = 20 log10 100 = 40 d B This is midband gain the gain at cut-off frequencies is 3 dB less than the midband gain i.e., (Ad B) at cut-off frequencies = 40 – 3 = 37 d B The plot of frequency response curve is given in Fig. P (13.1) Example 3. The parameters of the transistor in the circuit shown are : hfe = 50 ; hie = 1.1 k , hoe = hre = 0. Calculate (a) Midband gain ; (b) The value of CB necessary to give a lower 3 dB frequency of 20 Hz. (c) The value of CB necessary to ensure less than 10% tilt for 1 kHz square wave input signal.

583

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

Vin

50K

2K

50K

2K

50K

CB

2K

50K

C1

C2

2K

Fig. P (13.2)

Solution : (a) Midband gain Avm = =

h fe R C hie R C 50 2 = 32.26 11 . 2

(b) Low cut-off frequency f1 = 20 =

CB =

1 hic R C

2 CB

b

g

2 CB

1 11 . 10 3 2 10 3

d

i

1 = 2.57 F Ans. 2 20 31 . 10 3

(c) Percentage tilt P = f1 = CB =

f1 100 f

pF 1000 10 100 = Hz 100 100 1 2 f1 hie R C

b

g

=

= 1.613 F. Ans.

1

2

100 31 . 10 3

Example 4. It is desired to build an audio-amplifier with a passband of 20 Hz to 20 kHz and a midband gain of 64000. Since one stage can not give the required gain, 3 stages are used in cascade. What should be the midband gain and bandwidth of each stage ? Solution : Band width reduction factor = (21/n – 1)1/2 Where n is the number of stages in cascade.

584

BASIC ELECTRONICS ENGINEERING & DEVICES

For a three stage amplifier, n = 3 Band width reduction factor = (21/3 – 1)1/2 = 0.5098 The overall band width fH* is given as 20 kHz. So individual bandwidth f H can be calculated as follows : f * 20 fH = H = 39.23 kHz 0.5098 0.5098 Similarly

f L = fL* 0.5098 = 20 0.5098 = 10.196 Hz

Midband gain = 64000

1/3

= 40. Ans.

Example 5. A parallel resonant circuit has an inductance of 150 H and a capacitance of 100 pF. Find the value of resonant frequency. Solution : Given, L = 150 H = 150 10–6 H C = 100 pF = 100 10–12 F We know that the resonant frequency 1 fo = 2 LC = =

0.159 L .C 0.159

d150 10 i . d100 10 i 6

12

= 1.3 106 Hz. = 1.3 MHz. Ans. Example 6. A parallel resonant circuit consists of a capacitor of 100 pF and an inductor of 100 H. The inductor has a resistance of 5. Find the value of frequency at which the circuit will resonate and the circuit impedance at resonance. Solution : Given, C = 100 pF = 100 10–12 F L = 100 H = 100 10–6 H R =5 We know that the resonant frequency fo =

1 2 LC

=

= 1.59 MHz. Circuit impedance at resonance

0.519

d100 10 i d100 10 i 6

12

MULTISTAGE AMPLIFIER AND TUNED AMPLIFIER

585

We also know that the circuit impedance at resonance, ZP = =

L CR

100 10 6

d100 10 i 5 12

= 2 105 = 200 k. Example 7. A tuned circuit has resonant frequency of 1600 kHz and a band width of 10 kHz. What is the value of its Q-factor ? Solution : Given, f o = 1600 kHz Let Qo be the quality factor We know that the band width (BW),

B = 10 =

fo Qo 1600 Qo

Qo = 160.

Example 8. A tuned amplifier has its maximum gain at a frequency of 2 MHz and has a band width of 50 kHz. Calculate the Q-factor. Solution :

f o = 2 MHz = 2 106 Hz BW = 50 kHz = 50 103 Hz

Let Qo be the quality factor. We know that the band width (BWo) 50 103 =

fo 2 10 6 Qo Qo

Qo = 40.

1. A transistor multistage amplifier contains two stages. The voltage gain of the first stage is 50-dB and that of the second stage is 100. Calculate the overall gain of the multistage amplifier in dB. [Ans. 90 dB] 2. The overall voltage gain of a two stage RC coupled amplifier is 80 dB. If the voltage gain of the second stage is 150, calculate the voltage gain of the first stage in dB. [Ans. 36.47 dB] 3. The voltage gain of a multistage amplifier is 65-dB. If the input voltage to the first stage is 5 mV. Calculate the output voltage of the multi-stage amplifier. [Ans. 8.89 v]

586

BASIC ELECTRONICS ENGINEERING & DEVICES 4. An amplifier has an input signal is 20 V peak to peak and an input impedance of 400 K. It gives an output of 10 V peak to peak across a load resistance of 5 . Calculate the power gain in d B. [Ans. 43 d B] 5. The output power of an amplifier is 100 mV. When the signal frequency is 5 kHz. When the frequency is increased to 25 kHz the output falls to 50 mV. Calculate the dB change in power. 6. A single stage CE amplifier is measured to have a voltage gain band width f2 of 5 MHz with RL = 500 . Assume hfe = 100, gm = 100 mA/V, rbb = 100 , CC = 1 pF and f T = 40 MHz. (a) Find the value of the source resistance that will give the required bandwidth. (b) With the value of RS found in part (a) find the midband voltage gain. 7. A parallel RLC circuit is resonant at 2.7 kHz. The circuit has L = 0.15 H, C = 0.232 F and a parallel resistance of 30,000 ohms. (a) What is the circuit impedance at resonance ? (b) What is the value of the circuit Q ? (c) What is the bandwidth ? (d) What is the circuit impedance at f 2, the upper band limit ? 8. A circuit is resonant at 455 kHz and has a 12 kHz bandwidth. The inductive reactance is 1255 ohms. What is the parallel impedance of the circuit at resonance ? 9. A CE amplifier with gm = 5000 mhos Cd = 50 PF is to be shunt compensated. The value of AVm is to be 18. Find the values of R and L needed to shunt-compensate the circuit to as high a frequency as possible what is that frequency ?

14 At the end of this unit you will be able to learn about What are large signal amplifiers Need of large amplifiers Classification of large signal amplifiers Direct coupled class-A amplifier Transformer coupled class-A amplifier Design theory of power amplifier Conversion efficiency or collector efficiency Harmonic distortions in amplifiers Class-A push-pull amplifier Class-B push-pull amplifier with design Crossover distortion Class-AB push-pull amplifier Conversion efficiency of class-B amplifiers Complementary symmetry amplifier Thermal runaway

In almost all electronic systems the last stage has to be large signal or power amplifier (it means large signal amplifier is nothing but a power amplifier), this is because input signal is generally small ranging from few microvolts to few millivolts. These signals if feed directly, cannot drive the loud speakers or public address system (speaker or other power handling device), therefore the signal is first fed to the voltage amplifier, so that the voltage level of this signal is first raised to sufficiently high value. This voltage is then used by power amplifier. Thus, power amplifier then provides sufficient power gain to drive an output device. The power amplifier is capable of delivering power to the loud speaker. The loud speaker finally converts the electrical energy into sound energy. When we say, “a 3-W stereo tape recorder”, it means the peak power fed to the loudspeaker is 3W. The word “stereo” means “three dimensional”. Block diagram representation of a public address system is shown in Fig. 14.1. 587

Comp-1/Laxmi-5/Computer/Revision/Belec-14—26.4.07

10.5.07

588

BASIC ELECTRONICS ENGINEERING & DEVICES

Microphone

Sound

On-Off Switch

Voltage * amplifier

*

Voltage amplifier

Power amplifier Voltage amplifier

Loud Speaker

Sound

Fig. 14.1. Block diagram of a public address system.

This amplified voltage signal is then fed to the final stage of multistage amplifier. In multistage amplifier there is a number of voltage amplifiers. Thus, we found that power amplifier is an essential part of every electronic device. Finally, we conclude that most electronic devices use at least one amplifier, but there are many types of amplifiers. This module will not try to describe all the different types of amplifiers. You will be shown the general principles of amplifiers and some typical amplifier circuits. Most amplifiers can be classified in two ways. The first classification is by their function. This means they are basically voltage amplifiers or power amplifiers. The second classification is by their frequency response. In other words what frequencies are they designed to amplify ? If you describe an amplifier by these two classifications (function and frequency response) you will have a good working description of the amplifier. You may not know what the exact circuit is, but you will know what the amplifier does and the frequencies that it is designed to handle.

As we have just discussed that the primary function of the voltage amplifier is to raise the voltage level of the signal. It is designed to achieve the largest possible voltage gain. Only a very little power can be drawn from its output. On the other hand, a power amplifier is required to deliver a large amount of power and as such it has to handle large current. To obtain a large power at the output of the power amplifier its input signal voltage must be large. That is why, in an electronic system, a voltage amplifier, invariably proceeds the power amplifier. Also that is why the power amplifier are called large signal amplifiers. An important questions arises here – “Does a power amplifier actually amplify power ?”. The answer is “no”. In a real manner, no device can amplify power. This is because amplification of power contradicts the basic principle of physics i.e., law of conservation of energy. In fact, a power amplifier, during its operation, takes power from the dc power supply and converts it into useful ac signal power. This power is feed to the loudspeaker (i.e., load). The type of ac power developed at the load (output) of the power amplifier is controlled by the input signal. Thus, we may say that a power amplifier is a dc-to-ac power converter, whose action is controlled by the input signal for better understanding. The comparison between voltage amplifier and large signal (power) amplifier as shown in Table 14.1.

589

LARGE SIGNAL (POWER) AMPLIFIERS

Table 14.1 S. No.

Characteristic

Voltage amplifier

Power amplifier

(i)

high 100

low (20 to 50)

(ii)

RC

high ( 10 k)

low (~ 40 )

(iii)

Input voltage

low (few mV)

high (few V)

(iv)

Power output

low

high

(v)

Collector current

low (1 mA)

high (100 mA)

(vi)

Output impedance

high

low

(vii)

Coupling

usually R-C coupling is used

invariably transformer or tuned circuit used

Following are the conditions for a power amplifier : In power amplifier, input resistance of transistor is very large as compared to

its output resistance. The current gain of a transistor used in power amplifier is smaller compared

to that of voltage amplifier. In power amplifiers, transformer coupling for impedance matching should be

used. Power amplifiers need large size, because a considerable amount of heat is

dissipated within the transistor and hence the large surface area is required for heat dissipation. + VCC

R1

RC C

CC

+

B E

Rs Vs

CC

VO

+ –

R2

RE

CE –

Fig. 14.2. Simple CE amplifier circuit.

Reason Why Voltage Amplifier Cannot Work as a Power Amplifier (Large Signal Amplier) and its Remedy For the transistor to work as a voltage amplifier need not to have a power dissipation rating. It is generally not used to handle large power. However, if we want transistor to work as a power amplifier, the transistor must have large power dissipation rating.

590

BASIC ELECTRONICS ENGINEERING & DEVICES

Practically, it is found, for voltage transistor power dissipation < 0.5 W and for power transistor power dissipation > 0.5 W. Let us consider a simple amplifier circuit. In fact this is a good voltage amplifier circuit shown in Fig. 14.2. Now, the question is that whether the circuit would work as a good power amplifier if we replace the transistor with another transistor of higher power dissipation rating. We will see that this circuit cannot work as a power amplifier. Applying KVL to the output loop, we have VCE = VCC – IC (RC + RE)

...(14.1)

The dc power that goes into the transistor is PDQ = VCE IC

...(14.2)

This represents that when dc power is applied to the amplifier only a portion of this power can be converted by the amplifier into the useful ac power because there is a voltage drop across resistance RC and RE (where RC is the collector resistor between collector and base of the transistor and RE is the emitter resistance between emitter and ground). There are two parameters RC and RE which are the main cause of power loss (i.e., dc input power). If RE is replaced by the short-circuit (i.e., the absence of emitter resistance), results in the poor stabilization of operating point. In other words the circuit stability becomes poor due to the short-circuit of emitter resistance. Now, we have only option to avoid power loss i.e., RC. One can think whether we can avoid the dc power loss in RC by short-circuiting, its answer is “no”, because in ac equivalent circuit (which will be discussed in next chapter) the load also becomes short. Since load resistance is equal to RL || RC = 0 when RC = 0 (i.e., short-circuited). It means no power is transferred to the load RL. The amplifier becomes useless. The remedy of this difficulty is that we must replace R C by a component whose dc resistance is zero, but ac resistance (or impedance) is very high, the solution of this problem is choke coil or an inductor. There are two main advantages of using choke coil. No dc voltage drop across the choke (since for dc f = 0 ; XL = 2f L = 0) The dc power loss in the choke coil is almost nil.

Fig. 14.3 shows a typical single ended transistor power amplifier. Single ended means only one transistor. It is basically the last stage of a multistage audio amplifier. In many electronic system, such as radio, television, public address system, tape recorder etc., the final output is in the form of sound. The power amplifier makes the final stage and it drives the loudspeaker. We already know that maximum power will be transferred to the loudspeaker from the power amplifier, only if its output impedance is same as the impedance of the loudspeaker. If it is not so, the loudspeaker gets less power. Maximum power can be transferred by using transformer impedance matching.

591

LARGE SIGNAL (POWER) AMPLIFIERS + VCC

R1

LoudSpeaker

CC

C

B

E

RS + VS –

R2

RE

CE

Fig. 14.3. Single-ended power amplification.

A typical circuit diagram of transformer impedance matching is shown in Fig. 14.4. A load resistance RL is connected across the secondary of a transformer with turns ratio

FG N IJ . Let the resistance seen looking into the primary of the transformer be R , now HN K F V I F I I N . N FG N IJ V /I R = = G JG J V /I R HV K HI K N N HN K F N IJ or R = R G ...(14.3) HN K 1

L

2

2

L

1

1

1

1

1

1

1

L

2

2

2

2

2

2

2

2

L

L

1 2

N 1 : N2 +

+

+

I1

I2 V2

V1

–

–

RL

Speaker

–

RL

Fig. 14.4. Transformer impedance matching.

Thus, by using a step-down transformer of proper turns ratio, we can match a low RL with high output impedance of the transistor.

Classification of power amplifiers is based on transistor biasing and amplitude of the input signal i.e. The portion of the cycle for which the transistor conducts their

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BASIC ELECTRONICS ENGINEERING & DEVICES

mode of operation. On the basis of biasing and the conduction of cycle, the classification of power amplifiers is as follows : Class-A amplifier. Class-B amplifier. Class-C amplifier. Class-AB amplifier.

Before discussing each power amplifier in detail it is very necessary to discuss the performance of power amplifier. The performance of amplifier is studied on the basis of quantities like distortion and power dissipation capability. These are discussed below in detail.

We have discussed earlier that the main purpose of an amplifier is to boost up the voltage or power level of a signal. During this process, the waveshape of the signal should not change. If the waveshape of the output is not an exact replica of the waveshape of the input we may say that distortion has been introduced by the amplifier. Since power amplifier handles large signal, distortion is always present. A number of factors are responsible for causing distortion. It may be caused either due to the relative components of the circuit or due to the non-linear characteristics of the transistor. Some types of distortion is given below. These may exist either separately or simultaneously in an amplifier : (i) Frequency distortion (ii) Phase or time-delay distortion (iii) Harmonic, Amplitude or non-linear distortion. (i) Frequency distortion : We know that practically, the signal is not a simple sinusoidal voltage. It has a complex waveshape. Such a signal is equivalent to a signal obtained by adding a number of sinusoidal voltages of different frequencies. These sinusoidal voltages are called the frequency components of the signal. If all the frequency components of the signal are not amplified equally well by the amplifier, frequency distortion is said to occur. The cause for this distortion is non-constant gain for different frequencies. This occurs due to inter electrode capacitance of the active device and other relative components of the circuit. (ii) Phase distortion : Phase distortion occurs if the phase relationship between the various frequency components making up the signal waveform is not the same in the output as in the input. The main cause of the phase distortion is the reactive components of circuit. This distortion is not important in audio amplifiers. Because our ears are not capable of distinguishing the relative phases of different frequency components but this distortion is considerable in video amplifiers used in television. (iii) Harmonic distortion : This type of distortion occurs when the output contains new frequency components that are not present in the input signal. These new frequencies are the harmonics of the frequencies present in the input.

593

LARGE SIGNAL (POWER) AMPLIFIERS

Harmonic distortion in an amplifier occurs because of the non-linearity in the dynamic transfer characteristics curve. Hence this distortion is also called non-linear distortion. In case of voltage amplifier, where small signals are handled, no harmonic distortion occurs. However, in power amplifier due to the large input signal the change in the output current is no longer proportional to the change in input voltage. This type of distortion is also called as amplitude distortion.

Calculation for Harmonic Distortion in Power Amplifiers If we apply for sinusoidal signal as input vi = V sin t to the input of the power amplifier the waveform of the output signal can be mathematically represented as : i0 = I0 + I1 sin t + I2 sin 2t + I3 sin 3t + where,

...(14.4)

I0 = dc component I1 = Peak value of the first harmonic (or the fundamental) I2 = Peak value of second harmonic

The harmonic distortion for each of these components is then defined as : Second harmonic distortion, D2 = Third harmonic distortion, D3 =

I2 I1

I3 and so on. I1

When distortion occur, the output power due to the fundamental component of the distorted signal is :

I12 R L ...(14.5) 2 The total power due to all the harmonic components at the output is : P1 =

i R2 FI I FI I = 1 G J G J HI K HI K = d1 D D i P d

PT = I12 I 22 I 23 2

or or

PT PT

2

2

3

1

1

2 2

L

2 3

I12 R L 2

1

...(14.6)

We may define the total distortion or distortion factor as : D = so,

D 22 D23

...(14.7)

PT = (1 + D2) P1

If the distortion is 10%, then the total power is : PT = [1 + (0.1)2] P1 = 1.01 P1 This shows that a 10% distortion represents a power of only 1% of the fundamental. Thus, only a small error is made in using only the fundamental term P1 for calculating the output power.

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BASIC ELECTRONICS ENGINEERING & DEVICES

The ability of a power transistor to dissipate heat developed in it during operation is known as its power dissipation capability or power rating. If the heat generated within the transistor due to excessive current passing through it is greater than its power dissipation capability, then the transistor may burn out. For good power transistor, the power dissipation capability should be high. The power dissipation capability of a transistor may be increased by connecting a metallic structure called heat sink to the transistor case. It keeps the transistor case temperature within the permissible limits. Now, we will discuss first of all the brief classification of power amplifiers (large signal amplifier). (i) Class-A amplifier : It is an amplifier in which the transistor is biased such that the output current flows for complete cycle (i.e., 360°) of the input signal. Fig. 14.5 (a), shows output for a class-A amplifier. (ii) Class-B amplifier : It is an amplifier in which the transistor is biased such that the output current flows for only half cycle (i.e., 180°) of the input signal. Fig. 14.5 shows output for a class-B amplifier. (iii) Class-C amplifier : It is an amplifier in which the transistor is biased such that the output current flows for less than half cycle of the input signal. Fig. 14.5 (c) shows the output for a class-C amplifier.

2 t

Vin

AV

Vo

Vo

Vo

Input Voltage

(a)

o

2 t

Vin

AV

Input Voltage

(b)

o

2 t

Vin

AV

(c)

Output Voltage

o

2 t

Output Voltage

o

o

2 t

Output Voltage

Input Voltage

(iv) Class-AB amplifier : It is an amplifier in which the transistor is biased such that the output current flows for more than half cycle of the input signal. Fig. 14.5 (d) shows the output for class-AB amplifier.

o

t

595

o

2 t

Vin

AV

Vo

(d)

Output Voltage

Input Voltage

LARGE SIGNAL (POWER) AMPLIFIERS

o

t

Fig. 14.5. Classification of power amplifier.

As we have already discussed that the large signal amplifier in which operating point is so adjusted that the collector current flows during whole cycle of the input signal is known as class-A amplifier. Fig. 14.6 shows the circuit arrangement of class A direct coupled large signal amplifier with resistive load. One thing always should be kept in mind that the operating point (or Q point) is selected in such a way that the transistor operates only over the linear region of its load or we can say that at the middle of the AC load line. Fig. 14.7 shows the output characteristics with operating point Q. Here I CQ and VCEQ represent no signal collector current and collector to emitter voltage respectively. When signal is applied, the Q-point shifts to Q1 and Q2. The output collector current increases to IC (max) and decreases to IC (min). Similarly the collector to emitter voltage increases to VCE (max) and decreases to VCE (min). D.C. power drawn from the collector battery VCC is given by + VCC

R1

RC +

Cb

Input Signal

R2

VO CE –

Fig. 14.6. Class-A direct coupled amplifier with resistive load.

Pin = Voltage Current or

Pin = VCC ICQ

This power is used in the following two parts :

596

BASIC ELECTRONICS ENGINEERING & DEVICES t pu l in gna i s

Ic IC(max)

Q1 Q

Out put current ICQ waveform IC(min)

Q2

VCE VCE (min)

VCE (max) VCEQ

Fig. 14.7. Output voltage waveform.

(i) Power dissipated in the collector resistance i.e., load resistance RC as heat is given by 2 PRC = I CQ . R C and

...(14.9)

(ii) Power given to transistor is given by

or

Ptr = Pin – PRC

...(14.10)

2 Ptr = VCC . ICQ – I CQ . RC

...(14.11)

Now, when signal is applied, the power given to transistor is used in the following two parts namely. a.c. power developed across the load resistance R C which constitutes the power

ouput. i.e.,

PO

(a.c.)

V2 = I . RC = = RC 2

FV I GH 2 JK M

2

.

1 VM2 = RC 2R C

...(14.11)

where I = rms value of ac output current through load and Vm is the maximum value of V. The dc power dissipated by the transistor (collector region) in the form of heat.

In order to better memorizing the things discussed above are shown below in the form of tree diagram. Pin (dc)

PRC (dc)

Ptr

PC (dc)

PO (ac)

LARGE SIGNAL (POWER) AMPLIFIERS

597

Terms Frequently Used in Large Signal or Power Amplifier (i) Overall efficiency : The overall efficiency of the amplifier circuit may be defined as the ratio of a.c. power delivered to the load to the total power delivered by dc supply i.e.,

(overall) =

=

ac power delivered to the load total power delivered by dc supply Po a acf Pin b dc g

(ii) Collector efficiency : The collector efficiency of a amplifier is the ability of an active device to convert the dc power of the supply into the ac (signal) transferred to the load is called collector efficiency or conversion efficiency. Sometimes also called theoretical efficiency. i.e.,

(collector) =

=

average ac power output average dc power input to transistor Po a acf Ptr b dcg

In more simple words collector efficiency is nothing but a ratio of ac output power to the dc input power (i.e., zero signal power). We have discussed earlier that a power amplifier just converts dc power received from the battery (source) into ac power which fluctuates according to the input signal. This ac power is supplied to the load. Really, collector efficiency tells us the percentage of dc power converted into ac power by the amplifier. For example, if the dc power supplied is 20 W and the ac output power is 5 W, then the conversion or collector efficiency is 25%. The greater the collector efficiency better is the amplifier.

The parameter i.e., collector resistance RC is the main cause of power loss (i.e., dc input power loss). Now, we have only one option to avoid power loss i.e., RC. One can think whether we can avoid the dc power loss in RC by short circuiting, its answer is “no”, because in ac equivalent circuit the load also becomes short. Since load resistance is equal to RL || RC = 0 when RC = 0 (i.e., short-circuited). It means no power is transferred to the load RL, ultimately the amplifier becomes useless. The remedy of this difficulty is that we must replace R C by a component whose dc resistance is zero, but ac resistance (or impedance) is very high, the solution of this problem is choke coil or inductor. There are two main advantages of using choke coil. No dc voltage drop across the choke (since for dc f = 0 i.e., XL = 2nf L = 0). The dc power loss in the choke coil is almost nil.

598

BASIC ELECTRONICS ENGINEERING & DEVICES

Fig. 14.8 circuit arrangement of transformer coupled class A amplifier. Here resistance R1 and R2 provide potential biasing arrangement for forward biased base-emitter junction of the power transistor. REis the emitter resistor for bias stabilization and CE is bypass capacitor for RE to prevent ac voltage. + VCC

Loudspeaker R1 CC N1 : N2 Input signal

R2 CE

RE

Fig. 14.8

The capacitor CC blocks any dc from the previous stage. Input signal from a preamplifier is applied to the input terminals. T is step down transformer. The high impedance primary of the transformer is connected to the high impedance collector circuit. The low impedance secondary is connected to the load (generally loudspeaker).

Transformer Impedance Matching The transformer impedance matching can be considered with the help of Fig. 14.9. In Fig. 14.9, RL is the load connected in the secondary of a transformer. Let the reflected load in the primary of the transformer be R L . N1 and N2 are the number of turns in the primary and secondary respectively. Let V1 and V2 be the primary and secondary voltages and I1 and I2, be the primary and secondary currents respectively.

I1 n1 V1

V1 N I N2 = 1 and 1 = V2 N2 I2 N1 V1 =

N1 N2 V2 and I1 = I N2 N1 2

FG IJ H K

2

n2

RL

We know that,

or

I2

Hence

V1 N1 = N2 I1

But

V1 = R L = effective input resistance I1

V2 I2

RL

Fig. 14.9

V2

599

LARGE SIGNAL (POWER) AMPLIFIERS

V2 I 2 = RL = effective output resistance

and

R L

where

F N IJ =G HN K

2

1 2

n =

RL = n2 RL

...(14.12)

number of turns in primary N1 = number of turns in secondary N2

For example, if we want to match a 40 speaker load to a power amplifier so that the effective load may be 4 K, then the turn ratio should be

FG N IJ HN K 1

2

=

2

R L 4000 = 100 RL 40

N1 = n = 10 N2 In this way a power amplifier may be matched by taking proper turn ratio in step down transformer.

Circuit Operation In order to get maximum ac power output, the peak value of the collector current due to signal should be equal to zero signal collector current. Thus, Q should be located at the centre of load line. The output voltage and current waveforms are shown in Fig. 14.10. IC

Ic (max)

2ICQ

ICQ

Output Current Waveform

Load line

Q (at centre)

VCC IC (min)

O

(Vce) Q

2VCC (Vce) max

VCE

Output voltage Waveforms

Fig. 14.10. Output voltage and current waveforms.

When ac signal is applied, collector current fluctuates. Now the operating point Q moves up and down the load line. The collector voltage varies in opposite phase to the

600

BASIC ELECTRONICS ENGINEERING & DEVICES

collector current. The variation of collector voltage appears across the primary of transformer. Now ac voltage is induced in the secondary which in turn develops ac power in load.

IC Imax

1 Load line Im Q

Characteristics of Class-A Amplifier Following are the characteristics of a class-A amplifier The output current flows during the entire cycle of

the ac input signal.

Imin Im O Vmin

Output power is low, therefore the collector efficiency

Vm

Vm

2

Vmax

VCE

Fig. 14.11

is less than 50%. Since the transistor operates over the linear region of the load line, therefore the

output waveform is almost similar to the input waveform. The ac power output per transmitter is smaller than that of class-B or class-C

amplifier. Maximum power dissipation is at the zero signal (i.e., in the absence of the

signal).

Derivation of Maximum Efficiency for Class-A Amplifier Fig. 14.11 shows the load line for calculating the conversion or collector efficiency of an ideal distortion less class-A power amplifier. It is assumed that the static waves are equally spaced in the region of load line for equal increment in excitation (base current). Thus (in Fig. 14.11), the distance from 1 to Q is same as that from Q to 2. It is also assumed that the excitation is such that it gives zero minimum current. The construction in Fig. 14.11 may be used to analyse either a series-fed or a transformer-fed load. The only difference between these two circuits is that the supply voltage VCC equals Vmax in the series-fed case, whereas VCC is equal to the quiescent voltage VC in the transformer coupled amplifier. Now, for series-fed class-A amplifier IC = Im and Vm =

Vmax Vmin 2

=

Vm I m /2 VCC I C

or

=

I 2VCC

or in %,

=

Vmax Vmin 100 4VCC

or

=

25 Vmax Vmin Vmax

{ for series-fed, VCC = Vmax}

b

FG V H

max

Vmin 2

g

IJ K

...(14.13)

601

LARGE SIGNAL (POWER) AMPLIFIERS

This equation indicates that the upper limit of the conversion efficiency is 25%, when Vmin = 0. If the load is transformer-coupled, then

Vmax Vmin 2

VCC = VC = = 50

so,

FG V HV

max max

IJ K

Vmin % Vmin

...(14.14)

Therefore for transformer coupled maximum frequency is , max = 50%.

The distortion introduced by non-linearity of the dynamic transfer characteristic using a single transistor as amplifier can be minimized by push-pull arrangement. The amplifier is then known as push-pull amplifier. Push-pull amplifier circuit is employed in the output stages of electronic circuits.

Circuit Description of Class-A Push-Pull Amplifier The circuit arrangement of push-pull amplifier is shown in Fig. 14.12. Ic Q ic

Q1 Tr

1

R1

1

Tr +

–

Input

R2 Biasing network

2

Loudspeaker

VCC Q2

ic 1 Ic

Q

Input transformer Push pull circuit

Output transformer

Load

Fig. 14.12. Class-A push-pull arrangement.

In push-pull arrangement two identical transistors Q 1 and Q2 are used. The emitter terminals of the two transistors are connected together. The input signal is applied to the inputs of two transistors through centre tapped transformer, Tr1. This transformer provides opposite polarity signals to the two transistor inputs. The collectors of both the transistors are connected to the primary of output transformer Tr2. This transformer is also centre tapped. The collector terminals of the two transistors are connected to the supply VCC through the primary of output transformer. Resistors R 1 and R2 provide the biasing arrangement. The load (generally a loudspeaker) is connected across the secondary of output transformer. The turns ratio of the output transformer is chosen in such a way that the load is well matched with the output impedance of the transistor. So maximum power is delivered to the load by the amplifier.

602

BASIC ELECTRONICS ENGINEERING & DEVICES

Circuit Operation of Class-A Push-Pull Amplifier As shown in Fig. 14.12, the two transistors Q1 and Q2 carry dc components of collector currents ICQ. These currents are equal in magnitude and flow in opposite directions through the primary of transformer Q 2. So there is practically no net dc component of current through the primary of transformer Q2. This will increase the a.c. power output which is obtained by a single transistor. Let us consider that ac signal is applied to the input. When the input signal voltage is positive, the base of transistor T1 is more positive while the base of transistor Q2 is less positive. Hence the collector current ic1 , of transistor Q1 increases while the collector current ic2 of transistor Q2 decreases. These currents flow in opposite directions in two halves of the primary of output transformer. Moreover, the flux produced by these currents will also be in opposite directions. As a result, the voltage across the load will be induced voltage whose magnitude will be proportional to the difference of collector

d

i

currents i.e., ic1 ic2 . Similarly, for the negative input signal, the collector current ic2 will be more than

ic1 . In this case the voltage induced cross the load will again be due to the difference

di

c2

i

ic1 . As ic2 ic1 , the polarity of voltage induced across load will be reversed. The

overall operation results in an a.c. voltage induced in the secondary of output transformer and hence a.c. power is delivered to the load. ic

1

IC

Q

Ic + (– Ic ) 1

Ic IC

2

2

Q

Addition Ic + (– Ic ) 1

2

– ic

2

– IC

Q

Fig. 14.13. Showing the difference of

di

c1

i

ic2 .

The difference of two collector currents is shown in Fig. (14.13).

d i

ic1 ic2 = ic1 ic2

It is obvious that during any given half cycle of input signal, one transistor is being driven (or pushed) deep into conduction while the other being non-conducting (pulled out). Hence the name push-pull amplifier.

603

LARGE SIGNAL (POWER) AMPLIFIERS

Distortion in Class-A Push-Pull Amplifier The base currents ib1 and ib2 of transistors T1 and T2 respectively are expressed as and

ib1 = Ib sin (t)

...(i)

ib2 = Ib sin (t + )

...(ii)

Their collector currents are expressed as ic1 = Ic + I1 sin t + I2 sin 2t + I3 sin 3t

...(iii)

ic2 = Ic + I1 sin (t + ) + I2 sin 2 (t + ) + I3 sin 3 (t + ) or

ic2 = Ic + I1 sin (t + ) + I2 sin (2t + 2) + I3 sin (3t + 3)

or

ic2 = Ic – I1 sin t + I2 sin 2t – I3 sin 3t Thus

ic1 ic2 = 2I1 sin t + 2I3 sin 3t +

...(iv) ...(v)

The output voltage induced in the secondary of the output transformer is proportional

d

i

to ic1 ic2 . Hence,

d

vo = K ic1 ic2 or

i

= K 2

[I1 sin t + I3 sin 3t + I5 sin 5t]

vo = 2K [I1 sin t + I3 sin 3t + I5 sin 5t + ]

...(vi)

In equation (vi), there is no even harmonic terms, hence all even harmonics are eliminated.

Advantages of Class-A Push-Pull Amplifier Following are the advantage of Class-A Push-Pull Amplifier : Even harmonics are absent in the output. High a.c. output power is obtained. The effect of ripple voltages contained in the power supply due to inadequate

filtering are balanced out.

Disadvantages of Class-A Push-Pull Amplifier Following are the disadvantage of Class-A Push-Pull Amplifier : Two identical transistors are required. If the parameters of the two transistors are not the same, there will be unequal

amplification of two halves of the signal. Centre tapping is required in transformer. Transformers used are bulky and expensive.

The power amplifier in which the transistor operating point and amplitude of the input signals are such that the output current flows for only half cycle (i.e., 180°) of the input signal is known as class-B amplifier, as shown in Fig. 14.14. For class-B operation of the amplifier, the biasing circuit is so adjusted that operating point Q lies very near

604

BASIC ELECTRONICS ENGINEERING & DEVICES

the cut-off region, i.e., zero collector current (IC = 0). During the positive half-cycle of the signal collector current flows, however during the negative half-cycle of the signal, the input circuit is reverse biased. In other words we can say that output obtained from class-B amplifier is just like an amplified half wave rectification.

Output current

Input signal IC

2

0

0

2 3

VCE

0

2 3 Output voltage

Fig. 14.14

It may be noted that there is no input signal due to the transistor biased at cut-off. At this point there is no current flow through the transistor and hence no power is dissipated by the transistor. However in class-A amplifier maximum dissipation occurs at zero signal condition.

Characteristics of class-B Amplifier Following are some of the important characteristics of class-B amplifier The output current flows only for one-half cycle of the input signal. The transistor dissipates no power with zero input signal. However, it increases

with the increase in amplitude of input signal. It is contrary to class-A amplifier operation in which the transistor dissipation is maximum with no input signal and minimum with the largest input signal. The average current drawn by the circuit in class-B operation is smaller than

that in class-A. As a result of this, the amount of power dissipated by the transistor is less in class-B. Thus, the overall efficiency of the circuit is higher than that of class-A. The main disadvantage of class-B amplifier is that the harmonic distortion is

higher, self biasing method cannot be used, and the supply voltage must have good regulation.

Power and Efficiency Calculation Input dc power,

Pdc = VCC Idc

1 2

z

I c max sin d =

where

Idc =

so,

Pdc = 2VCC .

0

Im

I c max 2

cos

0

=

I c max

=

Im

605

LARGE SIGNAL (POWER) AMPLIFIERS

{here factor 2 in this expression arises because two transistors are used in the push-pull system (discussed later)} The ac output power ; P0 = Now, efficiency

=

b

Vm I m I m VCC Vmin 2 2

g

P0 100 Pin

b

g

Im VCC Vmin 100 = 2 I 2 VCC m =

or

FG H

IJ K

FG H

IJ K

V V 1 CC 100 0.785 1 CC 100 4 Vmin Vmin

...(14.15)

max = 78.5% Thus, the conversion efficiency of class B amplifier is 78.5%.

It is an amplifier in which the transistor biasing and amplitude of input signal are such that the output current flows for less than half cycle of the input signal. For class-C operation of the amplifier, the biasing circuit is so adjusted that operating point Q lies below the cut-off region, which is practically impossible resulting is much higher distortion. This is the reason why such amplifiers are never used for power amplification. However they are used as tuned amplifiers (in RF range) due to high efficiency of class-C amplifier. Thus, class-C amplifier is basically a radio frequency (RF) power amplifier and not an audio power amplifier like class-A and class-B amplifier.

Characteristics of Class-C Amplifier Following are some important characteristics of class-C amplifier. The output current flows for less than half cycle of the input signal. This

condition is achieved by biasing the transistor below cut-off. The output signal does not resemble the input signal because it consists of

narrow pulses. The class-C amplifier is the most efficient power amplifier and its overall efficiency

under certain conditions may approach even 100%. Reason why class-C Amplifier is not used in power amplifier We have discussed just above that for class-C operation collector current flows for less than half cycle of the input which results in maximum distortion. Class-C amplifier is mostly used where maximum efficiency or maximum output is the prime requirement. For example, generally class-C amplifier is used in T.V. receivers, Radio receivers where this signal is passed through the tuned-circuit. Tuned circuit is nothing but a L-C circuit, it may be also noted that the frequency of signal which passes through the tuned circuit is not considered, since signal after passing through the tuned circuit will

606

BASIC ELECTRONICS ENGINEERING & DEVICES

pass through frequency =

F 1 I , however, it may have any initial frequency. This GH 2 LC JK

is the main feature of tuned circuit.

A circuit arrangement of a push-pull amplifier uses two transistor as shown in Fig. 14.15. This circuit may work in class-B or class-A operation. Because of the special circuit connection, it generates a very low distortion. In the circuit, the excitation is introduced through a centre tapped transformer. Thus, when the signal on transistor T1 is positive, the signal on T2 is negative by an equal amount. Any other circuit that provides two equal voltages which differ in phases by 180° may be used in place of the centre tapped transformer. The collector terminals of the two transistors are connected to the supply VCC through the primary of the transformer. The load resistance is connected across the secondary of the output transformer. The turn ratio N1 : N2 at the transformer is chosen so that the load RL is in matched conditions. Maximum power is delivered here resistance R1, R2 and RE form the biasing network. VCC

i1 Tr

1

+

R1

RE

N1 N2

Vi

–

RC

X

iL

Tr2

T1

Loudspeaker

N1

Biasing network T2

i2

Input transformer

Load Push-pull circuit

Output transformer

Fig. 14.15

Consider the input signal (base current) of the form ibi = Ibm sin t applied to T1. The output current of this transistor (i.e., T1) is given by equation (14.16) i1 = I0 + I1 sin t + I2 sin t + I3 sin 3t + ...

...(14.16)

for the transistor T2 the base current

I b2 = Ibm sin (t + ) or or

Its output can be written (14.16) as i2 = I0 + I1 sin (t + ) + I2 sin 2 (t + ) + I3 sin 3 (t + ) + ... i2 = I0 + I1 sin (t + ) + I2 sin (2t + 2) + I3 sin (3t + 3) + ... i2 = I0 – i1 sin t + I2 sin 2t – I3 sin t + ...

...(14.17)

Here we have assumed identical characteristics for the two transistors. We have seen that voltage induced in the secondary of the output transformer is proportional to the difference (i1 – i2).

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LARGE SIGNAL (POWER) AMPLIFIERS

Now from equation (14.16) and (14.17), we have

v0 = K (i1 – i2) v0 = 2K (I1 sin t + I3 sin t + I5 sin t + ...) ...(14.18) where K is some constant of proportionality. Thus, we can say that a great deal of distortion introduced by the non-linearity of the dynamic transfer characteristics may be eliminated by the circuit shown above known as push-pull configuration. From equation (14.18) it is clear that even harmonics get cancelled because of push-pull connection. The net distortion in the output of the push-pull amplifier is much less than it would have been seen in a single ended amplifier.

Advantages of a Push-Pull System Because no even harmonics are present in the output of a push-pull amplifier, such circuit will give more output per device (or transistor) for a given amount of distortion. For this reason to get a given output power, we prefer using two transistors in push-pull connection rather than using a single larger power transistor in a single ended circuit. The main advantages of the push-pull circuit connection are given below : Their collector efficiency is quite high 75.8%) due to class-B operation. The output has much less distortion due to the cancellation of all the even

harmonic components. The net current flowing through the emitter resistor R E is the sum of the two

collector currents ic1 (or I c1 ) and ic2 (or I c2 ). There is no need of by pass capacitor CE for the fundamental frequency components. And to by pass the second harmonic term, we can use a smaller capacitor. The cost is thus reduced. The d.c components of the collector currents oppose each other in the transformer.

This results in zero d.c flux in the core. The magnetic saturation of the core the by d.c current does not occur. We can use the smaller sized transformer, the cost thus becomes low. They give more a.c output power per device or transistor. It reduces the humming noise in the circuit.

Disadvantages of Push-Pull System Following are disadvantages of Push-Pull system : Two identical transistors are required, which is usually not found. It requires two equal and opposite voltages at the input, therefore driver stage

has to be employed. If the parameter (mainly ) of the two transistors differs, there will be an unequal

amplification of the two halves of the input signal which introduces more distortion.

Relation Between Maximum Output Power and Maximum Dissipated Power for Class-B Amplifier As we have discussed earlier that dissipation power is given as, PD = Pi – Po

...(14.19)

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BASIC ELECTRONICS ENGINEERING & DEVICES

where

PD = Dissipation power Pi = Input power Po = Output power

Now,

Pi = VCC . ICQ

R|since, I V U| R S| V| where R Load Resistance T W

V V V2 V .I Po = m m = m . m m 2 2 R L 2 R L

m

m

L

L

2I m Substituting these values in equation (14.19), we have For full wave rectifier, ICQ =

PD = VCC . or

PD =

2I m V2 m 2R L

2 VCC . Vm V2 m . RL 2R L

...(14.20)

Differentiating equation (14.20) w.r.t. Vm for maximum or minimum value of power dissipation.

LM N

d 2 VCC . Vm V2 d m PD = d Vm d Vm RL 2RL

OP Q

d PD 2 VCC 2Vm = d Vm R L 2R L for maximum or minimum value put 0 =

d PD = 0, we have d Vm

2VCC Vm RL RL

2VCC Also on putting the value of Vm in equation (14.20), we have Vm =

PDmax = = PDmax =

2 VCC V2 . Vm m R L 2R L

b

g b

2 VCC . 2VCC / 2VCC / RL 2R L 2 2 VCC 2 R L

g

2

...(14.21)

But we know that maximum output power (PDmax) PDmax =

VCC 2R L

...(14.22)

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LARGE SIGNAL (POWER) AMPLIFIERS

Hence from equations (14.21) and (14.22), we have PDmax = or

4 Po max 2

PDmax 4 Pomax

... (14.23)

This is the required relation between maximum dissipated power and maximum output power. This relation is for the two transistor. Note : For example, if we wish to deliver 10 W from a class-B push-pull amplifier then PD max = 4 W, or we must select transistors which have collector dissipation of approximately 2 W each. In other words, we can obtain a push-pull amplifier output of five times the specified power dissipation of a single transistor. On the other hand, if we connect two transistors in parallel and operate them as class-A to obtain 10 W output, the collector dissipation of each transistor would have to be at least 10 W (assuming 50% efficiency). This statement follows from

Po 10 = 20 W, this input power must be dissipated in the two collector at 0.5 no signal (As we has discussed earlier that in class-A amplifier the maximum dissipation occurs at zero signal) or PD = 10 W, each transistor. This example clearly indicates the superiority of the push-pull over the parallel configuration. the fact that Pi =

It is possible to eliminate both the input and output transformers in an ordinary push-pull amplifier circuit, the solution is by using complementary push-pull circuit. Here complementary means if one transistor is taken pnp then other must be a npn transistor. The circuit arrangement of the complementary push-pull circuit is shown in Fig. 14.16. Note that the complementary symmetry circuit requires two power supplies namely VCC1 and VCC2 . Push-pull amplifiers means the two transistors are conducting alternatively. The term ‘symmetry’ means that the biasing resistors are equal. As a result of this, the emitter base junctions of each transistor is biased with the same npn B1

C1 T1 E

R1

R2

VCC1 RL

Input signal

R1

R2

VCC

VO 2

E2 T2

B2 pnp

C2

Fig. 14.16. Complementary symmetry push-pull circuit.

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BASIC ELECTRONICS ENGINEERING & DEVICES

voltage. A complementary symmetry push-pull amplifier works on the same principle i.e., for the first half-cycle one transistor conducts and the other remains in cut-off state and in the second half-cycle, the action is reversed. Both the transistors work in class B operation. The important point to note is that no centre tap transformer is required. However, an ordinary output transformer is used for impedance matching to get maximum output across the load.

Operation The input signal appears across the terminals AB during the positive half cycle of the input signal, the transistor T1 (npn) conducts while at the same time transistor T2 (pnp) does not conduct. During the negative half cycle transistor T 2 (pnp) conducts while at the same time transistor T1 (npn) does not conducts. Hence npn transistor amplifies the positive half-cycle whereas pnp transistor amplifies the negative half-cycle. Thus, we get amplified output across the load for complete cycle of the input signal. Advantages of complementary symmetry Push-Pull amplifier : The circuit does not require centre tap transformers. Hence it’s weight and cost

is less. Efficiency is high. At the output of circuit transformer is not necessary.

Disadvantages of complementary symmetry Push-Pull amplifier : We require two batteries (or supply). It is difficult to get a pair of transistors (npn and pnp) having exactly same

characteristics. Note : All modern power amplifier circuits are transformer-less and use complementary transistors.

As we have already discussed that in the class-AB power amplifier output current (i.e., collector current) flows for more than half cycle of the input signal. In addition to the distortion introduced by not using matched transistors and that due to the non-linearity of the collector characteristics, there is one more source of distortion that is caused by non-linearity of the input characteristic. As we know that in the case of transistor (any type whether npn or pnp of any configuration), no appreciable base current flows until the emitter junction is forward biased by the cut in voltage V, which is 0.2 V for germanium transistor and 0.6 V for silicon transistor. Under these circumstances a sinusoidal base voltage excitation will not result in a sinusoidal output current. The distortion caused by the non-linear transistor input characteristics is indicated in Fig. 14.17. To eliminate (Remedy) cross-over distortion, it is necessary to add a small amount of forward bias to take the transistor to the average of conduction or slightly beyond. This does slightly lower the efficiency of the circuit and there is a waste of stand by power, but it alleviates the cross-over distortion problem. Technically the operation

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LARGE SIGNAL (POWER) AMPLIFIERS

of transistors lies between class-B and class-A mode. Therefore, the circuit operation is often referred to as being class-AB operation.

T1 conducts Cross-over distortion

iC

iB

T2 conducts Output

Input

Fig. 14.17. Illustration of cross-over distortion.

In other words, we can say that such distortion would not occur if the driver stage were a true current generator, in other words, if the base current (rather than the base voltage) were sinusoidal. Thus, the transistor must operate in a class-AB mode. Where a small stand by current flows at zero excitation.

The rated power of a transistor solely depends upon the construction of the transistor, however, temperature limits the maximum power that a transistor can withstand. Usually, power rating of transistors lies in the range of few milli watts to 200 W. For Si transistors, the temperature ranges from 150°C to 225°C and for Ge it is between 60°C to 100°C. Now the question arises that what are the causes which tend to increase the junction temperature ? The junction temperature rises either because of ambient temperature or because of self-heating. Here, our main attention is over self-heating part, which is responsible for the thermal runaway. The self-heating can destroy the unstabilized transistor. The thermal runaway can be defined as the self destruction of collector junction because of self-heating.

Reason of Thermal Runaway It is very important to note that reverse saturation current I CO changes greatly with the temperature. (It nearly gets doubled for each 10°C rise in temperature).

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BASIC ELECTRONICS ENGINEERING & DEVICES

When current IC causes the collector junction temperature to rise, ICO increases because ICO depends upon minority carrier concentration and minority carriers are thermally generated. Now, as a result of growth of ICO, IC will increase, which may further increase the junction temperature and consequently I CO. It is more likely to have a cumulative succession of this phenomenon. Thus, the ratings of the transistors are exceeded, permanently damaging the transistor.

Condition for Thermal Stability To prevent thermal runaway the condition ;

PD 1 < should be satisfied H Tj where,

Tj = Junction temperature in (°C) PD = Power delivered at collector junction in watts. H = Constant of proportionality known as thermal resistance in °C/W

The maximum collector power PC allowed for safe operation is specified at 25°C. For ambient temperature above this value ; PC must be decreased and at extreme temperature at which the transistor can operate safely PC is reduced to zero. Following curve shows the relationship between power and temperature. Typically, this curve is named as derating curve; because as long as ambient temperature increases, the power gets derated. Pc,W 150 120 90 60 30

0

20

40

60

80

100 Case-temperature, °C

Fig. 14.18. Power-temperature derating curve for a Ge Power-Transistor.

How to avoid thermal runaway ? In this article, we are going to discuss the restrictions to be fulfilled for avoidance of thermal runaway. The required condition is that the rate of release of heat at the J C (collectorjunction) must not exceed the rate at which the heat can be dissipated. Mathematically ;

PC 1 < should be satisfied for thermal stability of the transistor. H Tj

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LARGE SIGNAL (POWER) AMPLIFIERS

In order to avoid thermal runaway :

VCC 2 RE RC

IC >

b

g

should be satisfied.

Heat-sink As we know that the increase in junction temperature causes self destruction of the collector junction. In order to avoid the phenomenon of thermal runaway (specially for the transistors handling high magnitude power signals) there should be some arrangement with the transistor which could wipe off the heat generated instantly. For this purpose, we often use a heat-sink. A heat-sink is a metallic foil either rectangular or circular that is used to dissipate heat developed at the collector junction of transistor.

In the power amplifiers, power transistors are employed which handle large currents. Because of heavy current these transistors are heated up during operation. Heat-sinks are not only used with power transistors but they are also used with other electronic device like SCRs : trioc, TCs, etc. Heat-sink is just a sheet of metal (Generally aluminium) which improves the heat dissipation ability of power transistor and keeps its temperature within permissible limits. Since-the quantity of heat to be dissipated depends upon the surface area of the heat-sink therefore heat-sinks are designed in various shapes. Thus, by using heatsinks, phenomenon of thermal runaway can be easily overcome.

Mathematical Analysis The permissible power p dissipation of transistor is very important term of power transistor. The permissible power rating of a transistor is determined from the expression. PTotal = where,

Ptotal Tj

(max)

Tj a max f Tambient

= Total power dissipated within the transistor in watts = Maximum permissible junction temperature

Tambient = Ambient temperature i.e., temperature of surrounding air in °C. = Thermal resistance i.e., resistance of heat flow from junction to the surrounding air. Its units are °C/watt. The value of is usually given in the transistor manual. Low value of means heat flows easily from junction to surrounding air i.e., more dissipation and smaller rise in temperature. In fact, heat-sink reduces the value of appreciably resulting an increase in power dissipation.

Summary 1. Power amplifier is a DC-to-AC power conversion whose action is controlled by the input signal.

614

BASIC ELECTRONICS ENGINEERING & DEVICES 2. For voltage transistor amplifier power dissipation < 0.5 watt. However for the power transistor power dissipation > 0.5 watt. 3. When only one transistor is used in the final stage of multistage amplifier, it is called single-ended power amplifier. 4. The ratio of ac output power to the d.c input power or zero signal power of an amplifier is known as collector or conversion efficiency : =

a f a f

Poutput ac 1 Pinput dc H

5. The change of output waveform from the input waveform of an amplifier is known as distortion. 6. The ability of a power transistor to dissipate heat developed in it during operation is known as its power dissipation capability. 7. The Relation between load Resistance (rL), turns ratio and the input resistance of the transformer in the case of transformer impedance matching is given by the relation

R L = R L where

FG N IJ HN K

2

1 2

RL = load impedance

R L = resistances seen looking into the primary of the transformer N1 = turns in primary side N2 = turns in secondary side. 8. For class-A amplifier the maximum collector efficiency max = 50% 9. There are two main advantage by using choke coil in place of RC (Collector Resistance) (i) no d.c voltage drop across the choke (ii) the d.c power lost in choke coil is almost nil. 10. Main classification of a power amplifier is class-A, class-B, class-C and class-AB. 11. The amplifier stage that immediately precedes the output stage and supplies the necessary power to the output stage is known as driver stage. 12. Maximum efficiency is class-B amplifier is about 78.5%. 13. The final stage of an audio multistage amplifier that provides the necessary power to drive the load is known as output stage. Usually, a push-pull amplifier is used as an output stage. 14. For class-A operation the biasing resistors are so adjusted that the operating point Q lies in the middle of the load line. 15. For class-B operation the biasing resistor are so adjusted that the operating point Q lies in the cut-off region. 16. The order of increasing distortion in the different class of amplifier is given as : class-C > class-B > class-AB > class-A 17. The order of increasing efficiency in the different class of amplifier is given as : class-C > class-B > class-AB > class-A

615

LARGE SIGNAL (POWER) AMPLIFIERS 18. Usually there are three types of distortion exists in an amplifier (i) Frequency distortion (ii) Phase or time-delay distortion (iii) Harmonic amplitude or non-linear distortion 19. Total distortion or harmonic distortion factor.

D22 D32 D24

D = where

D2 =

I2 called second harmonic distortion I1

20. Total power output due to all the harmonic components as the output is : PT = (1 + D)2 Pin 21. In push-pull amplifier, two transistors are needed and they conduct alternatively i.e., one conducts during positive half cycle and the other conducts during negative half cycle of the signal. The two transistor works in class-B operation. 22. A complementary symmetry push-pull amplifier is a circuit in which pair of npn and pnp transistor is used. The two transistor conducts alternatively. 23. Dissipated power is given by : PD = Pi – Po watts where

Pi = input power (dc) Po = output power (ac)

24. Relation between output maximum power and dissipated maximum power for class B amplifier. max

0.4 Po

PD

max

= maximum dissipated power

Po

max

= maximum output power

PD where

max

25. Cross-over distortion is reduced by using class-AB operation. 26. Second harmonic distortion in terms of VCE relation D2 =

1 2

dV

CE max

max,

VCE

i

min

VCE min VCE Q

VCE max VCE min

and VCE

Q

is given by the

.

? 1. Distinguish between voltage amplifier and power amplifiers. 2. Derive expression for efficiency of class-A amplifier. Show that its maximum value is 50%. 3. Draw the circuit of a single ended class-A amplifier. Explain its working what will be its collector efficiency. 4. Why is a power amplifier also known as “Large signal amplifier ?” Why does a power amplifier generally employ a step down transformer in its collector circuit ? Explain.

616

BASIC ELECTRONICS ENGINEERING & DEVICES 5. What is heat sink ? Why do we use heat sink in power amplifiers ? 6. Draw the block diagram of an audio amplifier and mention the function of different stages. 7. Define and explain the following terms as applied to power amplifiers ? (i) Collector efficiency

(ii) Distortion

(iii) Power dissipation capability. 8. Why harmonic distortion is prominent in power amplifiers ? Support your answer with mathematical expressions. 9. Draw the circuit diagram of a push-pull amplifier circuit. Explain (a) How proper biasing is achieved in this circuit. (b) How ac power, free from even harmonics is developed across the load ? 10. Draw the circuit diagram of a push-pull amplifier circuit and explain its working. Why this circuit is called push-pull ? 11. Draw a practical circuit of a complementary symmetry push-pull amplifier and explain its working. Why this circuit has become more popular in modern circuits ? 12. Explain how to complementary transistors in a class-B push-pull amplifiers act simultaneously as phase inverters and an output push-pull pair.

Example 1. Fig. P (14.1) shows the circuit of a common emitter amplifier. Determine the values of collector current and collector-to-emitter voltage at the points of saturation and cut-off under ac signal operation. Also draw the ac load line, assume V BE = 0.7 V. Solution : Given that VCC = 10 V,

R1 = 10 k

R2 = 5 k,

RC = 1 k

RL = 1.5 k,

RE = 500

= 100 and

VBE = 0.7 V

With the help of Thevenin equivalent model (which have been already discussed).

FG R IJ HR R K F 5 IJ = 10. G H 10 5K

VBB = VCC .

2

1

8.78

AC Load line

2

= 3.33 V

Q

5.26 IC (mA)

Value of emitter current, IE =

VBB VBE 3.33 0.7 RE 500

= 5.26 mA

0

2.11 VCE (in volt)

Fig. P (14.1)

5.27

617

LARGE SIGNAL (POWER) AMPLIFIERS

Value of collector current, ICQ = IEQ = 5.26 mA Collector to emitter voltage. VCEQ = VCC – ICQ (RC + RE) = 10 – (5.26 10–3) (1000 + 500) = 2.11 V. + VCC = 10 V

10 k

RC = 1 k CC C

R1

CC

B

B = 100

RS Vin

E 6 k

Ri = 1.5 k

R2 RE = 500

CE

Fig. P (14.2)

Now, we shall find the values of collector current and collector-to-emitter voltage of saturation and cut-off points. We know that at saturation point, the collector current, IC

(sat)

= ICQ +

VCEQ R L

where ( R L = RC || RL)

R L = RC || RC = 1000 || 1500 = 600 IC

(sat)

5.26 10 –3

=

2.11 1000 ||1500

= 8.78 10–3 A = 8.78 mA. Ans. and the collector to emitter voltage VCE

(sat)

= 0. Ans.

Similarly, the collector current at cut-off point and

IC

(cut-off)

= 9. Ans.

VCE

(cut-off)

= VCEQ + ICQ . rL = 2.11 + 5.26 10–3 600 = 5.27 V. Ans.

The ac load line may be obtained by plotting the points of a.c saturation and a.c cut-off and then joining them by a straight line as shown in Fig. P (14.2). Example 2. A power amplifier is operated from a 10 V d.c supply. It gives an output of 3W. Find the maximum collector current in the circuit.

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BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : Let IC be the maximum collector current. Power = Supply voltage collector current 3 = 10 IC IC =

3 = 0.3C Amp. Ans. 10

Example 3. Determine the turn ratio of the output transformer to match an 10 speaker load to an amplifier having effective load of 1.8 k . Solution : Let the turn ratio of output transformer be n =

N1 N = P N2 NS

We know that,

R L = n2 . RL n2 =

R L RL

R L RL

n = where

R L = effective load RL = Load resistance (i.e., speaker)

1800 10

n =

180 = 13.42 14. Ans.

Example 4. For a power transistor working in class-A operation has zero signal power dissipation of 8 W. If the AC power is 4 W, determine (i) Power rating of transistor (ii) Collector efficiency Solution : We know that in class-A operation the power rating of transistor = zero signal power dissipation = 8 W. Ans. Pdc = 8 W

i.e., Given Collector efficiency,

Pac = 4 W =

Pac 100 Pdc

4 100 = 50%. Ans. 8 Example 5. The transistor of a class-A power amplifier is supplied from a 6 V Battery. If the maximum collector current change is 30 mA, find the power transferred to an 10 loudspeaker when : =

619

LARGE SIGNAL (POWER) AMPLIFIERS

(i) It is connected directly to the collector circuit. (ii) It is coupled through a transformer for maximum power. Also determine the turns ratio of coupling transformer. Solution : Here, given that IC

max

= 30 mA.

VCE

max

= 6 V.

RL = 10 (i) When loudspeaker is connected directly

[see Fig. P (14.3)]

+ VCC = 6 V

R1

10

Loudspeaker

CC

Input signal R2

RE

CE

Fig. P (14.3)

Maximum voltage across loudspeaker = IC RL = 30 mA 10 = 300 mV. Power delivered to the loudspeaker = 300 mA 30 mA = 9 mW. (ii) When loudspeaker is connected through a coupling transformer, as shown in Fig. P (14.4). Output impedance of transformer is the ratio of maximum change in collector to emitter voltage to the maximum change in collector current. i.e.,

RS =

VCE max I C max

=

6V = 200 30 mA

We know that for maximum power transformer, the load resistance referred to primary side must be equal to output impedance of transistor i.e., R L = 200

620

BASIC ELECTRONICS ENGINEERING & DEVICES

10

+ VCC = 6 V

R1

Loudspeaker

CC

Input signal

R2 RE

CE

Fig. P (14.4)

R L = n2 RL

Now,

n =

R L RL

200 10

20 4.47 5

Now, secondary voltage i.e., voltage across the speaker VL = V S = Load current,

IL =

VP Vce 6 = 1.2 V n n 5

VS 1.2 = = 0.12 Amp. VL 10

Power transferred to speaker = IL VL = 0.12 12 = 0.144 W or = 144 mW.

Example. 6. For class-A, CE transistor amplifier, the operating point is located at IC = 250 mA and VCE = 8 V. Due to input signal the output collector current goes in between 450 mA and 40 mA. The VCE swings between 15 V and 1 V. Determine : (i) The output power delivered, (ii) The input power, (iii) Collector efficiency, (iv) Power dissipated by the transistor. Solution : Given :

IC = 250 mA VCE = 88 V IC

(max)

= 450 mA

IC

(max)

= 40 mA

VC

(max)

= 15 V

VC

(min)

= 1 V

(i.e., zero signal or ac condition) (zero signal condition or dc condition)

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LARGE SIGNAL (POWER) AMPLIFIERS

(i) Output power delivered or ac power output

bV

max

=

g bI

max

2

P(ac) = =

Vmin

bV

max

I min

g

2 2

Vmin

g bI

max

I min

g

RS P T

ac

8

a15 1f V a450 40f mA 8

=

Vm I m 2

UV W

14 410 = 717.5 mW. 8

(ii) Input power or dc input power Pdc = VCE IC = 8 250 = 2000 mW (iii) Collector efficiency, =

Po a ac f Pin a dc f

100

717.5 100 = 35.87% 2000 (iv) Power dissipated by the transistor =

PD = Pdc – Pac = 2000 – 717.5 = 1282.5 mW. Example 7. A transistor BC 147 is used as a medium power transistor. Its thermal resistance is 0.29°C/mW when no heat sink is provided. The maximum junction temperature is 90°C. If the ambient temperature is 25°C, find : (i) The maximum power dissipation that can be allowed. (ii) The maximum power dissipation that can be allowed with aluminium heat sink of 12.5 cm2 area which reduces the thermal resistance to 0.08°C/mW. Solution : (i) When no heat sink is used Tj

(max)

= 90°C

Tamb = 25°C = 0.29°C/mW Ptotal =

Tj a max f Tamb

=

90 25 = 224 mW. 0.29

=

90 25 = 812.5 mW. Ans. 0.08

(ii) When heat sink is used Tj

(max)

= 90°C

T(amb) = 25°C = 0.08°C/mW Ptotal =

Pj a max f Tamb

Example 8. We are to match a 20 speaker local to an amplifier so that the effective load resistance is 10 k. What should be the transformer turns ratio ?

622

BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : We know that,

R L = R L where

FG N IJ HN K

2

1 2

R L = effective load resistance RL = load resistance or speaker N1 = Primary turns N2 = Secondary turns

Given

R L = 10 k = 10 1000 RL = 20

FG N IJ HN K

2

= n2 =

1 2

n =

R L RL

R L RL

1000 20

500 = 22.36 23

N1 = 23 : 1. N2

or

Example 9. A sinusoidal signal VS = 1.75 sin 600 t is fed to an amplifier the resulting output current is of the form l0 = 15 sin 600 t 1.5 sin + 1200 t + 1.2 sin 1800 t + 0.5 sin 2400 t. Calculate : (a) Second, third and fourth harmonic distortions, (b) Percentage increase in power because of harmonic distortion. Solution : We know that (i) Second harmonic distortion, D2 =

I2 1.5 = = 0.10 I1 15

D3 =

I3 1.2 = = 0.08 I1 15

Fourth harmonic distortion, D4 =

I4 0.5 = = 0.03 I1 15

Third harmonic distortion,

(ii) To calculate the percentage increase in power, first-of-all calculate total distortion factor (D). And assume that input power is P1. The distortion factor is : D = =

D22 D32 D24

a0.1f a0.08f a0.03f 2

The net output power is : Ptotal = (1 + D2) P1

2

2

= 0.1323.

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LARGE SIGNAL (POWER) AMPLIFIERS

= {1 + (0.1323)2} P1 = 1.0175 P1. Thus, the percentage increase in power is : % Increase in power =

Ptotal P1 1.0175 P1 P1 100 = 100 P1 P1

= 1.75%. Ans. Example. 10 (a) If the transfer characteristics of the power transistor can be approximated by a second degree equation as ic = G1 ib + G2 ib2 , show that collector current contains a second harmonic components, B2 and a dc component B0 in addition to the fundamental component B1. [Given that ib = im cos wt]. (b) Calculate the value of B0, B1 and B2 in terms of IC

max,

Imin and IC.

(c) A transistor supplies 0.85 Watts total power to a 4 k load. The dc collector current is 31 m A. When there is no signal. When si

RL = RL

10000 20

500

again applied, the dc collector current increases to 34 m A. Find the percentage 2nd harmonic distortion. Solution : (a) Given that, ib = im cos t ic = G1 ib + G2 ib2

so,

ic = G1 im cos t + G2 . im2 cos2 t or

ic = G1 im cos t + G2 im2

or

ic =

FG 1 cos 2t IJ H 2 K

G2 2 G im + G1 im cos t + 2 im2 cos 2t 2 2

R| Let us S|assume T

ic = B0 + B1 cos t + B2 cos 2t

or

Now, taking quiescent current (I C) into account. ic = IC + B0 + B1 cos t + B2 cos 2t (b) when

t = 0, then ic = Imax = IC + B0 + B1 + B2

2 ic = IC + B0 – B2

When

t =

When

t = ic = Imin = IC + B0 – B1 + B2

0 1

2

G 2 im2 2

G 1 im G 2 im2 2

U| V| W

624

BASIC ELECTRONICS ENGINEERING & DEVICES

Also, from above B0 = B2 From above equations, we have Imax – Imin = 2B1

I max I min 2

B1 =

I max I min 2 (c) We know that B0 = 34 – 31 = 3 mA = B2. B0 = B2 =

12 R L 2

P = or

2P RL

B1 =

2 85 = 20.6 mA. 4 1000

We know that second harmonic distortion.

B2 3 mA 100 100 = 14.6%. Ans. B1 20.6 mA

D2 =

Example 11. The maximum collector dissipation of a transistor used in a class-A amplifier is 10 W. When a signal is applied, the collector efficiency of circuit is 32%. Calculate the ac power output. Solution : Given

PD = 10 W = 32% = 0.32 Po

(a.c)

=?

We know that, =

Po a a.c f Pi a d .c f

...(1)

Also we know that Pi = Po + PD So, from equations (1) and (2), we have =

Po Po PD

0.32 =

Po Po 10

0.32 Po + 3.2 = Po Po (1 – 0.32) = 3.2 Po =

3.2 = 4.7 watt. Ans. 0.68

...(2)

625

LARGE SIGNAL (POWER) AMPLIFIERS

Example 12. An amplifier has a collector efficiency of 50% and operates from a 24 V supply if the output power is 3.5 W, what is the total dissipated within the circuit ? What is most likely source for most of this power loss ? = 50% = 0.5

Solution : Given : Po

(ac)

= 3.5 V

VCE = 24 V PD = ? We know that =

50 =

Po a a.c f Pi a d .c f

100

3.5 100 Pi a d .c f

...(1)

Also from equation, Pi

(dc)

= Po

(a.c)

+ PD

...(2)

Hence from equations (1) and (2), we have 0.5 =

3.5 3.5 PD

P, = 3.5 W. The power PD = 3.5 W is dissipated in the form of heat within the transistor collector regions. Example 13. A three stage amplifier has higher cut-off input frequency is 50 Hz. What is the value of output frequency ? Solution : We know that

21/n 1

f H* = f H where

f H* = upper 3d B or cut-off frequency of the output f H = upper 3d B or cut-off frequency of the input n = number of stages

Here given,

n =3 f H = 50 f H* = ? f H* = 50 21 / 3 1 = 24.49 = 24.5 Hz. Ans.

Example 14. A four stage amplifier has lower cut-off input frequency is 100 Hz. What is the value of lower cut-off output frequency ? Solution : We know that, f L* =

fL 1/ n

2

1

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BASIC ELECTRONICS ENGINEERING & DEVICES

Given

f L = 100 Hz n =4

So,

100

f L* =

21/ 4 1

= 229.89 230 Hz. Ans.

Example 15. An output waveform displayed on an oscilloscope provided the following measured values. (a) VCE min = 1.2 V, VCE max = 22 V, VCEQ = 10 V (b) VCE min = 2 V, VCE max = 18 V, VCEQ = 10 V Determine the percentage second harmonic distortion. Solution : Second harmonic distortion in terms of VCE max , VCE min and VCEQ is given by the relation.

1 VCEmax VCEmin VCEQ D2 = 2 100 VCEmax VCEmin

d

i

b

g

1 1 22 1.2 10 23.2 10 2 2 100 = 100 = 7.7%. Ans. D2 = 22 1.2 29.8

(a)

a

f

1 18 2 10 D2 = 2 18 2

(b) or

D2 =

10 10 = 0 16

i.e., 0% or no distortion. Ans.

Example 16. In class-B push-pull operation the dc power drawn is 25 W. At the ideal efficiency of power conversion what is the power delivered. Solution : Given

Pi

(d.c)

= 25 W

= 78.5% = 0.785 Po

(a.c)

=?

= Po

(a.c)

Po a a.c f Pi a d.c f

= 0.785 25 = 19.625 W. Ans.

Example 17. Fig. P (14.5) shows a push-pull class-B amplifier using complementary symmetry transistors. Given VCC = 6 volts. Peak output current amplitude is 1 amp. What is the dc power drawn from each power supply ? Solution : Given VCC = 6 volts Im = 1 amp Assume

= 78.5% = 0.785

627

LARGE SIGNAL (POWER) AMPLIFIERS + VCC

in the case of class-B push-pull amplifier. =

0.785 =

Po a ac f Pi a dc f Po a ac f

or

VCC . I C

0.785 =

Po a ac f

VS

6 1

VO RL

( IC = Im in class-B push-pull amplifier) Po

(ac)

= 6 0.785 = 4.71 W

dc power drawn from each power supply is – VCC

4.71 = = 2.355 W. Ans. Fig. P (14.5) 2 Example 18. For the circuit given underhere find out the value of H required for the Ge transistor circuit to be thermally stable. Assume

VCC = 30 V and RC = 2.0 K and RC = 4.7 K. VCC

RC

R1

IC

VC

+

C

B IB

Vi

E

R2

RC N

–

Fig. P (14.6)

Solution : Above mentioned self bias circuit can be simplified by using Thevenin’s theorem as under : IC RB

RC C

B

VCE

IB + –

E

V

RE N

Fig. P (14.7)

+ –

VCC

628

BASIC ELECTRONICS ENGINEERING & DEVICES

Applying KVL in output ; we get

I C = 1.5 mA and RE = 4.7 k is assumed. PC = 30 – (2) (1.5) (4.7 + 2.0) = 9.9 V IC

Now,

For an increase in temperature from 25°C to 75°C I C increases by 0.131 mA

IC 0.131 10 3 = = 2.62 × 10–6 A/°C T j 75 25

Now,

9.9 2.62 10–6

1.

(iii) If A is equal to unity, no change occurs in the output and we get an output with constant magnitude is known as undamped oscillations as shown in Fig. 15.7 (c).

Vt t

O

Fig. 15.7 (c). Undamped oscillations when A = 1.

638

BASIC ELECTRONICS ENGINEERING & DEVICES

These oscillators use resistors and capacitors are used to generate low or audio frequency signals. Thus, they are also known as audio frequency (AF) oscillators, such oscillators are given below namely : (i) Phase shift oscillator (ii) Wein bridge oscillator

Basic principle of phase shift oscillator is that a fraction of the output single-stage amplifier is passed through a phase-shift network, before feeding back to input. The phase-shift network gives another phase-shift of 180 in addition to the phase-shift of 180 introduced by the amplifier. Thus, there is a total phase-shift of 360, which is also equal to 0. The RC oscillator, utilizing this principle is known as phase-shift oscillator. Circuit arrangement of phase-shift oscillator is shown in Fig. 15.8. Resistance R 1, R2 and R3 are the biasing parameter and Rc is the load resistance. There are three R-C combinations forming feedback network. Each R-C combination provides a phase shift of 60. Hence the net phase shift produced by three RC networks is 180 and another 180 phase shift is provided by transistor itself. Thus, total 360 phase shift is produced between the input and output signal. The phase shift , given by each RC

1 if R is made zero then will be become 90. But making CR R = 0 is impractical because if R is zero then voltage across it will become zero, therefore in practice the value of R is adjusted such that become 60. section is = tan 1

+Vcc

R1

Rc

In

R C

C

C

C

Ib

V1

R2

R RE

C

C +

+ R

R

R

VC

R

CE

Fig. 15.8. Phase shift oscillator.

–

–

Fig. 15.9. Feedback network.

The transitor used in this circuit is C-E configuration. Let for this circuit hoe RC < 0.1 so that we may use the approximate hybrid model (as discussed earlier). Also, it is assumed that biasing resistor R1, R2, and RE have no effect on the signal operation and are neglected in the analysis. The circuit for the feedback network is shown in Fig. 15.9. Since it is the case of voltage shunt feedback hence input and output can be

639

OSCILLATORS

separated without feedback by using V0 = 0 and I1 = 0 respectively. The frequency of oscillation is given by 1 fr = 2 RC 6 4 K

1 . 29 In order that |A| shall not be less than unity. It is required that the amplifier gain |A| must be more than 29 for oscillator operation. At this frequency, it is found that the feedback factor of the network is || =

Derivation of Frequency Oscillation First of all draw its approximate hybrid model as shown in Fig. 15.10 (a). C

Ib

hfelb

hie

C

Rc

C

R

R

R

Fig. 15.10 (a). Approximate hybrid model for h RC > 0.1.

From the Fig. 15.10 (a), loop gain =

I3 Ib

Now, to make calculation easy, apply the source transformation technique in Fig. 15.10 (a) and the equivalent circuit is shown below in the Fig. 15.10 (b). C

Rc

Ib

hie

C

R

hfelb

I1

C

R I2

R I3

Fig. 15.10 (b). The equivalent circuit for which to calculate the loop gain.

Now, applying KVL in the loop (1), (2) and (3) we get – hfe Ib RC – I1 [(RC – JXC) + R] + I2R = 0

...(15.1)

(2R – JXC) I2 – I1R – I3R = 0

...(15.2)

(2R – JXC) I3 – I2R = 0

...(15.3)

1 RC X and = C = , on putting these value equations (15.1), (15.2) R R CR and (15.3) may be rewritten as Let K =

– hfe Ib RC – I1 {K + 1 – J} + I2 = 0

...(15.4)

I2 (2 – J) – I1 – I3 = 0

...(15.5)

(2 – J) I3 – I2 = 0

...(15.6)

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BASIC ELECTRONICS ENGINEERING & DEVICES

From equation (15.5) and (15.6), we get (2 – J) I3 (2 – J) = I1 + I3 or

...(15.7)

I3 (2 – J) (2 – J) = I1 + I3

or

I3 {(2 – J) (2 – J) – 1} = I1

or

I3 {3 – 2 – 4J} = I1

...(15.8)

On substituting the values of I1 and I2 in equation (15.4). In order to calculate ratio

I3 , we get Ib

– hfe Ib K = I3 {(3 – 2 – 4J) (k + 1 – J)} – (2 – J) I3 – hfe Ib K = I3 {3K + 3 – 3J – K2 – 2 + J3 – J4K – J4 – 42 – 2 + J} – hfe Ib K = I3 {1 + 3K – (5 + K) 2 – J (6 + 4K) – 3}

From equation (15.9) the loop gain

...(15.9)

I3 and if this is to be real co-efficient of J, must Ib

be equal to zero i.e., (6 + 4K) – 3 = 0 or

2 = 6 + 4K

1 = CR 1 = 2 f CR f =

RS 1 UV T CR W

6 4K

=

6 4K 6 4K

{ = 2f }

1 2CR

...(15.10)

6 +4K

This is the required condition for the frequency of oscillation in phase shift oscillator. Now,

h fe K I3 = Ib 1 +3K – 5 +K 2

or

h fe K I3 = Ib 1 +3K – 5 +K 6 4K

or

h fe K I3 = Ib 1 +3K – 30 – 24K – 4K 2

or

h fe K I3 = 2 Ib 4K 23K +29

a

a

But loop gain 1 or

I3 1 Ib

f

fa

f

{ 2 = 6 + 4K}

641

OSCILLATORS

h fe K

or

2

4K 23K +29

1

29 ...(15.11) K Now, we will calculate the minimum or maximum value of hfe (i.e., gain of the transistor). To calculate it we must differentiate equation (15.11) with respect to K, we get h fe 29 4 – K K2 hfe 4K + 23 +

h fe

For maximum or minimum value,

K

0 =4 – K =

= 0

29 K2

29 2.75 4

On putting the value of K in equation (15.11), we get hfe 44.5

...(15.12)

Thus, the value of K which gives the minimum hfe turns out to be approximate 2.75 and for this value hfe = 44.5, i.e., a transistor with a small signal common emitter short circuit current gain less than 44.5 cannot be used in the phase shift oscillator.

Advantages of Phase Shift Oscillator Following are the advantages of phase shift oscillater : It does not require transformers or inductors, that’s why it is less bulky. Cheap and simple circuit as it contains resistors and capacitor only. Waveform is exceptionally pure and sinusoidal since the core saturation effect

and harmonic distortion are absent as no transformer is used.

Disadvantages of Phase Shift Oscillator Following are the disadvantages of phase shift oscillater : The main disadvantage of this circuit is the high gain requirement (approximately

> 44.5) which is practically impossible. It gives only small output due to smaller feedback. Feedback is less and it is difficult for the circuit to start oscillations. This is

because of high reactance of R and C. It requires high supply voltage i.e., VCC > 12 V.

Example 1. Select the value of capacitor C and transistor hfe to provide an oscillator frequency f = 2 KHz in phase shift oscillator Given

RC = 10 K, R = 8 K

642

BASIC ELECTRONICS ENGINEERING & DEVICES

Solution : Given that f = 2 KHz = 2 103 Hz RC = 10 k = 10 103 R = 8 K = 8 103 We know that the frequency of oscillation in the case of phase shift oscillation is given by relation (equation (15.10)).

1

f =

2 RC 6 +

4R C R

1

2 × 103 =

2 8 10 3 C

6+4.

10 10 3 8 10 3

or

1 2 × 103 = 2 8 10 3 C

or

2 × 103 =

or

C =

or

C = 3.0 × 10–9 F = 0.003 µF

6+5

1 2 8 10 3 C 3.32 1 16 10 3 2 10 3 3.32

Value of transistor gain hfe is given by relation hfe 23 + 29

R R 4 C RC R

or

hfe 23 + 29

FG 8 10 IJ 4 . FG 10 10 IJ H 10 10 K H 8 10 K

or

hfe 23 + 23.2 + 5

or

hfe 51.2

or

hfe = 51.2. Ans.

3

3

3

3

In the circuit for wein bridge oscillator as shown in Fig. 15.11. A second-stage of amplifier is used for producing another 180 phase shift in addition to the phase shift of 180 produced by the first stage. Thus, there is total phase shift of 360, which is the basic requirement. A fraction of output from the second stage is feedback to the input of the first stage without producing any further phase-shift. The RC oscillator utilizing this principle, is known as wien bridge oscillator.

643

OSCILLATORS +Vcc

R

2

R1

R5

C1

Rc

R7

Rc

Cc +VO

C

2

Cc Q2

Q1 R

4

R6

R3

R8

RE

RE

CE

Negative feedback

Fig. 15.11. Wein bridge oscillator.

The wein bridge oscillator consists of two transistor (CE configuration) which provides an approximately 360 or 0 phase shift so the feedback network has no need to introduce any additional phase shift where R5, R6, R7 and R8 are biasing resistors. The feedback network consists of C1–R1 and C2–R2 (called a lead-lag network) and R3–R4 (called a voltage divider). The lead-lag network provides a positive feedback to the input of the first stage and the voltage divider provides the negative feedback to the emitter of the transistor Q1.

Derivation for frequency of oscillation For calculating the frequency of oscillation the feedback network of wein bridge oscillator is shown in Fig. 15.12. We know that at balanced condition phase shift must be zero. According to wheat stone bridge, P R = Q S

R3

1 R1 j C1

R4 1 R2 j C2 1 R2 j C2

=

S

R1 C1

C2

R

2

Q

+

4

R

R

3

P R

So,

–

Fig. 15.12. Feedback network or wein bridge oscillator.

644

BASIC ELECTRONICS ENGINEERING & DEVICES

R 3 j C1 R = 4 ( jC2R2 + 1) R2 jR1 C1 1

j

–

FG R R H 2

FG R R H 2

3

R2R3 jC1 = R4R1 j22C1C2R2 + R4R1jC1 + R4 + R4 jC2R2 3

R4

IJ K

C2 R 2 C = R – R R R C C 2 1 4 1 2 4 1 2 C1

R 4 R1 R 4

IJ K

RS T

C2 R4 R2 = j R 4 R1R 2C1C2 C1 C1

UV W

...(15.13)

the oscillation will be possible only when phase shift zero. The oscillation frequency is given by

R4 – C2R4R2R1 = 0 C1 2 =

or

f =

1 C1C 2 R1R 2

{ = 2f }

1 2 R1R 2 C1C 2

...(15.14)

Condition for oscillation : R 2R 3 – R1R 4 – R 2R 4

C2 =0 C1

R 3 R1 C = 2 R4 R2 C1

...(15.15)

This is the required condition for oscillation. If,

R1 = R2 = R and C1 = C2 = C, then from equation (15.15).

R3 – 1 = 1 R4

R1 C1

R3 = 2 R4 We know that

=

C2 R2

Vo

V f

Vf

R4

R3

Vo

But from Fig. 15.13 applying potential divider Fig. 15.13

rule Vf = Vo.

or

Vf Vo

=

R4 R3 R 4

R4 R3 R 4

645

OSCILLATORS

or

=

R4 2R 4 R 4

or

=

1 3

...(15.16)

Also since as we know that A 1 A

1 1 3 A 3

...(15.17)

Thus, for oscillation produced gain must be equal to or greater than 3.

Advantages of Wein Bridge Oscillator Following are the advantages of wein bridge oscillator : It has better stability. Output is constant. Its working quite simple and easy. Overall gain in high as two transistors are used. Frequency of oscillations can be easily adjusted by varying gang capacitors C 1

and C2.

Disadvantages of Wein Bridge Oscillator Following are the disadvantages of wein bridge oscillator : Costlier as more components are used. It cannot be used to generate very high frequency (> 1 MHz) this is the main

draw back of this circuit. Note : Why wein bridge oscillator used for audio frequency oscillator ? Since the frequency of oscillation for the wein bridge oscillator is f = f =

1 or R1R 2 C1C 2

1 , when R1 = R2 and C1 = C2 and the practical feasible value of RC gives the frequency 2 RC

of audio range that’s why this oscillator is mainly used as audio frequency oscillator.

Example 2. A wein bridge oscillator is used for operation at f = 10 KHz. If the value of R is 100 K. Find the value of the capacitor C. Solution : Given :

f = 10 KHz = 10 103 Hz R = 100 K = 100 103

We know that frequency of oscillation in a wein bridge oscillation is given by relation.

646

BASIC ELECTRONICS ENGINEERING & DEVICES

f = 10 103 =

1 2RC 1 2 100 10 3 C 1 2 100 10 3 10 10 3

or

C =

or

C = 159 10–12 F

d

i

C = 159 PF. Ans.

These oscillators called tuned circuit oscillator are also known as LC oscillators resonant circuit oscillators or tank circuit oscillators. These oscillator are used to produce an output with frequencies ranging from 1 MHz to 500 MHz. Hence they are also known as radio frequency (RF) oscillators.

Fig. 15.14 shown the circuit of a Hartley oscillator. Tank circuit consists of two coils L1 and L2 and a capacitor C. The coil L1 is inductively coupled to the coil L2 and the combination works as an auto transformer. A coil called Radio Frequency Choke (RFC) is connected between the oscillator and VCC supply. The feedback between the output and input circuit is accomplished through auto transformer action, which also introduceds a phase shift of 180. The phase reversal between the output and input voltage occurs because they are taken from the opposite ends of the coils (L 1 and L2) with respect to the tap, which is grounded. Since the transistor also introduces a phase shift of 180, therefore, the total phase shift is 360 and hence feedback is positive. Ignoring the loading effects of the base, the feedback fraction is given by the relation. = Also since

L2 L1

A 1

L A . 2 1 L1 A

L1 L2

It means voltage gain must be equal to

L1 L2

647

OSCILLATORS +Vcc RF Choke Cc

R1 CB

+ L1 C

R2 RE

Vo L2

CE

–

Fig. 15.14. Hartley oscillator.

The resistor R1, R2 and RE are used to provide dc bias to the transistor. When the circuit is energised, switching on the supply, the collector current flows. The oscillations are produced because of positive feedback from the tank circuit.

General Derivation for Frequency of Oscillations Before the derivation for frequency of oscillation for Hartley Oscillator. Let us derive the general theory for Hartley and Colpitts oscillator. The equivalent circuit is shown in Fig. 15.15. Here we have made some assumptions. First, hre of transistor is negligibly small and so the feedback source hre Vo is neglected from the equivalence circuit. Second, hoe of transistor is very small i.e.,

1 is also neglect from the equivalent circuit. hoe

1 output resistance is very large. So hoe

Let us calculate the ZL (load impedance) between output terminals 2 and 3. Here ZA and hie are in parallel. Their impedance is in series with ZC, the resultant impedance is in parallel with ZB hence,

1 1 1 = ZA Z A hie Z A =

i.e.,

Z A . hie Z A hie B

C IC

1 I1

hfeIB

hie

IB

ZA

E I1

2 ZC

Fig. 15.15

ZB

3 I1

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BASIC ELECTRONICS ENGINEERING & DEVICES

Impedance of ZA and ZC is given by ZA + ZC =

b

Z A hie ZC Z A hie Z A . hie + ZC = Z A hie Z1 hie

=

Z A hie ZA ZC Z C hie Z A hie

=

hie Z A ZC Z A ZC Z A hie

b

g

g

Load impedance is given by

1 1 1 = ZL ZB Z A ZC =

=

=

ZL =

1 Z A hie Z B hie Z A ZC Z A ZC

b

(Put the value of ZA)

g

b

g bZ

b

hie ZA ZC Z A ZC ZB ZA hie ZB hie

b

A

g

g

ZC Z A Z C

g

hie Z A Z B ZC ZA Z B ZA ZC

b bZ

g Z gZ Z

Z B hie ZA ZC ZA ZC Z B hie

A

B

A

C

hie Z A Z B ZC ZA Z B ZA ZC

...(15.18)

The voltage gain without any feedback is A = –

h fe ZL

...(15.19)

hie

The feedback factor can be calculated as follows : The output voltage between terminal 3 and 2 Vo = (ZA + ZC) I1

FG Z h Z IJ I HZ h K L Z h Z Z Z h OP = I M Z h N Q L bZ Z g h Z Z OP = I . M N Z h Q A

Vo =

ie

A

1

C

ie

A

ie

1

A

1

A

1

C

C

ie

ie

B

A

ie

A

C

ie

The voltage feedback to the input terminal (1) and (2), given by Vf b = ZA I1 =

Z A hie I1 Z A hie

...(15.20)

649

OSCILLATORS

Vf b Z A hie = Vo hie Z A ZC Z A ZC

=

b

g

For condition A = 1, we get

LM MN h bZ LM MN h bZ

h fe Z L hie or

b

ie

g

h fe ZB hie ZA ZC Z A ZC

b

g

hie ZA ZB ZC ZA Z B ZA ZC

ie

A

Z A hie ZC Z A ZC

A

ZA ZC Z A ZC

g

g

OP PQ OP PQ

= 1

= – 1

hie Z B Z A = – 1 hie Z A Z B ZC Z A Z B Z A ZC

or

b

or

g

hie (ZA + ZB + ZC) + ZAZB (1 + hfe) + Z1Z3 = 0

...(15.21)

Equation (15.21) is the general equation for the oscillator.

Derivation for Frequency of Hartley Oscillator In the case of hartley oscillator (See Fig. 15.14) ZA = jL1 + jM ZB = jL2 + jM

1 j = – jC C

ZC =

Put these values in general equation (15.21), then we get hie

LMb j L N

1

g b

g

j M j L2 j M

j C

OP + ( jL Q

1

+ jM)

(jL2 + jM) (1 + hfe) + (jL1 + jM) – j hie

LML N

1

L 2 2M –

1 2C

OP Q

– 2 (L1 + M) (L2 + M) (1 + hfe) +

bL

1

j = 0 c

M C

g

= 0

Simplify the above equation as j hie

LML N

1

L 2 2M –

1 2C

OP Q

– 2 (L1 + M)

LMbL N

2

Equating the imaginary part equal to zero, we get hie

LML N

1

L 2 2M –

L1 + L2 + 2M –

1 2C

OP Q

=0

1 =0 2C 2C =

gd

i

M 1 h fe

1 L1 L 2 2M

OP Q

1 = 0 ...(15.22) 2C

650

BASIC ELECTRONICS ENGINEERING & DEVICES

=

1

bL

f =

f =

g

L 2 2M C

1

1 = 2 2

bL

2

1

bL

1

1

g

L2 2M C

1

...(15.23)

g

L 2 2M C

Conditions for oscillations can be obtained by equating coefficients of real part of equation (15.5) to zero. Thus (L2 + M) (1 + hfe) –

1 =0 2C

(1 + hfe) = or

(1 + hfe) = =

1 C L2 M

b

2

bL

1

g

g

L 2 2M C C L2 M

b

g

L1 L 2 2M L2 M

b

g b L Mg bL Mg = b L Mg F L M IJ =G H L MK 1

2

= 1 +

1 2

2

hfe

FG L HL

1

M M

IJ K ...(15.24)

2

Example 3. Calculate the frequency of a transistor Hartley oscillator. If L1 = 200 µH, L2 = 2 mH, mutual inductance between the coils M = 20 µH and C = 20 pF. 1 Solution : f = (From equation (15.23)) 2 L1 L 2 2 M C

b

Given :

g

L1 = 200 µH L2 = 2 µH M = 20 µH C = 20 pF f =

1 2 314 .

f =

1 2 3.14

1

a200 2000 2 20f 10

6

20 10 12

1 2240 10

6

20 10 12

f = 7523.20 KHz. Hartley oscillator is probably the most popular oscillator and is commonly used in radio receivers. It is because of its easy adaptability to a wide range of frequencies.

651

OSCILLATORS

Colpitts oscillator is similar to Hartley oscillator. The only difference is that in case of colpitts oscillator, coupling is capacitive instead of being inductive. Fig. 15.16 shows the colpitts oscillator circuit. The tank circuit is made up of two capacitors C 1 and C2 connected in series with each other across a fixed inductance (L). The resistors R 1, R2, RE and RF choke have the same function as mentioned in Hartley oscillator. The feedback between the output and input circuit is accomplished by the voltage developed across the capacitor C2. Ignoring the loading effect of the base, the feedback fraction

or

A

R2

C2 C1

L

C2 RE

C1 1 C2 A

A

Cc C1

A 1

But, since

RF choke C

R1 CB

C = 1 C2

or

+Vcc

CE

B

Fig. 15.16. Colpitts oscillator.

Thus, to start the oscillation, the voltage gain (AV) must be greater than

FG C IJ . The HC K 2 1

frequency of oscillation (neglecting mutual inductance) is given by the relation. f = where

C =

1 2 LC

C1C 2 (C is the effective value of capacitance) C1 C 2

It may be noted that in a Colpitts oscillator C1 and C2 act as a simple alternating voltage divider. Therefore, points A and B are out of phase with each other and another phase shift of 180 is provided by the transistor itself. Thus, there is a total phase shift of 360 between the emitter-base and collector-base circuits. Colpitts oscillator is widely used in commercial signal generator ranging from 1 MHz to 500 MHz. Frequency of oscillation is varied by gang-tuning the two capacitor C 1 and C2.

Derivation for frequency of oscillations for colpitts oscillator hie (ZA + ZB + ZC) + ZAZB (1 + hfe) + ZAZC = 0 In case of Colpitts oscillator ZA =

1 J = – J C1 C1

ZB =

1 J = – J C2 C2

ZC = JL

(From equation 15.21)

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BASIC ELECTRONICS ENGINEERING & DEVICES

Put these values in general equation (15.21), we get hie

LM– J N C

1

OP FG Q H

IJ FG J IJ d1 h i FG J IJ J L K H C K H C K F 1 1 1 IJ 1 h L – J h G H C C L K C C C F 1 1 LIJ LM 1 h L OP J h G H C C K N C C C Q

J J J L C2 C1

fe

2

fe

ie

1

2

2

1

2

1

2

2

1

= 0

1

fe

ie

= 0

1

= 0 ...(15.25)

1

2

Equating the imaginary part of equation (15.25) equal to zero then, we have hie or

FG 1 H C

1

IJ K

1 L = 0 C2 1 1 = L C1 C2 C2 C1 = L C1C 2 2 =

or

f=

C1 C 2 or = L C1C2

b

1 2

g

RSbC C g UV T LC C W 1

RSbC C g UV T LC C W 1

2

1

2

1

2

...(15.26)

2

The above equation gives the frequency of oscillations.

Condition for Oscillation Equate real part of equation (15.25) to zero, we get

1 h fe 2

C1C2

or

=

L or 1 + hfe C1

=

2 LC 2 C1 = 2LC2 C1

1 + hfe = hfe =

bC

g

C2 C LC2 = 2 + 1 LC1C 2 C1 1

C2 C1

Example 4. Calculate the frequency of transistor Colpitt’s oscillator. If C1 = 0.001 mF, C2 = 0.01 mF and L = 20 mH Solution :

f=

1 2

LM bC C g OP N LC C Q 1

2

1

2

(From equation 15.26)

653

OSCILLATORS

L1 = 20 H

Given :

C1 = 0.001 F C2 = 0.01 F =

1 2 3.14

a0.001 0.01f 10 i d0.001 10 i d0.01 10 i 6

d20 10

6

6

6

= 1181.5 KHz.

So far, we have studied the oscillators in which the oscillations are produced by the oscillatory circuit. The major problem in these circuits is that their frequency of operation does not remain perfectly constant. It is because the values of resistors and inductors change with temperature. However, in some of the applications it is necessary to maintain constant frequency with an extremely low tolerance. The solution to this problem is use of crystal oscillators. In crystal oscillators, piezoelectric crystal are employed in place of RL or RC circuit. The frequency of crystal oscillators remains more or perfectly constant even if temperature changes.

The crystal is usually made of quartz material and provides a high degree of frequency stability and accuracy or we can say that crystal oscillator is basically a tuned oscillator. It uses a piezoelectric crystal (when an ac voltage is applied across a crystal it starts vibrating at the frequency of supply voltage, the effect is known as piezoelectric effect and the crystal which exhibit this effect is known as piezoelectric crystals, conversely, when these crystals are placed under mechanical strain to vibrate, they produce an ac voltage. For example, rochelle salt, quartz and tourmaline are known as piezoelectric materials. Out of the three, rochelle salts exhibit the greatest piezoelectric activity) as a reasonant tank circuit. The crystal is usually, made of quartz material and provides high degree of frequency stability and accuracy. Therefore, the crystal oscillators are very useful in those applications where frequency stability is very essential. The crystal oscillators are widely used in communication transmiters, digital watches and clocks etc. Electrical equivalent circuit of a crystal : The electrical equivalent circuit of a crystal consists of series R-L-C in parallel with capacitor C m when the crystal is applied across the ac source it is not vibrating, it is equivalent to the capacitor C m. However, when crystal vibrating, it acts like tuned R-L-C circuit.

XL

R Xtal

L

Cm

(b) Equivalent cirecuit

Fig. 15.17

P

O

s

Xc

Reactive (Capacitance)

C

(a) Symbol

Reactive (Inductance)

(c) Reactance function (if R = 0)

654

BASIC ELECTRONICS ENGINEERING & DEVICES

Fig. 15.17 (a) shows the symbol of piezoelectric crystal while Fig. 15.17 (b) shows its equivalent circuit. However, Fig. 15.17 (c) shows the graph between reactance versus frequency. If this device is properly mounted deformation takes place within the crystal, and an electromechanical system is formed which will vibrate when properly excited. The resonant frequency and the quality factor (Q) depend upon the crystal dimensions. The crystal has two resonant frequencies viz series resonant frequency and parallel resonant frequency. In this case when the impedance of the circuit is equal to the resistance R X L = X C. S L =

Thus,

S =

or

1 C S 1 LC

Then frequency of oscillations is given by fS =

1 2 LC

...(15.27)

this frequency of oscillation is called series resonant frequency. This is occur when resistance of series arm equals the reactance of C m. p L –

1 pC

=

or

p L =

or

p2 L =

where

1 pCm 1 1 pCm pC 1 1 C +C m = Cm C C . Cm

p =

C +C m LCC m

fp =

1 2 LC eq

Ceq =

...(15.28)

C . Cm C +C m

usually the value of Cm is much larger than C therefore the frequencies Fp and Fs are very close to each other otherwise Fp is always more than Fs. However, when crystal is used as oscillator, the oscillation frequency always lie between Fs and Fp. The impedance versus frequency graph of crystal is shown in Fig. 15.18.

655

OSCILLATORS

Z R

fS

fP

f

Fig. 15.18. Impedance versus frequency graph of the crystal.

Transistor crystal oscillator : The circuit arrangement for transistor crystal oscillator is shown in Fig. 15.19. This arrangement is used in the place when a constant high frequency (25 kHz – 5 MHz) is required, a transistor crystal oscillator is always preferred. +Vcc R1 XtalCl

RFC +

V t

R2 RE

CE –

Fig. 15.19. Transistor crystal oscillator.

Advantages of Crystal Oscillator Following are the advantages of Crystal Oscillator : The circuit is very simple. It does require any tank circuit other crystal itself. It provides high degree of frequency stability. It possess very high quality factor. Different oscillation frequencies can be achieved by simply replacing one crystal

with another.

Disadvantages Crystal Oscillator Following are the disadvantages of Crystal Oscillator : These oscillators are used are not fit for frequencies less than 100 kHz. The crystal oscillators have very limited tunning range. The crystal oscillators are fragile and therefore, can be used in low power

circuits.

656

BASIC ELECTRONICS ENGINEERING & DEVICES

Example 5. Calculate the parallel resonant frequency, series resonant frequency and Q factor of the crystal oscillator, if the crystal of the oscillator has the following parameters : C = 0.06 µF ; L = 0.5 H ; Cm = 1 pF and R = 10 K. Solution : Given :

C = 0.06 pF L = 0.5 H R = 10 K Cm = 1 pF

Parallel resonant frequency of crystal is given by fp =

1 2

C +C m LCC m

=

1 2

a0.006 1f 10 d0.5 0.06 10 i d1 10 i

(From equation 15.28) 12

12

12

= 946 kHz.

Series resonant frequency of crystal is given by fs =

1 2 LC

=

1

2

a0.5f d0.06 10 i 12

= 918.9 kHz.

Q factor of the crystal is given by Q =

=

sL 2 fs L = R R

d

i

2 918.9 103 0.5 10 10

3

= 288.54.

The frequency stability of an oscillator measures its ability to maintain a constant frequency over a long time interval. However it has been found that if an oscillator is set at some particular frequency, it does not maintain for a longer period. In other words the frequency of oscillator changes slowly (or drifts away) from the initially set values. But at some times, it may be changing quite erratically. The change in oscillation frequency my arises due to the following factors. 1. Supply voltage : The change in dc supply voltage applied to the active device, shifts the oscillator frequency. This problem can be avoided by using highly regulated power supply. 2. Operating point of the active device : The operating point of the active device (i.e., bipolar transistor or FET) is selected in such a way that its operation in non-linear region, changes the values of device parameters which, in turn affects the frequency stability of the oscillator. 3. Circuit components : The values of circuits components (i.e., resistor, inductors and capacitors) change with the variation in temperature. Such changes take place slowly, they also cause a drift in oscillator frequency.

657

OSCILLATORS

4. Output load : A change in the output load may cause a change in the Q-factor of the tank circuit, thereby causing a change in oscillator output frequency. 5. Stray capacitances and inter element capacitances : Any change in the inter element capacitances of a transistor causes changes in the oscillator output frequency and thus affects the frequency stability. Similarly, the stray capacitance also affects the frequency stability of an oscillator. The effect of change in inter element. However it is very difficult to avoid the effect of stray capacitance.

Summary 1. Oscillator is a circuit which converts dc energy into ac energy. 2. There are two types of oscillator circuits namely sinusoidal or harmonic oscillators circuit and non-sinusoidal or relaxation oscillator. 3. The static electronic devices that produces sinusoidal oscillations of desired frequency is called a sinusoidal oscillator. 4. The electrical oscillation whose amplitude decreases with time are known as damped oscillation. 5. However the electrical oscillations whose amplitude does not decreases with time are known as damped oscillation. 6. A circuit that produces electrical oscillations of desired frequency is known as an oscillatory circuit or tank circuit. 7. The resonance frequency of oscillation is given by the relation. fr =

1 2 LC

8. In phase shift oscillator the frequency of oscillator. f =

1 R where, K = c R 2RC 6 +4K

Each RC network provides a phase shift of 60 ; = tan–1

FG 1 IJ H 2CR K

9. Minimum gain required in case of phase shift oscillator is 44.5 10. Frequency of oscillation in the Wein bridge oscillator is f =

1 2 R1R 2C1C2

11. Feedback ratio () in Wein bridge oscillator must be greater than

1 . 3

12. Frequency of oscillation in Hartley oscillator is f = or

1 where, Leq = L1 + L2 + 2M L eq C

Leq L1 + L2 (When mutual inductance M is neglected)

13. Frequency of oscillation in Colpitts oscillators is f =

1 C1C2 where, Ceq = C1 C2 2 LC eq

14. The percentage change of quantity (frequency) on either side is called tolerance.

658

BASIC ELECTRONICS ENGINEERING & DEVICES

? 1. What do you understand by damped and undamped electrical oscillations ? 2. What is the condition of oscillation ? 3. Draw and explain tuned collector oscillator. 4. Draw the circuit and explain the operation of Colpitt’s oscillator. 5. Discuss in detail Hartley oscillator. 6. Draw and discuss in detail the circuit of an R-C phase shift oscillator. 7. Draw the circuit of a Wein bridge oscillator and explained its working. Why is negative feedback employed in this oscillator circuit in addition to the usual feedback positive feedback. 8. Explained the properties of quartz crystal which are responsible for its use in oscillator. 9. Explain why : (i) Three R-C section are used R-C phase shift oscillator. (ii) Negative feedback is provided in Wein bridge oscillation. (iii) In Wien bridge oscillator, gangs are employed. (iv) At low frequency (1 Hz to 100 kHz) application, we employ R-C oscillators and not L-C oscillator. 10. What are the factors which affect the frequency stability of an oscillator ? 11. What is Bark hausen criterion for the frequency stability of an oscillator ? 12. Explain how L-C tank circuits is used to generate oscillations in an electronic oscillator.

Example 1. An oscillatory circuit has L = 0.01 H and C = 10 pF, find the frequency of oscillations. Solution : Frequency of oscillation f =

=

1 2 LC

=

1 2

0.01 10 10 12

10 6 = 550 kHz. Ans. 2 0.1

Example 2. A tuned collector oscillator has a fixed inductance of 150 µH and has to be tunable over the frequency band of 500 kHz to 1500 kHz. Find the range of variable capacitor to be used. Solution : Resonant frequency is given by f =

1 2 LC

659

OSCILLATORS

C = When,

1 4 f 2 L 2

f = 500 kHz C =

2

1

d

4 500 10

i

3 2

150 10

6

=

1 4 2 250000 100

= 1015 pF When

f = 500 kHz C =

2

1

d

4 500 10 3

i

2

150 10 6

= 113 pF

Hence, capacitor range required in (113 – 1015) pF Ans. Example 3. In a transistor colpitt’s oscillator, (i) Operating frequency (ii) Feedback fraction (iii) Minimum gain to sustain oscillations (iv) Emitter resistance if RC = 2.5 Solution : (i) Given

L = 100 H C1 = 0.001 H C2 = 0.01 F

Operating frequency,

where

f =

C =

= Now,

f =

1 2 LC

C1C 2 0.001 . 10 – 6 0.01 10 6 = C1C 2 0.001 . 10 6 0.01 10 6 0.001 0.01 10 6 = 0.0000909 10–6 0.011

1 2 100 10

6

0.0000909 10 6

= 528 kHz. Ans. (ii) We know that feedback fraction () is given by =

C1 0.001 10 – 6 = = 0.1 C2 0.01 10 6

(iii) Minimum gain to sustain oscillations, A 1 Amin = 1 Amin =

1 1 = = 10. Ans. 0.1

660

BASIC ELECTRONICS ENGINEERING & DEVICES

A

(iv) Since,

RE

or

RC RE RC 2.5 k = 0.25 . Ans. A 10

Example 4. In a transistorised Hartley oscillator, if L1 = 0.1 mH, L2 = 10 mH and mutual inductance (M) between the two coils = 20 µH, calculate the value of capacitor C1, of oscillatory circuit to obtain the frequency of 4110 kH2. Solution : We know that in Hartley oscillator, the tqo coil L1 and L2 are connected in series and coupled magnetically So, total inductance of the coils L = L1 + C2 + 2M = 100 H = 150 H Frequency of oscillations,

f =

4110 105 =

C =

1 2 LC

1 2 150 10 6 C

a2 f

1 2

150 10

6

d

4110 10 3

i

2

= 10 pF. Ans.

Example 5. A resistance of 10 k is connected in series with a capacitor. If an alternating frequency of 1 kHz is applied across the network, find the value of C for a phase shift of 60 (i.e., RC phase shift oscillator). Solution : We know

tan =

tan 60 =

1.732 =

1 C = R CR 1 2 1 10 C 10 10 3 3

1 2 10 10 10 3 C 3

C = 0.009 F. Ans.

Example 6. In a Wein bridge oscillator given that R1 = R2 = 200 k and C1 = C2 = 250 pF. Determine the frequency of oscillations. Solution : Frequency of oscillations in Wein bridge oscillator is given by f=

1 2 R1R 2 C1C 2

When

R 1 = R2 = R

and

C1 = C2 = C, then

661

OSCILLATORS

1 2RC

f =

1

or

f =

or

f = 3177.9 Hz. Ans.

2 200 10 250 10 12 3

Example 7. Consider the two-section RC network shown in Fig. P (15.1), find the

Vf Vo

function and verify that it is not possible to obtain 180 phase shif t with a finite attenuation. C

C

+

+ R

Vo I1

–

Vf

R I2

–

Fig. P (15.1)

Solution : Applying kVL in loop (1) and (2), we get

FG R + 1 IJ H j C K F 1 I 0 = GR + H j C JK I

Vo = I 1

2

– I 2R

...(i)

– I 1R

...(ii)

From equations (i ) and (ii )

F 1 I FG 2R + 1 IJ I FG R + 1 IJ – I R H R K H J C K H J C K O I LF 1 IF 1 I = 2R + R+ RP M G J G J R NH J C K H J C K Q

Vo =

Vo or

2

2

2

Vf = I2R I2 = Vf IR Vo =

or

or

LMFG 2R + 1 IJ FG R + 1 IJ – ROP R . R NH J C K H JC K Q V f

Vo J 3R C + 1 – R 2 2C2 = Vf R 2 2 C2 Vf Vo

=

2 C2 R 2 C R 2 1 3RJ C 2

2

662

BASIC ELECTRONICS ENGINEERING & DEVICES

1 XC = = R CR

Put

Vf Vo

=

1 2

1 J3

In order to have a phase shift of 180, tan = tan 1800 = 0 – = 0 or = 180. If = 0, then from the above expression

Vf Vo

3 . Hence either 1 2

= 1 it means phase shift is 0 not 180.

Note that = 0 requires either R = or C = which means that output is connected directly to the input. On the other hand if = , then

Vf

Vo

= 0 and this

woulde require an amplifier with infinite gain. Note that = means either C = 0 or R = 0 so the attenuation is infinite. Example 8. A Colpitts oscillator has a coil with an inductance of 50 H and is tuned by a capacitor of 300 pF across the output. Find the frequency of oscillation and the minimum gain for maintaining oscillation. Solution : For Colpitts oscillator the frequency is given as f =

=

C1C 2 1 ; where Ceq = C 1 C2 2 LC eq 300 100 300 100 = 75 pF

L = 50 H so,

1

f = 2

50 10

6

75 10

6

f 2.6 MHz. Ans.

or For maintaining oscillation

Aloop 1 or or

Aopen Aopen

or

loop

loop

Aopen

= 1

C2 = 1 C1 loop

=

{Aopen

loop

=

= open loop gain or gain}

C2 C1

C1 3 = = 3. Ans. C2 1

Example 9. Prove that in a crystal the ratio of frequencies in series and parallel resonance is given by 1 +

1 C . 2 C

663

OSCILLATORS

Solution : The equivalent circuit of a crystal oscillator is given by From the given Fig. series resonant frequency is given by fs =

1 2 LC

and parallel resonant frequency is given as fp = where Ceq =

L

1 ; 2 LCeq

C R

C . C C C

C

f s and f p may be written as

fs2 =

f p2 =

Fig. P (15.2). Equivalent circuit of a crystal oscillator.

1

a2 f

2

LC

1 2 . LCeq

a f

2

According to given condition,

f p2 fs2 f p2

or

fs2 f p2

or

fs2

fp

or

fs fp

or

fs fp

or

fs

F 1 I F a2f LC I GH a2f LC JK GH 1 JK 2

=

=

2

eq

LC C . C L. C C

= 1

C C

1

=

F H

= 1 = 1

C C

C C

I K

2

1 C (Neglecting the higher terms) 2 C

Hence proved.

1. An FET oscillator having gm = 6000 s, rd = 36 k, and feedback resistor R = 12 k is to operate at 25 kHz. Calculate the value of capacitance C. 2. For an FET Hartley oscillator calculate the oscillator frequency, given that C = 250 pF, L1 = 1.5 mH, L2 = 1.5 mH and M = 0.5 mH. 3. An oscillatory circuit has L = 0.2 H, C = 100 pF, find the frequency of oscillations.

664

BASIC ELECTRONICS ENGINEERING & DEVICES 4. A tuned collector oscillator has a fixed inductance of 150 H and has to be tunable over the frequency band of 500 kHz to 1000 kHz. Find the range of variable capacitor to be used. 5. In a transistor Colpitt’s oscillator, L = 100 H, LRFC = 0.6 H, C1 = 0.01 H, C2 = 0.01 F determine. (i ) Operating frequency (ii ) Feedback fraction (iii ) Minimum gate to sustain oscillations (iv) Emitter resistance if RC = 2.5 k. 6. Take into account the loading of RC network in the phase-shift oscillator. If R o is the output impedance of amplifier (assume that CS is arbitrary large) then prove that the frequency of oscillation f and the minimum gain A are given by f =

1 2 RC

1

b

6 4 R o IR

g

; A = 29 + 23

F I H K

Ro Ro 4 R R

2

7. For the FET oscillator shown in Fig. N (15.1) : (a)

Vf Vo

(b) The frequency of oscillations (c) The minimum gain of the source follower required for oscillation. VDD R + C

R

C

R

+

RS

– C

Vo

Vf

–

–

VSS +

Fig. N (15.1)

A Acceptors, 22 Amplifier coupling, 544

B Brief Review of Historical Significance and Development of Electronics, 1 Brief Introduction, 5 Breakdown Mechanism, 146 Breakdown Characteristic of a Zener Diode, 148 Basic Construction of a Junction Transistor, 168 Biasing of JFET, 280 Basic Operation and Characteristics of n-channel Depletion-Type MOSFET, 305 Basic Operation and Characteristics of Enhancement-Type MOSFET, 308 Binary Coded Decimal (BCD), 326 Boolean Algebra, 347 Bandpass of cascaded stages, 543 Bandwidth of RLC (tuned series circuits), 572 Bark hausen criterion, 636 Base spreading resistance (rbb), 478 Basic concept of feedback, 506 Bootstrapping, 568

C Comparison between Electron Tubes and Solid State Devices, 2 Covalent Bond, 7 Conduction in Intrinsic Semiconductors, 30 665

Comp-1/Laxmi-5/Computer/Revision/Belect-in—15.5.07

Comparison of Rectifier Circuits, 108 Choke Input or L-section Filter, 124 Capacitor Input or -Filter, 126 Clipping Circuits, 130 Clamping Circuits, 134 Comparison in Different Configurations, 179 Classification of Amplifiers, 231 Computation of AI , AV , Zi , Zo of Single Stage Transistor CE and CC Amplifier Configuration, 249 Classification of Field-effect Devices, 264 Comparison between BJT and FET, 265 Computation of Av , Ri , Ro of Single FET Amplifiers, 283 Comparison of JFET and MOSFET, 311 Conversion of Bases, 318 Complements, 331 Concept of Op-Amp, 404 Concept of Virtual Ground, 410 Cascade amplifier, 542 Choke coil, 597 Circuit components, 656 Class A amplifier, 592, 594 Class-A push-pull amplifier, 601 Class-AB amplifier, 592, 594 Class-AB operation and cross-over distortion, 610 Class-B amplifier, 592, 594, 603 Class-B push pull amplifier, 606 Class-C amplifier, 592, 594, 605 Classification of negative feedback, 511 Collector efficiency, 597 Colpitts oscillator, 651

666

BASIC ELECTRONICS ENGINEERING & DEVICES

Complementary symmetry push-pull amplifier, 609 Controlled current source (gmVbe), 478 Conversion efficiency, 597 Coupling, 545 Crystal oscillators, 633, 653 Current amplifier, 517 Current gain, 467 Current law (kcl), 464 Cut-off frequency, 496

Effect of negative feedback on amplifier output impedance, 523 Effect of negative feedback on bandwidth and frequency response, 524 Effect of negative feedback on stability, 521 Effect of source resistance on frequency response, 491 Effects of feedback circuits, 521 Electrical equivalent circuit of a crystal, 653 Emitter follower, 561

D

F

Doping, 14 Donors, 21 Diode Capacitance, 62 Different Ratings of Diode, 64 Different Types of Transistor Configuration, 171 Depletion-type MOSFET, 304 Damped oscillations, 633 Darlington connection, 563 Direct coupled amplifier, 559 Direct coupling, 545 Distortion in amplifiers, 592 Double tuned voltage amplifier, 577 Dual miller’s theorem, 526

Fermi Level, 19 Full Wave Rectifier (FWR), 99 Full Wave Bridge Rectifier, 106 Filters, 122 FET as an Amplifier, 282 FET Applications, 287 Feedback, 506 Feedback factor, 508 Feedback in amplifier, 506 Feedback network, 519 Feedback ratio, 508 Frequency distortion, 5