Antenna-on-Chip: Design, Challenges, and Opportunities (Antennas) 1608078183, 9781608078189

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Antenna-on-Chip Design, Challenges, and Opportunities

For a complete listing of titles in the Artech House Antennas and Electromagnetics Analysis Library, turn to the back of this book.

Antenna-on-Chip Design, Challenges, and Opportunities

Hammad M. Cheema Fatima Khalid Atif Shamim

Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the U.S. Library of Congress. British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library. Cover design by Charlene Stevens

ISBN 13: 978-1-60807-818-9

© 2021 ARTECH HOUSE 685 Canton Street Norwood, MA 02062

All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher.   All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark.

10 9 8 7 6 5 4 3 2 1

Contents

Preface

xi

1

Introduction to Antenna-on-Chip

1

1.1

Antennas and ICs: A Brief History

2

1.2 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5

Circuit Integration Technologies Interconnection Technologies MCMs SiP SoP SoC

5 6 8 12 14 17

1.3 1.3.1 1.3.2 1.3.3 1.3.4

On-Chip Antennas: Benefits and Opportunities Cost and Size The 50Ω Boundary: Not Needed Anymore Integration and Robustness Fabrication Precision and Repeatability

19 20 22 23 25

1.4

AoC: An Inevitable Choice for the Future

26

1.5

Conclusion

27

References

27

v

vi

Antenna-on-Chip: Design, Challenges, and Opportunities

2

Design and Implementation Challenges

31

2.1 2.1.1 2.1.2 2.1.3

Incompatible Silicon Substrate Low Resistivity of Silicon High Dielectric Constant of Silicon Surface Waves

32 33 35 36

2.2

Limitations of the CMOS Stack-Up

41

2.3 2.3.1

Modeling and Simulation Challenges Cosimulation Tools

42 42

2.4 2.4.1

Size and Layout Challenges DRC

45 46

2.5

Fabrication Tolerances

53

2.6 2.6.1 2.6.2

Coupling and Interference Issues Coupling from the Antenna to the Circuit Coupling from Circuits to the Antenna

54 54 56

2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5

Characterization Challenges Reflection from the Probe Radiation of the Probe Radiation Blockage or Shadowing AUT Movement Restrictions Measurement of Standalone Antennas

61 63 64 64 65 66

2.8

Packaging Challenges

67

2.9

Conclusion

68

References

68

3

Radiation Enhancement and Measurement Techniques 73

3.1 3.1.1 3.1.2 3.1.3

Substrate Post-Processing Techniques Substrate Thinning High-Resistivity Substrates Substrate Micromachining

75 75 78 79

3.2 3.2.1

On-Chip Reflecting Surfaces AMCs

83 85

3.3 3.3.1

Off-Chip Techniques Dielectric Superstrates

90 91



Contents

vii

3.3.2 3.3.3 3.3.4

Artificial Dielectric Layers Dielectric Resonator Loading Dielectric Lens

94 96 100

3.4 3.4.1 3.4.2 3.4.3 3.4.4

3-D and MEMS-Based Antennas Suspended Antennas Vertical Monopoles Movable Antennas Bond-Wire Antennas

103 104 104 106 107

3.5 3.5.1 3.5.2

Measurement and Characterization Techniques Mitigating the Effects of On-Chip Circuits Mitigating the Effects of Measurement Setup

111 111 113

3.6

Conclusion

119

References

120

4

Codesign of Circuits and Antennas

125

4.1 4.1.1 4.1.2 4.1.3

Codesign Considerations AoC in Receiver AoC in Transmitter AoC in the Transceiver

126 126 130 132

4.2

Choice of Transistor Technology

133

4.3 4.3.1 4.3.2 4.3.3

Impedance Matching LNA-Antenna Matching PA-Antenna Matching T/R Switch-Antenna Matching

135 137 140 142

4.4 4.4.1 4.4.2 4.4.3

Circuit-Compatible Antenna Layout and Design Size and Layout Codesign Differential and Single-Ended Feeding On-Chip Antennas with Added Functionality

146 146 148 148

4.5

Codesign to Prevent Antenna-Circuit Coupling

151

4.6

Antenna Circuit Cosimulation

156

4.7

Codesign of Package and Antenna

161

4.7.1 4.7.2 4.7.3

Packaging Design Considerations Packaging Materials Codesign for Performance Enhancement

161 163 165

viii

Antenna-on-Chip: Design, Challenges, and Opportunities

4.8

Conclusion References

169 169

5

AoC Design Example

175

5.1

Design Flow

175

5.2

71-GHz Oscillator Transmitter with an On-Chip Monopole Antenna

178

5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5

Antenna Simulation Substrate Antenna Element AMC Superstrate Layer Lens Integrated Package

182 182 185 188 193 194

5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7

Circuit Simulation Adding a Design Library Schematic Design Layout Design DRC LVS Parasitic Extraction Post-Layout Simulation

196 198 198 205 207 210 211 214

5.5 5.5.1 5.5.2

Cosimulation Simulating the Circuit in EM Simulator Simulating the Antenna in the IC Simulator

214 214 218

5.6

Fabrication

221

5.7 5.7.1 5.7.2

Measurement and Characterization Standalone Characterization Active Characterization

222 222 225

5.8

Conclusion

227

References

228

6

Future Trends in AoC

229

6.1

Performance Enhancement: A Continuing Challenge

230

6.2

Codesign and Multifunctional Role of AoC

231



Contents

ix

6.3

Specialized Radios and Implantable Applications

232

6.4

Energy-Harvesting AoCs

234

6.5

Miniaturization of Low-Frequency AoCs

235

6.6

Terahertz Applications

236

6.7

MEMS and CMOS Codesign

237

6.8

Wireless Networks on Chip

238

6.9

Future Role of Foundries in AoC

240

6.10

Advances in Simulation and Measurement

241

6.11

Conclusion

242

References

242



Acronyms

247



About the Authors

255



Index

257

Preface More than a century has elapsed since Heinrich Hertz first demonstrated a functioning antenna in his lab in 1888. The antenna, a 1m long dipole, was able to transmit a 50-MHz signal, thus proving for the first time the existence of electromagnetic waves. Since then, antennas have been extensively studied and utilized to create the ubiquitously connected world we have today. As the key radiating element, the designs, the size, and the technologies of antennas have changed drastically from large parabolic reflectors to millimeter-sized metal structures in modern smartphones and sensor nodes. At the same time, unprecedented advancements in semiconductor technology have led to highly integrated on-chip circuits that drive these antennas and constitute the backbone of wireless communication. Antenna-on-chip (AoC) represents the ultimate integration of these two sides; the antenna and the front-end circuits. It conceptualizes the integration of the antenna with the circuits directly on the silicon chip, resulting in smaller and more compact system sizes as well as lower interconnection losses. AoC also opens the door to an array of untapped applications in areas of medical implants, specialized radios, imaging systems, and wireless sensing units. The journey toward this book started with the publication of a review article on this topic by the authors in 2013. The article, “The Last Barrier: OnChip Antennas,” explored the opportunities and challenges related to on-chip antennas at the time and envisioned their potential in future applications. It generated considerable interest in the research community and since then, the need of a thorough text on the subject was felt. This need has been further augmented by the rapid development of silicon technologies, simulation software, and packaging techniques in the past decade. Moreover, the shift toward higher xi

xii

Antenna-on-Chip: Design, Challenges, and Opportunities

frequencies made the design and implementation of microscale antennas all the more feasible as an intrinsic part of the chip. The book’s objective is to introduce, in a logical order, the design, challenges, and solutions associated with antenna-on-chip technology. It is written for academics and researchers, on both sides of the conventional divide of circuits and antennas, who are now gearing to design and integrate radiating structures on silicon substrates. The book is also intended to serve as a guideline for designers to be able to apply the stated concepts for on-chip antenna design for a range of real-life applications. In Chapter 1, the concept of antenna-on-chip is introduced with a brief history of both antenna and integrated circuit technologies, followed by advancement in their respective fields that led to the need for their unification. The antenna-on-chip technology is also compared with other existing antenna integration solutions with a focus on the benefits and opportunities it brings along. Like every new integration technology, AoC comes with its own set of challenges. Chapter 2 gives an overview of these challenges, which revolve around the limitations of silicon technologies, constraints in IC design, and the lack of adequate simulation tools and characterization techniques. The chapter also includes solutions to mitigate many of these challenges. Following the bottlenecks discussed in Chapter 2, the subsequent chapters introduce the solutions and strategies that can be used to overcome them. These solutions are divided into two categories: radiation performance enhancement and seamless integration. Ever since AoC technology was introduced, scientists—both in industry and academia—have made valuable efforts in improving its performance. Chapter 3 objectively compares these approaches in terms of cost, complexity, and extent of gain improvement while also discussing important advancements in measurement techniques. The challenges related to the integration of antennas with on-chip circuits are addressed in Chapter 4, which introduces the unique approach of codesign. Aspects such as impedance matching, effective layout, and crosstalk mitigation under the codesign realm are discussed in detail and provide the way forward for efficient coexistence of on-chip antennas and circuits. The book includes a step-by-step design example of an actual on-chip antenna. Detailed in Chapter 5, this example takes the reader through all the stages in the design flow of an on-chip antenna using current simulation tools. The chapter is meant for beginners in the field of AoC design and addresses common issues such as importing antenna or circuit layouts across various simulation platforms and including the effect of different on-chip elements in final antenna measurements. Finally, Chapter 6 discusses the recent trends and future opportunities in AoC design. This chapter is especially helpful for young academics as it



Preface

xiii

identifies the yet-unsolved challenges in the field of AoC such as gain enhancement, THz applications, RF energy harvesting, and miniaturization. These challenges could prove to be promising areas of active research in the future. The authors would like to thank Mr. Haoran Zhang in providing valuable data and research material, especially for Chapter 5. We also thank our families for their strong support and understanding during this arduous but fulfilling project.

1 Introduction to Antenna-on-Chip In April 1973, history’s first mobile phone call was made by Motorola engineer Martin Cooper using the world’s first commercial cell phone. The call was placed from Sixth Avenue, New York, to the headquarters of Bell Labs in New Jersey, marking the beginning of a remarkable journey of mobile cellular technologies. Fast forward to today, more than 5 billion of the nearly 7.8 billion inhabitants of this planet are mobile phone users [1]. This unprecedented growth in the last 3 decades is not only limited to cellular technologies; Wi-Fi, Global Positioning System (GPS), Bluetooth, radio frequency identification (RFID), and a plethora of other wireless standards have also become mainstream. How did this happen? Among the factors contributing to this explosive growth and popularity of wireless, the principal reason was the ever-decreasing cost of electronics. This affordability found its roots in high levels of integration, in other words, by maximizing functionality on a single chip. This integration, in turn, was bolstered by the rapid scaling of semiconductor processes, new fabrication and packaging methodologies, and innovation in electronic system architectures, circuits, and devices. Although the integration helped to develop multifunction, multistandard, end-to-end complex chipsets, one component that remained largely detached from the integration story was the antenna. Antenna is an intriguing transducer linking an enclosed circuit to the outside world. Needless to say, it is the key component through which decades of wireless communication has been made possible. Traditionally, it was seen as a large, metallic structure, bulging out of gadgets enabling them to transmit and receive radio waves. However, with time, it too scaled down from bulky horns and large Yagi antennas to miniature, almost invisible, structures in modern-day gadgets. Aided by advances in semiconductor technology, fabrication techniques, and computational power, this journey, to shrink the physical 1

2

Antenna-on-Chip: Design, Challenges, and Opportunities

dimensions of antennas without degrading their performance, has been no less than fascinating. However, the last barrier of truly integrating the antenna onto the chip and that too at scale, remains to be conquered. The advent of the Internet of Things (IoT), wearable electronics, and the shift towards millimeter-wave frequencies for fifth generation (5G), sixth generation (6G) wireless communication, and automotive radar has further necessitated the pervasive need of integrated circuits (ICs) with antennas on chip (AoC). As a result, the last decade has seen a surge in the research community’s interest to surpass the numerous challenges posed by this approach, and the quest continues. This chapter recounts the evolution of antennas and ICs through the years and the ultimate union of the two. A brief history of antenna and circuit integration technologies is recounted followed by the major advances in AoC technology. Also discussed are the existing approaches to integrate antennas into the mix of circuits and ICs along with their advantages and drawbacks with a special focus on miniaturization challenges. In the end, the benefits of AoC technology with regard to system costs, size constraints, reliability, and ease of integration is investigated.

1.1  Antennas and ICs: A Brief History The origins of antenna technology can be dated back to the unification of electricity and magnetism by James Clark Maxwell in 1873. The set of equations proposed by him has weathered the test of time and stands today as the guiding principles of electromagnetic transmission. In 1886, Heinrich Hertz verified Maxwell’s work by demonstrating the first wireless transmission. He was able to create radio waves by generating a spark between the arms of a dipole antenna and receive them in a loop antenna nearly 1.5m away. In 1901, Guglielmo Marconi took this concept one step further and demonstrated the first long-distance electromagnetic transmission across the Atlantic Ocean. From then on, every decade has seen significant new developments in the field of antennas and signal propagation. In the 1930s, systems engineering heavily influenced antenna design, which began to take specialized forms to suit various applications. New radio electronic systems were introduced such as television (TV) and frequency modulation (FM) broadcast, microwave communications, tropospheric scatter communications, very high frequency (VHF) and centimetric radars, and advanced navigational aids [2]. However, most antennas were still wire-based designs. World War II triggered the need for advanced antenna designs, and, as a result, horns, reflectors, and arrays were introduced. The 1950s saw a wider use of broadcast television with more than 40 million households in the United States owning one. Antennas such as dipoles, cross-dipoles, Yagi-Udas, and logperiodic dipole arrays were in high demand to enhance the reception and expan-



Introduction to Antenna-on-Chip

3

sion of broadcast television. During the 1960s and 1970s, advances in satellite communication resulted in global industrial advancement with electrically large antennas at the helm. Moreover, in the same period, the microstrip antenna was also invented and designing low-profile antennas that could be horizontally connected to electronics became possible. In the 1980s, with the introduction of cellular phones, wireless technology, in many ways, was reinvented. The turn of the twenty-first century saw an explosion in consumer demand for wireless devices, digital streaming, and social connectivity. The desire to interconnect electronic systems and enable ubiquitous communication between them demanded the need for integrated and miniaturized antennas. Shrinking the size of an antenna was no easy task, but researchers invented remarkable innovative ways to miniaturize many different types of antennas. What is seen today are tiny antennas, assisting cell phones, wearable smart devices, medical implants, sensing devices, and many more portable gadgets to perform tasks that seemed fictional a couple of decades ago. As wireless communication shifts towards higher frequencies in the order of terahertz, the antennas are expected not only to shrink further, hence aiding on-chip integration, but also to become smart, multipurpose, and virtually invisible. Accurate modeling and characterization of antennas were also key factors in the accelerated growth of communication technology. The development of computational technology in the latter half of the twentieth century led the way for electromagnetic modeling of radiating structures. Computational electromagnetics (CEM) was introduced with advanced techniques such as method of moments (MoM), finite-difference time-domain (FDTD) method, finiteelement method (FEM), eigenmode expansion (EME), and Uniform Theory of Diffraction (UTD), which allowed better design and analysis of antennas. These advances enabled not only the antenna structure, but also its environment to be simulated, which is essential for miniaturized and complex electronic systems. It also allowed exploration of novel materials in order to realize antenna systems with smaller footprint using exotic substrates. Antenna measurement techniques have also undergone huge changes to cater to the everevolving types of antenna designs. From large, open-air test sites to anechoic chambers and microscopic probe-based techniques, extensive work has been done on specialized methodologies for every type of antenna system. Around the time Marconi was experimenting with electromagnetic transmission, the vacuum tube was invented as a simple device to convert alternating current (AC) to direct current (DC). Soon after, in 1947, the transistor was invented that aimed to replace the expensive and rather bulky vacuum tube. The transistor was a revolutionary device for electronics, opening up new avenues for circuit design and its applications. As circuits became increasingly complex with more components being piled on and the connecting wires growing exponentially, fabrication of circuits with large number of transistors became a

4

Antenna-on-Chip: Design, Challenges, and Opportunities

difficult task. This led to the first IC, based on the idea that the same process used to make clusters of transistors on silicon wafers might be leveraged to make a functional circuit, such as an amplifier or a computer logic circuit. British engineer Geoffrey Dummer is credited for conceptualizing this idea. In 1952, based on the maturity of transistor and semiconductor technology, he proposed the combination of multiple electronic circuits on a single solid block with no connecting wires. Jack Kilby of Texas Instruments and Robert Noyce of Fairchild Semiconductor Inc. were the first ones to demonstrate a working and repeatable model of an IC. In a major significant moment in 1965, Gordon Moore of Intel, after observing the rapid progress of ICs, made an empirical prediction that the number of transistors on an IC would double every 2 years. This prediction, now well known as Moore’s law, defined how the semiconductor industry has evolved in the last 50 years. The ensuing ICs were able to achieve, typically, either one of digital, analog, or radio frequency (RF) functionality forming only one part of the system. Therefore, in order to conceive the whole system on a single platform, IC integration technologies quickly followed suit. These included, for instance, multichip modules (MCM), system-in-package (SiP), system-on-package (SoP), and system-on-chip (SoC), each aiming to combine digital, RF and mixed-signal ICs along with antennas and passives on a single platform, albeit in different ways. Among the above-mentioned techniques, SoC held the most promise of providing a single-chip solution for a wide spectrum of applications. It was accomplished, initially, by combining the traditional microprocessor, digital memories and mixed signal circuits such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) and then by integrating analog circuits and the RF front end on one chip. Over the years, highly integrated, single-chip, multiband radios, radar chipsets, and the like were successfully demonstrated. However, the center of all communication technology, the antenna, was left behind in this integration race. In most technologies, the antenna was still used as an external component connected to ICs through lossy and large interconnections. However, this changed at the close of the twentieth century, driven by an unprecedented development in the field of ICs and associated fabrication methodologies making researchers bold enough to envision the entire wireless communication system, including the antenna, on a single chip. Although the AoC technology officially took off around the early 2000s, there do exist some isolated examples of antennas designed on the chip before this time period. For instance, an on-chip antenna integrated with a 95-GHz impact ionization avalanche transit-time (IMPATT) diode oscillator on a high-resistivity silicon substrate was reported as early as 1986 [3] and a loop antenna integrated with a 43.3-GHz IMPATT diode oscillator on a gallium arsenide substrate was demonstrated in 1988 [4]. In 1998, a study [5] was published to prove the feasibility of using on-chip antennas for radio communication within and between chips.



Introduction to Antenna-on-Chip

5

This experiment involved specialized measurement setups that observed reasonable gains for on-chip antennas above 15 GHz. Earlier implementations of onchip antennas focused more on intrachip communications. In [6], the propagation mechanisms of radio waves on the chip were investigated and it was found that surface waves were the dominant way of signal transmission in intrachip channels. In 2002, Floyd et al. [7] demonstrated the first wireless interconnect system which was able to transmit and receive RF signals across a chip using integrated antennas. The majority of applications of AoC technology, however, lie in the domain of interchip communication or in other words transmission over free space. Hence, in 2004, Lin et al. [8] experimentally demonstrated wireless communication between two on-chip antennas placed 5m apart. With AoC being a relatively new technology, the successful characterization of these antennas posed greater challenges and new measurement techniques needed to be devised. In 2005, for the first time, Zhang et al. [9] were able to successfully design, fabricate, and characterize on-chip inverted-F and quasi-Yagi antennas at 60 GHz. The AoC approach had its downsides and the poor performance of antennas on silicon substrates was quickly revealed to be a daunting challenge [10]. From there on, AoC research took a new direction and techniques were developed to enhance the radiation efficiency, such as proton implantation [11], micromachining [12], and the use of artificial magnetic conductors [13] and superstrates [14]. The current focus of AoC research is towards greater performance enhancement and venturing into terahertz and optical domains for applications involving imaging, automotive sensing, and advanced single-chip radios. Figure 1.1 illustrates the historical events in antenna and IC integration that have made the AoC technology a possibility today. �

1.2  Circuit Integration Technologies A typical wireless communication systems consist of four functionality-specific components: (1) the digital IC, which handles the logic operations, signal processing algorithms, and memory functions; (2) the mixed-signal IC, which provides signal conditioning in the form of ADC and DAC; (3) the RF front-end IC that performs the upconversion and downconversion of the desired frequency band; and (4) the antenna, which transmits and receives radio waves. The former three already exist in IC form. Historically, the different types of ICs were housed on individual boards and then interfaced together resulting in systems that were bulky, costly, and inferior in performance and reliability. Spurred by these challenges, a number of diverse integration and packaging technologies have been introduced over time to satisfy the requirements of functionality, miniaturization, robustness, and cost. Each has tried in its own way to include the antenna so that it takes up the least space while providing maximum radia-

6

Antenna-on-Chip: Design, Challenges, and Opportunities

Figure 1.1  A brief history of antenna and circuit integration technologies leading up to the advent of AoC.

tion. The methodologies discussed are MCMs, SiP, SoP, and SoC. This section provides an overview of these technologies and discusses how integrating the antennas on the chip accomplishes all the above-mentioned requirements. The focus of this book is on antenna integration, so packaging technologies will be assessed based on how efficiently they can incorporate otherwise large and bulky antennas into their design. Most of the circuit integration or packaging technologies reviewed in this chapter invariably require interconnection between various ICs. It is, therefore, appropriate to briefly introduce the methods adopted for this purpose. 1.2.1  Interconnection Technologies 1.2.1.1  Wire Bonding

Wire-bonded interconnects are widespread and very popular due to their robustness and rather simple and well-established technology. Wire bonding starts by mechanically attaching the chip to a substrate that consists of appropriately spaced conductive pads. The wires, typically made of gold (Au) or aluminum (Al), are bonded one at a time between the pads on the chip and the substrate as depicted in Figure 1.2. It can also be between the bond pads and an IC holder, which in the second step is encapsulated in an insulated package. Three methods, namely thermo-compression, ultrasonic, and thermosonic, are used to bond the wires with the pads. As wire bonds add parasitic capacitance and inductance to the circuits, their effects are usually incorporated in design



Introduction to Antenna-on-Chip

7

Figure 1.2  High-resolution image of bond-wire interconnections. (Courtesy of Rocket PCB Solutions.)

through advanced simulation tools. The key challenge associated with bond wires is their performance degradation due to reactance at high frequencies. Moreover, with the increasing number of chip components and interconnections, wire bonding has become quite difficult to implement in highly complex chips. 1.2.1.2  Flip-Chip

Flip-chip, as the name suggests, involves placing the chip upside down on the substrate. To achieve the interconnection, solderable metal is first deposited on the substrate pads forming an array of bumps, the chip is then aligned with the substrate pads and finally placed face-downwards on the substrate and heated for robust connection. The process is visually described in Figure 1.3. The flip-

Figure 1.3  Flip-chip assembly IC over PCB.

8

Antenna-on-Chip: Design, Challenges, and Opportunities

chip approach is superior in terms of area efficiency compared to wire bonding as it requires no additional contact area on the chip. Furthermore, it is better suited for higher frequencies as the length of the interconnections and hence parasitics are smaller. Flip-chip interconnection technology is simpler and faster as all connections can be fabricated in a single turn. Some of the drawbacks of this method are the overall complexity of the mounting process, dielectric detuning due to the opposite substrate, lack of direct visual control, and high thermal resistance. 1.2.1.3  Through Silicon Vias (TSVs)

One of the latest interconnection approaches between ICs is called TSVs. This method is used for connecting multiple ICs vertically using conductive vias that completely pass through the silicon substrate as shown in Figure 1.4. TSVs make the integration between ICs more compact than bond wires and offer higher density of interconnections as they do not require custom-sized pads or solder bumps. TSVs have become a staple in three-dimensional (3-D), largescale ICs and provide efficient interlayer routing of signals. 1.2.2  MCMs

The first mainstream IC integration technology introduced in the early 1980s was MCM. This technology involved placing two or more chips on a common substrate in a horizontal arrangement. The individual packaged chips were connected to each other through interconnects on the substrate (Figure 1.5). In addition, passive components such as resistors and capacitors were also placed directly on the substrate mostly as surface mount components. The driving force behind the success of MCMs was the elimination of parasitics associated with individual connected modules and reduction in chipto-chip interconnection delay. MCMs also provided miniaturization of systems

Figure 1.4  TSVs between stacked chips.



Introduction to Antenna-on-Chip

9

Figure 1.5  MCM illustration consisting of function-specific ICs, passive components, and antenna in a horizontal arrangement.

by packing bare chips in a high-density environment, which resulted in the reduction of weight and volume. This is evident from Figure 1.6(a), which shows the difference in size of a conventional 1990s RISC processor and a similar MCM-based design. The first industrial MCM was demonstrated by IBM in 1982. The module exhibited considerable performance enhancement over the conventional approach in which individually packaged chips on separate PCBs were interconnected. Figure 1.6(b) shows a comparison between the wiring delays of two processors, the IBM 3033 and the IBM 3081. The former, using four circuits boards each housing a single chip, resulted in the package and interconnects taking over 50% of the timing budget, whereas the MCM-based IBM 3081 significantly reduced the wiring delays from 28 to 9 ns. The substrate is the key component in a multichip module. It provides the chips with mechanical support, interconnections, power and ground and also facilitates interfacing it with the next level in the packaging hierarchy. It also plays a vital role in thermal management and protection of the chips from environmental factors. In some cases, it is composed of multiple layers connected through conductive vias. It is important to note that, in a typical MCM structure, these layers are for improving wiring density while the ICs are still arranged horizontally on the substrate. The MCM technology can be categorized into three basic types, defined according to the process used in fabricating the interconnect substrate. They have been classified as MCM-D (deposited thin film), MCM-C (ceramic thick film), and MCM-L (plastic laminate). MCM-D, the first MCM type to be developed, uses micro-fabrication techniques for depositing conductive metal for interconnecting chips on a base

10

Antenna-on-Chip: Design, Challenges, and Opportunities

Figure 1.6  (a) Comparison of conventional and MCM-based RISC Microprocessor Chip Sets [15], and (b) reduction in wiring delays using MCM-based processor (IBM 3081) in comparison to single-chip board strategy (IBM 3033).

substrate typically made with silicon. Dielectric layers of polyimide or benzocyclobutene (BCB) coatings are deposited over the etched conductors and vertical vias are metallized to form electrical connections between the layers. Of



Introduction to Antenna-on-Chip

11

the three MCM types, MCM-D provides the finest line widths and spacings (width of 25 μm or less), and smallest vias (diameter of 25 μm or less). It may also be multilayered to form up to eight conductor layers. Although MCM-D is process-intensive and expensive per unit substrate space, it typically covers less area because of higher wiring density for a given circuit application and, thus, can be cost-competitive, especially in large volumes [16]. MCM-C substrates are fabricated from ceramic or ceramic-glass materials using traditional thick-film fabrication. There are two basic types of MCM-C substrates: high-temperature cofired ceramic (HTCC) and low-temperature cofired ceramic (LTCC). Individual layers are printed with thick-film paste to create the metallization patterns, aligned with the other layers and baked to form a monolithic structure. MCM-C substrates can have up to 100 conductor layers, although most applications require 2–20 layers. Vias for interconnections are created through the screen printing process, where a conductor paste is pressed through a screen onto the ceramic substrate. MCM-C has wider lines and spacing (less than 50 μm) than MCM-D and is lower in cost. The MCM-L technology is based on PCB technology. It uses plastic laminate-based substrates, typically with copper as the conducting material. Interconnections between layers are formed by through vias, which extend all the way through the board; blind vias, which extend from the surface to partly through the board; or buried vias, which connect specific inner layers. The major advantage of MCM-L is the low cost, as it is a mature technology and utilizes an existing infrastructure that is suitable for high-volume production. Typical MCM-Ls have lower wiring density than the other two MCM classes making them unattractive for complex applications. MCM-L laminates are available in a diverse amount ranging from the low-cost FR4 to the more costly polymer-based dielectrics such as Duroid [17]. The MCM integration approach has the advantage of using the best technology for each component. For instance, digital circuits can be implemented using complementary metal-oxide semiconductors (CMOS), RF components using silicon germanium (SiGe) bipolar technologies, and power amplifiers using III-V compound semiconductor technologies. However, with the continuous demand for miniaturization of cellular and wireless devices, the horizontal integration in MCMs fails to cater the stringent size constraints. One of the first MCM receivers with a substrate integrated antenna on the PCB had the dimensions of nearly 22.5 × 5.4 mm2 in an unpackaged form, which is quite large compared to other packaging technologies [18]. Efficient integration of antennas with MCMs is another challenge. Antennas are typically implemented on conventional laminates such as FR4 and are simply interfaced to the MCM at the substrate level, thus making it difficult to achieve the overall system miniaturization goals.

12

Antenna-on-Chip: Design, Challenges, and Opportunities

1.2.3  SiP

SiP refers to combining various ICs of a system that may have been implemented in different technologies in a single 3-D package. This 3-D integration approach utilizes the third dimension to combine multiple ICs, stacking them in a vertical arrangement that provides multiple functions associated with a system or subsystem. For wireless applications, SiP has enabled the rapid integration of SiGe, GaAs, Si-based ICs, and other passive devices into a single package that would be otherwise costly and larger in size using MCMs. For instance, Sony introduced a 60-GHz transceiver and baseband circuit occupying only 4.2 × 4.2 mm2 and 3 × 3 mm2, respectively, and, by arranging them in a vertical fashion, provided a clear advantage over the MCM counterpart [19]. Stacking logic and memory chips in a single package is another fast-growing application for SiP through which highly miniaturized commercial memories have been made possible. The vertical stacking in SiP configuration reduces system size and eliminates the cost of individual packages for each die. SiP can also improve signal transmission times and reduce power consumption by minimizing resistive and capacitive loads between the ICs. It must be noted that although SiP is sometimes defined as the entire SiP, in this book, it will only refer to the stacking of ICs in a single package. The miniaturization of all components of the system (including passives, interconnections, power sources, and system board) and their integration into a complete system is described as SoP, which is discussed in detail in the next section. A typical SiP is illustrated in Figure 1.7. The bare dies of digital, analog, and RFICs are usually stacked using one or a combination of wire bonding, flip-chip, or lately TSVs, as discussed earlier. The antenna and the discrete

Figure 1.7  SiP illustration consisting of function-specific ICs stacked in a vertical arrangement connected to an external antenna.



Introduction to Antenna-on-Chip

13

components are present on the substrate. The former is fabricated through various etching techniques and the latter are placed as surface mount components. Typical SiP substrates include standard PCB laminates, polymer-based laminates, or ceramics and have the major requirement of supporting high-density interconnects. The 3-D integration in SiP occupies lower area due to vertical stacking and provides higher functionality per unit volume. It can also support a higher density of interconnections compared to previous technologies and, like MCM, it has the advantage of choosing the best technology for each component. The SiP technology can be broadly classified into two categories: (1) stacking of ICs (bare chips or packaged) using wire bonds or flip-chips, and (2) stacking using TSVs. Variations of SiP stacking are shown in Figure 1.8. There exist a number of downsides to the SiP approach as well. Although the stacked arrangement of the components saves on the horizontal area, the vertical dimension of the system in SiP is increased, compromising the overall size. Furthermore, the thermal management of closely stacked ICs is also a challenge. SiP allows the use of separate substrate technology for each IC, which, although useful in terms of performance, leads to multiple fabrication runs increasing cost and time to market. The additional post-processing steps such as the creation of interconnections in the package take a further toll on cost and time. Another limitation in the SiP approach lies in the antenna integration. Although SiP is able to extend integration in the third dimension, the vertical stacking is limited to ICs only, which accounts for only 10% to 20% of the system. Most conventional SiPs still use external ceramic or PCB-based antennas through various interconnection techniques as shown in Figure 1.7. However,

Figure 1.8  IC stacking in SiP using: (a) wire bonds, (b) flip-chip and wire bonds, (c) 3-D stacking using TSVs, and (d) flip-chip on chip.

14

Antenna-on-Chip: Design, Challenges, and Opportunities

this defeats the idea of overall system miniaturization as antennas that occupy the largest amount of space are not part of the SiP vertical stacking approach. There have been instances of innovative approaches to integrating the antenna with SiP stacked dies. One such approach uses a 3-D antenna folded around the SiP structure, which reduces the system size by 25% compared to a twodimensional (2-D) planar antenna but adds to the form factor [20]. However, these antennas are still not a part of the package but incorporated as separate components. So the package in the SiP remains a mere holder of the chips, providing no useful functionality for the system operation. SiP technology is being primarily driven by applications in wearables, mobile devices, and the IoT. The vertical stacking of ICs in a system provides some level of miniaturization, which is highly desired in compact sensor modules and communication devices. However, if the goal is miniaturization of the entire system, SiP lags behind technologies that can efficiently integrate a range of components other than the ICs. 1.2.4  SoP

Historically, the only purpose of an IC package has been to provide mechanical and thermal stability. However, in the last decade, researchers have worked to transform packages into functional enclosures using novel materials and embedding components in them to form miniaturized systems. The concept of SoP was pioneered by Georgia Tech’s Microsystems Packaging Research Center (MPRC) in 1994. In the SoP approach, the components, package, and system board are integrated into a single system package that can perform all systemrelated functions. SoP technology merges the PCB and the package into one module. By utilizing multilayer substrates such as LTCC and liquid crystal polymer (LCP), passive components such as inductors capacitors, filters, and antennas are embedded in the package as shown in Figure 1.9. The surface mounted and embedded components are connected through ultrahigh-density stacked interconnects with extremely low pitches that allow for faster communication between layers. Thus, the package not only houses the ICs but also becomes the host substrate for highly integrated passive components, making the package a functional part of the system. SoP is able to build on the shortcomings of existing integration technologies. In a typical cellular phone, only 10% of the system components are made up of ICs, while the remaining 90% are passives, board, antennas, and interconnections. Hence, by incorporating these into the fabric of the package, SoP is able to achieve true system-level miniaturization. Other advantages of SoP include lower system cost and greater amount of design flexibility due to the use of high-quality factor passive components. As the entire package is



Introduction to Antenna-on-Chip

15

Figure 1.9  Illustration of SoP, which embeds discrete components in the packaging material itself.

connected through TSVs, SoP reduces the number of conventional interconnections, which, in turn, reduces the associated losses and parasitics. Multilayer packaging in SoP also reduces component size and allows multifunctional modules to be realized in a single package. � Of all the embedded passive components in SoP, the integration of antenna in the package has attracted considerable interest in the research community and a lot of work has been reported in this domain, coining the terms antenna-in-package (AiP) and antenna-on-package (AoP), both referring to an antenna that has been realized in a package. The antenna is often integrated with the bare dies as a surface mount component and the combination is then encapsulated in a package. This configuration is shown in Figure 1.10(a) where a dipole antenna is connected to the transmitter IC through flip-chip interconnects before packaging [21]. Another approach is to place the antenna on top of the package as shown in Figure 1.10(b), where a U-shaped slot antenna has been integrated at the top of an LTCC package [22]. Fabricating an antenna directly on the package has the advantages of reduced losses and compact system size. The major challenges faced during such integration are the gain and bandwidth constraints due to high permittivity substrate and interference between the closely packed antenna and circuits. SoP technology has the potential to overcome the shortcomings associated with existing integration technologies as well as traditional packaging which is bulky and costly. However, the challenges for SoP lie in the infrastructure and investment domain. At the time of its inception in the mid-1990s, SoP was an extremely advanced concept and the existing electronics industry was not able

16

Antenna-on-Chip: Design, Challenges, and Opportunities

Figure 1.10  Antenna integration approaches in SoP: (a) antenna on same substrate as IC [21] with (b) photograph of packaged chip and (c) antenna on top of package with photograph of packaged chip [22].



Introduction to Antenna-on-Chip

17

to immediately adapt to it. Today, it seems that the industry has caught up to its possibilities and is exploring this concept for various applications. Currently SoP appears to be a promising choice for circuit integration with numerous applications in mobile communications. However, as wireless applications shift towards higher frequencies, the SoP approach to packaging is expected to become more challenging and the cost and size metrics may not remain the same. 1.2.5  SoC

The SoC integration approach, as briefly discussed in Section 1.1, aims to incorporate digital baseband circuits, mixed signal circuits, the RF front ends, and other passives on a single chip. Historically, from an IC perspective, the requirements of digital, mixed signal, and RF subsystems have been very different. For instance, CMOS scaling has generally been more helpful for digital than RFIC design due to pronounced short-channel and leakage effects in the latter. However, over the years, this gap vanished due to improvements in device structures and design processes, for instance, through having specific transistor models for digital and RF design within the same base semiconductor technology. As a result, these technologies have now become suitable for digital, analog, and RF circuit integration and the codesign between these subsystems has become possible, resulting in SoCs that are highly functional, miniaturized, and, most importantly, lower in cost. The preceding discussion on MCM, SiP, and SoP reflects that, from an antenna integration and overall system miniaturization perspective, all three technologies face various trade-offs. MCM, due to its horizontal integration, SiP, due to nonfunctional packaging and external antenna integration, and SoP, due to relatively higher costs and design time, indicate the need of exploring SoC as the go-to circuit integration technology. Until recently, the SoC research focused on integrating as many components on a single chip and only rarely has the antenna been included in this mix. One factor to blame is the large size of the antenna, which is not affected by technology scaling. However, as integrating the antenna is inevitable to achieve truly compact single-chip devices, a new subset of the SoC technology eventually emerged, aptly coined as the antenna-on-chip. With the aim of combining both transmit and receive antennas with RF front ends, mixed signal, and digital baseband circuits as illustrated in Figure 1.11, a new generation of true SoC has fast emerged in the last decade. A number of commercial SoCs are available in the market for wireless communication applications. However, a single-chip transceiver with on-chip antenna is almost nonexistent. Take, for instance, Nordic Semiconductor’s stateof-the-art Bluetooth SoC, nRF52840, which is a multiprotocol single-chip solution for ultralow-power wireless applications. This award-winning SoC has

18

Antenna-on-Chip: Design, Challenges, and Opportunities

Figure 1.11  SoC illustration that hosts all major ICs and, more importantly, the antenna on the same substrate.

abundant applications in smart homes, advanced wearables, and interactive entertainment devices. It incorporates a radio transceiver, a 32-bit processor, on-chip memory, analog and digital I/Os, and system peripherals, all in a highly integrated SoC measuring just 3.5 × 3.6 mm in a wafer-level chip-scale package (WLCSP) form and 7 × 7 mm in quad-flat no-leads (QFN) package form. This is smaller than an adult fingertip, as shown in Figure 1.12. Despite all the positives, the only component missing from this chip is the antenna, which is required to be connected externally, along with a few matching components. This approach naturally entails extra cost and time and loses the advantage achieved

Figure 1.12  Nordic Semiconductor’s low power Bluetooth SoC: (a) with a size of only 7 × 7 mm in packaged form, and (b) is smaller than an adult fingertip and contains a 32-bit processor, memory, general purpose input/output (GPIOs), and radio [23].



Introduction to Antenna-on-Chip

19

via its IC miniaturization. Therefore, bringing the last remaining component on the chip is a natural step towards overall miniaturization. The new SoC realm comes with its own set of challenges. The silicon substrate, due to its high relative permittivity and lossy nature, is far from ideal for getting good antenna performance. The miniaturization of on-chip antennas for inclusion with rest of the on-chip components is another issue, especially at lower frequencies. Moreover, the antennas placed in the vicinity of other electrical devices can cause coupling and interference. Thus, to design a truly functional all-in-one SoC, it is imperative to devise a codesign strategy for antenna and circuits in terms of feeding methods, interconnections, size constraints, interference, and overall performance. Despite the above-mentioned hurdles, SoC appears to be a strong candidate to efficiently incorporate the antenna into a wireless system, particularly for short-range systems. Advancements in the field of ICs, the application push towards higher frequencies in general and millimeter-wave and subterahertz frequencies in particular, have reduced the antenna sizes to less than 1 mm, which makes them realizable and practical for on-chip implementations. To this end, extensive research is underway to demonstrate highly miniaturized on-chip antennas with moderate gain and efficiency to achieve true RF SoC solutions, which will be the main topic for remaining part of this book. A comparison of the discussed circuit integration technologies is shown in Table 1.1. Compared to SiP and SoP, the SoC approach is cheaper for mass manufacturing and more area-efficient. It is also the most promising technology for antenna integration with minimal compromise on the size and cost of the chip. The biggest obstacle for SoCs becoming a mainstream antenna integration technology is the inferior antenna performance, largely because of the nonideal substrate properties. However, many ingenious approaches are now available to mitigate this issue and will be discussed in more detail in Chapter 3. An important thing to note is that the widely available chip antennas are not to be confused with antennas integrated directly on the chip. The former is a ceramic-based, miniaturized antenna, which is placed on the system PCB as a separate component. AoC is a silicon-based antenna that is realized on the chip itself. Figure 3.13 visually compares the two types of antennas.

1.3  On-Chip Antennas: Benefits and Opportunities Transferring the antenna from its traditional off-chip status to being an on-chip component is an important development and brings a lot of advantages with itself. This section further examines the motivation of why AoC is the right choice for upcoming applications in terms of cost, compactness, ease of integration, matching requirements, and performance accuracy.

20

Antenna-on-Chip: Design, Challenges, and Opportunities Table 1.1 Comparison of MCM, SiP, SoP, and SoC Technologies Maturity Area Efficiency Fabrication Cost Antenna Integration Antenna Performance

MCM High Low Low On PCB

SiP Medium High Medium On PCB

SoP SoC Low High High Very high High Very low On package On chip

High

High

High

Low

Figure 1.13  Ceramic-based chip antenna and silicon-based on-chip antenna.

1.3.1  Cost and Size

In today’s competitive market, cost is the foremost factor behind the success of a technology. Integrating the antenna on the chip, particularly at higher frequencies, reduces the overall cost due to a number of factors. It is well known that in high-volume manufacturing, the cost of an IC comes down to tens of cents due to the maturity of silicon foundry processes. For instance, the cost of a single QFN packaged Bluetooth low-energy chip is about $6. Wireless modules (also called breakout boards) that combine such chips with external antennas are widely available. However, the addition of an off-chip or in-package antenna increases both the cost and size. As an example, consider the comparison of Laird and Texas Instruments Bluetooth modules shown in Table 1.2. Both



Introduction to Antenna-on-Chip

21

modules consist of Bluetooth SoC ICs interfaced with off-chip PCB-based antennas. The addition of the antenna and associated matching circuit increases the module dimensions up to 200% compared to the original IC. Furthermore, the packaging adds a finite height of 2.2 mm and 1.4 mm, respectively, which does not bode well for achieving thin form factor devices. �������������������� The cost of the module also doubles from that of the individual chip. Another Bluetooth module, the ISP1507 by InsightSiP, uses the antenna in package technique to obtain a relatively smaller size; however, it is still 77% bigger than the original Bluetooth chip [28]. For millimeter-wave and terahertz frequencies, conventional antenna integration technologies become even more expensive. Laminates characterized above 100 GHz are rarely available in the market. Therefore, designers have to characterize the materials before initiating antenna design. For example, PCBbased antennas for 77-GHz automotive applications may be possible, only after carefully knowing the substrate properties as the readily available market options are only characterized up to few tens of gigahertz. In addition, highfrequency PCB fabrication component assembly typically requires specialized processes that increase the cost and turnaround time even further. In contrast to the above examples, fabricating the antenna on the same chip as the circuit only adds a small incremental cost that is mostly negligible in volume production. Using the same semiconductor substrate and lithographic processes, the complete end-to-end system is fabricated during one process, reducing the time to market. To curtail the costs further, innovative antenna and circuit designs are being demonstrated to reduce the silicon footprint. The on-chip antenna can be meandered or folded to take up less area. It can be

Table 1.2 Size Comparison of Commercially Available Bluetooth ICs with and without Integrated Antennas IC with Integrated IC Antenna Bluetooth SoC IC by Bluetooth module with Nordic Semiconductors antenna on PCB by Laird [23] 7 × 7 mm Technologies [24] 15 × 10 × 2.2 mm Bluetooth Low Energy Bluetooth module with SoC IC by Texas antenna on PCB by Texas Instruments [25] Instruments [26] 8 × 8 mm 7 × 14 × 1.4 Bluetooth SoC by Nordic Bluetooth Module with Semiconductors [27] antenna in package by 6 × 6 mm InsightSiP [28] 8 × 8 × 1 mm

Increase in Size After Addition of Antenna ≈200%

≈50%

≈77%

22

Antenna-on-Chip: Design, Challenges, and Opportunities

smartly placed on the edge of the chip or around the circuits to give more room to other components. On-chip antennas can also be implemented in one of the top metal layers with the bottom layers reserved for other on-chip components. As wireless communication is shifting towards the millimeter-wave and terahertz regimes, the implementation of AoCs is becoming easier and inevitable. Although reduction in antenna size with increasing frequency is true for any technology, in the case of AoC implementation, it has a much more pronounced effect in terms of cost. For example, at a frequency of 5 GHz, an on-chip λ/4 monopole has a length of 0.43 mm and reduces to only 0.02 mm for 94 GHz. Therefore, the addition of antenna on the chip incurs a very small area penalty and larger off-chip alternatives can be avoided. To correlate with other on-chip components, these dimensions are comparable to an inductor or a metal-insulated-metal (MIM) capacitor. At frequencies above 100 GHz, the antenna dimensions are even smaller and comparable to a typical bond pad. For instance, an entire 170 GHz imaging radar transceiver with two on-chip dipole antennas has been realized in an area less than 1 mm2 (Mostajeran, et al.). At the lower end of the frequency spectrum where the wavelength is much longer, antenna miniaturization techniques can be adopted to attain a reasonable on-chip size. For instance, in [27], the loop-shaped, on-chip antenna at 5.2 GHz has the dual function as an inductor for the voltage controlled oscillator as well as the radiator. At the same time, the area inside the loop is reused for the active circuitry for efficient utilization of the chip area (Figure 1.14(a)). As a result, the dimension of the antenna is only 0.5 mm2. Similarly, in [28], a meandered slot design is adopted to achieve a miniaturized on-chip antenna at 9 GHz that occupies only 0.3 mm2 (Figure 1.14(b)). The electrical dimensions of the antenna are 0.017λ0 × 0.017λ0, making it 30 times smaller than traditional dipole or slot antennas operating in the same frequency band. 1.3.2  The 50Ω Boundary: Not Needed Anymore

The antenna being the first component on the receiver (Rx) side and the last component on the transmitter (Tx) side has to be interfaced typically to a low noise amplifier (LNA) and a power amplifier (PA), respectively. Impedance matching between the antenna and the circuit is an essential requirement to ensure maximum power transfer from one component to the other. In conventional circuit integration technologies, antenna and IC design engineers have worked separately, each relying on the standard 50Ω impedance to achieve a matched condition. This approach has two major disadvantages. The first is the need of matching networks on both sides that convert complex impedances to the 50Ω reference. Especially on the circuit side, these matching circuits are, at times, difficult to design and take up extra space on the chip. The second disadvantage is the losses incurred, either through bond wires or PCB traces,



Introduction to Antenna-on-Chip

23

Figure 1.14  Examples of miniaturized on-chip antennas at low frequencies: (a) 5.2 GHz [29] and (b) 9 GHz [30].

when off-chip antennas need to be interfaced with integrated circuits. These interconnects, if not compensated in design, can drastically affect matching, especially at higher frequencies at which they are not accurately characterized. On-chip antennas, being codesigned with the circuits, do not necessarily need to be designed for 50Ω impedance and can thus be directly matched to the circuits without the need of typical matching networks as shown in Figure 1.15. Due to the codesign strategy, both the circuit and antenna designers design keeping in mind the requirements of the other. The codesign of AoC and circuits provide the designer with 2 degrees of freedom so that matching optimization can be achieved by leveraging the two domains between the circuit and antenna [31]. In this work, it is shown how conjugate matching, where impedance of the antenna is designed to be the complex conjugate of the impedance of the interfaced circuit, can be utilized to completely eliminate the matching network. This aspect will be discussed in detail in Chapter 4. 1.3.3  Integration and Robustness

Conventional wireless systems require off-chip antennas to be connected to ICs using techniques like wire bonding and flip-chip assembly. As there is little to

24

Antenna-on-Chip: Design, Challenges, and Opportunities

Figure 1.15  (a) Traditional 50Ω boundary between IC and antenna designers, and (b) codesigned matching between IC and on-chip antennas [10].

no codesign strategy in place between the antenna and the rest of the circuit, the connections may result in some level of performance uncertainty, particularly for higher frequencies. Bond-wire interconnects are prone to performance degradation as a result of reactance introduced at higher frequencies. Flip-chip interconnects require complex mounting processes for the correct alignment of solder balls. Both these processes are potential bottlenecks for high-frequency ICs and add to the cost and fabrication time. In addition, the connections are not as robust, particularly the bond wires, as the interconnects realized on the chip through metal traces and vias. Therefore, if the antenna is on the chip, then there is no need for these external, less sturdy connections and thus the overall system robustness is enhanced. On-chip antennas are easier and cheaper to integrate with ICs. The direct connection of the antenna and the circuit on the same chip eliminates a number of uncertainties that hinder accurate modeling and characterization. Today’s CMOS processes have multiple metal layers, giving designers flexibility in implementing the antenna on any metal layer that fulfills performance requirements. Other metal layers can also be used at will to design intermediate ground layers, antenna feed lines, and transitions between feed lines (microstrip, coplanar stripline, and coplanar waveguide) and auxiliary components such as artificial magnetic surfaces (AMCs) and high-impedance surfaces (HIS). Furthermore, on-chip fabrication provides designers the liberty of controlling the placement, orientation, and effective size of the antenna according to system requirements. For example, monopole and dipole antennas are often meandered or folded to occupy less space. In many cases, the circuit components can be placed inside the loop or folded dipole antennas so that the inner chip area is reutilized. Designers can choose to place antennas on the chip edge to prevent unnecessary interference and mutual coupling. Figure 1.16 shows some layout variants of on-chip antennas demonstrating the ease of integration.



Introduction to Antenna-on-Chip

25

Figure 1.16  Some variations of antenna layout on the chip to meet design requirements: (a) folded dipole antenna designed to surround circuit components to save chip area [31], (b) placement of Tx and Rx on-chip antennas so as to prevent the mutual disruption of radiation pattern [32], and (c) folded monopole placed at the edge of chip to save area and isolate it from electronic circuits [33].

1.3.4  Fabrication Precision and Repeatability

Fabrication accuracy is yet another area where on-chip antennas surpass their off-chip counterparts. Conventional PCB-based antennas are fabricated using milling or chemical etching. Milling can be done mechanically or through lasers while chemical etching is further subdivided into wet and dry etching. All these methods have certain resolution and accuracy limitations as well as fabrication tolerances. Furthermore, repeatability is a concern in PCB fabrication whereby different samples of the same batch exhibit slight difference in performance. CMOS lithographic processes provide much superior resolutions and are highly accurate and repeatable. Furthermore, on-chip antenna is part of the

26

Antenna-on-Chip: Design, Challenges, and Opportunities

same mask that is prepared for the adjoining circuits. Thus, there is no extra cost for mask preparation as is the case for off-the-chip implementations. Table 1.3 provides a comparison between these approaches and reflects that on-chip antennas can have finer, accurate, and repeatable dimensions.

1.4  AoC: An Inevitable Choice for the Future The advances in IC technologies and improvement in fabrication processes has opened the way for wireless applications that were not perceivable before. There is a growing focus on wireless communication at extremely high frequencies (>100 GHz) and the global push for miniaturization has led to commercialization of application-specific SoCs. As the world shifts towards chip-based electronics, it is only a matter of time before the antenna becomes an inherent part of the chip. AoC technology has amassed a large number of potential applications since its introduction. These include IoT devices, communication modules for 5G and beyond, highly integrated transceivers for a wireless personal area network (WPAN), automotive radars, imaging radar sensors at subterahertz frequencies, interchip, and intrachip communication links, and biomedical implants. The aforementioned advantages of AoC can potentially reduce wireless sensors to the size of rice grains and cut costs to such an extent that they may eventually be disposable. The first instances of on-chip antenna design and fabrication in mainstream semiconductor technologies emerged in the early 2000s. Since then, AoC has only attracted further attention from the research community. Figure 1.17 shows the growth of the AoC research papers from early 2000s to date. Interest in the potentials of AoC technology by the academic community has seen a steady rise for the past two decades and this trend is expected to grow further in the coming years. �Table 1.3 Comparison of State-of-the-Art Minimum Feature Sizes for Various Antenna Fabrication Methods Fabrication Technology Mechanical milling Laser milling Dry plasma etching

Typical Minimum Feature Size (mm) 0.3 [34] 0.3 [35] ≈3

Manufacturing Tolerance Repeatability High Low Medium Medium Medium Medium

Wet etching

≈30 [36]

Medium

Medium

On-chip

≈0.05* [37]

Low

High

*For Metal-1 in TSMC 5-nm technology.



Introduction to Antenna-on-Chip

27

Figure 1.17  Number of IEEE research publications related to on-chip antennas over the last 20 years.

1.5  Conclusion AoC technology has taken advantage of the multilayered semiconductor processes to introduce new means of incorporating antennas, grounds, and performance-enhancing structures into the fabric of a chip. An important part to consider during the AoC development cycle is the impact of the antenna on the circuit and vice versa. The methodology and tools to codesign the two sides are now available, and a new breed of designer has emerged, one that can collaboratively design antenna and the circuit so that the two complement and aid each other. AoC is expected to have a significant impact in terahertz and optical electronics as miniaturization capabilities at these frequencies have the potential to launch it as a standard integration technology. It will continue to provide direct antenna solutions to large-scale integrated circuits and is expected to assimilate other circuit integration technologies such as SiP and SoP to introduce levels of integration unconceivable in modern-day electronics.

References [1] “Global Digital Overview,” DataReportal – Global Digital Insights, https://datareportal. com/global-digital-overview. [2] Ramsay, J., “Highlights of Antenna History,” IEEE Antennas and Propagation Society Newsletter, Vol. 23, No. 6, 1981, pp. 7–20.

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Antenna-on-Chip: Design, Challenges, and Opportunities

[3] Buechler, J., et al., “Silicon High-Resistivity-Substrate Millimeter-Wave Technology,” IEEE Transactions on Microwave Theory and Techniques, Vol. 34, No. 12, December 1986, pp. 1516–1521. [4] Camilleri, N., and B. Bayraktaroglu, “Monolithic Millimeter-Wave IMPATT Oscillator and Active Antenna,” IEEE Transactions on Microwave Theory and Techniques, Vol. 36, No. 12, December 1988, pp. 1670–1676. [5] Kim, K., and K. K. O, “Characteristics of Integrated Dipole Antennas on Bulk, SOI, and SOS Substrates for Wireless Communication,” Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102), San Francisco, CA, 1998, pp. 21–23. [6] Zhang, Y. P., Z. M. Chen, and M. Sun, “Propagation Mechanisms of Radio Waves over Intra-Chip Channels with Integrated Antennas: Frequency-Domain Measurements and Time-Domain Analysis,” IEEE Transactions on Antennas and Propagation, Vol. 55, No. 10, October 2007, pp. 2900–2906. [7] Floyd, B. A., C. -M. Hung, and K. K. O, “Intra-Chip Wireless Interconnect for Clock Distribution Implemented with Integrated Antennas, Receivers, and Transmitters,” IEEE J. Solid-State Circuits, Vol. 37, No. 5, May 2002, pp. 543–552. [8] Lin, J. -J., et al., “Integrated Antennas on Silicon Substrates for Communication over Free Space,” IEEE Electron Device Lett., Vol. 25, No. 4, April 2004, pp. 196–198. [9] Zhang, Y. P., M. Sun, and L. H. Guo, “On-Chip Antennas for 60-GHz Radios in Silicon Technology,” IEEE Transactions on Electron Devices, Vol. 52, No. 7, July 2005, pp. 1664–1668. [10] Cheema, H. M., and A. Shamim, “The Last Barrier: On-Chip Antennas,” IEEE Microwave Magazine, Vol. 14, No. 1, January 2013, pp. 79–91. [11] Chan, K. T., et al., “Integrated Antennas on Si, Proton-Implanted Si and Si-on-Quartz,” International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), December 2001, p. 40.6.1–40.6.4. [12] Jefors, E., et al., “Micromachined Loop Antennas on Low Resistivity Silicon Substrates,” IEEE Transactions on Antennas and Propagation, Vol. 54, No. 12, December 2006, pp. 3593–3601. [13] Kang, K., et al., “A 60-GHz OOK Receiver with an On-Chip Antenna in 90 nm CMOS,” IEEE J. Solid-State Circuits, Vol. 45, No. 9, September 2010, pp. 1720–1731. [14] Ou, Y. -C., and G. M. Rebeiz, “Differential Microstrip and Slot-Ring Antennas for Millimeter-Wave Silicon Systems,” IEEE Transactions on Antennas and Propagation, Vol. 60, No. 6, June 2012, pp. 2611–2619. [15] Nafe, M., A. Syed, and A. Shamim, “Gain-Enhanced On-Chip Folded Dipole Antenna Utilizing Artificial Magnetic Conductor at 94 GHz,” IEEE Antennas and Wireless Propagation Letters, Vol. 16, pp. 2844-2847, 2017, doi: 10.1109/LAWP.2017.2749308. [16] Blum, N. A., H. K. Charles, and A. S. Francomacaro, “Multichip Module Substrates,” Johns Hopkins APL Technical Digest, Vol. 20, No. 1, 1999, p. 8. [17] Buschow, K. H. J., Encyclopedia of Materials Science and Technology, New York: Elsevier, 2010.



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[18] Samanta, K. K., D. Stephens, and I. D. Robertson, “60 GHz Multi-Chip-Module Receiver with Substrate Integrated Waveguide Antenna and Filter,” Electronics Letters, Vol. 42, No. 12, June 2006, pp. 701–702. [19] Okada, K., et al., “A Full 4Cchannel 6.3Gb/s 60GHz Direct-Conversion Transceiver with Low-Power Analog and Digital Baseband Circuitry,” IEEE International Solid-State Circuits Conference, San Francisco, CA, 2012, pp. 218-220, doi: 10.1109/ISSCC.2012.6176982. [20] Tsai, M., et al., “Innovative Packaging Solutions of 3D System in Package with Antenna Integration for IoT and 5G Application,” 2018 IEEE 20th Electronics Packaging Technology Conference (EPTC), December 2018, pp. 1–7. [21] Pfeiffer, U. R., et al., “A Chip-Scale Packaging Technology for 60-GHz Wireless Chipsets,” IEEE Transactions on Microwave Theory and Techniques, Vol. 54, No. 8, August 2006, pp. 3387–3397. [22] Wi, S. -H., et al., “Package-Level Integrated LTCC Antenna for RF Package Application,” IEEE Transactions on Advanced Packaging, Vol. 30, No. 1, February 2007, pp. 132–141. [23] Nordic Semiconductors, “nRF52840,” March 24, 2020, https://www.nordicsemi.com/ Products/Low-power-short-range-wireless/nRF52840. [24] Laird Connect, “BL654 Bluetooth Module - Nordic nRF52840 with BLE and NFC,” https://www.lairdconnect.com/wireless-modules/bluetooth-modules/bluetooth-5modules/bl654-series-bluetooth-module-nfc. [25] Texas Instruments, “CC2564C Data Sheet, Product Information and Support,” https:// www.ti.com/product/CC2564C. [26] Texas Instruments, “CC2564MODA Data Sheet, Product Information and Support,” https://www.ti.com/product/CC2564MODA. [27] Nordic Semiconductor, “nRF52810, Get Started,” https://www.nordicsemi.com/ Products/Low-power-short-range-wireless/nRF52810/GetStarted. [28] Insight SIP, “ISP1507 Miniature Bluetooth Low Energy (BLE) Module,” https://www. insightsip.com/products/bluetooth-smart-modules/isp1507. [29] Popplewell, P., et al., “A 5.2-GHz BFSK Transceiver Using Injection-Locking and an OnChip Antenna,” IEEE J. Solid-State Circuits, Vol. 43, No. 4, April 2008, pp. 981–990. [30] Behdad, N., et al., “A 0.3mm2 Miniaturized X-Band On-Chip Slot Antenna in 0.13μm CMOS,” 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Honolulu, HI, June 2007, pp. 441–444. [31] Arsalan, M., et al., “A Fully Differential Monolithic LNA with On-Chip Antenna for a Short Range Wireless Receiver,” IEEE Microwave and Wireless Components Letters, Vol. 19, No. 10, October 2009, pp. 674–676. [32] Tabesh, M., et al., “A Power-Harvesting Pad-Less Millimeter-Sized Radio,” IEEE J. SolidState Circuits, Vol. 50, No. 4, April 2015, pp. 962–977. [33] Kulkarni, V. V., et al., “A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter with Embedded On-Chip Antenna,” IEEE J. Solid-State Circuits, Vol. 44, No. 2, February 2009, pp. 394–403.

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Antenna-on-Chip: Design, Challenges, and Opportunities

[34] LPKF, “ProtoMat S104–RF and Microwave PCB Prototyping|LPKF,” https://www. lpkf.com/en/industries-technologies/research-in-house-pcb-prototyping/produkte/lpkfprotomat-s104. [35] LPKF, “LPKF ProtoLaser R4,” /en/industries-technologies/research-in-house-pcbprototyping/produkte/lpkf-protolaser-r4. [36] Manz, “PWE Series – PCB Wet-Chemical Horizontal Etching,” https://www.manz.com/ en/product-detail/pwe-series-pcb-wet-chemical-horizontal-etching/1911/. [37] Taiwan Semiconductor Manufacturing Company Limited, “5nm Technology,” https:// www.tsmc.com/english/dedicatedFoundry/technology/5nm.htm.

2 Design and Implementation Challenges This chapter is concerned with providing the reader with an in-depth review of AoC design challenges. The majority of these challenges stem from the relative infancy of AoC technology and the lack of established antenna integration practices in the IC industry. First, an overview of the stack-up of existing semiconductor technologies is examined with a focus on how the antenna can be effectively included into this stack-up. An IC can be imagined to be a perfectly harmonious and balanced environment into which the antenna, an essentially foreign element is inserted, giving rise to a plethora of challenges that require ingenuous solutions. These issues arise due to the interaction of the antenna and circuit components and the antenna’s nonconformance to the strict circuit layout requirements. Often, this integration demands trade-offs in the antenna’s performance that need to be carefully balanced against technology constraints and application requirements. AoC design and performance challenges are covered in three major areas: the limitations of semiconductor technology for antenna integration, the lack of adequate modeling and simulation tools, and complications that arise in the characterization of fabricated AoCs. Adequate examples are given at each step to help the reader understand the bottlenecks and hurdles in AoC design and strategies that can be employed to overcome them. Having a good knowledge of these tactics and trade-offs helps the designer to make logical and timely choices for efficient and practical antenna designs. As silicon is the semiconductor material of choice for AoC design today, it is the primary focus of discussion, but several results are also valid for III-V process technologies such as gallium arsenide (GaAs) and indium phosphide (InP).

31

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Antenna-on-Chip: Design, Challenges, and Opportunities

2.1  Incompatible Silicon Substrate The foremost challenge in the on-chip integration of antennas is posed by the substrate itself. Bulk silicon is the most commonly used substrate in standard CMOS processes due to its low resistivity, which it is highly suitable for circuit integration. Moreover, silicon’s natural abundance makes CMOS processes cheap and widely used. However, certain properties of silicon and the CMOS stack-up make it unsuitable for efficient realization of antennas. A typical CMOS stack-up can be seen in Figure 2.1. The silicon substrate, nearly 300–500-µmthick, is located at the bottom. On top of it, thin layers of dielectric (also known as the intermetal dielectric (IMD) region, approximately 7–15 µm thick) are embedded with 6–9 metal layers, each with a thickness approximately 500 nm, except for the top metal layer, which has a thickness of 1–2 µm. The metal layers are used to realize the passive components, such as capacitors, inductors, transmission lines, and interconnections, which make use of the interlayer vias. The top metal layer is the preferred choice for antenna implementation because its relatively higher metal thickness minimizes the skin depth effect, especially at millimeter-wave and subterahertz frequencies. The placement of antennas in the top layer also facilitates them to radiate upwards into the air. The dielectric layers (typically SiO2) between the metal layers provide good insulation. The top of the chip is typically covered with a thin layer of silicon nitride (Si3N4) or polyimide. This layer is known as the passivation layer and provides the chip with added external protection.

Figure 2.1  Cross-section of a typical CMOS technology stack-up (dimensions not to scale).



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Generally, antennas perform best when mounted on thick substrates with low dielectric constants, and transmission lines and other passive components perform better on thin, high dielectric constant substrates. The high dielectric constant enables tightly bound fields to minimize undesired radiation and coupling, leading to smaller element sizes; however, due to greater losses, these substrates are less efficient for antenna design and lead to relatively smaller bandwidths. These contradictory requirements may theoretically imply that an optimal antenna cannot coexist on the same chip with an efficiently performing circuit. This dilemma is especially true in the case of conventional CMOS technology, where the silicon substrate results in suboptimal antenna performance manifesting through two main reasons, namely, the low resistivity and the high permittivity of silicon. These issues are discussed in detail in the following sections. 2.1.1  Low Resistivity of Silicon

Substrate choice for antenna design is dependent on two factors: the dielectric constant and the loss tangent. A number of commercial substrates are available for the design and fabrication of planar antennas with dielectric constants in the range of 2.2 ≤ εr ≤ 12. The ones that are most desirable for good antenna performance are thick substrates whose dielectric constant is at the lower end of the range as they provide better efficiency and larger bandwidth and loosely bind the electromagnetic (EM) fields so that they can radiate efficiently into space. Some commercially available substrates used in antenna fabrication include the Rogers substrates, also referred to as PTFE (polytetrafluorethylene), which is basically woven glass laminates popular for microstrip designs, and FR4 (Flame Retardant 4), which is inexpensive and commonly used in antenna prototyping. However, the dielectric constant of silicon lies at the higher end of the range at 11.7 to 12.9. A high εr causes the fields to be confined tightly within the substrate, causing most of it to be either dissipated as heat or radiated in unwanted directions through surface waves. While a high dielectric constant substrate comes with its own set of challenges, which will be discussed comprehensively in the next section, here the detrimental effects of low silicon resistivity on antenna radiation are analyzed. Dielectric materials are commonly specified by their complex relative permittivity εr given by:

 σ  εr = εr′ − j  εr′′ − ωε0  

(2.1)

where ω is the angular frequency, ε0 is the permittivity of vacuum, ε′ and ε′′ are the real and imaginary parts of permittivity, respectively, and σ is the conductiv-

34

Antenna-on-Chip: Design, Challenges, and Opportunities

ity of the substrate. It is clearly seen that the imaginary part of the permittivity contains two terms. The first one is associated with the dielectric loss mechanisms, and the second one is associated with the material conductivity. The dielectric loss, which is typically expressed as the loss tangent, is the measure of signal loss due to the inherent dissipation of EM energy in the substrate. It is mathematically expressed as the ratio of the imaginary part of the permittivity to its real part:

tan δ =

Im ( εr ) ε′′ σ = + = tan δd + tan δc Re ( εr ) ε′ ωε0 ε′

(2.2)

As seen from (2.2), the loss tangent consists of two parts: tan δd indicates the dissipation caused by dielectric damping, and tan δc refers to the loss due to conductivity of the substrate. When an EM field is incident on a dielectric material, polarization of charges or dipoles forces them to be displaced relative to the applied field. The dipole moments cannot react instantaneously to the applied field due to thermal agitation, which tends to randomize their polarizations. Hence, energy is absorbed by the dielectric to reorient its dipoles and is termed dielectric damping. This damping effect is the ratio of the complex part of permittivity to its real part. The second part in (2.2) shows the loss due to conductivity of the dielectric. This part is often ignored in traditional microwave substrates such as PTFE or GaAs, as they exhibit extremely low conductivity values. However, in a standard silicon processes, the substrate resistivity is typically between 1 Ω-cm and 15 Ω-cm, which means that the conductivity is as high as 100 S/m. Such high conductivity values translate to an extremely high loss tangent unacceptable at microwave frequencies. Moreover, when the antenna is placed on top of silicon substrates, the EM waves find a low resistive path through the substrate, causing a major portion of the RF power to be absorbed by it instead of being radiated into the air. The absorbed radiation is largely dissipated in the substrate as heat and causes severe reduction in antenna gain and consequently in the total efficiency of the SoC. This is why most AoCs exhibit low radiation efficiencies unless a gain-boosting mechanism is employed. This concept can be better understood from Figure 2.2, which shows a dipole antenna fabricated on a silicon substrate. More than 90% of the radiation is confined in the substrate below the antenna with a small amount radiating into air. One might argue that the backside radiation of the antenna can be utilized as the main radiation; however, due to the highly lossy nature of the substrate, much of the energy is lost, leading to poor performance. Due to its low resistivity and resulting high loss tangent, silicon can be classified as a lossy substrate for antenna implementation. It is important to understand why the resistivity of silicon substrates is kept so low. It is the direct



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35

Figure 2.2  Radiation distribution of antenna fabricated on low resistivity silicon substrate [1].

result of a high level of doping used in silicon processes and is advantageous for IC design, as low resistivity is helpful for avoiding latch-up issues. Latch-up occurs due to current conduction by parasitic negative-positive-negative (NPN) or positive-negative-positive (PNP) devices formed in the substrate. Through the use of low-resistivity substrates, the gain of these devices can be reduced, which, in turn, reduces the probability of latch-up. While advantageous to IC design, this low resistivity is highly detrimental to antenna performance. Printed antennas undergo energy dissipation in the conductive metal parts as well as in the substrate. In conventional microstrip antennas on lowloss dielectric substrates, the conductive losses typically account for the greatest amount of dissipation. However, as the operating frequency increases, dielectric losses become a larger part of the loss budget. In the case of highly lossy substrates like silicon, it has been observed that the substrate-based loss mechanisms dominates over the loss due to metallization. 2.1.2  High Dielectric Constant of Silicon

The second major issue of the silicon substrate from antenna integration perspective is its high dielectric constant of εr ≈ 11.9. A high εr causes most of the radiated power to be confined in the substrate rather than being radiated into free space. To better understand this effect, consider the dipole antenna at the interface of air and a dielectric material as shown in Figure 2.2. The ratio of the power radiated into air to the total power can be approximated by:

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Antenna-on-Chip: Design, Challenges, and Opportunities



Pair 1 = Ptotal ε3 2

(2.3)

where Pair is the power radiated into air and Ptotal is the total radiated power. For silicon with a dielectric constant of 11.9, only a small portion of the total power will radiate into the air (about 3%) and almost 97% will be coupled into the substrate [2]. Compared to this, other commercially used substrates with lower relative permittivity values transmit a bigger portion of the radiation into the air such as FR4 glass epoxy (≈12.5%) and RT Duroid (≈30%). The highly uneven division of radiated and absorbed power in silicon substrates applies to transmission as well as reception. If, for example, 97% of the power transmitted by the antenna is absorbed into the substrate and only 3% is radiated into air, then reciprocity dictates that, at reception, the power received by the antenna will also be 3%. Silicon can be imagined as a sink, attracting all antenna radiation towards itself and leaving little to none that can be usefully radiated into air. Hence, without any mechanism to reroute the power coupled into silicon substrate back into the air, it is not possible to implement a high-efficiency antenna on the chip. In addition to the fact that planar antennas should have a high front-to-back radiation ratio, this backward radiation in CMOS technology is undesirable as it interferes with the circuits realized at the substrate-oxide layer interface. It can be summarized that, while silicon is the best choice for IC design, its low resistivity and high permittivity are major causes for the low radiation efficiency of antennas. The low resistivity gives rise to conductive losses and high permittivity is responsible for the excitation of surface waves in the substrate; together, they constitute the two main loss mechanisms in on-chip antennas. A detailed discussion on surface waves is given next. 2.1.3  Surface Waves

Typical silicon wafers have thicknesses in the range of 300 to 500 µm, which are considered electrically thick for millimeter-wave frequencies and beyond. The thick substrate, combined with the effect of high silicon permittivity, leads to the excitation of higher-order substrate modes. These modes produce surface waves in the substrate that are a major concern for on-chip antennas because they can degrade radiation patterns and reduce the overall efficiency. The energy coupled into surface waves can radiate out of the substrate’s backside, diffract from the chip edges (causing side-lobes in the radiation pattern), or be resistively lost as heat within the conductive doped silicon substrate. The major factors contributing to the excitation of substrate modes are the dielectric constant εr, the substrate thickness h, and the presence of ground planes on one or both sides of the substrate.



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37

In general, the excitation of higher-order modes is inevitable when antennas are fabricated on a substrate with εr > 1. This can be better understood from a ray optics point of view. Consider an antenna on top of a grounded dielectric material as illustrated in Figure 2.3. The antenna radiates waves into the free space above and into the dielectric material below. In the dielectric material, these waves are reflected by the boundaries and propagate in a zig-zag path between the dielectric-air interface. The incident waves with an angle θi smaller than the critical angle θc = sin −1 1/ εr are partly reflected by the dielectric-air interface and partly leaked into the free space. The latter can then add to the radiated waves either constructively or destructively, depending on the phase. The waves that are incident at the dielectric-air interface at an angle equal to or larger than the critical angle θc are completely reflected and trapped inside the dielectric material. These waves propagate as surface waves and are diffracted at the edges of a finite-sized dielectric material. Thus, their amplitude can be high when they reach the edges of the dielectric slab, where they are reflected or diffracted from the edges, interfering with the waves radiated by the antenna. Consequently, not only is the antenna’s radiation efficiency degraded, but the far-field patterns and the polarization purity are also deteriorated. A complete investigation of the surface waves in the homogeneous dielectric slabs is presented in [3, 4]. Surface waves are essentially the power coupled to higher-order transverse magnetic (TM) and transverse electric (TE) modes that are attenuated along the plane perpendicular to the antenna. They propagate along the antenna plane when the frequency of operation is above their corresponding cutoff frequency. The cutoff frequency of high-order modes is computed by the equations:

(



f c,TM =

)

nc (2m − 1) c ; f c,TE = 2h εr − 1 4h εr − 1

Figure 2.3  Surface waves in a finite high dielectric slab.

(2.4)

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Antenna-on-Chip: Design, Challenges, and Opportunities

where n = 0, 2, 4.... and m = 1, 3, 5 are the order of the mode, c is the speed of light, and h is the substrate thickness. As noted from the above expression, the substrate will always support a TM0 mode and an additional mode for approximately every quarter-wavelength (c / 4 εr − 1 to be exact) of substrate thickness. For a silicon substrate of thickness h = 500 µm and relative permittivity of 11.9, the first higher-order mode TE1 has a cutoff frequency of only 45 GHz. This implies that many of the natural substrate modes for a typical silicon die size fall right in the middle of the millimeter-wave bands of interest and cannot be avoided. Figure 2.4(a) shows the various substrate modes that can be excited due to an on-chip dipole antenna, as the ratio of the substrate thickness to the wavelength is increased. It is important to note that while these values are specifically for the dipole antenna, they show a general trend of mode excitation once the thickness of the substrate is above the cutoff for that mode in the substrate. One of the important parameters used in analyzing the substrate modes is the effective guide thickness heff. It is a term from the ray optics perspective of wave propagation in ICs and is given by the actual thickness plus the apparent penetration depth of the ray. The complete analysis of substrate modes and the derivation of heff is out of the scope of this book and can be found in detail in

Figure 2.4  (a) Normalized power of various substrate modes excited by a dipole for different substrate thicknesses. (b) Effective guide thickness heff versus substrate thickness for different substrate modes (er = 4) [5].



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39

the works of Kogelnik [6] and Rutledge et al. [7]. Here, only the end result is shown to signify the role of effective guide thickness in calculating the power coupled to each mode, using the following expression:

P=

EHh eff 4

(2.5)

where E and H are the maximum transverse electrical and magnetic field amplitudes. Figure 2.4(b) shows how heff varies for the different modes and substrate thicknesses for a relative permittivity of εr = 4 [5]. The relation of substrate thickness to the excitation of surface waves can also be expressed in terms of operating frequency. By rearranging (2.4), the critical height hc can be calculated, beyond which higher-order surface waves begin to originate:

hc =

nc 4f h εr − 1

(2.6)

where fh is the highest operating frequency of the on-chip antenna. As the thickness of silicon substrate is increased, the E-field is confined to the substrate, producing an asymmetric antenna radiation pattern that degrades the radiation efficiency. Figure 2.5 shows critical substrate thickness as a function of operating frequency for three dielectric materials. As the general thickness of the substrate layer in a CMOS process is around 300 to 500 µm without any special post-processes, at a commonly utilized millimeter-wave frequency of, say, 60 GHz, the substrate must be thinner than about 377 µm to prevent the excitation of surface waves. Compared to one of the most commonly used antenna substrates, RT/Duroid 5880 (εr = 2.2), the critical thickness of the silicon substrate is nearly three times smaller. Consequently, the generation of substrate modes in on-chip antennas is highly susceptible to variations in the substrate size. To further illustrate the effect of substrate modes on an on-chip antenna’s radiation performance, 3-D radiation patterns of a 77-GHz bow-tie antenna are presented in Figure 2.6 with varying substrate thicknesses [8]. A satisfactory doughnut-shaped radiation pattern is obtained when the silicon substrate thickness is set to 20 µm. As the silicon substrate thickness increases, the radiation pattern begins to distort. For the 77-GHz antenna, the first higher-order mode, TE1, occurs at a critical thickness of 295 µm, hence the radiation pattern appears significantly distorted when the thickness is increased to 300 µm. Therefore, in AoC design, it is generally advisable to avoid the excitation of any higher-order modes by selecting a substrate thickness that ensures that the

40

Antenna-on-Chip: Design, Challenges, and Opportunities

Figure 2.5  Critical substrate thickness (hc) as a function of the operating frequency with varying dielectric properties.

Figure 2.6  The 3-D radiation patterns of a planar on-chip bowtie antenna at 77 GHz for substrate silicon thicknesses of: (a) 20 µm, (b) 50 µm, and (c) 300 µm [8].

cutoff frequency for the nearest mode is above the frequency of operation. Postprocessing of the die in the form of wafer-thinning is commonly used to achieve reasonable radiation efficiency at higher frequencies. For very thin substrates (below the TE1 cutoff frequency), antenna efficiencies are very high because not only is the excitation of higher-order modes prevented but also the mean path length traveled by surface waves in the lossy substrate is reduced. It is clear that surface waves are a major threat to the boresight radiation of the antenna and adversely affect the entire radiation pattern. This affect is



Design and Implementation Challenges

41

enhanced in on-chip arrays where the unwanted radiation can interfere with other antenna elements, leading to nonuniform radiation patterns that degrade the beam scanning accuracy and may even tilt the main beam direction, leading to an inefficient and flawed system design. Because surface wave excitation is a major concern for AoC designers, a number of techniques have been developed over time that aim to prevent their excitation in order to improve AoC performance. These techniques include modifications in the substrate thickness to eliminate higher-order modes and the attachment of special structures that can give the substrate a semi-infinite feel so that the internal reflection of incident fields is avoided.

2.2  Limitations of the CMOS Stack-Up A detailed overview of the typical CMOS stack-up used for the implementation of state-of-the-art ICs and antennas was discussed in the beginning of the chapter. Reverting back to Figure 2.1, it can be seen that the fixed number, thickness, and spacing of the different layers in the stack-up leave the antenna designer in a highly inflexible design environment. Apart from the antenna itself, gain enhancing or isolating meta-surfaces and ground planes that are to be inserted in lower metal layers are also affected by the constraints of the CMOS stack-up and require novel solutions for effective implementations. The average thickness of the oxide layer in modern CMOS processes ranges from 7 to 15 µm, with the metal layers being approximately 0.5 µm thick. These values are extremely small and are thus not suitable for many design techniques and strategies, especially at lower frequencies. For example, the best way to isolate the antenna from the lossy silicon substrate is to have a ground plane in the lower metal layers. However, due to the extremely thin oxide layer, the spacing between the antenna and the ground plane is so small (100 GHz) does the wavelength become so small that a metal ground plane can be used in one of the metal layers without having a detrimental effect on bandwidth. This is especially an issue for the antennas excited in a microstrip mode, as they cannot have a ground plane in the metal layers (at least at lower millimeter-wave frequencies), whereas placing the ground plane at the bottom of the substrate means that the EM fields will interfere with the ICs and be absorbed by the substrate as well. The design of multilayer antennas and meta-surface layers also becomes complicated due to the limited availability of space in the IMD region. Meta-surfaces can be realized in the interlayers of the metal stack-up and act as

42

Antenna-on-Chip: Design, Challenges, and Opportunities

reflection planes below the antenna to improve the antenna bandwidth and gain. Due to the limited availability of usable space in the oxide layer, the designer has to either modify the geometry of the metasurface elements or change them completely to satisfy technology constraints. It is desirable to have greater separation between the on-chip antenna and ground layer for higher radiation efficiency, which translates to using a lower metal layer for ground. However, using a lower layer for ground results in fewer metal layers being available for the routing of circuits beneath the ground plane, hence generating a trade-off. In digital circuit blocks, a static random access memory (SRAM) contains the densest metal routing in very large-scale integration (VLSI) and can be taken as a benchmark to determine the minimum number of layers needed for routing. In a typical design, SRAM uses a minimum of four routing layers, including one ground layer. So the best approach would be to consider the fourth metal layer, M4, as a shared ground plane for both digital circuits and the patch antenna, providing not only a good AC ground for the RF return current path, but also a good global DC ground. However, this causes a lowered patch antenna height and, consequently, a reduction in radiation efficiency compared to when the lowest metal layer (for instance, metal 1) is used as a ground. Huang and Wentzloff [9] reported a 15% efficiency reduction by shifting the ground to cater to the needs of the digital circuit side.

2.3  Modeling and Simulation Challenges Accurate modeling and simulation of antennas in standalone and integrated form play a big part in efficient design. These simulations are crucial for the proper analysis of the interference effects of the circuit and substrate on the AoC and vice versa. The challenges of simulating on-chip antennas range from unavailability of specialized design tools to long simulations of complex integrated structures that cost designers valuable time and resources and will be the topic of this section. 2.3.1  Cosimulation Tools

Antennas are radiating structures and are typically designed using EM simulators such as Ansys HFSS [10] or CST STUDIO SUITE [11], which work by computing solutions to Maxwell’s equations using appropriate boundary conditions. Circuit designers do not require EM field analysis and use circuit simulators such as Cadence [12] or Keysight ADS [13], which perform voltage or current-based nodal analysis. These softwares are very well suited for IC design as they allow the use of foundry-based technology files for various device models, provide detailed circuit layouts, and have built-in functionality to perform design rule check (DRC). DRC is a part of the IC design process to determine



Design and Implementation Challenges

43

if the chip layout satisfies a number of rules defined by the semiconductor manufacturers that ensure proper functioning and reliability of the fabricated devices. More details on these rules and their implications for AoC design will be discussed in Section 2.4.1. To date, there exist only a few mainstream simulation tools (e.g. CST Studio, Cadence) that provide the functionalities to simultaneously tackle both EM and circuit simulations; however, accurate analysis of coupling effects between AoC and circuits still remains elusive. In a typical AoC design process using existing technologies, the antenna is first designed and optimized in the EM simulator; then its layout is exported to an IC design tool and optimized along with the circuit layout. During AoC design, any errors arising from DRC violations or coupling between the antenna and circuit can take the designer back to the starting point of the layout design. If a single tool was able to simultaneously perform both these checks, the design time would be drastically reduced. Hence, one of the major bottlenecks that AoC designers have yet to overcome in the simulation domain is that the complete on-chip system cannot be simulated altogether. The challenges of commonly used cosimulation strategies are discussed next. 2.3.1.1 

Simulating Antenna in IC Simulator

A true cosimulation of AoC and on-chip circuits using current tools might not be possible; however, there are indirect methods that can help to partially investigate the effect that both sides have on each other. The most common method is to extract the S-parameters of the optimized on-chip antenna from the EM simulator and import them into an IC design tool. This allows the circuit to be cosimulated with the AoC’s input impedance characteristics. Figure 2.7 shows the cosimulation of an on-chip antenna with a voltage-controlled oscillator (VCO) in Cadence where the AoC has been inserted in the schematic in the

Figure 2.7  Cosimulation of the AoC and VCO circuit in the IC simulator (Cadence design environment).

44

Antenna-on-Chip: Design, Challenges, and Opportunities

form of its S-parameter file. In order to achieve an optimal overall design with good impedance matching between the circuit and the antenna, several iterations between the EM simulator and IC design tool are usually required. The designers have to move back and forth between EM and IC simulators until satisfactory performance is achieved, and this has a considerable toll on complexity and simulation time. Moreover, the extracted S-parameters of the AoC are in the frequency domain and cannot be directly used in the time-domain analysis of IC simulators. In addition, the AoC’s S-parameters are influenced by the port impedance selected in the EM simulator, so it is important to ensure that when cosimulating the antenna block with the circuit in the IC simulator, the interface impedance is kept consistent with the port impedance of the former. � 2.3.1.2  Simulating a Circuit in the EM Simulator

Analyzing the effect of circuit components on the radiation performance of the antenna is as important as the antenna’s effect on the chip layout. It has been observed that large metal structures such as inductors, bond pads, and metal fills have a degrading effect on the antenna’s performance. To correctly simulate this effect, the commonly used approach is to model these structures in the EM simulator with the antenna and ensure that the coupling between them is minimized. As an example, see Figure 2.8, which shows a coplanar waveguide (CPW) monopole antenna simulated in HFSS with a simplistic representation of an oscillator transmitter circuit with components such as metal fills, inductors, RF pads, and transmission lines. However, this approach has several associated challenges. First, circuit layout is the last step in the design cycle, and because the antenna and circuit designs have been done in parallel, the antenna might need reoptimization based

Figure 2.8  Cosimulation of on-chip monopole and circuit elements in an EM simulator (HFSS).



Design and Implementation Challenges

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on any discrepancies arising in the layout stage. So not only will the designer be required to cosimulate the circuit’s effects in the EM simulator, but in some cases the antenna might also require a complete resimulation. This, in turn, may affect overall design specifications and cost crucial time before the chip tape-out. Second, it is difficult to realize accurate models of circuit components in EM simulators. The entire layout of the circuit can usually be imported in EM simulators for coupling analysis, but it is still not an ideal representation, as the circuit is not in working form, rather, only a collection of copied metal layers. For example, simulating the coupling between an antenna and a nearby inductor modeled without any currents would not give the same results as modeling it with real currents. Third, a challenge often encountered in simulating large ICs is the spatial complexity of on-chip components. An IC is densely packed with components ranging from transistors to simple metal fill structures. Simulating the exact layout of the chip in EM simulators makes the meshing extremely complex and can considerably increase simulation run times, forcing the designers to often adopt a simplification of these structures. � Most of the issues related to antenna-on-chip simulation can be resolved when the full-wave EM simulations and circuit simulations can be run together, in either a single simulator or two simulators running in conjunction. AoC is a nascent technology and the existing cosimulation techniques are not at par with the challenges encountered in the design process. However, with its rapidly increasing potential and market applications, it is only a matter of time before a robust method can be devised that accurately simulates all the aspects of integrated on-chip antennas.

2.4  Size and Layout Challenges The inclusion of AoC greatly reduces system size as it eliminates the need of bulky off-chip components and interconnections, but, in doing so, the size of the individual chip becomes comparatively larger. Although the added cost of the larger chip with an AoC becomes negligible in volume production, it is still an ongoing research challenge to miniaturize AoCs so that they take up minimum chip area. Next, the layout of antenna on the chip is also an extremely important step in the design procedure as it has an impact on signal coupling, system size, and the manufacturability of the IC. When an antenna is to be integrated with a front-end circuit, layout design rules come into play that are enforced by foundries to comply with well-defined fabrication steps. Adhering to these design rules is important to ensure that the chip layout does not need redesigning at a later stage, which can incur cost and time penalty. At the same time, the fulfillment of these rules comes at a cost of multiple design challenges to the antenna and its auxiliary structures. Below are some of the major is-

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sues that designers have to overcome to reach a layout that allows the antenna and the circuit to operate effectively together while satisfying the fabrication requirements. 2.4.1  DRC

The layout of silicon ICs is governed by a set of foundry-defined rules that are put in place to ensure design for manufacturability (DFM) and to obtain high yields. DFM is the general practice of designing parts, components, or products in such a way that they are easy to manufacture and incur a lower cost. Designers typically perform numerous iterations of circuit layouts to ensure that these design rules are not violated, a process called DRC. DRC is a major step during the physical verification or sign-off of IC designs, which also involves layout versus schematic (LVS) checks, XOR checks, electrical rule check (ERC), and antenna checks. These checks are in place to ensure correct electrical and logical functionality and manufacturability of IC designs. For example, DRC verifies that the chip layout meets all technology-imposed constraints, LVS checks detect whether a particular IC layout corresponds to the schematic, exclusive OR (XOR) checks involve comparing different design layouts to find mismatches and ERC checks verify the correctness of power and grounding connections. IC design tools either have built-in functionalities or third-party tool integration options to perform these verifications. Of all the physical verification checks, the DRC is of special interest to antenna designers because it dictates, among other things, the minimum and maximum allowable widths of metal lines, spacing between adjacent lines and the required metal densities on different process layers. As antennas are not conventionally implemented on the chip, there are no specific rules or exemptions for them in the current mainstream DRC. Consequently, it becomes difficult to resolve the DRC errors that arise due to the on-chip antenna layout. Some of the important DRC errors that need to be mitigated in AoC design are discussed in the next sections. 2.4.1.1  Metal Density Rules

The most commonly faced issue in DRC is the requirement of a specific metal density in each metal layer. This rule is important, as nonuniform metal density can induce thermal expansion stress and affect etching during fabrication. There are two types of metal density rules. Global metal density rules that indicate the metal density constraints for the entire chip, and local density rules that define the metal density requirements for a certain area (normally 100 × 100 µm). There are two further classifications of the metal density rule based on minimum and maximum density limits. The minimum density rule stipulates that the allowable metal density in a chip area cannot be less than a threshold value (typically 30%). For example, in large empty spaces surrounding anten-



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nas, the metal density falls short of the minimum limit and dummy metal fills need to be added. Similarly, when large contiguous metal exceeds the limits (normally 70%), the maximum density rule comes into play and slots need to be etched in the metal. The minimum density rule is put in place to ensure uniform etching of metal layers. When the oxide layer is deposited over widely spaced metal lines, deep troughs or valleys are formed that lead to nonuniform etching as shown in Figure 2.9. This results in shorts forming in the subsequent metal layers, which are catastrophic for circuit performance. Compared to this, tightly packed metal lines cause oxide to deposit in hills, and this is easily etched away to create a uniform metal layer [14]. One way to overcome density restrictions is to modify the antenna design by adding strips or patches to it. However, this is not always feasible and might come in the way of achieving optimum performance. The second method is to add dummy metal fill in large empty spaces that fall below the required density. Metal fill refers to floating metal pieces inserted around large structures such as the antenna and inductors. Figure 2.10 shows dummy metal fill placed in an empty region around the circuit components in an IC layout. The presence of these dummy fillings around and below the antenna structure can potentially degrade its performance by causing disturbance to the radiation pattern and variations in the resonant frequency. For example, in the design of on-chip antennas and arrays [15, 16], insertion of metal fill is observed to have lowered the radiation efficiency by up to 20% and significantly affected its gain. However, in most cases, the effect of metal fill, if properly simulated beforehand, is not so significant. It has been experimentally observed that the antenna is most affected by the dummy metals directly below it. In order to satisfy minimum density rules, the dummy metals can be concentrated in areas away from the antenna so that it is least affected [17]. In newer technologies, foundries allow areas of very low metal density through block layers, which can be used when designing critical transmission lines and inductors. Antenna designers can also use this layer to their advantage when the design may seem

Figure 2.9  Chip fabrication with and without dummy metal fills. Violation of density rules causes shorts to be formed in metal layers.

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Figure 2.10  Microscope view of an RFIC with dummy metal fills.

highly sensitive to the interference of metal fills. However, for such an allowance, foundries need to be informed prior to fabrication. Contrary to minimum density rule, the maximum density rule is employed to ensure that metal lines are not too tightly packed. When the density on a layer exceeds the design rule limits, slots need to be created in large metal surfaces (such as required for antennas). The exact size of the slot depends on the design rules and extent of density violation, and there are typically fewer degrees of freedom for a designer on the placement of slots. For example, in [18], an on-chip patch antenna designed for a terahertz imaging application (shown in Figure 2.11(a)) has been slotted to fulfill the DRC of a 40-nm CMOS process. As seen in Figure 2.11(b), the gain of the antenna is not significantly altered; however, the input return loss is shifted towards the lower end of the frequency spectrum. Apart from the antenna, the ground layers are also subject to the density rules and often require slotting to avoid crossing the maximum density limit. This leads to a nonuniform ground plane below the antenna and can cause potential degradation in the antenna performance. A solution to this problem is the formation of ground plane through stitching of multiple metal layers to cover the slots of one layer by another layer. For example, metal layers M1 and M2 in Figure 2.12 are connected or stitched together through vias to create a continuous ground plane below the top metal layer antenna [19]. 2.4.1.2  Metal Width, Spacing, and Geometry Rules

The DRC rules prescribe the maximum and minimum allowable metal line widths, minimum spacing between metal lines, and the bend angles of metal lines as depicted in Figure 2.13. A minimum line width is imposed on all layers and may be much higher than the technology parameter (minimum channel length). This guarantees that etching is successful, deposition has enough space



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Figure 2.11  (a) On-chip patch antenna with slots added to satisfy DRC, and (b) simulated antenna gain and input return loss of the patch antenna with and without slots [18].

Figure 2.12  Cross-section view of on-chip patch antenna with slotted ground plane. Layers M1 and M2 are stitched or connected to provide a uniform ground [19].

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Figure 2.13  Common DRC rules for metal line widths, spacing, enclosure, and vias.

to take effect, and corners are not affected by oxide thickness variations. Normally, this lower limit does not affect antenna design, as it is on the nanometer scale. However, the maximum limit of the metal line width, which typically ranges from 20–30 µm for most processes, can restrict the flexibility in required antenna dimensions. The maximum limit is imposed to avoid electrostatic charge buildup that could damage the transistors with which these large metal areas are connected. This is contradictory from an antenna’s perspective, which requires greater widths as larger metals offer low resistance, handling more current, resulting in higher EM radiation. Often, due to limitation on the maximum width of metal line, the implementation of large structures such as patch antennas cannot be done. Designers have to devise workarounds by using slots or loop antennas in their place. Similar to line width, line spacing is also restricted by a minimum limit that might cause issues in the design of complex antenna structures such as slots and spirals. However, this limit is usually quite low and does not hinder most antenna design. The DRC also dictates the exact line angles that can be fabricated in various metal layers. These rules impose limitations on size, shape, and geometry of allowable metal structures, thereby reducing design flexibility. For example, in many CMOS processes, slant metal strips can only have an orthogonal or 45° angle, and, in some older technologies, sharp angles such as 90° are not allowed. This means that any structure realized on the M1 layer that includes right angles will have to be approximated with non-90° angles or completely redesigned. Most often, the design of antennas and meta-surface layers is affected by these restrictions. Compromises have to be made as the metal shapes that give better efficiency in off-chip designs cannot be used in on-chip designs due to DRC violations. A good example of innovative antenna design in compliance with DRC is shown in Figure 2.14 [17]. The antenna shown has been designed for a 33-GHz



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Figure 2.14  AoC design process in compliance with DRC: (a) basic triangular patch, (b) Vshape antenna created by removing central part due to maximum width rules, (c) final design with strips added to fulfill metal density rules, and (d) close-up of DRC violations and their solution [17].

receiver in 28-nm CMOS and is initially a triangular patch with an open circuit stub at the beginning of the feed line to improve return loss. As the maximum width of the patch exceeds the metal width limitations, it is converted into a V-shaped antenna by removing the central part. By doing so, the metal width rules are satisfied but its performance suffers; therefore, metal strips are added to compensate performance degradation. Furthermore, at the connection of the metal strips to the V-shaped structure, separation between the two metal lines is extremely small, violating the minimum width rule, consequently, small metal patches are added at the connecting points. Similarly at the upper edges of the V-shape radiator, rectangular patches are added as the corners violate the minimum width criteria. This design flow gives a very good idea of the complexities involved in implementing an antenna using existing CMOS technologies whose DRC is not very accommodating to AoC considerations. 2.4.1.3  Via Design Rule

Via design rule includes the constraints on the size of a single via and via arrays. Under this rules the spacing of vias from metal line edges and between multiple vias is specified as shown in Figure 2.13. Via size becomes more important in case of multilayered AoC design where a solid RF connection between the layers is highly desirable. The number of vias in a specific metal region is also defined by the DRC. Another DRC check pertaining to minimum size of enclosure is quite important for via design. It stipulates that one layer must be enclosed within another by a minimum distance. This enclosure size ensures that etch variations do not affect the proper realization of the contacts in vias. 2.4.1.4  Antenna Rules

The antenna rule is added to counter the antenna effect. The antenna effect refers to accumulation of electrostatic charge that can have a devastating effect

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on the active circuits. It is also a misnomer because it does not actually refer to a radiating antenna. During fabrication of silicon ICs, a large amount of charge is induced at the time of plasma etching and ion implantation processes. If a large metal wire is connected to the gate of a transistor as shown in Figure 2.15(a), the discharging of the metal component through the thin gate oxide of the transistor may cause permanent damage to the transistors or degrade their performance. This effect may cause damage to the chip during the manufacturing process and is not detectable on a finished chip. However, it is possible for electrostatic discharge (ESD) to be induced in large on-chip metal structures due to human touch or through probes during characterization. To prevent this, antenna rules are imposed by the foundry as part of the DRC. They are normally expressed as the antenna ratio, which is an allowable ratio of the gate area to the gate oxide area as the magnitude of charge collection directly depends on the area of the conductor (gate area). When this ratio exceeds the value specified by the DRC, antenna violation occurs. Conventionally, antennas were not part of the IC; therefore, no allowance for antennas has been defined in the foundry

Figure 2.15  Antenna effect in large metal structures: (a) ESD from metal causes breakdown of gate, solutions to antenna effect include (b) addition of diode in the gate path to allow charge leakage, and (c) addition of ground connection that can be removed later.



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rules. When an antenna is present on the chip, this effect may be observed and, in some cases, amplified due to its relatively large metal area. Hence, antenna rules are a very important check for AoC design and layout. The effect of the antenna rule manifests in the form of size restrictions in AoC design. For example, the maximum metal width in a certain layer may be limited from few to several hundred micron depending upon the process technology. Most processes do not allow metal widths of more than 25 µm to be connected to the transistors because of ESD. This metal width is not sufficient for antenna design and affects its gain in a negative way. If the metal width is increased beyond this limit, it will result in the violation of DRC. A simple solution to the antenna effect is shown in Figure 2.15(b) where a diode is created near the gate of the transistor. In the finished circuit, this diode will not affect functionality due to the reverse bias. However, during fabrication, the reverse junction to the substrate or a doped well provides a path for the electrostatic charge to leak without destroying the gate oxide. Another shortcut to resolve this issue is to provide a ground connection to the antenna in the top metal layer. This ground connection will prevent any ESD issues during fabrication and can later be removed through microsurgery (lasering) as shown in Figure 2.15(c). DRCs not only complicate an AoC designer’s task but also take a toll on resources and design time. However, they are a necessary part of IC design and are important in ensuring the reliability of manufactured chips. Until CMOS processes develop special antenna-centric rules for AoC implementation, innovative solutions and workarounds will have to be adopted to accommodate antennas in the chip layout without invoking DRC errors.

2.5  Fabrication Tolerances The chip fabrication process can sometimes add uncertainties to the dimensions of AoC components such as the antenna, cavities, and substrate. For example, it was shown in [20] that the dimensions of the etched cavity below an AoC could vary up to 38% post-fabrication. Similarly, the fabricated chips are generally polished from the backside, sometimes resulting in a different silicon substrate thickness than specified in the foundry documentation. This discrepancy can not only alter antenna impedance but also cause surface waves to change antenna gain and radiation pattern especially at millimeter-wave frequencies. For instance, in [21], a frequency shift of 4 GHz (from 10 GHz in simulations to 14 GHz in measurements) is observed in the antenna’s reflection coefficient, which is ascribed to the variations in substrate height and relative permittivity value post fabrication. The production tolerance, although much better than other fabrication processes such as PCB etching or milling, is still

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another factor that has to be considered, as it is common for AoCs to vary a little during bulk production. Residual silicon substrate (RSS) is a form of a common fabrication flaw that needs to be considered in on-chip designs. It refers to the excess silicon deposit that is generated on the buffer area around an IC during the chip dicing process. Wafers used for chip fabrication are made from high purity silicon and contain multiple dies that need to be cut and separated into individual dies at the end. During the dicing process, a certain amount of silicon residue is produced regardless of cutting technology. RSS has a negative impact on the antenna performance and because it accounts for greater substrate loss, it also leads to gain reduction (up to 5 dB as reported by [22]). When the antenna is integrated with other on-chip circuits, this issue becomes more significant as all the extended silicon regions, including the circuits, can be considered as RSS for the AoC.

2.6  Coupling and Interference Issues� In an SoC, the on-chip antenna and the baseband circuits work simultaneously so the crosstalk between them is a concern for maintaining system performance. In AoC-based designs, the antenna and the high-frequency front ends are more closely packed, compared to other integration approaches (AiP and off-chip antennas). Today’s highly integrated RFICs include many top-metal inductors, capacitors, bond pads, and transmission lines, which are usually placed in close proximity to save silicon area and to achieve shorter interconnects. Hence, EM interference (EMI) resulting from mutual coupling between the antenna and the circuit manifests itself in various forms as shown in Figure 2.16. As an example, a digital signal operating beneath the ground plane could be picked up by the AoC and then radiated, causing the chip to exceed the U.S. Federal Communications Commission (FCC) noise emission mask. At the same time, the RF signal on the AoC may couple to the baseband circuits causing malfunction of a feedback loop, digital logic, or memory. It is important to carefully investigate circuit and bond pad placement with respect to AoC through EM simulations. The placement of inductors is even more challenging as they also tend to radiate. Additionally, effects of nearby radiator element on circuits must also be assessed in post-layout circuit simulations. As mentioned in Section 2.3, multiple time-consuming iterations are required between EM and IC simulation tools to achieve allowable levels of intercircuit crosstalk. 2.6.1  Coupling from the Antenna to the Circuit

There are two mechanisms of coupling from the antenna to the circuits: (1) direct coupling of EM radiation through air, and (2) coupling of EM energy



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Figure 2.16  The various forms of on-chip coupling mechanisms. (Reproduced with permission from Abbasi et al.)

through the substrate. Both forms of coupling, if not controlled, can degrade the system performance drastically. Coupling through the air is more likely to affect top metal structures such as inductors and transmission lines. Not much can be done for this type of coupling, except smart decisions in the layout so that the circuits are either placed towards the radiation null of the antenna or towards its minimum radiation direction. However, the signals through the substrate, shown as noise in Figure 2.17, reach the active region housing transistors and can severely affect their performance. Unwanted coupling between the AoC and transistors may become significant at high frequencies due to the drain and source junction capacitances and at low frequencies due to the body effect. This can be prevented through higher-resistivity doping on silicon

Figure 2.17  Effect of antenna generated currents on circuits due to substrate noise coupling [23].

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substrate and the use of guard rings around the antenna. Usually, such highfrequency signals coupled to the digital circuits are filtered out by the resistance and capacitances along the routing and do not cause significant skew or jitter problems. However, it is still worthwhile to understand the nature of signals that can be coupled from the antenna to the circuits. In 2011, a study done by University of Michigan used a specialized sensor array designed to detect the magnitude of coupling in different metal layers in the silicon stack-up beneath the antenna [9]. Fifty-six coupling sensors were spread out directly below the ground plane of a patch antenna as shown in Figure 2.18(a). The result of this study is shown in Figure 2.18(b) in the form of the surface plot and contour of the millimeter-wave signal coupled from the top-layer antenna to the bottom metal layers. The maximum magnitude of the coupled signal does not exceed –40 dB as the ground plane beneath the antenna shields the lower layers from unwanted interference. However, it may be noted that the surface plot follows a similar shape to the antenna’s standingwave radiation, which can provide designers with useful information about the placement and routing of circuits in an IC. Although this design was focused on a patch antenna with a ground plane, the interference impact of other on-chip antenna types can also be modeled in a similar way. Transceivers based on zero-IF architecture are particularly sensitive to crosstalk between the antenna port and the local oscillator (LO). In the receiver case, LO leakage that couples to the antenna can cause DC-offset problems, an increased noise floor, and blocking of the front end in extreme cases. Likewise, in the case of transmitters, the major concerns are instability and increased phase noise. One way of avoiding this is to employ a differential LO running at half of the received frequency, which results in negligible leakage to the on-chip antenna, as mainly odd LO harmonics are present at the oscillator output in addition to the subharmonic LO signal. The most straightforward way to reduce coupling and interference is a fully shielded antenna ground plane at the lowest metal layer M1. The presence of a ground plane can also potentially shield the antenna from the substrate and make the antenna performance less prone to variations in substrate dimensions. However, as explained in Section 2.2, the addition of a ground plane has a significant trade-off with regards to the bandwidth. Some designers have tackled this problem by using a patterned ground plane at M1 [24]. In this approach, a slot identical to the antenna is etched into the ground plane so that coupling is minimized without compromising the bandwidth. 2.6.2  Coupling from Circuits to the Antenna

It is seen how signals from the antenna can be coupled to on-chip circuit elements and affect their performance. Similarly, the radiation characteristics and



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Figure 2.18  Sensor array to detect coupling at different locations below a millimeter-wave AoC: (a) schematic of sensor array, and (b) surface plot and contour of signal coupled from the AoC to the bottom layers [9].

input impedance of the antenna are also at risk of being altered due to the effects of nearby circuit components. Because the physical distance between various on-chip components is very small, leakage signals radiated at discontinuities, such as open and short circuits or matching stubs, can be coupled with the antenna. Likewise, digital signals such as the transistor switching and digital clock can act as low-frequency noise sources for the RF signal radiated by the antenna.

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A circuit consists of active devices and passive elements. As CMOS technology has scaled down, the feature sizes of active devices has reduced. However, the sizes of passive elements such as inductors, capacitors, and transmission lines do not directly depend upon technology scaling but mainly on the frequency of operation and substrate properties. Typically, the sizes of passive elements such as inductors are much bigger than those of active devices such as transistors in the amplifier and varactors in the oscillator circuits. These passive elements contribute more to crosstalk with an antenna than active devices. The coupling between an antenna and a transistor may become significant at high frequencies due to the drain and source junction capacitances and at low frequencies due to the body effect. However, the coupling between the antenna and passive elements such as inductors is a far more critical issue. While it has a negative influence on the antenna’s radiation, it may also cause instability of the low noise amplifier (LNA) and deteriorate the phase noise of VCO circuits. Other circuit elements to be considered include bond pads and dummy metal fill whose large numbers and close proximity to the antenna can cause unwanted coupling effects, which, if not properly modeled and simulated, may affect the desired system performance. The following section deals comprehensively with the coupling effects of inductors on the antenna. 2.6.2.1  Coupling from Inductors

The coupling between on-chip antennas and inductors depends upon their placement, critical frequencies, and distances. Spiral on-chip inductors are particularly susceptible to crosstalk due to their large physical size and the ability to radiate. Although there are very few studies on coupling between on-chip antennas and inductors, the same between adjacent spiral inductors has been studied extensively [25]. Inductors and other passive elements such as capacitors and transmission lines act as parasitic patches for on-chip antennas when placed in the closed vicinity of the latter. Normally, the electric field generated by the antenna is terminated at the on or off-chip ground plane. When passive elements are placed, they tend to interact with the antenna by distorting its electric field distribution and causing it to terminate at these devices instead of the ground plane. This was verified by a study done on the mutual coupling effects and mechanisms of an on-chip monopole and a spiral inductor in 180-nm CMOS technology [26]. The monopole antenna, when measured separately, exhibited symmetrical broadside radiation with the cross-polarization being less than −40 and −10 dB in the E-plane and H-plane, respectively, as shown in Figure 2.19(a, b). When measured with a nearby inductor, the maximum radiation direction of the antenna shifted about 10° to 20° in the H-plane as seen in Figure 2.19(c, d). This shows that passive elements may be used as parasitic reflectors for the antenna similar to Yagi-Uda antennas. However, it was also observed that the inductor



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Figure 2.19  The far-field radiation patterns of a monopole at resonant frequency as a standalone monopole (a) in the E-plane and (b) in the H-plane, and as a monopole with inductor spaced at 100 µm at 40 GHz (c) in the E-plane and (d) in the H-plane [26].

increases the cross-polarization of the antenna in the E-plane by at least 20 dB, which is detrimental to the radiation performance. Conversely, it was observed

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that the antenna had limited influence on the passive elements with a slight reduction in the inductance and the quality factor of the inductor. An effective way of reducing such coupling is to insert a ground shield around each inductor as shown in Figure 2.20. EM simulations of the coupling between a spiral inductor and an on-chip dipole, spaced 500 µm apart in [27], show an improvement of nearly 22 dB in isolation due to the use of grounded metallic shields. One trade-off of using a ground shield with inductors is the reduction in inductance and quality factor caused by currents in the shield. Moreover, the ground shield occupies quite a lot of silicon area, which directly increases the chip size. Another technique for smart inductor layout in the

Figure 2.20  Antenna-to-inductor crosstalk reduction using ground shields: (a) without ground shield, and (b) with ground shield [29].



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vicinity of an AoC is to ensure that currents in these inductors are oppositely directed. This will cancel the radiated fields and reduce the mutual coupling [28]. Power distribution networks are another potential source of crosstalk with the antenna as the long transmission lines along the length of the circuit can act as radiators at the circuit operating frequency. To prevent signal leakage from the circuit to the antenna, it is important to provide efficient decoupling to powered subcircuits, such as a combination of inductor-capacitor (LC) and resistor-capacitor (RC) networks. Coupling in on-chip circuits and conventional off-chip antennas is not a new challenge in RF design. With the introduction of the AoC technology and the inclusion of the antenna on the same substrate as the IC, coupling is magnified due to the dense packing of components. Issues that did not arise in off-chip antennas now require critical solutions for AoC designs. Most of these solutions fall under codesign strategies of the antenna and front-end circuits. A comprehensive overview of these will be given in upcoming chapters.

2.7  Characterization Challenges Characterization is the final step in verifying the AoC performance, after the design and fabrication steps are complete. In view of the challenges and nonidealities mentioned in preceding sections, the measured versus simulated performance of on-chip antennas is prone to discrepancies. In addition, the complexity of typically adopted measurement processes add to the uncertainty in obtained results. Therefore, it is critical to know the techniques and best practices in AoC measurements. Conventional PCB-based antennas are characterized in an anechoic chamber by connecting the antenna to a network analyzer through a sub-miniature version A (SMA) connector, as presented in Figure 2.21(a). Although this connector-based characterization method is convenient and accurate for measuring relatively large-sized antennas, it is not feasible for AoC characterization. The size of a typical connector and its inner signal pin can be a few centimeters and millimeters, respectively, while the sizes of on-chip antennas are in the orders of hundreds of micrometers, depending on their operating frequencies. In the case of an AoC, bond pads are available on the chip that are connected to the actual feed point of the antenna through transmission lines. The dimensions of these pads are even smaller than the antenna, typically 50 × 50 µm2 to 100 × 100 µm2. Hence, the AoC is too small to be physically accessible by connectors. This is why, instead of connectors, probe-based methods are commonly used for AoC characterization (see Figure 2.21(b)). RF probes (typically in a groundsignal-ground (GSG) arrangement) are specially designed for proper landing on the bond pads of RFICs and on-chip antennas with the help of a microscope.

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Figure 2.21  Antenna characterization method: (a) connector-based, and (b) probe-based. caption. (Reproduced with permission from Zhang and Shamim.)

Moreover, specialized standard gain antennas are required for calibration purposes during measurements. Currently, only a handful of companies provide such antennas and they are expensive, especially at millimeter-wave frequencies. Similarly, standard anechoic chambers are also not ideal for accurate testing of AoCs; thus, specialized chambers are required, which are quite expensive. Figure 2.22 shows a probe-based AoC characterization setup, called µ-lab from Microwave Vision Group (MVG) [30], which has been specially designed for on-chip measurements. Greater details of probe-based measurement setups and lab facilities providing them can be found in [31]. Although probe-based setups enable effective characterization of on-chip antennas, there are still several challenges related to the measurement accuracy, the influence of the measurement equipment, and the mechanical difficulties in the flexible handling of the antenna under test (AUT). Some of these are discussed below.



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Figure 2.22  Probe-based AoC characterization setup in an anechoic chamber. (Courtesy of KAUST µlab.)

2.7.1  Reflection from the Probe

The interference between the on-chip antenna and the RF probe is a problem often encountered in AoC characterization. The RF probe consists of a large conductor body, and the probe tips are attached to a metallic arm, which is partially covered by an EM absorber. Because the probe body acts as a large conductor in close proximity to the AUT, EM waves from the antenna get reflected from it and interfere with the direct radiation as illustrated in Figure 2.23. The measured radiation pattern is therefore a superposition of the radiated and reflected waves and does not give an accurate depiction of the original radiation characteristics of the antenna. The reflected waves can interfere either

Figure 2.23  Interference between AoC’s radiation and its reflection from the probe. (Reproduced with permission from Abbasi et al.)

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constructively or destructively, depending upon the phase difference, producing regions of maximum and minimum radiation, resulting in a distorted radiation pattern. Although the probe’s inner impedance has been de-embedded through the impedance calibration, the unwanted reflections from the probe body can sometimes also cause unexpected changes in the reflection coefficient of the antenna. 2.7.2  Radiation of the Probe

Another challenge related to probe-based characterization is the radiation from the probe itself. The exposed tip and the metallic probe also radiate to some extent. Therefore, the measured radiation pattern is actually the combination of the radiation of the AUT and the probe. For this reason, it is very important to characterize the individual radiation pattern of the probe. This is done by landing the probe on a 50Ω load of the calibration substrate. This load represents an antenna matched to a 50Ω system and emits negligible radiation so that the radiation of the probe is not affected. The reason for using a matched load is to emulate the same conditions in which the probe tip would radiate when it is landed on an impedance-matched antenna. As an example, a probe at 60 GHz was characterized in [32] and the maximum gain of the probe radiation was measured to be −22 dBi. This means that the actual sensitivity of the measurement system is −22 dBi. It was observed that the radiation was strongest in the upwards direction normal to the probe. This self-radiation, although negligible for high gain antenna measurement, is considerable when measuring AoCs, which are essentially low-gain antennas due to the high permittivity of the substrate and the small aperture. Therefore, while characterizing on-chip antennas, the usually negligible gain of probe self-radiation becomes comparable to antenna gain and can add a significant amount of error in the antenna’s radiation pattern measurement. 2.7.3  Radiation Blockage or Shadowing

The measurement probe and the probe holder are normally much larger than the on-chip AUT. Due to this, the AUT’s radiation in certain directions is blocked and the complete radiation pattern cannot not be accurately measured. This is sometimes referred to as shadowing, and, in order to overcome this issue, it is important to simulate the blocking effects due to nearby equipment and components. For the correct radiation pattern measurements, the receiver antennas must be rotated over a full sphere around the AUT. Due to the probe station being in the way and the limited movement of the receiving antennas as shown in Figure 2.24, a large portion of the measurement sphere is missed and has to be estimated.



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Figure 2.24  The wafer probe limits the scannable area around the AUT.

2.7.4  AUT Movement Restrictions

Traditional antenna measurement setups cannot accommodate the feeding and movement restrictions of AoCs. In most testing setups, the AUT rotates and the reference antenna is kept stationary; however, the rotation of an on-chip AUT is not easy given its intricate feeding mechanisms. For this reason, instead of a 3-axis positioner used in conventional setups, the reference antenna is mounted on a modified positioner that can rotate around the AUT. The positioner needs to be specially designed so as to capture the radiation pattern from all directions without obstructing other equipment. This process becomes even more complex in near-field measurements where the scanning probe must rotate around the AUT in a confined area. Unlike conventional PCBs, silicon wafers are fragile and there is a higher likelihood of wafer damage during measurements. As mentioned earlier, the wafer probes have to land on the bond pads, and a required over-travel is necessary for good contact. This step sometimes lifts the metal from the wafer, permanently damaging the bond pad. In contrast, there is a possibility of weak or no contact if the probe is not adequately overtraveled on the bond pad. The precise alignment of the probe with the feeding point of an AoC is critical for correct results. If the probe tip is tilted with respect to the AUT or the AoC has been packaged in a nonplanar fashion, it is possible that not all probe pins make contact with the antenna bond pads simultaneously. This results in floating pins causing the probe to radiate as an antenna due to the coupling between the probe tip and the substrate. These floating pins also reduce the accuracy and reliability of calibration and measurements. The commonly used solution for this is to employ a microscope to monitor the alignment, especially with narrow pitch probes. However, incorporating a microscope within the test

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chamber can cause unwanted reflections and increases cost. Another approach is to use an on-chip short integrated with the AoC under test as shown in Figure 2.25 [33]. Using the on-chip short, the probes can be tested to calculate the required amount of force for proper pin contact prior to actual measurement. This method is cheap, generic to most probe types, and easy to integrate with the AoC; however, the short needs to be carefully arranged with the chip layout if the AoC under test is part of an on-chip circuit. The GSG pads added in the chip layout for measurement purposes can also have a negative impact on the characterization process. The pads add capacitance to the input impedance of the antenna and may change the resonant frequency of the AoC. This effect was observed in [34] where the resonant frequency of the antenna was shifted by almost 5 GHz. Furthermore, the GSG pads are required only when measuring independently fabricated antennas and are not present in the layout of antennas integrated with front-end circuits so their effect must be de-embedded from the antenna measurement results. 2.7.5  Measurement of Standalone Antennas

The ideal way to test an on-chip antenna is to isolate it from on-chip circuits and measure it as a standalone structure. Typically, this is done by including an identical antenna test structure on the chip in addition to the antenna that is integrated with the circuit. This approach costs valuable silicon area and incurs added costs as the size of the on-chip antennas is generally large compared to the on-chip circuits and because prototyping of on-chip components is expensive compared to mass production. Thus, inventive layout techniques have to be adopted so that the same antenna that is integrated with circuits can be used for individual characterization as well. This might imply adding extra bond pads close to the antenna or using the existing bond pads for multipurpose measurements. To that end, interconnects between the AoC and the circuit can be removed and the former can be measured as a standalone antenna (Figure 2.26). This is achieved through techniques like microsurgery (lasering), focused

Figure 2.25  On-chip short with two optional alignments [33].



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Figure 2.26  Layout concept for characterizing an AoC after isolating it from the ICs [1].

ion beam (FIB), and burning a fuse by the passage of direct current (DC). These techniques will be discussed further in Chapter 4.

2.8  Packaging Challenges Packaging of ICs is the final step before they are shipped off to vendors for use in real-life applications. A package is important to protect an IC from the environment and physical damage during handling. One of the biggest advantages of integration of on-chip antennas with RF ICs within a single package is that there is no longer a need to route the RF signals through the package lead frame onto the PCB and incur additional losses. For a typical IC without an antenna, the package must mainly provide a good thermal contact to drain excess heat, high-performance interconnections for off-chip integration and a robust outer shell for protection. However, when an AoC is included in the chip layout, a good packaging structure becomes all the more important because, apart from physically protecting the chip, the package must now also ensure unobstructed antenna radiation. The key challenges of a robust and efficient package design for AoC are: 1. The package must be designed such that the separation between the packaging material and antenna does not affect its radiation pattern. 2. The packaging material should be chosen such that it does not degrade the radiation coming to and from an AoC. 3. The impact of undesired EM coupling between various components of the package design is significantly increased due to the the proximity of on-chip components. This potentially degrades the far-field ra-

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diation pattern of the antennas and the overall package performance; hence, it must be considered in AoC design. 4. In transceivers with Tx and Rx antennas on the same chip, there is direct leakage from the Tx to Rx resulting in saturation of the receiver. The role of the package becomes important here in isolating the two radiation patterns and minimizing coupling.

2.9  Conclusion This chapter provides a comprehensive overview of the challenges that arise in the design of on-chip antennas. The lossy silicon substrate is quite easily the biggest issue encountered. Silicon’s high permittivity and low resistivity, although ideal for transistor integration, cause AoCs to have inherently low gains and efficiencies. For the AoC technology to pick up, it is essential to somehow minimize the losses due to underlying substrate technology and achieve antenna performance that is at par with its off-chip counterparts. As silicon semiconductor technologies have become the staple for ICs, designers will have to find new ways to suppress the impact of the substrate on AoC performance. Efforts to this end are underway in numerous research groups around the globe, and solutions ranging from modification of substrate properties to physical isolation of the antenna from the substrate are being implemented. The next chapter gives a detailed overview of the techniques that are being successfully used to enhance the radiation performance of on-chip antennas. Once the lossy substrate issue is resolved, it is important to address the challenges in AoC design phase, which include simulation and codesign issues, coupling and crosstalk between the AoC and circuit, layout restrictions, and fabrication-related problems. Accurate and proper characterization of fabricated AoCs is an extremely important step to not only validate the simulated results but also to assess their performance with application-based transceiver circuits. Finally, in order to create a good package design for AoC ICs, challenges such as proper choice of material and package dimensions must be considered. Hence, in order to design an efficient, compact, and high-performing antenna on the chip, these fundamental issues require innovative and ingenious solutions at the antenna level and the system level.

References [1] Cheema, H. M., and A. Shamim, “The Last Barrier: On-Chip Antennas,” IEEE Microwave Magazine, Vol. 14, No. 1, January 2013, pp. 79–91.



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[2] Babakhani, A., et al., “A 77-GHz Phased-Array Transceiver with On-Chip Antennas in Silicon: Receiver and Antennas,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 12, December 2006, pp. 2795–2806. [3] Mesa, F., C. di Nallo, and D. R. Jackson, “The Theory of Surface-Wave and Space-Wave Leaky-Mode Excitation on Microstrip Lines,” IEEE Transactions on Microwave Theory and Techniques, Vol. 47, No. 2, February 1999, pp. 207–215. [4] Marcuse, D., Theory of Dielectric Optical Waveguides, 2nd ed., New York: Academic Press, 2012. [5] Alexopoulos, N. G., P. B. Katehi, and D. B. Rutledge, “Substrate Optimization for Integrated Circuit Antennas,” IEEE Transactions on Microwave Theory and Techniques, Vol. 31, No. 7, 1983, pp. 550–557. [6] Kogelnik, H., “Theory of Dielectric Waveguides,” in Integrated Optics, Vol. 7, T. Tamir, (ed.), New York: Springer, 1975, pp. 13–81. [7] Rutledge, D. B., D. P. Neikirk, and D. P. Kasilingam, “Integrated-Circuit Antennas,” in Infrared and Millimeter Waves, Vol. 10, New York: Academic Press, 1983, pp. 1–90. [8] Marnat, L., et al., “New Movable Plate for Efficient Millimeter Wave Vertical on-Chip Antenna,” IEEE Transactions on Antennas and Propagation, Vol. 61, No. 4, April 2013, pp. 1608–1615. [9] Huang, K. -K., and D. D. Wentzloff, “A 60 GHz Antenna-Referenced Frequency-Locked Loop in 0.13 µm CMOS for Wireless Sensor Networks,” IEEE Journal of Solid-State Circuits, Vol. 46, No. 12, December 2011, pp. 2956–2965. [10] Ansys, “ANSYS HFSS: High Frequency Electromagnetic Field Simulation Software,” https://www.ansys.com/products/electronics/ansys-hfss. [11] “CST Studio Suite 3D EM Simulation and Analysis Software,” https://www.3ds.com/ products-services/simulia/products/cst-studio-suite/. [12] Cadence, “Computational Software for Intelligent System DesignTM,” https://www. cadence.com/en_US/home.html. [13] Keysight, “PathWave Advanced Design System (ADS) 2020,” https://www.keysight.com/ en/pd-2998595/pathwave-advanced-design-system-ads-2020?&cc=SA&lc=eng. [14] Abbas, K., Handbook of Digital CMOS Circuits, Technology, and Systems, New York: Springer Nature, 2020. [15] Edwards, J. M., and G. M. Rebeiz, “High-Efficiency Elliptical Slot Antennas with Quartz Superstrates for Silicon RFICs,” IEEE Transactions on Antennas and Propagation, Vol. 60, No. 11, November 2012, pp. 5010–5020. [16] Golcuk, F., O. D. Gurbuz, and G. M. Rebeiz, “A 0.39–0.44 THz 2x4 AmplifierQuadrupler Array with Peak EIRP of 3–4 dBm,” IEEE Transactions on Microwave Theory and Techniques, Vol. 61, No. 12, December 2013, pp. 4483–4491. [17] Hedayati, M. K., et al., “Challenges in On-Chip Antenna Design and Integration with RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems,” IEEE Access, Vol. 7, 2019, pp. 43190–43204.

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[18] Li, C. -H., et al., “A 340-GHz Heterodyne Receiver Front End in 40-nm CMOS for THz Biomedical Imaging Applications,” IEEE Transactions on Terahertz Science and Technology, Vol. 6, No. 4, July 2016, pp. 625–636. [19] Han, R., et al., “A 280-GHz Schottky Diode Detector in 130-nm Digital CMOS,” IEEE J. Solid-State Circuits, Vol. 46, No. 11, November 2011, pp. 2602–2612. [20] Seyyedesfahlan, M., and I. Tekin, “ACP Probe Measurement of On-Chip Strip Dipole Antennas at W Band,” IEEE Transactions on Antennas and Propagation, Vol. 64, No. 4, April 2016, pp. 1270–1278. [21] Klein, B., et al., “On-Chip Antenna Pattern Measurement Setup for 140 GHz to 220 GHz,” 2015 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB), October 2015, pp. 1–5. [22] Lin, C. -C., P. -Y. Lyu, and C. -C. Chang, “Experimental Investigation of Residual Substrate Effect in CMOS On-Chip Antenna Design,” 2018 Asia-Pacific Microwave Conference (APMC), November 2018, pp. 1085–1087. [23] Deng, T., and Y. P. Zhang, “On-Chip Antennas,” in Handbook of Antenna Technologies, Z. N. Chen, et al., (eds.), New York: Springer, 2016, pp. 1565–1584. [24] Caster, F., et al., “Design and Analysis of a W-Band 9-Element Imaging Array Receiver Using Spatial-Overlapping Super-Pixels in Silicon,” IEEE Journal of Solid-State Circuits, Vol. 49, No. 6, June 2014, pp. 1317–1332. [25] Mikkelsen, J. H., O. K. Jensen, and T. Larsen, “Measurement and Modeling of Coupling Effects of CMOS On-Chip Coplanar Inductors,” 2004 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Digest of Papers, September 2004, pp. 37–40. [26] Deng, T., Z. Chen, and Y. P. Zhang, “Coupling Mechanisms and Effects Between OnChip Antenna and Inductor or Coplanar Waveguide,” IEEE Transactions on Electron Devices, Vol. 60, No. 1, January 2013, pp. 20–27. [27] Ojefors, E., et al., “Monolithic Integration of a Folded Dipole Antenna with a 24GHz Receiver in SiGe HBT Technology,” IEEE Transactions on Microwave Theory and Techniques, Vol. 55, No. 7, July 2007, pp. 1467–1475. [28] Shamim, A., et al., “On-Chip Antenna: Practical Design and Characterization Considerations,” 2010 14th International Symposium on Antenna Technology and Applied Electromagnetics & the American Electromagnetics Conference, Ottawa, Ontario, Canada, July 2010, pp. 1–4. [29] Liu, D., (ed.), Advanced Millimeter-Wave Technologies: Antennas, Packaging and Circuits, New York: John Wiley & Sons, 2009. [30] MVG, “µ-Lab,” https://www.mvg-world.com/en/products/antenna-measurement/singleprobe-systems/m-lab. [31] Chen, Z. N., et al., (eds.), Handbook of Antenna Technologies, New York: Springer, 2016. [32] Ranvier, S., et al., “Compact 3-D On-Wafer Radiation Pattern Measurement System for 60 GHz Antennas,” Microwave and Optical Technology Letters, Vol. 51, No. 2, 2009, pp. 319–324.



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[33] Liu, Q., et al., “Improved Probing Reliability in Antenna-on-Chip Measurements,” IEEE Antennas and Wireless Propagation Letters, Vol. 17, No. 9, September 2018, pp. 1745–1749. [34] Seyyed-Esfahlan, M., et al., “SiGe Process Integrated On-Chip Dipole Antenna on FiniteSize Ground Plane,” IEEE Antennas and Wireless Propagation Letters, Vol. 12, 2013, pp. 1260–1263.

3 Radiation Enhancement and Measurement Techniques Conventional on-chip antennas have been plagued by poor radiation efficiency due in large part to the low resistivity and high dielectric constant of the silicon substrate. The low resistivity leads to losses in the substrate, and the high dielectric constant generates surface waves that distort the antenna’s radiation pattern, both of which are disastrous for the antenna’s radiation characteristics, especially in high-sensitivity applications. It is therefore quite natural that in order to enhance the radiation performance of AoCs, researchers have focused on tackling these issues and finding ingenious solutions to mitigate their impact. Efforts to that end include modifying the substrate properties to make it more antenna-friendly, adding on-chip and off-chip components that increase the gain and efficiency, and physically separating the antenna from the substrate. The techniques employed to enhance AoC gain and efficiency can be broadly classified into four main classes: 1. Substrate post-processing techniques: Modification of the properties and dimensions of the substrate below the antenna. 2. On-chip reflecting surfaces: Insertion of specialized structures in the metal layers below the antenna to isolate the lossy substrate as well as enhance the gain through in-phase reflections. 3. Off-chip techniques: Addition of superstrate layers, dielectric resonators, and focusing lenses on top of the antenna.

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4. 3-D and microelectromechanical systems (MEMS)-based AoCs: MEMS and radiators such as bond-wire antennas (BWAs) implemented as high-efficiency AoCs due to physical separation from the substrate. These methods, although they help in enhancing AoC performance, often come at a cost of compromising other characteristics of the on-chip circuit. For example, dielectric lenses that provide the highest gain improvement also result in a larger chip size. Radars and imaging detector ICs require longer range and high gain, so lenses and dielectric resonators are often employed compromising on chip size, whereas in the design of microscale implants and sensors, considerations need to be made to prioritize chip size over gain. Therefore, it is essential to adopt performance-enhancing techniques, keeping in mind the application requirements without unnecessarily trading off other performance parameters. A visual illustration of AoC gain enhancement is shown in Figure 3.1 and the subsequent sections discuss each technique in detail. Once a robust and efficient on-chip antenna is designed, its accurate characterization is equally important in achieving the desired end results. The previous chapter highlighted current challenges faced in AoC measurements using conventional setups. With the increasing demand of compact and highperforming systems, innovations in the field of millimeter-wave and terahertz AoC characterization have also seen an upsurge in the past few years. Specialized techniques and facilities have been introduced to tackle issues related to unwanted coupling, reflections, and mechanical obstructions in the way of onchip antenna measurement. An overview of these techniques is given in later sections.

Figure 3.1  Performance enhancement techniques of AoC: an overview.



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3.1  Substrate Post-Processing Techniques As discussed in the previous chapter, silicon’s low resistivity and high permittivity offer a highly lossy environment for on-chip radiators. Nonetheless, as silicon is the default preference for digital circuits and the most inexpensive option for large-scale integration, it must be altered in different ways to make it compatible to antenna design. This is done through post-processing techniques such as micromachining, thinning, and the use of high-resistivity substrates. These techniques modify the substrate either physically or chemically, leading to better antenna radiation. The next sections discuss each of these processes in detail. 3.1.1  Substrate Thinning

Substrate thinning, as the name suggests, is a process to reduce the thickness of the silicon substrate, which directly leads to a reduction in dielectric loss experienced by waves penetrating into the substrate. Moreover, substrate thinning also decreases the probability of surface wave excitation, leading to better antenna performance. To recognize the concept behind substrate thinning, it is important to understand why a thicker substrate leads to greater power attenuation. It is known that most of the power radiated by the antenna is coupled to the silicon substrate due to its high dielectric constant. This power is then attenuated in the form of heat or diffracted at the chip edges. The attenuation of EM waves in a dielectric substrate is given by:

P = P0e − δkz

(3.1)

where P0 is the initial power, δ is the loss angle, z is the propagation distance, and k = 2π/λ where λ is the wavelength in the dielectric material. The attenuation of a wave traveling in a dielectric is directly dependent on the propagation distance, and reducing this distance will, in turn, reduce loss. This is illustrated in Figure 3.2, which shows the gain and radiation efficiency of a 40-GHz dipole antenna on a silicon substrate whose thickness is varied from 0 to 600 μm. A resonant frequency of 40 GHz ensures that no higher-order substrate modes are generated at the investigated thickness values, allowing the examination of substrate losses purely due to its conductivity. It can be seen from the plot that a thicker substrate results in lower gain and radiation efficiency of the antenna. Hence, substrate thinning minimizes the path length through which the waves travel inside the low-resistivity silicon substrate, thereby reducing loss. Substrate thickness also plays a primary role in the excitation of surface waves leading to the distortion of the AoC’s radiation pattern. These waves are formed when the energy radiated by the antenna couples to the transverse electric (TE) and the transverse magnetic (TM) modes of the dielectric slab,

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Figure 3.2  Gain and radiation efficiency of dipole antenna with varying substrate thickness (εr = 11.9, f = 40 GHz).

whose intensity increases as the height and/or the permittivity of the substrate increases. The relation between the substrate thickness h and the number of TE and TM modes n for a given cutoff frequency fc in an ungrounded or grounded substrate is given by:

hungrounded =

 n = 1,2,3,….. for TE nc , 2 f c εr − 1  n = 1,2,3,….. for TM

(3.2)



hgrounded =

nc 4 f c εr − 1

 n = 1,3,5,….. for TE ,  n = 0,2, 4,….. for TM

(3.3)

where c is the speed of light and εr is the dielectric constant of the substrate. It can be seen that a grounded substrate supports the even TM modes and the odd TE modes. Moreover, the TM0 mode will always exist in the substrate, irrespective of the thickness. With the onset of higher-order modes, more energy is diverted into surface waves and the radiation efficiency of the antenna decreases. As discussed in the previous chapter, care should be taken in selecting substrate thickness, so that, ideally, no higher-order modes can be excited. There are four commercially used wafer-thinning methods: (1) mechanical grinding, (2) chemical-mechanical planarization (CMP), (3) wet etching, and (4) dry chemical etching through atmospheric downstream plasma (ADP DCE) [1]. These four methods fall into two distinct groups: mechanical and etching. In the mechanical category, a grinding wheel or chemical abrasive



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slurries are used to remove substrate material, as shown in Figure 3.3. CMP provides near perfect planarization compared to mechanical grinding but it is more costly and less clean. Etching techniques utilize chemical etchants to thin the substrate. Wet etching uses liquid chemicals, or etchants, to remove material from a wafer; however, it is more useful in situations where only portions of the wafer need to be thinned. ADP DCE is the newest wafer-thinning technique and uses either plasma or etchant gases or a combination of both to remove material. Specialized commercial methods to produce ultrathin chips have also been introduced in which a thin Si membrane is attached to conventional bulk silicon wafers using vertical silicon micro-anchors, which are controllably fractured at the end to enable detachment of thin chips [2]. Typical silicon thicknesses for CMOS processes range from 300 to 500 μm. Although substrate thinning has become a standard post-processing step in most AoC designs, it must be done keeping in mind the mechanical requirements and the fabrication and post-processing facilities. In [3], it was experimentally verified that decreasing the thickness of a low-resistivity silicon substrate from 670 to 100 μm improved the transmission gain between onchip antennas by nearly 10 dB. In [4], a 60-GHz frequency-modulated continuous-wave (FMCW) radar was fabricated on a grounded silicon chip that was thinned down to 200 μm such that only TE0 and TM0 were excited. These modes were then suppressed using carefully positioned on-chip metal plates. In [5], a dual-band, MEMS-based antenna was designed on a 500-μm-thick silicon wafer that was then back-etched with deep reactive ion etching to achieve a final thickness of about 200 μm. In another example, a lens-coupled AoC used in a 77-GHz phased array employed a substrate thinned down to 100 μm to minimize the path length through which the radiated wave travels inside the lossy doped substrate [6]. Substrate thinning is a fairly simple technique to control dielectric and surface-wave losses; however, its use is highly dependent on fabrication restrictions and foundry requirements. Thinning can be done to a certain extent keeping in consideration the mechanical stress and reliability issues of the chip.

Figure 3.3  Substrate thinning through the grinding of the processed wafer.

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3.1.2  High-Resistivity Substrates

The loss induced due to low resistivity of silicon substrates has been discussed thoroughly in the previous chapter. While substrate thinning can decrease this loss to some extent, it is not completely eliminated and causes attenuation of any radiation trapped inside. In order to minimize this loss to a higher extent, the issue must be nipped in the bud (i.e., the resistivity of the substrate must be increased). High-resistivity silicon substrates are available as a process option in addition to the standard low-resistivity wafers by many semiconductor manufacturers, thus facilitating the design of on-chip antennas with reduced substrate losses [7]. One of the methods used to increase substrate resistivity is ion implantation. In this process, high-energy ions (≈4 to 20 MeV) are extracted from plasma and are bombarded on a wafer placed in a vacuum chamber, thereby increasing its resistivity from the standard 10 Ω cm to nearly 106 Ω cm [8]. When high-energy protons are injected into a predominantly n-type silicon substrate, the ratio of minority carriers (holes) is increased, causing a greater resistance to the flow of electrons, thus increasing resistivity. Although many high-resistivity substrates are commercially available, their use limits the efficiency of active devices by introducing latch-up. In some works, ion implantation has been done in specific areas on the chip so that the active circuits are not affected. In this approach, ion implantation is carried out after chip fabrication to prevent any modifications to the standard CMOS process. The active areas of the chip are masked to protect transistors and windows in the mask allow ion bombardment in selected areas as shown in Figure 3.4. In this way, the substrate resistivity can be increased in areas underneath

Figure 3.4  Ion irradiation process to create a local, semi-insulated, high-resistive region in silicon substrate. A mask layer is used to cover active areas from exposure.



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the antenna while the rest of the circuit remains unaffected. This approach was demonstrated by [8] where the silicon substrate was irradiated with approximately 4-MeV protons using a 4-μm-thick masking layer. A monopole antenna fabricated on the irradiated chip area showed a gain enhancement of nearly 6.7 dB compared to standard silicon. In a similar process, the use of helium-3 ion bombardment showed a nearly 3-dB gain improvement in a 60-GHz on-chip dipole antenna on 65-nm CMOS technology [9]. Implantation using helium-3 is observed to show higher irradiation efficiency compared to proton implantation with lesser time and ion dosage required to achieve the same results [9]. The use of high-resistivity silicon substrates can permit antenna design with lower substrate loss; however, on-chip antennas are still predominantly designed using low-resistivity silicon substrates. This is due to multiple reasons. First, the goal of AoC technology is to implement antennas on the same substrate as the rest of the ICs. As mainstream IC design is done on standard silicon wafers (1 to 15 Ω-cm) to prevent latch-up issues and provide greater integration density, introducing a separate technology only for efficient antenna integration may be cost-prohibitive. Second, utilization of high-resistivity substrates precludes fabrication in low-cost technologies, which is a selling point of AoC integration. Moreover, selective ion implantation requires specialized processes that generally are not CMOS-compatible and lead to increased post-processing costs. Third, while high-resistivity substrates minimize dielectric loss, they do not provide a solution to the high dielectric constant of silicon, which is the source of surface waves. Despite the above-mentioned hurdles, as the popularity of on-chip antennas grows, it can be expected from foundries to tailor their processes, providing options of high-resistivity areas on the chip that could be designated for antennas and other RF components. 3.1.3  Substrate Micromachining

Micromachining is defined as the removal of part of a substrate or thin film using etching techniques in order to create micromechanical structures. When applied in areas beneath on-chip antennas, micromachining can create a physical separation between the antenna and the high-permittivity substrate. The absence of silicon substrate directly below the antenna greatly reduces dielectric loss and improves radiation efficiency. Because the antenna does not radiate into the substrate, the excitation of unwanted surface waves and its associated losses are also prevented. Furthermore, due to a mixture of air and silicon under the antenna, the effective relative permittivity of cavity decreases from 11.9 to a much lower value referred to as synthesized dielectric constant εcavity. Using quasi-static analysis and assuming the two dialectics (air and silicon) as a series combination of two capacitors, the synthesized dielectric constant of a patch antenna is derived as [10]:

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εcavity =

εair εsub εair + ( εsub − εair )x air

(3.4)

where εsub and εair denote the dielectric constants of the substrate and the air cavity, respectively, and xair is the cavity thickness ratio (xair = tair/t). As seen from Figure 3.5, xair is the ratio of the thickness of air cavity and the total substrate thickness. As depicted from (3.4), a greater amount of substrate removal will lead to a lower value of dielectric constant allowing the antenna to radiate more efficiently into the air, albeit with an increase in its required dimensions. This is illustrated in Figure 3.6, which shows the synthesized dielectric constant and the length of a 20-GHz micromachined patch antenna against the cavity thickness ratio. The size of the patch antenna is observed to increase with a greater amount of micromachining, which also leads to increasing fragility due to mechanical and fabrication stress. There are two ways to fabricate micromachining: surface and bulk micromachining. Surface micromachining is an additive process in which structural layers are added on top of the existing substrate. The process uses sacrificial layers, which are added to support the formation of suspended printed conductors and are later removed, as shown illustrated in Figure 3.7. Bulk micromachining shown in Figure 3.5 is performed by selectively removing part of the substrate, usually through wet or dry backside etching. In the wet etching, a silicon wafer is submerged in a chemical liquid to create cavities with slanted walls, whereas in dry etching, the wafer is bombarded with plasma ions to create cavities with vertical walls. A combination of surface and bulk micromachining is commonly used to form membrane-suspended antennas with cavities underneath. One of the earliest implementations of micromachined antennas was done by [11] in 1997. Closely spaced periodic holes were etched underneath a microstrip antenna on a high dielectric constant substrate (εr = 10.8) to synthesize a localized environment with a much lower dielectric constant (εr = 2.3). By doing so, the radiation efficiency of the antenna was increased from 48% to nearly 73%. Later in 1998, Papapolymerou et al. [10] proposed to remove

Figure 3.5  Bulk micromachining done to create an air cavity below an on-chip antenna.�



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Figure 3.6  Plot of the synthesized dielectric constant and antenna length versus the cavity thickness ratio (percent) for the silicon micromachined patch antenna at 20 GHz.

Figure 3.7  Surface micromachining done to create suspended antennas.

a bulk of material from under the antenna using selective etching techniques. With the dielectric constant reduced to εr = 2.3 from 11.9, the radiation efficiency of the patch showed an increase of nearly 28% but at the cost of a nearly 50% increase in antenna size. With the concept of radiation improvement through micromachining fortified, it has been applied to many different antenna topologies over the years. A loop antenna with membrane-covered trenches designed in [12] was able to house active components within the loop without significant degradation in the performance of either the antenna or the circuit. The antenna is shown in Figure 3.8 and uses a combination of surface and bulk micromachining since the deposition of membrane layers on top of the substrate is accompanied by backside etching. The designed AoC reported a 1-dBi gain at 24 GHz, which was a 5-dB improvement over an antenna without micromachined trenches. Micromachined dipole antennas were designed for a multiple-input multiple-output (MIMO)-based radar sensor with selectively etched cavities

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Figure 3.8  Micromachined loop antenna at 24 GHz: (a) top side and (b) cross-section [12].

that maintain mechanical stability [13]. Shown in Figure 3.9(a), the antennas achieved a gain of 3 to 5 dBi. Similarly, a Yagi-Uda antenna with localized backside etching was designed for end-fire radiation as seen in Figure 3.9(b) and achieved a 5-dBi peak gain with nearly 76% efficiency [14]. Efforts were made to ensure that the micromachining was done in such a way as to not interfere with the end-fire radiation of the antenna. Micromachining techniques offer a good approach to rid the antenna of the silicon substrate but come at a cost of complicated, time-consuming, and costly post-processing steps. It is not a mainstream technique and requires many additional steps. Moreover, micromachined antennas are often fragile and therefore require adequate packaging to survive normal handling.



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Figure 3.9  (a) Micromachined dipole antennas in MIMO-based radar sensor [13], and (b) micromachined Yagi-Uda antenna with end-fire radiation [14].

3.2  On-Chip Reflecting Surfaces In order to make AoC mainstream, its implementation must become inexpensive. This implies that, besides substrate compatibility, the antennas must be fabricated using the already available conductor and dielectric layers in modern silicon technologies. An ideal solution would utilize the options available on a standard CMOS process, with minimal or no post-processing at all, thereby reducing the costs. To achieve this goal, research on utilizing various embedded reflecting surfaces to aid the radiation of the AoC has been actively explored and will be discussed in this section.

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The most straightforward method to increase antenna gain through reflectors is the use of a perfect electric conductor (PEC) surface as a reflector below the antenna. Metals with electric conductivities in the range of 107 – 108 S/m and are good approximations of PECs, especially in their utilization as ground planes for antenna applications. According to image theory, when a vertical current-carrying antenna is placed over a PEC ground plane, image currents are induced. These image currents have the same direction as the original currents on the antenna and therefore enhance antenna radiation. However, designing a vertical on-chip antenna is not possible because, in a typical CMOS stack-up, the allowable metal thickness is restricted to a few microns. Moreover, on-chip antennas are mostly planar and have to be placed horizontally above the PEC surface to maintain CMOS compatibility and a low profile. In the case of a horizontal antenna, the image currents formed are opposite in direction to the original currents and, as a result, cancel out the radiation of the antenna. Now consider a perfect magnetic conductor (PMC) surface in place of a PEC; a horizontal antenna placed over it exhibits image currents in the same direction as the original currents and therefore aids the radiation. In other words, the radiation reflected from the PMC has a 0° phase difference compared to the waves radiated from the antenna. Table 3.1 summarizes the different antennareflector configurations discussed above and their effects on radiation and the profile of the antenna. Unfortunately, PMC materials are nonphysical and do not exist in nature due to the absence of free magnetic charges. Yet, in recent years, technologies have been developed to synthesize materials that exhibit unique EM properties and have gained the attention of both academia and industry. When these materials interact with EM waves, they exhibit some unique characteristics and phenomena that can be used to control and optimize the performance of RF devices, especially antennas. These materials, named metamaterials, do not exist in nature, but can be artificially synthesized. Metamaterial surfaces behave Table 3.1 Comparison of PEC and PMC for Use in AoC Designs Reflector Surface PEC Antenna Vertical Orientation Image Currents

Radiation Yes Enhancement Antenna Profile High

Horizontal

PMC Vertical

Horizontal

No

No

Yes

Low

High

Low



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as PMCs only over a limited frequency range, and this limited range is often referred to as bandgap. Over the years, a number of terms have been coined to describe these materials, for example, frequency-selective surfaces (FSS), artificial magnetic conductors (AMCs), high-impedance surfaces (HIS), and partially reflective surfaces (PRS). The presence of so many terms to describe more or less the same phenomenon can be explained by the fact that numerous independent groups in the scientific community were working on this idea and have viewed it from different perspectives. For convenience of the reader, these surfaces will be referred to as AMCs in this book, which is the term most often adopted in the AoC design community. It will also be shown how each of the terms essentially points to different characteristics of the same surface. 3.2.1   AMCs

The first AMC was designed in 1999 and was composed of periodic square patches connected to a grounded substrate through metallic vias that constituted a mushroom-like structure as shown in Figure 3.10(a) [15]. When an EM wave was incident on this AMC, it would mimic the behavior of a PMC surface by reflecting the wave with a 0° phase difference and adding to the original radiation of the antenna. This operation of the AMC was possible only over a specific frequency bandwidth, making them frequency selective surfaces. Surface-wave impedance is an important parameter in describing the behavior of AMCs. By modeling the mushroom AMC as a lumped parallel LC circuit, its surface impedance can be approximated by:

Zs =

j ωL 1 − ω2LC

(3.5)

The capacitance is primarily due to the fringing fields between adjacent metal elements while the inductance is attributed to the thin grounded dielectric. At the resonant frequency (Zs = 1/√LC), the surface impedance becomes infinite and the AMC surface acts as an open circuit to incoming radiation, earning it the name, high impedance surface. The AMC causes the incident radiation to reflect with a 0° phase difference, which then added constructively to the main radiation of the antenna, thereby boosting its gain. The vias used in the mushroom-type AMC were difficult to fabricate at millimeter-wave frequencies, so planar AMC configurations, or partially reflective surfaces, were introduced in which slotted metal sheets were fabricated as an array of periodic patches or slots as shown in Figure 3.10(b). The operation of planar (via-less) AMCs can be illustrated by a simple ray optical model, which is treated in detail in [16]. As shown in Figure 3.11, a radiating source is placed above the cavity formed by the PRS and a PEC. In AoC terms, this

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Figure 3.10  Types of AMC surfaces: (a) mushroom-like AMC surface and (b) partially reflective surfaces with square patches and wire slots.

translates into the antenna being placed in the top metal layers, while the PRS and ground plane are in the lower metal layers. This combination of the PRS and the ground plane realizes an AMC structure that prevents the radiation from traveling into the high-resistivity silicon. The waves radiated towards the PRS are reflected back from the ground plane with phase ϕ2 while the waves radiated into air have a phase of ϕ1. Following the paths of the direct and reflected radiations and taking into account the various phase shifts introduced to them, the resonance condition of the cavity can be derived. The PEC introduces a phase shift of π while the PRS introduces a phase shift of ϕt , equal to the phase of its transmission coefficient, which, in turn, is a function of its geometry. If



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Figure 3.11  Optical ray model showing in-phase reflection in planar AMCs.

the phase difference between the direct and reflected waves is ϕ2– ϕ1, the resonance or in-phase condition can be derived as [16]:

φ2 − φ1 = 2 × φt −

2π (2S ) − π = 2 πN N = 0,1,2,…. λ

(3.6)

where S is the spacing between the PRS and the ground plane. This resonant cavity formed by a properly designed PRS and ground plane behaves as a PMC and reflects normal incident waves with zero phase shift. Consequently, placing a simple point source in close proximity to the PRS would result in constructive interference between direct and reflected waves at the cavity resonance. This inphase reflection is the fundamental concept behind antenna gain enhancement due to planar AMC surfaces. A typical AMC surface is shown in Figure 3.12 and consists of specially designed metal-dielectric periodic structures over a ground plane. The operation of an AMC surface is primarily controlled by three important factors: (1) the thickness and the electrical properties of the substrate between the periodic structure and the ground plane, (2) the size of the AMC surface (number of unit cells), and (3) the geometry of the AMC unit cell. Of the three, the substrate thickness is not in the designer’s control and is typically fixed by the CMOS stack-up. Secondly, in theory, an infinite AMC surface would be the closest thing to a PMC; however, the AMC surface size is always restricted by the finite chip size. Therefore, the designer has to make a reasonable compromise between the number of unit cells and limited chip size. This leaves the dimensions and shape of the AMC unit cell as the only parameter that can be fully controlled by the designer to achieve an optimized design. AMC unit cells can be realized in a variety of shapes ranging from simple square patches to complex Jerusalem cross-structures as shown in Figure 3.12(b). When the spacing and dimensions of the unit cells are sufficiently small compared with the free-space wavelength of the antenna, the structure can be assumed to be

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Figure 3.12  (a) Square patch-based AMC surface in a typical CMOS stack-up, and (b) commonly used unit cell geometries.

a homogeneous surface, described by the its surface impedance. Theoretically, the unit cell spacing and dimensions can be tuned to make the AMC resonate at the desired frequency yielding a very high surface impedance over the operating range. The in-phase reflection condition of an AMC can be realized by placing the ground plane below the silicon substrate or directly beneath the PRS in the bottom metal layers of the stack-up. In the former scenario, as shown in Figure 3.13(a), the increased distance between the PRS and the ground plane ensures in-phase reflection and the designer has a greater degree of freedom in optimizing this distance by varying substrate thickness. However, in this case, surface waves can still be excited in the silicon substrate, as the PRS layer acts only as a reflector and not as a shield. An example of such an AMC integration was presented in [17], where a Jerusalem cross AMC was designed in the bottom metal layer (M1) with the ground plane below the substrate. The AMC layer helped improve the gain and efficiency of the antenna by 5 dB and 10%, respectively. However, the absence of a ground plane below the antenna caused the excitation of surface waves in the substrate, resulting in a low radiation efficiency of only 15%. In the second configuration, the ground plane is placed on the bottom metal layer (i.e., M1), while the AMC is placed in one of the upper metal layers, as shown in Figure 3.13(b). This configuration prevents the excitation of



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Figure 3.13  AMC ground plane locations: (a) below substrate, and (b) in bottom metal layers.

surface waves, but due to the extremely small thickness of the silicon dioxide layer in the CMOS stack-up, in-phase reflection is very difficult to achieve. Therefore, it is very challenging to realize an AMC and a ground plane above the substrate for frequencies below 100 GHz or so. There are some works that have successfully integrated an AMC using this configuration, but it is done through customized in-house facilities that allow for the fabrication of thicker oxide layers [18]. For example, a square loop-shaped AMC surface shown in Figure 3.14 is used in the interlayers under a dipole AoC with the ground plane at M1 and improves the antenna gain by nearly 8 dB. Efforts are underway to design an AMC with the ground plane above the antenna that is compatible with the current CMOS processes. It is also possible to use the AMC surface as the primary radiator instead of a reflector. For example, in a 94-GHz design [19], the AMC layer, realized using the top two metal layers, serves as the antenna while the bottom metal layer constitutes the ground plane. AMC-based on-chip antennas are known to have lower gains than other enhancement techniques. The advantages of this method lie in its cost-effectiveness as the AMC layers are realized using the existing metal layers of the CMOS stack-up. This also means that AMC design has to follow the strict

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Figure 3.14  A 94-GHz dipole antenna with AMC using custom fabrication: (a) top view, (b) cross-section, and (c) side view of the fabricated prototype [18].

metal density rules set out by the foundry, which can sometimes limit their geometry. Moreover, AMCs do not require any costly post-processing steps and do not compromise on the size of the chip in any way.

3.3  Off-Chip Techniques The AoC technology was introduced to integrate the entire RFIC, including the antenna on a single chip and eliminate the need of any external components. However, when modifications to the substrate and on-chip components are not enough to achieve the desired radiation performance, the antenna designer has to resort to off-chip techniques in order to satisfy design requirements. This includes placement of dielectric superstrates on top of the antenna, dielectric resonator loading, and lens integrated antennas. A substantial increase in the gain and in some cases radiation efficiency of the AoC has been observed through the use of off-chip methods, but the inclusion of components such as dielectric resonators and lenses to the chip considerably adds to the system size. Hence, a trade-off exists between achieving higher gain and making the system more compact. Efforts have also been made to integrate lenses and superstrates into the packaging of the chip to attain additional package functionality and



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protection. The following sections give a comprehensive overview of the various techniques that use off-chip components. 3.3.1  Dielectric Superstrates

The characteristics of printed antennas with superstrate layers were first studied in the early 1980s. It was demonstrated that by properly choosing superstrate parameters, a significant increase in gain, radiation resistance, and efficiency of the antenna could be achieved [20]. This was known as the resonance gain method and it was possible using superstrates with either relative permeability μr >>1 or relative permittivity εr >>1. When the superstrate thickness and the antenna position are chosen correctly, a resonance condition is created, whereby gain and radiation resistance of the antenna are significantly improved. Over time, many superstrate configurations have been developed such as dielectric slabs, EM bandgap structures, and HIS. However, the simplest technique is to deposit a layer of unpatterned dielectric on top of the antenna as shown in Figure 3.15. This technique has been utilized to enhance gains of on-chip antennas and has shown considerable potential. Superstrate layers used in AoC designs are generally made using quartz; however, any low loss dielectric material with εr between 3 and 12 can be used for this purpose. The thickness of the superstrate layer plays an important part in achieving the resonance condition. It has been demonstrated that best antenna performance is obtained when this thickness is selected as λd /4 where λd is the guide wavelength. This enables the superstrate to act as an impedance transformer and provide better coupling from the antenna to the free space. In terms of the transmission-line equivalence, the antenna will exhibit better radiation when the thickness is nλd /4 where n = 1, 3, 5, .... However, it has been observed that when n > 1 the superstrate layer becomes too thick, resulting in surface-wave excitation and consequent degradation of the radiation pattern. This can be understood by Figure 3.16, which shows the power coupled to surface waves in a quartz superstrate (PSS) when its thickness (hSS) is varied from 0 to 1,600 μm at 94 GHz. The coupled power is minimum (≈26%) when hSS is equal to a quarter of the wavelength and the onset of higher-order modes causes it to

Figure 3.15  Printed antenna loaded with superstrate.

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Antenna-on-Chip: Design, Challenges, and Opportunities

Figure 3.16  Ratio of power coupled to the substrate with varying superstrate height for εr = 4 and f = 94 GHz [21].

increase dramatically for thicker substrates. So even though the resonance condition occurs again at odd multiples of the quarter-wavelength thickness, it is shadowed by the power lost in the superstrate. It is also important to note that the above discussion pertains to the surface waves generated in the superstrate, while the loss induced due to surface waves excited in the substrate must be tackled separately. Hence, the thickness of both the substrate and superstrate must be optimized for best performance. One of the earliest implementations of a single-layer superstrate with an AoC was done in 2012 and was able to improve an AoC’s performance by 4 dB [21]. In this design, a 400-μm (≈λd /4) quartz superstrate without any metal patterns was loaded directly on top of an elliptical slot antenna. Figure 3.17 shows an exploded visual representation of the superstrate-loaded AoC. The AoC was designed for 89 GHz but could be easily optimized for frequencies above 100 GHz due to the electrically thick superstrate layer. Other examples include superstrate loading for on-chip antennas integrated with phased array transmitters [22] and imaging detectors [23] showing gain enhancement of nearly 3.1 and 6.8 dB, respectively. Another way of utilizing superstrates is to print the antenna directly on top of it and excite it through EM coupling using on-chip feed lines as shown in Figure 3.18 [24]. In this way, the superstrate layer not only provides a gain boost but also increases the separation between the antenna and the ground that is otherwise limited to the process-defined oxide thickness. Feed lines are typically present in the top metal layer of the stack-up. In theory, a thinner superstrate layer with a high dielectric constant will allow optimum coupling, but a higher dielectric constant will also cause more power to be lost through surface waves. Therefore, an optimized superstrate er and thickness need to be selected to ensure maximum coupling with minimum loss. This concept has also been extended to design on-chip phased arrays [25].



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Figure 3.17  Stack-up for on-chip elliptical slot antenna with a quartz superstrate for improved efficiency [21].

Figure 3.18  EM-coupled microstrip and slot-ring implemented on top of the superstrate [24].

Dielectric loading provides a cheap and convenient alternative to other AoC radiation enhancement techniques. It does not require a complex design, with the only parameters to consider being superstrate thickness and antenna position. The properties of superstrates make them a desirable part of the antenna as well as a protective layer. One major challenge of this method is that any misalignment between the superstrate and the antenna can cause degradation in the radiation efficiency. Another major disadvantage is the generation of surface waves in the superstrate, which can degrade its performance. Also, because the superstrate is designed on top of the AoC, the problem of surfacewave excitation and the resulting power loss remains unsolved. A solution to the former challenges of alignment and surface-wave loss in the superstrate is

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the introduction of specially designed patterned superstrates discussed in the next section. 3.3.2  Artificial Dielectric Layers

Artificial dielectrics are man-made materials with subwavelength metal particles periodically embedded in a uniform host material. They were introduced in the late 1940s as a lightweight alternative to real dielectric materials for use in microwave lenses [26] and are essentially identical to the electric metamaterials in the current terminology. The term “artificial dielectrics” came into use because they serve as the macroscopic analogs of natural dielectrics with the atoms or molecules being emulated by artificially constructed materials. The conductors respond to an EM field like atoms and molecules in natural materials, and the artificial dielectric layer (ADL) behaves much like dielectrics with an engineered dielectric constant. By specifying the dimensions and spacing of the metal shapes, the ADLs can be used to refract and diffract EM waves, making them useful in the design of lenses, diffraction gratings, mirrors, and polarizers for microwave devices. An artificial dielectric is conceptualized in Figure 3.19. The working principle of ADLs is that when an EM field is incident on the periodic conducting structures, it is scattered and this scattered field then adds into the incident field, creating an equivalent delay. Thus, the overall field can be seen as an EM wave propagating in a different homogeneous material with different electric and magnetic properties (as compared to the original host material). The effective electric parameters of ADLs can be engineered by varying the size and spatial density of the conducting structures. This allows designers to synthesize ADLs with very high equivalent permittivity (εr,eff > 30), enabling high-efficiency radiation compared to real dielectrics. Recently, ADLs have found a new application as superstrates to improve the radiation performance of planar AoC in the microwave and terahertz frequency range. Conventional dielectric superstrates, as discussed in the previous section, are able to boost gain but have the inherent disadvantage of surface waves originating in the superstrate material. ADLs provide a solution to this

Figure 3.19  ADL structure acts as an equivalent anisotropic medium.



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problem in the form of their anisotropic nature. Due to the planar arrangement of periodic metal structures, the electrical properties of ADLs become dependent on the polarization and direction of incident EM waves. This means that EM waves that are incident on the ADL at different angles do not encounter the same dielectric constant εrADL. For instance, the maximum value of the dielectric constant of the ADL will only be visible to EM waves that are orthogonal to the planar conducting structures and it will decrease as the angle of the incidence starts to increase. This phenomenon is illustrated in Figure 3.20 for better understanding. In a bare dielectric slab used as a superstrate above the antenna, the radiated waves undergo internal reflection giving rise to surface waves. In an ADL superstrate, the waves incident at an angle on the patterned surfaces see a decreased value of the dielectric constant, which increases the critical angle and reduces the probability of total internal reflection. This results in a majority of the wave being radiated out into the air and the gain of the antenna is enhanced. So far there have been very few implementations of ADLs as AoC superstrates. ADLs are useful in enhancing the front-to-back ratio of AoCs and do not have the risk of surface-wave excitation, with a consequent increase in gain and efficiency. A conventional double-slot antenna loaded with an ADL superstrate was designed and characterized in 2015 and showed an almost 2-dB increase in gain at 300 GHz [27]. The ADL was fabricated in an in-house CMOS process using silicon dioxide (εr = 4) as the host material and pure aluminum for the metal structures. As shown in Figure 3.21, the ADL was implemented

Figure 3.20  Radiation of antenna in: (a) a bare dielectric slab and (b) an ADL slab.

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Antenna-on-Chip: Design, Challenges, and Opportunities

Figure 3.21  Exploded view of the slot antenna loaded by an ADL superstrate (only three layers of ADL have been shown) [27].

on top of the AoC as a stack of 7 layers with a 5-μm vertical separation resulting in an effective dielectric constant of (εr eff  = 32). The anisotropic properties of the designed artificial slab allow the antenna to have a front-to-back ratio larger than 10 dB, with essentially no power lost into surface waves. This is due to the fact that the ADL is dense and electrically thick for waves radiated by the slot in directions close to the normal, whereas it exhibits lower permittivity and is electrically thin for the waves radiated in directions almost parallel to the slab. Artificial dielectrics can be designed and manufactured independently from the antenna and the integrated circuits and can be used as add-on components because no alignment is required between the antenna and the superstrate layers. They offer a broadband response because of their nonresonant periodic nature. This concept is highly desirable for a number of on-chip radiating structures, including antenna arrays. ADLs are a relatively new concept in AoC design and are still in the research phase; they provide a promising option for AoC gain enhancement. 3.3.3  Dielectric Resonator Loading

Introduced in 1983, dielectric resonator antennas (DRAs) have become potential candidates to replace traditional radiating elements at high frequencies, especially for millimeter-wave and terahertz applications. This is because DRAs offer the advantages of smaller size, higher radiation efficiency, and wider bandwidth [28]. Due to the absence of conducting material, they do not suffer from conduction losses and are characterized by high-radiation efficiency when excited properly. This characteristic renders them very useful at higher frequencies in comparison to metallic antennas. Moreover, DRAs are also easy to be integrated with other active or passive circuit elements. DRAs are often integrated as a



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gain-enhancing feature in SoC designs with the feeding mechanism fabricated on the chip and the resonator placed on top of it. Using a suitable excitation technique, any dielectric structure can be used as a radiator at specified frequencies. The basic principle of operation of dielectric resonators is similar to cavity resonators. A feeding structure is used to introduce radio waves inside the dielectric radiator where they bounce back and forth, forming standing waves. These high-energy waves are then radiated from the walls of the radiator, giving the antenna a high gain and directivity. DRAs can be realized in many shapes, with cylindrical and rectangular ones being the most common. They are excited using a variety of feeding structures such as coaxial lines, microstrip lines, coplanar waveguides, aperture excitation, and conformal strip excitation. However, the fabrication of DRAs in the millimeterwave range is challenging, due to the small feature sizes. Any misalignment between the DRA and the feeding structure results in significant impedance mismatch and in efficiency degradation. There are two ways to design an on-chip DRA: (1) micromachining the DRA from the same wafer as the chip, and (2) hybrid integration of an external DRA on the chip. The first method can be considered a truly on-chip technique as no off-chip component is being attached. For example, in [29], a cylindrical DRA was micromachined from the silicon wafer using deep reactive ion etching (DRIE). A 675-μm wafer was etched to create the cylindrical DRA with a height of 400 μm, and the remaining 275 μm was used as the substrate. The antenna gain and radiation efficiency were reported to be 7 dBi and 79.35%. The CPW feeding network was fabricated on the unetched bottom side of the wafer. The simulated model and fabricated prototype of this design are shown in Figure 3.22. There are two advantages to this type of DRA design. First, because the dielectric resonator and the substrate are essentially part of the same wafer, there is minimum misalignment between the DRA and the feeding network. Second, the simplicity of the structure implies more mechanical stability and less fabrication costs compared to alternative millimeter-wave DRAs that require hybrid integration. Micromachining to create an on-chip antenna is a complicated procedure and very few designs have been reported. The more common method is to integrate an external dielectric resonator on top of the chip while the feeding network is fabricated using the top metal layers of the IC. The whole assembly with on-chip and off-chip components is often loosely termed as an AoC in the existing literature. However, as the DRA is essentially an external component constructed from a material different from the substrate, it is classified as an off-chip gain enhancement technique in this book. Off-chip DR loading has been utilized extensively in AoC designs to improve performance. A 340-GHz DRA with nearly 10-dBi gain and 80% radiation efficiency was reported in [30]. In this design, a cavity-backed on-chip

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Figure 3.22  Micromachined DRA operating at 60 GHz: (a) simulated model, top side; (b) cross-section; (c) fabricated prototype, top side; and (d) feeding network at bottom of the chip [29].

antenna was fabricated using a standard CMOS technology. Then, a low-permittivity supporter and a dielectric resonator were vertically stacked on the chip as shown in Figure 3.23(a), forming a 3-D Yagi-like antenna to further enhance the gain and radiation efficiency. The resonator was designed to operate at fundamental frequency by reducing its thickness to 100 μm. The use of a thin dielectric resonator is able to suppress higher-order modes and increase radiation efficiency, but this also makes it susceptible to damage during fabrication. Alternatively, thicker dielectric resonators that operate at higher-order modes can also be utilized but with a different set of properties. For example, a DRA also operating at 340 GHz and using an on-chip patch as a feeding structure was presented in [31] with nearly similar gain and efficiency. However, this design (shown in Figure 3.23(b)) keeps the dielectric resonator thickness as 500 μm, which allows the excitation of higher-order modes to increase the antenna’s directivity but also induces higher losses. Advanced configurations of integrated dielectric resonators have also been fabricated. Multiple dielectric resonators were stacked on top of the antenna in [32] to achieve up to 11 dB of gain improvement. Dielectric resonators have also been developed for on-chip arrays where either a single or multiple dielectric resonators or multiple dielectric resonators could be used for each array element. Designing individual dielectric resonators for each array element is expensive and time-consuming and requires complex fabrication, especially at high frequencies where antenna elements are close together. A simpler solution



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Figure 3.23  On-chip DRAs at 340 GHz utilizing: (a) the fundamental mode [30], and (b) the higher-order mode radiation [31].

was used by [33] where a single dielectric resonator structure was used to cover the entire array and the gain was improved by nearly 8 dB. DRAs offer a low-cost solution to increase the radiation performance of AoCs. They are easy to design and integrate with on-chip circuits and offer

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design flexibility through to a number of feeding mechanisms, shapes, and sizes. The major issues in on-chip DRA design are misalignment between the dielectric resonator and the feeding antenna and the proper fabrication of the dielectric resonator shape, both of which, if not done accurately, cause degradation in the antenna’s performance. 3.3.4  Dielectric Lens

The utilization of optical methods has always been a popular feature of microwave antenna designs. The concept of integrated lenses began with single-material hemispherical lenses placed on top of IC antennas to eliminate substrate modes and increase radiation efficiency [34]. Today, dielectric lens loading is the most widely used method for performance enhancement of on-chip antennas in receivers and imaging systems and provides considerably higher gain improvement compared to most other techniques. A lens bends the rays radiated by the integrated antenna towards the broadside direction as illustrated in Figure 3.24, thereupon sharpening the pattern and effectively increasing the gain. When used on the backside of the chip, it suppresses the excitation of unwanted surface waves. Dielectric lenses also act as an excellent heat sink and can be a useful part of chip packaging. Lenses are designed and fabricated according to the antenna’s frequency of operation and are then either glued on to the IC containing the AoC with the help of an adhesive material or attached with the help of posts. The design considerations of a lens-coupled antenna system can be split into two categories: the design of the lens itself, and the design of its assembly on the chip. In the design of the lens, the shape, size, and material of the lens are primary concerns. Silicon and Teflon are the materials commonly used to fabricate dielectric lenses while their exact shape and size are dictated by the antenna’s operating frequency as well as the application requirements. Lenses can be realized in a number of shapes but the most commonly used are hemispherical, hyper-hemispherical, and extended lenses. These are particularly attractive

Figure 3.24  Lens integrated antenna with various types of lenses.



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for antenna applications because they are aplanatic (i.e., adding no spherical aberration or coma). This implies that if an optical system is designed such that all the rays are being focused at a point, the lens can be added to the system and all the rays will still focus to a point. The placement of the lens on the chip is very important in terms of the antenna’s radiation enhancement. Primarily, three configurations of lens assembly have been investigated: placing the lens at the bottom of the chip, aligning it at the top of the chip, and integrating it into the package. The first configuration displayed in Figure 3.25(a) makes use of backside radiation of the antenna. It is well documented that in bulk low-resistivity silicon, a major portion of antenna’s radiation is coupled into the substrate and only a tiny amount radiates into air. Attaching the lens to the backside of the chip makes use of this trapped radiation by efficiently coupling into the air. In order to eliminate any power lost at the substrate-lens interface, the lens is made of the same material as the substrate, hence giving it the name of substrate lens. Apart from gain improvement, the backside attachment of the lens also prevents the generation of unwanted surface waves. Surface waves are generated due to total internal reflection at the air-dielectric interface when the angle of incidence of the waves is greater than the critical angle. When the lens and the substrate have the same dielectric constant, most of the incident rays are nearly normal to the air-dielectric interface of the curved lens surface, minimizing total internal refection and thus suppressing the associated surface waves. The impedance mismatch at the lens-to-air transition also causes reflections, which degrade the antenna’s efficiency. A quarter-wavelength matching layer is often coated on top of the lens to minimize this mismatch. When attaching the lens to the backside of the chip, an intermediate dielectric layer can also be added to mitigate mismatch issues [35]. The thickness of this layer heavily effects the efficiency of the lens and must be optimized for best performance. Figure 3.25(a) shows a silicon lens integrated with the backside of a packaged chip using a thermally conductive adhesive [36].The lens-coupled antenna has a high gain of 16.7 dBi and a radiation efficiency of 86.4%. Another such lens assembly was reported in [6] and exhibited a gain improvement of more than 10 dB. The interesting thing about this design was that the antenna was fabricated using the lower metal layers of the CMOS stack-up to reduce its distance to the substrate. In the second configuration, the dielectric lens is placed on top of the antenna at a certain distance, which is typically one focal length. In such an arrangement, an air cavity is created between the lens and the antenna as shown in Figure 3.25(b). One such assembly was reported in [37], but the antenna displayed a gain of only −1 dB due to the power lost in the substrate. Because the majority of the radiated power is confined to the substrate, unless there is a mechanism to reroute this power into the air, it is not possible to achieve a high

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Figure 3.25  AoC lens configurations: (a) silicon hemispherical lens attached to the backside of 120-GHz IC [36], (b) extended-hemispherical lens placed at the boresight of the antenna [37], and (c) Fresnel lens integrated as part of the packaging layer of 70-GHz AoC [38].



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efficiency using a lens at the top. Moreover, front-side lens placement can incur additional losses due to the air gap between the chip and the lens and due to surface-wave excitation in the substrate. One rather obvious drawback of conventional dielectric lens attachment is its relatively larger size compared to the chip. This leads to the third configuration, which is relatively new and aims to reduce the size of the lens by integrating it into the package structure. In [38], a Fresnel lens was used to realize a functional package for a 71-GHz transmitter chip. A Fresnel lens is a phasecorrecting lens that consists of a set of planar grooved circular plates composed of a low-loss material. By selecting the material and dimensions of the lens, it can be used be used for effective beam-forming of the antenna’s radiation. As shown in Figure 3.25(c), the lens is placed at a height of 2.7 mm from the antenna to maintain the required focal length. It was demonstrated that the lens enhanced the antenna’s gain by almost 12 dB while also providing protection and stability as part of the system package. Due to its simple construction and robustness, the substrate lens approach has been extensively used in AoC applications such as sensing [39], spectroscopy [40], imaging [41], and radars [42]. In a distance sensor designed at 120 GHz [39], the addition of a lens to the system increased the antenna gain by nearly 20 dB, which is one of the highest reported gain improvements in AoCs. The potential downsides of this technique are the performance degradation due to antenna-lens misalignment, reflections due to lens-to-air transition, and the increase in system size and cost. However, in terms of antenna gain, dielectric lenses surpass most other performance enhancement techniques, which account for their widespread use in numerous millimeter-wave and terahertz applications. Efforts are also underway to incorporate lenses as a functional part of the chip package as they provide mechanical rigidity and thermal stability to the chip.

3.4  3-D and MEMS-Based Antennas One of the more exotic methods to reduce the loss induced by the lossy silicon substrate is to physically separate the antenna from it. This gives rise to the concept of 3-D antennas either using MEMS or wire-bonding methods for their fabrication. These technologies allow for suspended and vertical onchip antennas, which demonstrate significantly improved gain and efficiency. Although MEMS have been used to design and fabricate high-performance on-chip antennas, the process is not always CMOS-compatible. It is always important to ensure that the MEMS structures used in AoC design are made of the same material as the chip. Nowadays many commercial semiconductor processes allow direct integration of MEMS structures during the fabrication

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process, which has made the design of MEMS-based antennas relatively easier and cost-efficient. 3.4.1   Suspended Antennas

Planar antennas can be isolated from the lossy substrate by suspending them in the air by means of polymer MEMS structures such as pillars, cantilevers, and bridges. In the past, high-temperature silicon etching techniques were used, which were expensive and inefficient. Polymer processing is fast and costeffective and can be done at low temperatures (80 GHz). In 2010, self-assembled 3-D monopoles were introduced using MEMS technology [46]. The proposed technique enabled control over the length, angle, and curvature profile of the antennas. The designers used a multilayer structure composed of materials with different thermal expansion coefficients. As a result, the structure lifted through the residual stresses and tilted



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Figure 3.26  MEMS-based suspended antennas: (a) 60 GHz 2 × 1 elevated patch array [43], and (b) Ka-band elevated patch antenna [44].

the monopole at different angles with respect to the chip plane (Figure 3.27). While it provides considerable gain improvement, so far the vertical antenna approach has only been feasible for on-chip monopole fabrication.

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Figure 3.27  MEMS-based vertical antennas: (a) oblique (45°) and (b) straight [46].

3.4.3  Movable Antennas

MEMS-based structures and actuators can be used to add reconfigurability and flexibility to on-chip antennas. This concept was proposed in a movable AoC design in 2013 in which a metallic bowtie radiator was printed on a movable polyamide plate [5]. A buckled cantilever plate (BCP) was designed through post-processing of the polyamide layer on top of the silicon wafer. The cantilever allowed the antenna to be moved from planar horizontal to a vertical position through voltage or current actuation as shown in Figure 3.28(a,b). In the vertical position, the antenna is completely separated from the lossy substrate and its gain improves by 6.9 dB compared to the horizontal position. Moreover, significant improvement is observed in the radiation pattern as shown in Figure 3.28(c). The MEMS-based movable antenna concept can enable radiation pattern and polarization diversity as the same antenna can be in a vertical or horizontal position, thus changing the radiation pattern and polarization accordingly. This approach can also be extended to fabricate antennas, which can



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Figure 3.28  MEMS-based movable on-chip antenna concept: (a) moving mechanism with voltage/current actuators, (b) fabricated antenna in the vertical position, and (c) radiation pattern improvement [5].

be reconfigured to radiate in the broadside as well as end-fire directions. However, this approach to on-chip antenna design is still new and requires novel and complex design and fabrication processes. 3.4.4  Bond-Wire Antennas

BWAs were introduced almost a decade ago to counter the low-radiation challenges of planar on-chip antennas. While they may not be fully CMOScompatible, BWAs are often placed in the same category as on-chip antennas. They use standard wire-bonding techniques to form radiating structures and are generally cost-efficient for low-volume production. BWAs have a number

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of advantages over planar on-chip antennas including improved radiation efficiency (up to 90%) due to the absence of substrate coupling, capability to radiate horizontally, and area efficiency, as they require only a small space for attachment of the wire pad on the chip. On the downside, their fabrication requires post-processing of the finished chip and an increase in chip size. As an example, dipole and monopole antennas formed using this method are shown in Figure 3.29. The concept of BWAs were first introduced in the United States through a patent in 2004 [47]. Since then, a number of different antenna configurations have been developed. In 2009, a half-loop BWA, combined with 43-GHz transceivers to create a short-distance, high-speed communication link, was demonstrated [48]. The antenna exhibited a gain of 2 dBi along the axis of the loop. In the same year, a highly directional Yagi array in SiGe BiCMOS technology was reported [49]. It was fabricated using six conventional low-cost wire bonds constituting one driven element, one reflector, and four directors. The antenna was able to achieve a gain of nearly 8 dBi and a radiation efficiency of 82%.

Figure 3.29  BWAs: (a) dipole [50] and (b) monopole [51].



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Due to their 3-D nature, BWAs can be designed to exhibit end-fire and omnidirectional radiation, making them highly useful as on-chip interconnects [50, 51]. In 2017, the first omnidirectional on-chip antenna was designed using a wire-bonded monopole [51]. Compared to other BWAs, monopoles eliminate the need of additional counter pads on the chip surface that are otherwise required by dipoles and loops to connect the dangling edges of the AoC. This antenna showed a gain of 4.9 dBi and an efficiency of around 90%. It is also possible to fabricate circularly polarized antennas by proper arrangement and feeding of multiple bond wires. In a recently reported design, four radiating structures based on a Quadrifilar helix antenna were wire-bonded around a ground plane on the chip surface [52]. A power divider was used to excite the radiators with a 90° phase shift resulting in a circularly polarized radiation. Although most BWAs exhibit efficiencies higher than 90%, which is considerable for on-chip antennas, their drawbacks in terms of size and fabrication complexity cannot be ignored. First, bond wires can only be used to form a limited type of wire-based antennas such as the monopole, dipole, and Yagi. This precludes a number of other antenna types and seriously limits flexibility and reconfigurability in AoC design. Second, BWAs increase the chip form factor and their nonplanar nature also makes them prone to damage and reliability issues. Even at higher frequencies such as the sub-terahertz spectrum, BWA sizes are in the range of a few hundred micrometers, which is comparable to substrate thickness. For example, in [51], a bond-wire monopole designed for 200 GHz exhibited a length of 435 μm, while the typical substrate thickness in this process is in the range of 200 μm. Third, fabrication of BWAs is not a part of the standard CMOS process and requires complicated post-processing. Moreover, the 3-D nature of the antenna and fabrication through wire-bonding leads to lower reproducibility, which can be a major hindrance in mass production. As a result, BWAs have not become a common on-chip antenna solution for millimeter-wave and terahertz ICs. Table 3.2 gives a comparative analysis of the radiation performance enhancement techniques discussed thus far. It can be observed that dielectric lenses offer the highest amount of gain improvement, while insertion of AMC layers proves to be the most area-efficient and cost-effective. Although each technique has certain advantages and drawbacks, the choice of implementation depends upon the type of application and fabrication constraints. Many offchip techniques result in greater chip size, which is not feasible for size-critical applications such as implants, but, at the same time, are essential in radar applications requiring large gain values. In most AoC designs today, a combination of these techniques is utilized, and the substrate, stack-up, and package are all modified to aid the antenna’s radiation.

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Antenna-on-Chip: Design, Challenges, and Opportunities Table 3.2 Comparison of AoC Performance Enhancement Techniques PostIncrease Typical Gain Processing in Chip Improvement* Required Size Drawbacks

Technique

Principle

Substrate thinning [3–6]

Surface-wave suppression, path loss reduced

1 to 5 dB

Yes

No

High-resistivity substrates [8, 9]

Lower loss in silicon substrate

6 dB

Yes

No

Micromachining [12–14]

Physical separation between antenna and substrate

5 dB

Yes

No

AMCs [17–19, 38]

In-phase reflection; 8 dB shielding from lossy substrate Superstrate focusing; 6 dB resonance condition

No

No

Yes

Yes

Superstrate focusing; elimination of surface waves in superstrate Elimination of conductive losses; formation of standing waves inside dielectric resonator Surface-wave suppression using infinite dielectric technique; lensbased focusing Physical separation of antenna from substrate

2 dB

Yes

Yes

8 dB

Yes

Yes

Misalignment issues; increased size

20 dB

Yes

Yes

10 dB

Yes

Yes

Physical separation of antenna from substrate

5 dB

Yes

Yes

Post-fabrication processing; misalignment issues; increased size Increased form factor; complex fabrication; reliability issues Nonplanar nature of the antenna; increased form factor; reliability issues

Dielectric superstrate loading [21–25] ADLs [27]

DRA [29–32]

Dielectric lens [38–42]

MEMS [5, 43–46]

BWAs [50–52]

*These values are based upon existing literature and may need to be updated with time.

Reduced mechanical support and reliability, additional postfabrication step Not mainstream CMOS process, costly; surface waves not suppressed Complicated fabrication; post-fabrication processing Not suitable for lower frequencies Surface waves in superstrate degrade efficiency Complicated design; postprocessing



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3.5  Measurement and Characterization Techniques Chapter 2 gave a detailed introduction to the challenges encountered in the characterization of on-chip antennas. AoCs cannot be measured using conventional connector-based methods in an anechoic chamber, unless the chip is mounted on a PCB, which further complicates the accurate characterization of the antenna performance. Instead, sophisticated RF probe-based testing setups are used for AoC characterization. In recent years, although dedicated chambers for AoC characterization have become commercially available, they are extremely costly and complex to use. There are two main sources of error in AoC measurements: (1) effect of on-chip circuits on the antenna’s radiation, and (2) the effects of measurement setup (including the RF probes). The first source of error exists as the chip is densely packed with ICs and passive components, which, if connected to the antenna, can skew the impedance measurement results. The second source of error is the measurement setup itself, which not only obstructs the characterization process but also interferes with the accuracy of the measured results. In order to characterize an on-chip antenna accurately, these error sources should be identified and their impact removed or mitigated from the measurements. To this end, either the measurement setups are modified to reduce the probability of error or de-embedding techniques are employed post-measurement. 3.5.1  Mitigating the Effects of On-Chip Circuits

In most applications, on-chip antennas are integrated with front-end circuits, which makes their standalone characterization difficult. The latter requires them to be isolated from the IC, which can be achieved by either fabricating an identical antenna test structure on the same chip, physically separating the antenna from the circuit or going for innovative methods to individually characterize an integrated antenna. The first method offers accurate characterization but can be costly because a separate antenna takes up extra silicon area. In the second approach, the loading effects of the circuit are removed by physically separating it from the antenna through procedures such as lasering, focused ion beam (FIB), and passing high DC. In the first procedure, the connection between the antenna and circuits is removed using lasers as shown in Figure 3.30(a). FIB fires high-energy ions towards the sample to evaporate the target. Using FIB, a trench on the metallic traces of a test chip can be made as shown in Figure 3.30(b). The third method involves passing a high DC through a narrow and thin metal path connecting the AoC and circuits. Figure 3.30(c) shows connections at an antenna feedline burnt off using 990 mA where the current rating of the trace was 60 mA. However, it must be noted that cutting off onchip connections is an irreversible process and the targeted IC can therefore

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Figure 3.30  Procedures to physically disconnect on-chip antenna from circuits: (a) lasering, (b) FIB to produce trenches in metal traces, and (c) passage of high DC to burn off connections.

only serve as a test structure and not a working prototype. Moreover, an array of extra bond pads is inevitably required to enable individual testing of the AoC and the circuit. Physically destroying the path between the circuit and the antenna does allow for isolated characterization of both but also renders the IC useless.



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However, it would be much more cost-effective if the effect of circuit elements is isolated or de-embedded from antenna measurements. De-embedding the effect of connected circuits from the antenna’s measured results can remove the requirement of additional test structures or damage to fabricated chips. For example, in [53], the effect of a balun structure on the reflection coefficient of a 24-GHz on-chip dipole has been de-embedded through post-processing as shown in Figure 3.31. The balun is implemented using coplanar strips (CPS) to convert from the unbalanced GSG pad terminals to a balanced (nongrounded) resistive load. It is implemented in an EM simulator to feed the on-chip differential antenna and obtain single ended S-parameters along with the antenna radiation pattern. The S-parameters are also verified from simulations done in ADS and are then de-embedded from the antenna’s parameters using:

[S ]

ant 1×1

= [Sbalun ]2 × 2 [S ant +balun ]1×1 −1

(3.7)

3.5.2  Mitigating the Effects of Measurement Setup

Unwanted coupling between the antenna and the measurement equipment can cause considerable discrepancies in the measured results of the antenna. The probe body consists of a large conducting part that not only radiates itself but also tends to block and reflect the AUT’s radiation resulting in a distorted radiation pattern measurement. The same behavior is observed due to other conducting surfaces near the AUT such as metallic wafer chucks. Moreover, the impedance of the probe can also affect the reflection coefficient measurements of the AUT. These interferences are mitigated by proper de-embedding or through modifications in the measurement setup itself as discussed below. 3.5.2.1  Error Compensation Through Pre-Processing and Post-Processing Techniques

De-embedding the effects of the probe through pre-simulation or post-simulation is a time-saving and cost-saving method to accurately characterize an AoC. By properly modeling measurement equipment such as probes and wafer chucks, their effect on the antenna’s reflection and radiation characteristics can be quantified and removed from final measurements. The effect of the probe’s impedance can be eliminated by proper calibration at the plane of the probe tips. In [54], the effect of the air-coplanar (ACP) probe on the reflection coefficient/radiation pattern of the antenna was studied and de-embedded from the AoC’s measurement. The probe was first simulated with a calibration substrate that was then replaced by an on-chip antenna and the difference of the two simulations was used to remove the influence of the probe’s impedance. The simulation also accounted for the coupling effects

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Figure 3.31  De-embedding the effect of balun from 24-GHz dipole antenna: (a) equivalent circuit of balun, (b) assembly realization, and (c) fabricated structures [53].

between the probe and the antenna and simulated results with de-embedded probe effects demonstrated a good agreement with the measured results. Other than the reflection coefficient, the AoC’s radiation pattern measurement is also strongly affected by the presence of the RF probe. The metallic parts of an RF probe tend to radiate to some extent and because AoCs are essentially low-gain antennas, the probe radiation can interfere with antenna



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radiation. An easy solution to this problem is to design a long feedline for the antenna to increase its separation to the probe. The effect of the feedline can later be de-embedded from measurements. However, this method is only feasible for individual antenna characterization and not for antennas integrated with circuits. The other, more sound method is de-embedding the effect of probe’s self-radiation, which requires measurement of the probe’s radiation with and without the antenna. The simplest way to do this is through two test setups [55]. In the first setup, the RF probe is suspended in the air above the AoC as shown in Figure 3.32(a). Here, the self-radiation of the probe is measured denoted as (S21(P1)). In the second setup, shown in Figure 3.32(b), the probe is landed on the antenna to excite it and the overall radiation pattern is measured again. The overall radiation pattern (S21(total)) is the combination of probe selfradiation (S21(P2)) and the antenna’s radiation pattern (S21(A)). Now, to obtain the antenna’s radiation, the probe’s self-radiation measured in the first setup is de-embedded from the measured radiation pattern of the second setup.

S 21( A ) = S 21(total ) − S 21(P 2)

(3.8)

However, the self-radiation of the probe in setup 2 cannot be independently measured and one has to rely on the measurement from setup 1.

Figure 3.32  Characterization setups for the de-embedding of the probe self-radiation with (a) the measuring probe in air above the AUT and (b) probe placed on the AUT.

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Therefore, a scaling factor is introduced to approximate the self-radiation of the probe in setup 2 using the probe’s radiation in setup 1. The scaling factor depends upon parameters such as the position of the probe and its proximity to the antenna. Now the antenna’s radiation pattern can be found by [55]:

S 21( A ) = S 21(total ) − S 21(P 1) × S

(3.9)

The accuracy of this measurement can be further improved by taking into account multiple test setups involving the antenna and RF probe. In another method proposed in [55], two identical AoCs and probes are measured in four test setups. In the first measurement setup, both probes are landed on the antennas, indicated as (P, A)(P, A). For the second and third setups, one RF probe is landed, while the other probe is floating in the air, denoted by (P) (P, A) and (P, A)(P). In the fourth setup, the measured S21 parameter (P)(P) is obtained when both probes are floating in the air. The desired S21 parameter of the antenna, denoted by (A)(A), can be calculated according to the phasor subtraction, as follows:

( A )( A ) = (P , A )(P , A ) − (P )(P , A ) − (P , A )(P ) − (P )(P )

(3.10)

One disadvantage of this method is that the de-embedding results are obtained for only one direction or orientation of the antenna and probe. To obtain the complete radiation pattern based on this method, the relative locations of the two AoCs need to be adjusted as shown in Figure 3.33. However, to do this, the chip position needs to be changed multiple times, making it a cumbersome process while probes also become prone to damage due to repeated substrate landings.

Figure 3.33  De-embedding of the probe self-radiation using a pair of identical AoCs and probes. Both antenna chips are positioned on the measurement apparatus. Black squares indicate the location of the antenna, small light gray squares indicate the antenna positions at 10° steps, and C1 and C2 denote chips 1 and 2. Measurements were taken from 10° to 180° at 10° steps [55].



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3.5.2.2  Specialized Measurement Setups

Simulation-based de-embedding of probe interference greatly reduces the margin of error in AoC measurements; however, it is also helpful if the test fixtures are designed in a way to aid the measurement procedure. This implies use of materials and structures that ensure minimum interference and blocking effects from the probe and the holding assembly. The first approach to minimizing unwanted interference with the antenna’s radiation pattern is to remove any unnecessary conducting materials from the measurement setup that can radiate themselves or reflect the antenna’s radiation. Although conducting parts of the probe body cannot yet be fully replaced, it is possible to shield them using absorbing material as shown in Figure 3.34 [56]. Other components of the setup such as the wafer holder can be fabricated using materials with a lower permittivity, possibly close to 1. This not only reduces reflections but also allows full 3-D measurement of the radiation pattern because the material will appear virtually transparent to radiation. Chucks made of polystyrene and foam have been used in the past and have shown higher measurement accuracies compared to their metallic counterparts [57]. The probe body of standard wafer probes presents a comparably large reflective surface in the direct vicinity of the AUT and is the biggest source of radiation reflection and blockage. Therefore, it is only logical to try to place it as far from the AUT as possible. This has led to the design of customized probes and AUT holders. For example, in Figure 3.35(a), a special probe with an extended probe tip was designed to increase the separation from the AUT,

Figure 3.34  Probe body shielded using absorbing material and nonmetallic foam-based wafer holder to mitigate reflections [56].

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Figure 3.35  Modifications in AoC measurement setups to minimize interference from the probe body: (a) extended probe to separate the probe body from the AUT [58], and (b) bending the waveguide between the probe tip and the body to move the latter to the backside of the chip, the antenna feedline has also been extended to further distance it from the probe [59].

resulting in a measurement uncertainty and radiation blockage area of less than 20° [58]. It is also an option to design the probe in such a way that the bulk of its body is hidden from the AUT. Figure 3.35(b) shows a novel design in which bending the waveguide between the probe tips and the probe conductor body moves the large probe body to the backside of the AUT [59]. Insertion of an RF absorber between the chip and the probe further decreases any possible interference. Interference from the probe can also be minimized by designing the antenna with a long feedline to physically distance it from the probe as shown in Figure 3.35(b). Clearly, this method uses valuable silicon area and is usually adopted for custom-fabricated on-chip antennas.



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With the increasing focus on AoC research and the ever-reducing sizes of chips, specialized facilities for AoC characterization are required. Anechoic chambers with mechanisms dedicated for probe-based measurements have been established in a number of institutes such as the μlab at KAUST [60] and the robotic measurement setup at Ulm University [58]. Automated measurement setups such as the one shown in Figure 3.36 use robotic holders for receiving antennas to allow movement in three different axes (x, y, z), thus making highly flexible scan geometries possible. For higher measurement accuracy, additional equipment such as microscopes and laser pointers are also being used for probe positioning and measurement of device separations. A new type of measurement system known as quasi-in-air-based setup is also being explored to eliminate the issues associated with conventional probe-based systems [56]. In this setup, a supporting structure is used to hold the AUT in mid-air, away from the holding station resulting in extremely low reflections. However, elevating the antenna in the air reduces the stability of the AUT and complicates probe positioning.

3.6  Conclusion This chapter has provided an overview of the different techniques that are employed to enhance the radiation characteristics of AoCs and later aid in their

Figure 3.36  State-of-the-art AoC characterization setup using a robotic arm holding the receiving antenna [58].

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accurate characterization. To summarize, there are substrate-based techniques that modify its properties to lower the losses associated with the use of silicon. Techniques utilizing the existing semiconductor technologies have also been discussed, including the insertion of ground and meta-surface layers below the antenna to constructively aid in radiation. Off-chip methods add lenses and dielectric layers externally to the chip to focus or augment the waves radiated from the antenna while also reducing substrate losses. Finally, 3-D and MEMSbased AoC fabrication techniques are described that allow the antenna to be completely or partially elevated so that it is has no direct contact with the substrate. Each technique has its advantages and shortcomings and provides a certain extent of gain improvement based on its principle of operation. However, the use of each depends upon the constraints and allowances specified by the end application. AoC characterization techniques have also been discussed with a focus on addressing the challenges introduced in the previous chapter. These include removing the unwanted effects of on-chip circuits and test equipment from the antenna’s measurement results though physical modifications and deembedding techniques. Up until now, the discussion has centered on performance solutions related to standalone antenna design; however, greater challenges to AoC performance can be expected when it is integrated with the on-chip circuits. The subsequent chapters will discuss techniques that improve the performance of not only the antenna but the entire SoC. Effective codesign strategies will be discussed that enable efficient matching between the antenna and the circuit, compatible layout designs, cosimulation, and packaging considerations.

References [1] SVMI, “Wafer Thinning - Silicon Valley Microelectronics,” https://svmi.com/service/ thinning/. [2] Burghartz, J. N., et al., “A New Fabrication and Assembly Process for Ultrathin Chips,” IEEE Transactions on Electron Devices, Vol. 56, No. 2, February 2009, pp. 321–327. [3] Lin, J. -J., et al., “10x Improvement of Power Transmission over Free Space Using Integrated Antennas on Silicon Substrates,” Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), October 2004, pp. 697–700. [4] Adela, B. B., et al., “On-Chip Antenna Integration for Millimeter-Wave Single-Chip FMCW Radar, Providing High Efficiency and Isolation,” IEEE Transactions on Antennas and Propagation, Vol. 64, No. 8, August 2016, pp. 3281–3291. [5] Marnat, L., et al., “New Movable Plate for Efficient Millimeter Wave Vertical On-Chip Antenna,” IEEE Transactions on Antennas and Propagation, Vol. 61, No. 4, April 2013, pp. 1608–1615.



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[6] Babakhani, A., et al., “A 77-GHz Phased-Array Transceiver with On-Chip Antennas in Silicon: Receiver and Antennas,” IEEE J. Solid-State Circuits, Vol. 41, No. 12, December 2006, pp. 2795–2806. [7] Andre, N., et al., “Ultra Low-Loss Si Substrate for On-Chip UWB GHz Antennas,” IEEE J. Electron Devices Soc., Vol. 7, 2019, pp. 393–397. [8] Chan, K. T., et al., “Integrated Antennas on Si with over 100 GHz Performance, Fabricated Using an Optimized Proton Implantation Process,” IEEE Microwave and Wireless Components Letters, Vol. 13, No. 11, November 2003, pp. 487–489. [9] Wu, R., et al., “A 60-GHz Efficiency-Enhanced On-Chip Dipole Antenna Using Helium-3 Ion Implantation Process,” 2014 44th European Microwave Conference, Rome, October 2014, pp. 108–111. [10] Papapolymerou, I., R. Franklin Drayton, and L. P. B. Katehi, “Micromachined Patch Antennas,” IEEE Transactions on Antennas and Propagation, Vol. 46, No. 2, February 1998, pp. 275–283. [11] Gauthier, G. P., A. Courtay, and G. M. Rebeiz, “Microstrip Antennas on Synthesized Low Dielectric-Constant Substrates,” IEEE Transactions on Antennas and Propagation, Vol. 45, No. 8, 1997, pp. 1310–1314. [12] Jefors, E., et al., “Micromachined Loop Antennas on Low Resistivity Silicon Substrates,” IEEE Transactions on Antennas and Propagation, Vol. 54, No. 12, December 2006, pp. 3593–3601. [13] Ng, H. J., and D. Kissinger, “Highly Miniaturized 120-GHz SIMO and MIMO Radar Sensor with On-Chip Folded Dipole Antennas for Range and Angular Measurements,” IEEE Transactions on Microwave Theory and Techniques, Vol. 66, No. 6, June 2018, pp. 2592–2603. [14] Khan, W. T., et al., “A D-Band Micromachined End-Fire Antenna in 130-nm SiGe BiCMOS Technology,” IEEE Transactions on Antennas and Propagation, Vol. 63, No. 6, June 2015, pp. 2449–2459. [15] Sievenpiper, D., et al., “High-Impedance Electromagnetic Surfaces with a Forbidden Frequency Band,” IEEE Transactions on Microwave Theory and Techniques, Vol. 47, No. 11, November 1999, pp. 2059–2074. [16] Feresidis, A. P., et al., “Artificial Magnetic Conductor Surfaces and Their Application to Low-Profile High-Gain Planar Antennas,” IEEE Transactions on Antennas and Propagation, Vol. 53, No. 1, January 2005, pp. 209–215. [17] Kuo, H. -C., et al., “A 60-GHz CMOS Sub-Harmonic RF Receiver with Integrated OnChip Artificial-Magnetic-Conductor Yagi Antenna and Balun Bandpass Filter for VeryShort-Range Gigabit Communications,” IEEE Transactions on Microwave Theory and Techniques, Vol. 61, No. 4, April 2013, pp. 1681–1691. [18] Nafe, M., A. Syed, and A. Shamim, “Gain-Enhanced On-Chip Folded Dipole Antenna Utilizing Artificial Magnetic Conductor at 94 GHz,” IEEE Antennas and Wireless Propagation Letters, Vol. 16, 2017, pp. 2844–2847. [19] Pan, S., et al., “A 94-GHz Extremely Thin Metasurface-Based BiCMOS On-Chip Antenna,” IEEE Transactions on Antennas and Propagation, Vol. 62, No. 9, September 2014, pp. 4439–4451.

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[20] Alexopoulos, N., and D. Jackson, “Fundamental Superstrate (Cover) Effects on Printed Circuit Antennas,” IEEE Transactions on Antennas and Propagation, Vol. 32, No. 8, August 1984, pp. 807–816. [21] Edwards, J. M., and G. M. Rebeiz, “High-Efficiency Elliptical Slot Antennas with Quartz Superstrates for Silicon RFICs,” IEEE Transactions on Antennas and Propagation, Vol. 60, No. 11, November 2012, pp. 5010–5020. [22] Yang, Y., O. D. Gurbuz, and G. M. Rebeiz, “An Eight-Element 370–410-GHz PhasedArray Transmitter in 45-nm CMOS SOI with Peak EIRP of 8–8.5 dBm,” IEEE Transactions on Microwave Theory and Techniques, Vol. 64, No. 12, December 2016, pp. 4241–4249. [23] Uzunkol, M., et al., “A 0.32 THz SiGe 4x4 Imaging Array Using High-Efficiency OnChip Antennas,” IEEE Journal of Solid-State Circuits, Vol. 48, No. 9, September 2013, pp. 2056–2066. [24] Ou, Y. -C., and G. M. Rebeiz, “Differential Microstrip and Slot-Ring Antennas for Millimeter-Wave Silicon Systems,” IEEE Transactions on Antennas and Propagation, Vol. 60, No. 6, June 2012, pp. 2611–2619. [25] Atesal, Y. A., et al., “Millimeter-Wave Wafer-Scale Silicon BiCMOS Power Amplifiers Using Free-Space Power Combining,” IEEE Transactions on Microwave Theory and Techniques, Vol. 59, No. 4, April 2011, pp. 954–965. [26] Kock, W. E., “Metallic Delay Lenses,” Bell System Technical Journal, Vol. 27, No. 1, 1948, pp. 58–82. [27] Syed, W. H., et al., “Design, Fabrication, and Measurements of a 0.3 THz On-Chip Double Slot Antenna Enhanced by Artificial Dielectrics,” IEEE Transactions on Terahertz Science and Technology, Vol. 5, No. 2, March 2015, pp. 288–298. [28] Keyrouz, S., and D. Caratelli, “Dielectric Resonator Antennas: Basic Concepts, Design Guidelines, and Recent Developments at Millimeter-Wave Frequencies,” International Journal of Antennas and Propagation, Vol. 2016, 2016, pp. 1–20. [29] Sallam, M. O., et al., “Micromachined On-Chip Dielectric Resonator Antenna Operating at 60 GHz,” IEEE Transactions on Antennas and Propagation, Vol. 63, No. 8, August 2015, pp. 3410–3416. [30] Deng, X. -D., et al., “340 GHz On-Chip 3-D Antenna with 10 dBi Gain and 80% Radiation Efficiency,” IEEE Transactions on Terahertz Science and Technology, Vol. 5, No. 4, July 2015, pp. 619–627. [31] Li, C. -H., and T. -Y. Chiu, “340-GHz Low-Cost and High-Gain On-Chip Higher Order Mode Dielectric Resonator Antenna for THz Applications,” IEEE Transactions on Terahertz Science and Technology, Vol. 7, No. 3, May 2017, pp. 284–294. [32] Hou, D., et al., “130-GHz On-Chip Meander Slot Antennas with Stacked Dielectric Resonators in Standard CMOS Technology,” IEEE Transactions on Antennas and Propagation, Vol. 60, No. 9, September 2012, pp. 4102–4109. [33] Li, C. -H., and T. -Y. Chiu, “Single Flip-Chip Packaged Dielectric Resonator Antenna for CMOS Terahertz Antenna Array Gain Enhancement,” IEEE Access, Vol. 7, 2019, pp. 7737–7746.



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[34] Rebeiz, G. M., “Millimeter-Wave and Terahertz Integrated Circuit Antennas,” Proceedings of the IEEE, Vol. 80, No. 11, November 1992, pp. 1748–1770. [35] Jalili, H., and O. Momeni, “A 0.46-THz 25-Element Scalable and Wideband Radiator Array with Optimized Lens Integration in 65-nm CMOS,” IEEE J. Solid-State Circuits, Vol. 55, No. 9, September 2020, pp. 2387–2400. [36] Goettel, B., et al., “Packaging Solution for a Millimeter-Wave System-on-Chip Radar,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 8, No. 1, January 2018, pp. 73–81. [37] Shi, J., et al., “220 GHz High Spatial Resolution Detector with Above-Chip Mounted Dielectric Lens,” Electronics Letters, Vol. 53, No. 8, April 2017, pp. 538–540. [38] Zhang, H., and A. Shamim, “Gain Enhancement of Millimeter-Wave On-Chip Antenna Through an Additively Manufactured Functional Package,” IEEE Transactions on Antennas and Propagation, Vol. 68, No. 6, June 2020, pp. 4344–4353. [39] Sarkas, I., et al., “A Fundamental Frequency 120-GHz SiGe BiCMOS Distance Sensor with Integrated Antenna,” IEEE Transactions on Microwave Theory and Techniques, Vol. 60, No. 3, March 2012, pp. 795–812. [40] Han, R., and E. Afshari, “A CMOS High-Power Broadband 260-GHz Radiator Array for Spectroscopy,” IEEE Journal of Solid-State Circuits, Vol. 48, No. 12, December 2013, pp. 3090–3104. [41] Statnikov, K., et al., “160-GHz to 1-THz Multi-Color Active Imaging with a LensCoupled SiGe HBT Chip-Set,” IEEE Transactions on Microwave Theory and Techniques, Vol. 63, No. 2, February 2015, pp. 520–532. [42] Grzyb, J., et al., “A 210–270-GHz Circularly Polarized FMCW Radar with a Single-LensCoupled SiGe HBT Chip,” IEEE Transactions on Terahertz Science and Technology, Vol. 6, No. 6, November 2016, pp. 771–783. [43] Kim, J. -G., et al., “60-GHz CPW-Fed Post-Supported Patch Antenna Using Micromachining Technology,” IEEE Microwave and Wireless Components Letters, Vol. 15, No. 10, October 2005, pp. 635–637. [44] Pan, B., et al., “Analysis and Characterization of a High-Performance Ka-Band Surface Micromachined Elevated Patch Antenna,” IEEE Antennas and Wireless Propagation Letters, Vol. 5, No. 1, December 2006, pp. 511–514. [45] Pan, B., Y. Yoon, P. Kirby, J. Papapolymerou, M. M. Tenzeris and M. Allen, “A W-Band Surface Micromachined Monopole for Low-Cost Wireless Communication Systems,” IEEE MTT-S International Microwave Symposium Digest, Fort Worth, TX, USA, Vol. 3, 2004, pp. 1935-1938. [46] Mahanfar, A., et al., “Self-Assembled Monopole Antennas with Arbitrary Shapes and Tilt Angles for System-on-Chip and System-in-Package Applications,” IEEE Transactions on Antennas and Propagation, Vol. 58, No. 9, September 2010, pp. 3020–3028. [47] Gaucher, B. P., et al., “Apparatus and Methods for Constructing Antennas Using Wire Bonds as Radiating Elements,” U.S. Patent 7295161B2, November 13, 2007.

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[48] Chen, W. -H., et al., “A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 10, October 2009, pp. 2711–2721. [49] Willmot, R., D. Kim, and D. Peroulis, “A Yagi–Uda Array of High-Efficiency Wire-Bond Antennas for On-Chip Radio Applications,” IEEE Transactions on Microwave Theory and Techniques, Vol. 57, No. 12, December 2009, pp. 3315–3321. [50] Deferm, N., and P. Reynaert, “A 120 GHz Fully Integrated 10 Gb/s Short-Range StarQAM Wireless Transmitter with On-Chip Bondwire Antenna in 45 nm Low Power CMOS,” IEEE J. Solid-State Circuits, Vol. 49, No. 7, July 2014, pp. 1606–1616. [51] Starke, P., et al., “High-Efficiency Wideband 3-D On-Chip Antennas for Subterahertz Applications Demonstrated at 200 GHz,” IEEE Transactions on Terahertz Science and Technology, Vol. 7, No. 4, July 2017, pp. 415–423. [52] Lin, T. -Y., T. Chiu, and D. -C. Chang, “Design of V-Band Wide-Beamwidth Circularly Polarized Wire-Bond Antenna,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 8, No. 2, February 2018, pp. 261–268. [53] Shamim, A., et al., “On-Chip Antenna Measurements: Calibration and De-embedding Considerations,” 2005 IEEE Instrumentation and Measurement Technology Conference Proceedings, Vol. 1, May 2005, pp. 463–466. [54] Seyyedesfahlan, M., and I. Tekin, “ACP Probe Measurement of On-Chip Strip Dipole Antennas at W Band,” IEEE Transactions on Antennas and Propagation, Vol. 64, No. 4, April 2016, pp. 1270–1278. [55] Murdock, J., et al., “Challenges and Approaches to On-Chip Millimeter Wave Antenna Pattern Measurements,” 2011 IEEE MTT-S International Microwave Symposium, June 2011, pp. 1–4. [56] Zhang, H., and A. Shamim, “Tackling the Issues of Millimeter-Wave On-Chip Antenna Measurements,” 2019 13th European Conference on Antennas and Propagation (EuCAP), March 2019, pp. 1–5. [57] Titz, D., F. Ferrero, and C. Luxey, “Development of a Millimeter-Wave Measurement Setup and Dedicated Techniques to Characterize the Matching and Radiation Performance of Probe-Fed Antennas [Measurements Corner],” IEEE Antennas and Propagation Magazine, Vol. 54, No. 4, August 2012, pp. 188–203. [58] Boehm, L., et al., “The Challenges of Measuring Integrated Antennas at Millimeter-Wave Frequencies [Measurements Corner],” IEEE Antennas and Propagation Magazine, Vol. 59, No. 4, August 2017, pp. 84–92. [59] Reniers, A. C. F., et al., “The Influence of the Probe Connection on Mm-Wave Antenna Measurements,” IEEE Transactions on Antennas and Propagation, Vol. 63, No. 9, September 2015, pp. 3819–3825. [60] KAUST, “Lab Resources | Impact | Integrated Microwaves Packaging Antennas & Circuits Technology,” https://cemse.kaust.edu.sa/impact/impact-lab-resources.

4 Codesign of Circuits and Antennas Antenna and IC design have traditionally been distinct fields with designers working rather independently to create devices that are later integrated to form a system. Following the inception of AoC technology, both domains have been intertwined in different ways. This implies that the design and performance expectations from the IC are given by the antenna designer and those of the antenna are provided by the IC designer. This concurrent design process, termed as codesign, aims to achieve the optimum performance by utilizing the flexibility on both sides. Interestingly, this is also generating a new breed of IC designers who understand the antenna world much better than their predecessors, and the opposite is true for antenna designers. The codesign approach enables designers to simultaneously design the IC and antenna, keeping in view their interdependencies. These are present at all levels of system, circuit, layout, and packaging. At the system level, technology choice, architecture, and cost are factors of interest. At the circuit level, maintaining the performance of components on both sides through innovative designs and achieving optimum power transfer between the antenna and the circuit are important considerations. At the layout level, meticulous placement of antenna and circuits is required to mitigate crosstalk and effectively use chip space to minimize cost penalty. Lastly, at the packaging level, the chip must be designed keeping in mind the package material properties, its effects, and testability requirements. In an ideal codesign, the antenna and IC are designed in parallel according to these requirements to leverage the best of both worlds and meet the application specifications at the same time.

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4.1  Codesign Considerations A typical SoC for wireless communication consists of three main components: the digital baseband circuit, ADCs and DACs, and the RF front end. Since the introduction of AoC technology, the antenna has become the fourth component, capable of being implemented on the chip, leading to the ultimate on-chip integration of a complete system. On the chip, the AoC is directly connected to the front-end circuit, and most of the challenges in AoC integration stem from the interaction or interference between the front end and the antenna. Therefore, the focus of this chapter is to equip the reader with knowledge of codesign strategies at all levels of design. An RF front end commonly interacts with the signal at the intended radio frequency, after being upconverted in a transmitter or downconverted to an intermediate frequency (IF) or baseband in a receiver. There are three ways that an AoC is used with a front end: (1) as a receiving antenna connected to low noise amplifiers (LNA) in a receiver chip, (2) as a transmitting antenna connected to a power amplifier (PA) in a transmitter chip, and (3) as a transmit/ receive antenna connected to both sides through a switch. These configurations are shown in the next subsections. 4.1.1  AoC in Receiver

In most on-chip receivers, the AoC is connected directly to an LNA as shown in Figure 4.1. The LNA, being the first component in the Rx chain, has to amplify signals while introducing minimum noise to the system. As a result, the characteristics of the LNA set the upper limit on the entire receiver performance. The principal LNA design requirements for an RF front end are noise figure (NF), input matching, and gain. The designer’s task in the codesign process is to identify direct or indirect linkage between these performance metrics and the on-chip antenna and find strategies that can be adopted to mitigate resultant performance issues.

Figure 4.1  Block diagram of a wireless receiver (with a shaded front end).



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The foremost consideration in LNA design is the NF, which is a measure of the signal-to-noise ratio (SNR) degradation when the signal passes through a component. The noise in an LNA originates from thermal noise, shot noise, and flicker noise and typically accounts for one-third of the total receiver noise. It is therefore critical in the determination of the system NF [1]. Figure 4.2 shows the equivalent circuit of an antenna connected to an LNA where Vn2,RS and Vn2 denote the rms noise power generated by the antenna and the LNA, respectively. The NF is the ratio of the input SNR to output SNR and is given by (4.1) (a complete explanation is found in [1]):

NF =

SNRin V2 1 = 1 + 2n 2 × SNRout α Av V RS2

(4.1)

where |α| = Zin/(Zin + RS) is the attenuation due to impedance mismatch between the antenna and the LNA and Av is the LNA’s voltage gain. It is evident that the LNA’s NF depends on the noise generated by the antenna as well as the impedance mismatch between them. Therefore, to design an LNA with a low NF, both these considerations must be appropriately considered. The NF is also very much dependent on LNA topology, as will be discussed shortly. The second major LNA design consideration is the gain that is closely related to the NF. The gain determines the amplification of the input signal and,

Figure 4.2  (a) On-chip antenna followed by an LNA, and (b) equivalent circuit.

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in a cascaded chain, reduces the noise contribution of the succeeding stages. Hence, it is common to design the LNA with a low NF and adequately high gain [1]. The commonly used gain definition in amplifier design is the transducer power gain expressed in (4.2), which takes into account both source and load mismatch.

G=

1 − ΓS

2

1 − S11Γ S

2

S21

2

1 − ΓL

2

1 − S22 Γ L

2



(4.2)

where S11, S22, and S21 are the LNA scattering parameters, and ΓS and ΓL are the reflection coefficients seen from the device towards the source and the load, respectively. However, in modern RF design, the LNA is directly connected to the downconversion mixer without any impedance matching and provides a voltage gain to the succeeding stages instead of delivering power to a load. Thus, when discussing the LNA’s output interface, voltage gain Av is considered a more useful and meaningful definition. The third metric of LNA design, the input return loss, expresses the quality of the impedance match between the antenna and the LNA. Describing an LNA in terms of its Z-parameters as shown in Figure 4.3, the return loss is given by: 2



Γ=

Zin − ZS Zin + ZS

(4.3)

where Zin and ZS show the input impedances of the LNA and antenna, respectively. A conjugately matched antenna and LNA (Zin = ZS*) would provide maximum transfer of power and consequently maximum gain as seen from (4.2). However, for best noise performance, the antenna should provide an optimum impedance to the input of the LNA. Thus, a trade-off exists between the gain and the NF with regard to input impedance matching, and optimizing the

Figure 4.3  Input and output impedances and network parameters of a two-port LNA.



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129

LNA for the lowest NF and maximum gain becomes a challenging task. With regard to the output impedance matching between the LNA and the mixer, the maximum transfer of power is not the main concern and the matching is instead designed to maximize voltage swings. The stability of an LNA is also very much dependent on the AoC’s input impedance and must exhibit acceptable performance for all impedances at all frequencies in the band of interest. This is important because the source impedance, provided by the AoC, is subject to change, depending on the location and orientation of the chip as well as with different packaging materials. Furthermore, for off-chip antenna-based front ends, band-select filters can be used before the LNA to mitigate the effects of changes in source impedance. However, when the antenna is integrated on the chip, the effect of a changing source impedance is more pronounced and implementing band-select filters is challenging due to the low Q factor of on-chip passives. Therefore, it is important that all possible values of antenna input impedance be checked against the LNA during the codesign process to ensure the LNA stability, which otherwise becomes prone to oscillations leading to nonlinearity and degraded gain. Having seen the major design considerations of an LNA, it is important to discuss the predominant LNA topologies in RF design as they have a direct bearing on input matching requirements. These include the common source (CS) and the common gate (CG), both using single transistors by stage, and one of the most popular implementations is the Cascode topology. All other LNA configurations are derivatives of these major topologies, formed using multiple stages, differential stages, and/or current reuse. The CS LNA is able to provide a low NF and high gain while the CG LNA topology provides a broadband input impedance match that is less sensitive to parasitic capacitances. Consequently, the choice between them is a compromise between superior noise performance and robust input impedance matching. The Cascode LNA, which is widely used in CMOS RF LNAs, can be considered as a current reuse configuration of a CS stage, followed by a CG stage. Thus far, it is seen that integration of on-chip antenna leads to two major changes in receiver design: (1) the antenna-LNA matching network is integrated on the chip, and (2) the LNA can be designed to match the input impedance of the antenna at a complex value other than the standard 50Ω. It has been shown that the input matching of the LNA is governed by conflicting requirements for noise, gain, and power consumption. These tight trade-offs could be somewhat relaxed if a high quality factor Q input matching network is utilized. However, due to losses in silicon, Q values of on-chip spiral inductors for standard CMOS technology are typically limited to Radiation. This concludes the simulation setup of a standalone antenna on a CMOS substrate. The antenna is then simulated by specifying the required frequency range, number of frequency points, and mesh settings. HFSS uses adaptive meshing in which the mesh is constructed to conform to the electrical performance of the device. This number of passes that the adaptive mesh routine will perform is controlled by the designer with a higher number giving more accurate results at the expense of greater simulation time. Once the simulation has finished,

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Figure 5.10  Radiation boundary specified around the AoC.

plots are created to view the results. Rectangular plots are typically preferred for plotting S-parameters and VSWR data while radiation patterns are plotted using defined geometry planes. The simulation process and results of a standalone monopole antenna are shown in Figure 5.11. This process is repeated for each subsequent step to analyze the antenna’s performance in the presence of structures such as the AMC layer, the superstrate, the package, and the on-chip circuit. 5.3.3  AMC

Silicon-based on-chip antennas, due to their inherent low gains and efficiencies, almost always need some form of gain-boosting mechanism. For instance, the quarter-wavelength monopole antenna, when simulated on the CMOS stackup without any superstrate or reflector, yields a gain of –13.6 dBi. This value is not viable for typical transmitters, and, hence, a suitable gain enhancement method is required to improve the radiation performance. In this design, an AMC is designed on the bottom metal layer M1. Following the in-phase reflection concept explained in Section 3.2.1, the AMC acts as a PMC in the required frequency band. The AMC unit cell geometry is chosen to be a square patch as shown in Figure 5.12 due to its larger bandwidth and lower substrate loss compared to other AMC unit cell structures [9]. First, a single unit cell is modeled in HFSS using the Draw commands, which were used to model the substrate and the antenna as well. The excitation source to the AMC is provided vertically above the unit cell at a distance of at least λ/4 to ensure that the higher-order modes are sufficiently attenuated.



AoC Design Example

189

Figure 5.11  Simulation settings and results of an on-chip antenna in HFSS.

Figure 5.12  AMC unit cell: (a) isometric view and (b) cross-section.

This is done by first modeling an air waveguide structure above the unit cell and then assigning its top surface as a wave port to simulate backside radiation of the antenna (Figure 5.13). The procedure to assign a wave port is similar to the one followed for a lumped port in the preceding section. The parameter of interest in AMC design is the phase of the signal reflected the AMC surface. For maximum gain enhancement, the reflection phase must be 0° at the frequency of operation, while the frequencies at which the reflection phase is within +90° and –90° determine the bandwidth of the AMC. Therefore, the unit cell is simulated in a way to analyze the reflection phase at its surface. The port is assigned at a distance above the unit cell, so, to ensure that the phase of incident and reflected signal is measured exactly at the surface of the unit cell, post-processing is required. In the post-processing tab of the wave port, the

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Antenna-on-Chip: Design, Challenges, and Opportunities

Figure 5.13  AMC unit cell port assignment and de-embedding.�

de-embedding option is checked and the de-embedding distance is manually provided from the port to the unit cell. In this way, the reference plane is shifted from the wave port to the unit cell surface, allowing the designer to accurately analyze the reflection phase. Conventionally, a large array of unit cells can be modeled to simulate the effects of an infinite AMC. However, simulating large periodic surfaces is timeconsuming, so in an alternate approach, a single-unit cell can be simulated to give the effect of an infinite surface. This is done by applying symmetric PEC and PMC boundary conditions on the opposite walls of the waveguide structure as shown in Figure 5.14. An AMC surface can be optimized to achieve a 0° reflection phase at the desired frequency by tuning the geometry and dimensions of the unit cells and the size of AMC (total number of unit cells). In this design example, the dimensions of the unit cell are therefore optimized as shown in Figure 5.15 to provide a reflection phase of 0° at 71 GHz and a frequency bandwidth of 60.8 to 81.4 GHz. From the parametric analysis of AMC unit cell, the relation between the dimensions and operating frequency can be roughly expressed as:

f AMC ∝

L D ×H

(5.2)



AoC Design Example

191

Figure 5.14  Application of PEC and PMC boundaries to unit cell to simulate infinite AMC surface.

Figure 5.15  Plot of the AMC reflection phase against frequency with an optimized unit cell parameter resulting in a 0° phase at 71 GHz.

where fAMC is the frequency at which the AMC exhibits zero reflection phase and D, L, and H represent unit cell dimensions as shown in Figure 5.12. It can be observed from (5.2) that a larger unit cell and thicker substrate results in a lower frequency of operation, while smaller unit cells with thin substrate

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Antenna-on-Chip: Design, Challenges, and Opportunities

increase the frequency of operation. The frequency of operation is also proportional to the spacing between unit cells, with a wider spacing leading to a higher fAMC. It must be remembered that these proportionalities are specific to the AMC design being discussed, and although reduction in component size leads to an increase in the operating frequency, the exact expression may be different for other AMC geometries. Once the AMC is optimized at the required frequency, it is simulated with the on-chip antenna, as shown in Figure 5.16(a), to see the effect on its

Figure 5.16  (a) AMC inserted below monopole and (b) plot of maximum gain versus the number of AMC unit cells.



AoC Design Example

193

radiation performance. Ideally, an infinite AMC surface will behave like a PMC surface and yield the best performance. While this behavior can be simulated by applying symmetric PEC and PMC boundary walls to a unit cell, in reality, an infinite AMC surface cannot be realized due to the limited chip area. So the gain-enhancing property of the AMC surface will inevitably be lower than the ideal case. To determine a reasonable AMC size (number of unit cells (n)), the stack-up with the antenna on top is simulated with various sizes of the AMC and the results are shown in Figure 5.16(b). In this case, the maximum gain of the monopole increases with a larger number of square patch unit cells but begins to saturate when n becomes larger than 30. Generally, this trend depends upon the type of antenna, unit cell, and frequency of operation. For this AMC surface, n = 6 × 8 is selected as it offers a good compromise between AMC performance and chip size. The simulation results of the AoC with the AMC surface reveal a nearly 3-dB gain improvement compared to standalone antenna simulations in the previous section. 5.3.4  Superstrate Layer

The gain of the AoC is further enhanced by implementing a superstrate on top of the antenna. The presence of a superstrate with a thickness of λd  /4 (where ld is the guide wavelength) and a high εr on top of the antenna acts as an impedance transformer and enhances the radiation in the boresight. The superstrate is modeled as a solid box above the passivation layer as shown in Figure 5.17. The material specified for the superstrate is PREFERM FLX 1100 (εr = 11 and loss tangent of tanδ = 0.006 at 71 GHz) and is added to the materials library in the same way as described earlier. The lateral dimensions of the superstrate are the same as the substrate while its thickness is optimized through parametric simulation as shown in Figure 5.18(a).The thickness is varied up to 1 mm and its effect on the antenna’s radiation is shown in Figure 5.18(b). The radiation efficiency is maximum when the superstrate thickness is equal to odd multiples of λd /4 (see Section 3.3.1 for more details on superstrate design). For the 71-GHz AoC, superstrate thicknesses of 300 μm (~λd /4) and 900 μm (~3λd /4) yield the best results. Therefore, the superstrate is designed at the optimized thickness of 300 μm. In terms of the transmission-line equivalent model, the superstrate layer acts as an impedance transformer, thereby improving the antenna coupling to the free space. Apart from gain improvement, there are several other benefits of adding a superstrate layer. Because a λd /4 superstrate is considered elect rically thick, it acts as an external layer capable of providing protection to the chip. It also does not require any metal patterning or alignment, making it easy to design and fabricate. Upon simulating the antenna with the superstrate, an improvement of 7 dB in the gain is observed.

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Figure 5.17  Addition of superstrate layer on top of AoC chip in HFSS.

5.3.5  Lens Integrated Package

Packaging is the last stage of AoC design, and the package structure must be modeled and simulated with the antenna to analyze its effect on the AoC’s radiation efficiency. Moreover, AoC packages are often designed to enhance the antenna’s gain, which makes them an important part of the EM simulation. In this design, the AoC is encapsulated using a package integrated with a Fresnel lens, which enhances the antenna’s gain through beam shaping. Unlike traditional curved lenses, the focusing effect in a Fresnel lens is achieved by controlling the phase-shifting property of the surface [10]. This allows it to be relatively flat and more compact. The Fresnel lens consists of a set of planar grooved circular plates made from a low-loss dielectric material (PREFERM 3D ABS filament, εr = 10, tanδ = 0.02 at 71 GHz). Due to the high dielectric constant, the thickness of the lens plates is further reduced, leading to a more compact design. It is assembled on top of the transmitter chip using a circular support ring made of the same material. The lens and package supports are modeled in HFSS as shown in Figure 5.19, and parameters such as the number of lens plates, its diameter, and separation from the AoC are optimized to provide maximum antenna gain. The finalized package has a diameter of 13.16 mm with a height of 9.02 mm. Other types of packages (glob tops, QFN, curved lens-based packages) can also be simulated in the EM software to examine their performance. Another important part of package codesign is



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Figure 5.18  Optimization of the superstrate thickness: (a) frequency sweep in HFSS, and (b) simulated radiation efficiency versus superstrate thickness.

to include the effect of the PCB and other large off-chip components such as metal traces and connectors, if applicable. The complete AoC is assembly is simulated and it is observed that, compared to the solitary antenna, the gain of the end product is improved by nearly 21 dB. In this, 3 dB is accounted for by the AMC surface, 7 dB is contributed

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Figure 5.19  AoC with a Fresnel lens-based package modeled in HFSS.

by the superstrate, and nearly 11 dB is due to the lens integrated package. The lens is able to add the highest gain boost but also adds a considerable size penalty to the system. However, because it is intended as a package as well, the increase in size is acceptable. The various design stages of AoC simulation are illustrated in Figure 5.20(a–d), and their simulated gain results are shown in Figure 5.20(e). In most AoC designs, it is common to include multiple levels of gain enhancement techniques to achieve an acceptable performance for the front-end system. For the purpose of continuity, the antenna simulation is shown in the absence of on-chip circuits, which are discussed in subsequent sections. However, it is a good design practice to include the circuit layout in the AOC stack-up in the beginning of antenna design, so that the performance degradation due to circuit components can be evaluated and minimized in the earlier stages.

5.4  Circuit Simulation The circuit components in this work have been designed using Cadence Virtuoso, which is an industry standard schematic and layout editor providing design and layout capabilities for ICs. From the AoC perspective, the main tools needed are the Virtuoso Schematic Editor and Virtuoso Layout Suite. The Schematic Editor provides the capabilities of circuit design, routing, hierarchical management, and access to component libraries. The Layout Suite allows designers to create the layout of circuit components at chip level and provides functionalities to perform DRC and Layout Versus Schematic (LVS) checks. The following sections provide a step-by-step guide to designing and simulating a transmitter circuit using Virtuoso tools and its subsequent integration with the AoC.



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Figure 5.20  Simulation models of the multiple stages in the AoC design: (a) standalone AoC, (b) AoC with AMC layer, (c) AoC with AMC and superstrate layers, (d) AoC with AMC and superstrate layers and Fresnel lens package, and (e) simulated gains of the antenna at four design stages.

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5.4.1  Adding a Design Library

Cadence stores all design data in library files that are predominantly of two types. The first type is the design files provided by manufacturers that contain information specific to the design processes such as component models, available layers, and design rules. The second type of libraries are project files created by the designer that contain schematics and layouts. To address the complexities of modern IC design, each step of the design process must be done in accordance with foundry requirements to prevent fabrication inconsistencies. For this purpose, the foundry provides a set of files called the Process Design Kit (PDK), which is linked to the IC simulation environment for enabling a foundry-compatible design. The PDK helps to jumpstart the design process by providing the designer with all of foundry-specific process models and data needed for circuit design. This includes information such as device model parameters, schematic, symbol, and layout views, layer stack-up information, and various rule files pertaining to a specific technology. The PDK can be used to create, simulate, and verify circuit layouts before sending them to the foundry for fabrication. In standard practice, the PDK file is added in Cadence as a library before initiating the design in Virtuoso. To do this, it is added via Library Path Editor, which is accessed from the Tools menu of Cadence. In this design, the PDK provided by TSMC for its 180-nm CMOS process is added as shown in Figure 5.21(a). The added PDK is then visible in the Library Manager shown in Figure 5.21(b). Next, the designers can create their own design files in form of a library and attach it to the existing PDK library, thereby allowing the PDK data to be used in actual circuit design. For example, a new library named “AoC_Circuit” is added in the Library Manager and linked to the TSMC 180-nm PDK as depicted in Figure 5.22. 5.4.2  Schematic Design

The on-chip circuits are designed in Virtuoso’s Schematic Editor in separate cells views. In Virtuoso, a typical design follows a hierarchical pattern of library > cell > cell view where the library and cell view represent the highest and lowest abstraction levels, respectively. For example, a library encompasses the entire project and can be expanded into cell views containing individual circuit designs such as VCO and frequency multiplier. The steps to create a library named “AoC_Circuit” are shown in the previous section. Following the same procedure, a cell view for the schematic of the VCO circuit is created as shown in Figure 5.23. Once a cell view for the VCO circuit is created, the required components (transistors, passive components, and current and voltage sources) can be placed in the Editor window using the Create Instance command. As shown



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Figure 5.21  (a) Adding the foundry PDK into Virtuoso, and (b) Library Manager.

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Figure 5.22  Adding a new library and linking it to the process library.

Figure 5.23  Creating a new cell view in Virtuoso.

in Figure 5.24, the designer can add any component model from the library and specify its parameters through the Properties Editor. In contrast to discrete



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Figure 5.24  A component (NMOS transistor shown on right) is added with the desired parameters in the Virtuoso Schematic Editor using the Add Instance command.�

transistors that have fixed dimensions, the length and width of CMOS transistors can be chosen as per design requirements. However, because the schematic is attached to the foundry library, a parameter violating its constraints cannot be assigned. In this way, the design remains compliant with the foundry rules at the schematic level. The schematics for the frequency doubler and the matching network are also simulated using the procedure described above. Once the circuit components are simulated individually and exhibit the desired response, they are converted into symbols and simulated together in a new schematic view, which could be thought of as a test bench connecting different components. For example, the entire schematic of the VCO circuit can be converted into a symbol with the desired number of input/output ports. The VCO shown in Figure 5.25 has two inputs (VDD and Vtune), a pair of differential output ports and ground ports. Hence, it is converted into a symbol with five I/O ports as shown in Figure 5.26. Similarly, the frequency doubler and matching network schematics are also converted into symbols and connected as shown in Figure 5.27, representing a higher abstraction level of the design.

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Figure 5.25  Cell views of the VCO: the frequency doubler and the matching circuit.

Figure 5.26  Symbol generation in Virtuoso (a) Options window and (b) VCO symbol.

Figure 5.27  Transmitter circuit test bench with circuit components implemented as symbols.

All circuit blocks are typically provided with the same VDD but can have different bias voltages. As seen in the figure, it is important to consider the effect of bond-wire inductance, which is introduced when the fabricated circuit is powered up. The typical approximation of bond wires inductance is 1 nH/mm;



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however, more complex calculations can be done based on the wire’s material, diameter, and proximity to other bond wires. In this design, the inductance is specified to be 3 nH. Circuit simulation is performed in the time and frequency domains to characterize critical performance metrics. The choice of domain depends on a number of factors, including the type of circuit and its complexity, the type of simulation, and the desired output. After individual simulations at block level, the entire test bench is verified at the top-level. In Cadence Virtuoso, circuit simulation is performed using the Virtuoso ADE (Analog Design Environment) as shown in Figure 5.28. The ADE is launched from the Schematic Editor menu and the appropriate analysis (AC, DC, noise, etc.) is chosen for the corresponding circuit. The results are displayed through an appropriate display for the simulation type selected. The data display in Figure 5.29 shows the simulated output results of the VCO, frequency multiplier blocks, and the time-domain and frequencydomain output waveforms of the complete circuit. The transient analysis of the VCO output exhibits a signal at 35.5 GHz, which is doubled by the frequency multiplier to 71 GHz. Figure 5.29(c) shows the output of the matching network, which filters out the DC component. Figure 5.29(d, e) display the Sparameter and harmonic balance simulation results of the complete test bench respectively. It can be seen that the circuit generates a –10-dB output signal at approximately 71 GHz. Once acceptable simulation results are achieved, the circuit layout can be designed.

Figure 5.28  Circuit simulation in Virtuoso: (a) main ADE window, and (b) choosing ADE analysis.

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Figure 5.29  Data display of simulated circuit block outputs, transient analysis of: (a) VCO output, (b) frequency doubler output, (c) matching network output, (d) S-parameter results of the test-bench output, and (e) harmonic balance simulation of the test-bench output.



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Figure 5.29  (continued)

5.4.3  Layout Design

The schematic level design can verify the circuit performance but does not consider physical features such as interconnects and parasitic capacitances. Therefore, after optimizing component parameters in a schematic simulation, the layout of each circuit needs to be created. Here, the individual circuit components are physically laid out using the different layers of the stack-up and connected. In the Layout Editor, the designer can judiciously utilize built-in tools to verify circuit connectivity and DRC. The layout of a circuit can be generated directly from its schematic in Virtuoso XL and the instances and I/O pins are imported to the layout as shown in Figure 5.30. Because the schematic and layout are connected, clicking the components in the layout window will pinpoint the corresponding component from the schematic, resulting in easier identification.

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Figure 5.30  Layout generation: (a) specifying components to import from the schematic and (b) the schematic versus layout of frequency doubler.



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The designer can then arrange the components and enable physical connections between them by creating paths or metal shapes. This is done by selecting the suitable layer (for example, METAL 1/drawing, as seen in Figure 5.31(a)) from the Layers menu and creating the desired shape in the Editor window. The dimensions of the created object can be specified in the Properties Editor as shown in Figure 5.31(b). In layout design, bond pads need to be added to provide connectivity for wire-bonding as well as probe placement. The PDK library normally contains its own ready-to-use pad instances that can be easily inserted into the layout. Although only the top metal is required to create a connection with the bond wire, the bond pad is typically made from all the metal layers stacked on top of each other and connected through vias. In a finished chip, the passivation layer is added on top of the stack-up to prevent external damage. Because bond pads need to be accessible for connection to the chip package, they cannot be covered by this passivation layer. Hence, specific layers are designed to identify bond-pad placement for the foundry. The complete layout of the oscillator transmitter is shown in Figure 5.32 where all the components are placed and routed while fulfilling the space requirements. The next step in the design process is verifying the layout for design errors. 5.4.4  DRC

A DRC of the layout is carried out before proceeding to the next design stage. Although designers might be conscious of the main rules when designing the

Figure 5.31  Creating connections: (a) Virtuoso XL layers menu, and (b) rectangular shape drawn in Editor (below) and its material and dimensions are assigned in Property Editor.

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Figure 5.32  Layout of the transmitter circuit in Virtuoso.

layout, there is still a possibility of violation of the minor ones. It is important because the violation of any design rules would result in a higher probability and, in some cases, certainty of malfunctions in the fabricated chip. In Virtuoso, this capability is provided by built-in tools such as Assura [11] or third-party tools such as Calibre from Mentor Graphics [12]. In this design, Calibre is utilized for DRC and LVS checks and can be accessed from Virtuoso’s menu bar. In the Calibre interactive window as shown in Figure 5.33(a), the design rule files included in the PDK must be loaded so that the DRC can run according to the correct technology. The rules specified by the foundry can also be viewed before running the DRC. Calibre also provides a Result Viewing Environment (RVE), which shows a detailed report of all the DRC violations existing in the layout such metal width, length, spacing, overlap, and density as shown in Figure 5.33(a). The RVE also provides the coordinates of the DRC violation and, when clicked, places the marker at the exact location, which is extremely helpful in complex layouts. Correcting the DRC errors is an iterative process and may require considerable time for complex designs. The final aim of the DRC is to have an error-free layout, which is a mandatory requirement from the foundries. In order to better understand the DRC check, some examples are discussed next. In the first example, shown in Figure 5.34, a separation of 0.2 μm between two adjacent metal rectangles is violating the minimum spacing rule. The rule as stipulated by the foundry indicates the minimum space between two metal objects to be greater than 0.6 μm. The error is consequently removed



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Figure 5.33  Calibre interactive windows: (a) DRC and (b) RVE.

by increasing the separation to 0.7 μm. Another commonly faced error (particularly in AoC design) is the metallization density rule, which defines the minimum and maximum allowable densities of a metal in a particular layer. As seen from Figure 5.35, a continuous stretch of metal incurs a maximum density violation and is slotted to resolve the error. As part of the foundry-defined rules, the maximum width of a continuous metal object in M1 layer cannot be greater than 35 μm. In light of this rule, ground planes realized in the bottom metal layers and antenna structures in the top layers often require slotting to remain within density limits. Similarly, metal fills are added in the layout in large, unused areas to satisfy the minimum density rule. Although the DRC tools only check dummy metals, a script can be generated to automatically generate metal fill in appropriate areas as well.

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Figure 5.34  DRC minimum spacing error between metal shapes, error window (bottom), and error list (top right).

Figure 5.35  DRC maximum density error in metal shape, error window (bottom), and error list (top right).

5.4.5  LVS

LVS ensures that the netlist extracted from the schematic matches with the layout and will show the same performance after fabrication. To run LVS using Mentor’s Calibre, a process similar to the DRC is followed. In Calibre’s interactive window, the rules file from the PDK is inserted as shown in Figure 5.36 and the layout versus netlist option is selected. This allows Calibre to match the layout against the final schematic for any dissimilarities in connections. It is important therefore to select the final versions of the layout and the schematic in the input tab of the interactive window. If there are no errors, the layout is



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Figure 5.36  Initiating the LVS check through the Calibre interactive window.

complete and correct. If there are mismatches in the design, Calibre’s RVE will show a detailed report on the errors similar to that in a DRC. The designer must then go back to the layout view, fix the problems, and rerun LVS until there are no more errors. 5.4.6  Parasitic Extraction

The next step in the design process is to extract layout parasitics. This step is crucial as high-speed requirements of RF circuits make them extremely sensitive to the effects of parasitics. Once extracted, these effects are added to the circuit simulations. For sensitive blocks such as VCOs and critical radio blocks, full-wave 3-D EM simulations can also be carried out using CST or HFSS to allow the extraction of the full layout at the block level. However, built-in tools in Virtuoso also enable rigorous simulation of all high-frequency layout effects including on-chip inductors, interconnects, coupling between on-chip passives and to other interconnect structures, and substrate coupling. This procedure is carried out without any assumptions regarding parasitics or coupling, resulting in highly accurate models of components that can then replace the models that were created earlier in the design process.

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The layout can be extracted using the Verify->Extract command in Virtuoso as well as using Mentor’s Calibre. Here, the extraction is performed using Calibre, which is accessed using Calibre > Run PEX and has an interface similar to the Calibre DRC and LVS views. Calibre extracts a netlist from the circuit layout that includes parasitic resistances and capacitances associated with the components and interconnects. The extraction program uses rules defined in the technology file to recognize devices and establish electrical connections or nets; hence, the required file from the PDK must be inserted as shown in Figure 5.37(a). In the input menu, the layout must be exported in the layout tab while the schematic must be exported in the netlist tab. In the output tab, the designer can choose the type of parasitics to be extracted depending upon the type

Figure 5.37  Parasitic extraction: (a) Calibre interactive PEX window, (b) Calibre RVE showing extracted parameters, and (c) extracted capacitance visible in the layout.



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Figure 5.37  (continued)

of simulation. Commonly used parasitics include Transistor Level, inductances, and RC extraction. There are many more options that can be explored in the parasitic extraction tool (PEX), including only extracting parasitics for a few nodes instead of every node and changing the lumped reference node (which allows computing parasitics between two components instead of the ground). After the setup is complete, the extraction process can be started as shown in Figure 5.37(a). Once the extraction is completed, the RVE window shown in Figure 5.37(b) pops up and shows the extracted parameters. Another window called the Calibre View setup will also appear and allows the designer to open the extracted components in the schematic view. The extracted view of the layout can be opened from the library manager and shows devices and parasitic elements dispersed throughout the design as shown in Figure 5.37(c).

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5.4.7  Post-Layout Simulation

After verification of the layout matches the schematic, simulations can be performed on the extracted layout to determine its performance. Here, the extracted parasitic capacitances based on the physical dimensions of the devices and interconnects are included in the simulation, therefore providing a more realistic analysis. Simulation of the extracted layout is performed via ADE by setting up the type of simulation, input stimulus, and output display, in the same way as the original schematic was simulated. However, in the environment tab of the ADE, the extracted view of the project must be selected from the switch view list option as shown in Figure 5.38, so that the new simulation takes into consideration all the parasitic elements of the layout. The switch list is an ordered list of cell views that determines what view (i.e., schematic, Calibre) is added as a netlist. Next, the simulation is run and after completion, the outputs can be plotted and compared to the results of the schematic simulation. If there are significant discrepancies, it is often useful to look at the textual netlist and check sensitive nodes for large parasitic capacitances or resistances. The circuit is then reoptimized until it gives the same response in the presence of associated parasitic elements. Once the post-layout simulations yield acceptable results, the fabricated chip is more likely to perform as required.

5.5  Cosimulation The most important part of the design cycle is the cosimulation of the on-chip antenna and circuits. Due to their close proximity, it is imperative for better performance that their interference effects on each other be analyzed and mitigated. Because there is no comprehensive tool for simultaneous design and cosimulation of antenna and circuits, it is carried out separately using both simulation environments, as explained next. 5.5.1  Simulating the Circuit in EM Simulator

The goal of cosimulation in the EM simulator is to analyze the coupling between the antenna and the metallic parts of the circuit and the resultant degra-

Figure 5.38  Specifying the extracted view in ADE environment for post layout simulation.



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dation in the antenna’s performance. Therefore, it is important that the antenna be simulated with the circuit and the CMOS stack-up. Because the circuit is typically not designed in the EM simulator, its layout is imported from Cadence, for which there are two possible methods: 1. Importing the circuit layout from the IC simulator to the EM simulator; 2. Manually drawing a representation of the circuit in the EM simulator. Both methods are discussed next. 5.5.1.1  Importing the Circuit Layout in the EM Simulator

The final layout of the circuit can be exported from an IC simulator and imported to an EM simulator and analyzed with the antenna. However, the circuit layout consists of a large number of metal interconnects, vias, and transmission lines and is extremely complex, so, if imported in its entirety, it can lead to a very long simulation time. Therefore, usually only the top metal layer is exported containing larger metallic structures such as inductors, dummy metal, and bond pads, which have a greater probability of affecting the AoC’s performance. It must be remembered that the circuit layout is included in the EM simulation to analyze its negative effects on the antenna’s radiation. Therefore, it can be simplified to a certain extent unlike the antenna’s layout, which must be imported to the IC simulator in its original form. The circuit is exported from Cadence via file > export > stream, which opens to the Cadence export setup shown in Figure 5.39. Here, the file to be exported can be specified and the designer can choose which layers are to be exported. As can be seen from the figure, for simplicity, only the metal layers and pads are included in the export file. Cadence then generates a file in the GDSII format, which can be imported in HFSS. The GDSII stream format, commonly known as GDSII, is the standard file format used for interchange of information related to ICs or IC layout. It is

Figure 5.39  Exporting circuit layout from Cadence.

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a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form. The GDSII is used to send IC information for fabrication as well as for exchange between different CAD programs. In this case, the GDSII file is used to transfer layout information from Cadence to HFSS so that it can be simulated with the on-chip antenna. It is imported directly into HFSS using the Modeler > import command and selecting the specified file. While importing, the designer again has the choice of selecting the layers to be imported. Figure 5.40 shows the layout of the driving circuit that has been imported from Cadence. The layout initially appears in the form of a 2-D model without any thickness or material specified. At this stage, the layout can be further simplified by removing components that are not likely to influence antenna performance. For example, the transistor models are removed as they are extremely small compared to the AoC. Through the Materials Library, specific materials such as copper can be assigned to the metal layers in the layout. In order to convert the 2-D layout to 3-D components, the designer can select the concerned structures and edit their thickness according to foundry specifications as shown in Figure 5.41. Once this is done, the circuit is ready to be simulated with the antenna. The limitation of this cosimulation is that the layout of the circuit represents inactive, nondriven metallic structures without any currents or voltages. Although it can help in analyzing the coupling between the antenna and the circuits to a great extent, it is still not an ideal representation of the actual circuit.

Figure 5.40  Circuit layout imported into HFSS.�



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Figure 5.41  Converting the 2-D layout into a 3-D structure.

5.5.1.2  Modeling the Circuit in the EM Simulator

The second method to include the circuit in EM simulations is to manually model it in the simulator as shown in Figure 5.42. Using the Draw commands, nearly all components of the layout can be recreated in HFSS with the desired dimensions and material specifications. However, this is a time-consuming and tedious approach, feasible only when the circuit is relatively simple and is expected to have a small effect on the antenna. Due to a simpler representation of the circuit, this approach also leads to a cosimulation with lower accuracy. An-

Figure 5.42  Circuit layout modeled in HFSS as: (a) real representation through discrete components and (b) an approximation using a metal plate.

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other approach often used by designers is to model the entire circuit or dummy metal area as a uniform metal surface to assess the worst-case effects on the antenna. This approach leads to an overestimation of the coupling effects, but is helpful in maintaining a reasonable simulation time. Once the circuit layout is placed in the EM simulator, using any of the methods described above, the antenna is simulated again. The simulation process is no different from that descried in Section 5.3.2. The antenna is excited and its impedance parameters and radiation characteristics are observed. The impact of circuit components on the AoC’s performance is quantified in terms of change observed in these parameters. Pinpointing the specific components that are affecting the antenna is not a straightforward process. Rather, it is based on hit and trial and different components can be tuned or moved to check their effect on the antenna. For example, moving a large inductor or transmission line away from the antenna and the resultant change in its radiation properties can give some idea of the relationship between both components. Due to the limited space available on the chip, the front end and the antenna are placed close together, so some influence of the circuit on the antenna’s performance is inevitable. Hence, a certain level of reoptimization is unavoidable. However, if the circuit accounts for a considerable degradation in the radiation, both the antenna and the circuit layout require substantial redesign. 5.5.2  Simulating the Antenna in the IC Simulator

In the IC simulator, the effects of the antenna are included at two design stages: the schematic and the layout. In the schematic, the antenna’s parameters are added as a block at the output of a transmitter or at the input to a receiver to investigate the effect of the antenna’s input impedance on the circuit. However, in the layout stage, the antenna’s footprint needs to be included for fabrication as well as to perform DRC. The procedure for cosimulation at both stages is described next. 5.5.2.1  Importing the Antenna S-Parameters into Virtuoso

The antenna’s S-parameters can be extracted from HFSS in the form of a Touchstone file and imported into Virtuoso. Touchstone files are used to store the measured or simulated S-parameter data of an n-port device and have the extension .sNp, where N is the number of ports. Being a single-port device, the antenna’s parameters are stored in an .s1p file format. In the schematic, a single port component is inserted from the analog library and connected to the output of the transmitter as shown in Figure 5.43. This component can be made to represent the AoC by linking it to the antenna’s S-parameter file through its Properties Editor. The antenna’s S-parameters are influenced by the port impedance selected in the EM simulator (see Figure 5.9), so it is important to en-



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Figure 5.43  Inserting the antenna’s S-parameters into the circuit schematic as an n-port component.

sure that the output impedance of the circuit is consistent with the port impedance. If the port impedance is specified as 50Ω, the circuit’s output impedance must also be 50Ω. If the antenna and circuit are to be conjugately matched, the port impedance and the circuit output impedance should be set as the complex conjugate of the antenna’s impedance. Moreover, since the antenna’s impedance is influenced by the packaging, the antenna block added to the circuit should contain the S-parameters of the complete AoC simulation and not just the standalone antenna. Alternatively, in receiver design, the antenna’s S-parameters can be added as a port between the signal source and input of the front end.� 5.5.2.2  Importing the Antenna Layout into Virtuoso

The antenna’s layout must be a part of the finalized IC layout in order to be fabricated. However, before this is possible, a lot of design effort is required to position the antenna on the chip such that it is adequately far from inductors and bond pads and does not incur any DRC violations. There are two ways to add the antenna layout in an IC simulator: 1. Import the antenna layout from the EM simulator. 2. Draw the layout directly in the IC simulator. In the first method, the designer selects the structures to be exported from the EM simulator (which in this case are the antenna and the AMC layer) and exports them as a GDSII file. The layout file is imported into Virtuoso using the file > import > stream command. Figure 5.44 shows the components of the monopole antenna selected for export in HFSS and subsequently added as a layout in Virtuoso. A common problem is that Virtuoso maps the imported layout to the wrong layers, for instance, assigning the antenna to an active device layer instead of a metal layer. To solve this, the layers need to be manually

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Figure 5.44  Importing the AoC layout from (a) HFSS to (b) Virtuoso.

remapped to the intended positions. Another issue encountered is that the imported antenna layout is off-grid and needs to be moved to align to the grid in the layout window. The second method is to draw the antenna layout directly in the Virtuoso layout editor. The different parts of the antenna can be drawn as blocks and lines in the desired metal layers. Although this method allows greater flexibility in adapting the antenna to the layout, it is not feasible for complex antenna designs having large number of elements. When the antenna is in place with the circuit’s layout, the DRC and LVS are performed again. Similar to the DRC examples discussed in Section 5.4.4, the antenna also undergoes a detailed rule check according to the foundry specifications. To comply with foundry rules, slots and metal fills need to be added in specific areas in the chip layout. A good designer must be well aware of these rules beforehand and consider them during antenna design. However, if they are not catered for and become apparent in the DRC, suitable modifications need to be done to the antenna structure. Moreover, sharp bends in the antenna can also add capacitance along the metal lines and must be considered in layout. To examine the effects of any modifications in antenna design, it requires resimulation and optimization in HFSS and is then imported back into Virtuoso to run DRC again. This process is repeated until there are no DRC violations. The next step is LVS and post-layout simulation as described in Section 5.4.5. Although the antenna is not part of the schematic, an LVS check to verify its connection to the circuit is extremely important. If the LVS check is cleared and post-layout simulations are successful, chip design is complete and can be sent for fabrication. Due to the exhaustive iterations required to reach a layout that complies with the DRC while also showing good antenna and circuit performance, the finished design is indeed a moment of triumph for the designer. The final chip layout of the 71-GHz transmitter is shown in Figure 5.45. It can be seen that the layout is also designed to accommodate measurement requirements. A second circuit is fabricated on the chip to allow for standalone circuit measurement. Furthermore, the antenna is not connected to the driving circuit



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Figure 5.45  Layout of the optimized 71 GHz transmitter chip with on-chip monopole antenna.

directly, but rather through a short transmission line that, when removed, will allow standalone characterization of the antenna. Bond pads are also added at the antenna interface to enable probe-based measurements. However, it must be remembered that these features are only required at the prototyping stage and may be eliminated at the mass-manufacturing stage, leading to a more compact chip. It should be remembered that AoC design is not a straightforward process and the design flow described here is not absolute. Designers may often find themselves in an iterative cycle between the two simulation environments. Sometimes the antenna may show acceptable performance when simulated with the circuit in an EM simulator but may incur DRC violations when imported into the IC simulator. However, if the antenna design is optimized to fit into the layout without any violations, it may not show optimum performance. Hence, a number of different design flows can be followed depending upon the complexity of the design as well as the ease and preferred simulation method of the designers.

5.6  Fabrication Once layout is complete, the chip is ready for tape-out. Tape-out is the term used for creating the final GDSII file that the foundry uses to manufacture an IC. In the foundry, the design again goes through a thorough verification process. After this check is done, prototypes are fabricated and packaged if required. The time taken for the fabricated chip to be ready varies from foundry-to-foundry but generally lies in the range of 3 to 4 months. After a successful prototyping

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phase, the designer may choose to scale up to higher-volume production. The designed transmitter chip is fabricated using the TSMC 0.18-μm CMOS process as shown in Figure 5.46. The figure also shows slots and dummy metal fill added to the layout to meet metal density rules. The total area of the chip is 1.5 mm × 1.5 mm, including the antenna covering an area of 0.6 × 0.8 mm2 and the circuit occupying 0.56 × 0.50 mm2. Once the chip is fabricated, the superstrate layer is to be placed on top. Typically, wire-bonding is used to connect on-chip bond pads to the external PCB. To attach the superstrate, connections from pads to the carrier PCB are made using inkjet printing technology. An isolation layer is first printed on top of the chip covering the circuits and leaving the required bond pads exposed (VDD, Vbias, GND). The exposed pads are connected to chip edges using inkjet-printed silver traces as shown in Figure 5.47(a). The superstrate layer made of PREFERM FLX is simply cut according to chip dimensions and placed on top of the AoC. The chip package is 3-D printed according to the optimized dimensions and attached to the package supports as shown in Figure 5.47(b).

5.7  Measurement and Characterization 5.7.1  Standalone Characterization

For ease of characterization, an identical circuit is fabricated on the chip and serves specifically as the device under test (DUT) for the purposes of testing. The DUT is powered up through DC probes landed on the circuit DC pads

Figure 5.46  Micrograph of the fabricated 71-GHz transmitter chip with an integrated antenna.



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Figure 5.47  (a) Inkjet-printed connections on chip surface, and (b) 3D printed Fresnel lens package.

while the ground-signal-ground (GSG) output pads are connected to a spectrum analyzer through RF probes as shown in Figure 5.48(a). The circuit generates an output signal of –67.9 dBm at 70.846 GHz as shown in Figure 5.48(b). After de-embedding of the signal loss due to RF cables (54.3 dB), the measured output power is found to be –13.6 dB, showing a 1.5-dB difference from the simulated result, which is attributed to calibration and measurement tolerances. Similarly, the standalone characterization of the antenna is done by physically destroying the transmission line connecting the antenna and the circuit through a focused ion beam (FIB) as shown in Figure 5.49(a). The reflection coefficient and radiation pattern of the antenna is measured using a 16-dBi reference horn antenna in a specialized anechoic chamber. The measurement setup used for standalone measurements is shown in Figure 5.49(b), which involves probe-based excitation of the antenna. The antenna is placed on a plastic chuck to prevent reflections and is excited using GSG probes. As discussed in previous chapters, the on-chip circuit and measurement equipment has a significant effect on the AoC’s measured results. This is evident from the monopole’s reflection coefficient plotted in Figure 5.50(b) where the results show an error of nearly 44%. To analyze the root of these errors,

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Figure 5.48  Characterization of on-chip circuit: (a) probe connection to circuit pads (microscopic view), and (b) spectrum analyzer output of driving circuit.

post-processing is done in which the antenna with the measurement setup is modeled in HFSS as shown as shown in Figure 5.50(a) and resimulated. Through this post-simulation, it is concluded that there are two major reasons for the measurement discrepancies. The first is the coupling effect between the AoC and the driving circuits. The inductors, capacitors, interconnection lines, and dummy metal sheets in the circuit part can lead to EM coupling when the AoC is excited. The second error source is the measurement probe, which induces unwanted coupling between the probe tips and the antenna due to its metallic exterior. Additionally, although the inner impedance of the probe is



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Figure 5.49  Standalone antenna characterization: (a) disconnecting the antenna from the circuit cut through FIB, and (b) probe-based measurement setup.

de-embedded through calibration, its large conductor body still behaves as a load for the antenna, therefore skewing the reflection coefficient results. Based on these observations, the probe body is modeled in the HFSS and resimulation of the antenna shows a much closer match to measurements. The probe also influences the radiation pattern measurements of the AoC through self-radiation and reflections. These influences are also de-embedded from measurements through post-measurement simulations. 5.7.2  Active Characterization

The standalone measurements of the antenna and circuit are done to analyze their respective performances with respect to simulated results. To see the performance of AoC in the intended application scenario, active characterization is done. The measurement setup is shown in Figure 5.51(a) in which the on-chip circuit is powered using DC supply and the antenna’s radiation is measured us-

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Figure 5.50  Post measurement simulations (a) AoC with probe model and (b) simulation results.

ing a W-band reference horn antenna with a gain Gr of 24 dBi at 75–110 GHz. The receiving antenna and the AUT are aligned in a boresight-to-boresight configuration with a distance of 20 cm, which satisfies the far-field condition at 71 GHz. The RF signal received by the reference horn antenna was then transmitted to the spectrum analyzer through the RF cables and the mixer with a to-



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Figure 5.51  (a) Measurement setup for AoC active characterization and (b) simulated and measured radiation patterns of the packaged AoC: E-plane (left) and H-plane (right).

tal path loss of 51.2 dB at the operating frequency. Using the Friis transmission equation, the absolute gain of the packaged AoC is found to be 6.8 dB, while its simulated and measured radiation patterns are shown in Figure 5.51(b). The collective effect of applied gain enhancement methods gives the AoC a gain boost of nearly 20 dB, validating their effectiveness.

5.8  Conclusion This chapter has provided readers with a walkthrough of a real AoC design example indicating the intricacies involved in an antenna and circuit codesign cycle. It is seen that in absence of a unified simulation environment the design process requires learning and mastering different tools to obtain insights and hence the confidence for achieving a robust design on silicon. This, at times,

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is not only cumbersome but also a cause of increased design times. On the positive side, this leaves a huge room for improvement in the current simulation tools and development of new ones that could either encompass the entire design cycle on one platform or provide a seamless integration between antenna and circuit simulators.

References [1] Cadence, “Virtuoso Layout Suite,” https://www.cadence.com/en_US/home/tools/custom-ic-analog-rf-design/layout-design/virtuoso-layout-suite.html. [2] Synopsys, “Chip Design,” https://www.synopsys.com/implementation-and-signoff.html. [3] Siemens Digital Industries Software, “Calibre Design Solutions,” https://eda.sw.siemens. com/en-US/ic/calibre-design/. [4] Zhang, H., and A. Shamim, “Gain Enhancement of Millimeter-Wave On-Chip Antenna Through an Additively Manufactured Functional Package,” IEEE Transactions on Antennas and Propagation, Vol. 68, No. 6, June 2020, pp. 4344–4353. [5] Zhang, H., “Gain Enhancement Techniques for Mm-Wave On-Chip Antenna on Lossy CMOS Platforms,” Thesis, CEMSE, KAUST, 2019. [6] Ansys, “Ansys HFSS: High Frequency Electromagnetic Field Simulation Software,” https://www.ansys.com/products/electronics/ansys-hfss. [7] Weste, N. H. E., and D. M. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Reading, MA: Addison Wesley, 2011. [8] Yoon, Y. J., and B. Kim, “A New Formula for Effective Dielectric Constant in MultiDielectric Layer Microstrip Structure,” IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524), October 2000, pp. 163–167. [9] Cook, B. S., and A. Shamim, “Utilizing Wideband AMC Structures for High-Gain Inkjet-Printed Antennas on Lossy Paper Substrate,” IEEE Antennas and Wireless Propagation Letters, Vol. 12, 2013, pp. 76–79. [10] Ghaffar, F. A., et al., “24-GHz LTCC Fractal Antenna Array SoP with Integrated Fresnel Lens,” IEEE Antennas and Wireless Propagation Letters, Vol. 10, 2011, pp. 705–708. [11] Cadence, “Assura Physical Verification,” https://www.cadence.com/en_US/home/tools/ digital-design-and-signoff/silicon-signoff/assura-physical-verification.html. [12] Mentor, “IC Verification and Signoff Using Calibre,” https://www.mentor.com/products/ ic_nanometer_design/verification-signoff/.

6 Future Trends in AoC AoC has become a highly sought-after research domain in the RF and millimeter-wave community. In the last decade, silicon-based semiconductor technologies have enabled cost-effective and frequent integration of on-chip antennas than seen earlier. By implementing the antenna directly on the chip, AoC allows the ultimate on-die integration of entire wireless transceivers. Publications in the field of on-chip antenna design and integration have seen an upsurge in the past few years. However, numerous challenges still persist in achieving highperformance, compelling designers to introduce novel techniques and strategies with every passing day. It is believed that on-chip antennas will have a major impact in the future development of millimeter-wave and terahertz communication systems, particularly because reduced antenna sizes and the low cost of commercial-scale CMOS processes has the potential to rapidly push AoC integration forward. AoC designers are confronted with an interdisciplinary set of challenges ranging from incompatible semiconductor stack-ups to the codesign of antennas and circuits, and these challenges cannot be overcome by simply transferring classical antenna and circuit design techniques to the chip. Therefore, research into novel gain-enhancing methods, simulation strategies, and measurement setups is imperative to resolve these design challenges. Like any other technology, an AoC integration can only be commercially viable when it is usable in real-life applications. To this end, AoCs are finding use in specialized radars, sensors, and biomedical devices that impose compactness as a critical requirement. As the culmination of this book, this chapter attempts to predict the future trends and roadmap of AoC development in the coming years. By doing 229

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so, prospective students and researchers are provided with avenues for potential contributions in this domain.

6.1  Performance Enhancement: A Continuing Challenge Low radiation efficiency of antennas on silicon substrates has been a bottleneck in the widespread adaptation of AoC technology. As discussed in earlier chapters, the two major loss mechanisms responsible for this performance degradation are the low resistivity of bulk silicon and its high permittivity. To mitigate these losses and, in turn, boost the antenna’s radiation, various gain-enhancing methods are also investigated. These included modifications to the underlying silicon substrate, the dielectric, metal stack-up, and addition of off-chip components. Substrate parameters such as thickness and resistivity can be optimized to make it suitable for on-chip integration. The intermetal layers of the CMOS process can be exploited by implementing reflecting surfaces that boost’s AoC gain. Off-chip components such as dielectric superstrates, lenses, and resonator structures can enhance the gain to a great degree through focusing and impedance-transforming mechanisms. In order to further enhance gain, researchers have endeavored to introduce new layers and materials to the existing CMOS stack-up to allow novel AoC integration. Many of these techniques are focused on using the existing stack-up to the advantage of the antenna. Designing antennas on top of lowpermittivity substrates is being explored to achieve wider bandwidths and higher gains [1]. The insertion of ferrite materials sandwiched between the antenna and the oxide layer is also being investigated [2]. Another reason to utilize the existing CMOS stack-up for gain enhancement is to avoid compromise on the compactness of the system. One particularly interesting development is the utilization of silicon substrate as a dielectric resonator antenna. Also called chipscale dielectric resonator antenna (CSDRA), this technique tends to integrate the DRA inside the chip in contrast to conventional DRAs that are placed on top of the chip and thus increasing the system form factor [3]. Due to the lossy nature of silicon, a lot of attention is also being given to techniques that separate the antenna from the substrate while ensuring that it remains a part of the chip. Recent advances in inkjet printing technology have led to the possibility of printing micrometer-scale antennas on top of CMOS chips [4, 5]. In this process, first a relatively thick insulation layer is printed on top of the chip to isolate the antenna from the lossy Si substrate. The antenna is then printed on top of the insulating layer and connected to on-chip circuits using printed interconnects as shown in Figure 6.1. In some cases, a metal layer may also be printed as a ground plane to further enhance the isolation between the antenna and the substrate. Consequently, inkjet-printed antennas do not



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Figure 6.1  Inkjet-printed antenna on top of the CMOS IC (layer dimensions not to scale).

experience the loss induced by the low-resistivity silicon substrate and are also somewhat free of constraints imposed by the chip, its internal circuits, and metal fill sections. The vertically integrated, additive nature of inkjet printing has the potential of high-level integration in SoC and SoP systems [6]. It could eliminate complex procedures such as masking and etching, thus resulting in a cleaner process that produces less waste than traditional methods. Key research challenges of this area are high printing accuracy to fabricate submillimeter interconnects and pads on a chip surface that is uneven due to presence of metal fill. Moreover, issues related to RF structure design, such as the discrete thicknesses and properties of common printing material, as well as the difficulties of multilayer printing including stacking, bonding, and alignment of layers, will have to be resolved to prove printing as a viable technology for AoC design. AoC and AiP have emerged as competing technologies in the past decade, with the former providing a higher level of integration and compactness, and the latter achieving better radiation performance. This has led to a renewed interest in hybrid integration strategies aimed at combining both approaches to yield high-performance integrated antennas. To this end, work on AoCs assisted by AiPs and other package elements such as off-chip grounds and metallic enclosures is showing promising results [7, 8]. Although the above-mentioned techniques have largely been successful in achieving higher gains, any type of post-processing or deviation from the standard processes of chip manufacturing always leads to higher costs. Hence, the commercial viability and fabrication compatibility remain open questions for achieving robust performance-enhancing methods in the coming years.

6.2  Codesign and Multifunctional Role of AoC Future research is geared towards the development of millimeter-wave and terahertz front-end modules in a fully integrated manner with high efficiency. In this respect, large free-space path loss, line-of-sight propagation, unwanted

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crosstalk from circuits in the proximity of antennas, and high losses associated with feedlines and interconnects are all critical issues for AoC design in future wireless devices. Codesign methodologies and integration of antenna and frontend circuitry were introduced in Chapter 4 as a potential solution to these issues. These encompass multiple aspects of integration ranging from impedance matching to efficient layout strategies, crosstalk prevention measures, and allowances in the AoC layout to ease testing and characterization. This concept of cointegration is also being explored under the terminology of active integrated antenna (AIA) and has the advantages of higher efficiency and shorter design cycles with a lower chance of integration errors. Moreover, up until now, the IC accommodates the antenna predominantly as a radiating structure. To that end, one important development expected from future AoCs is to perform frontend functions such as matching, power combining, and interconnection alongside the radiation functions. This concept, also touched upon briefly in Section 4.4.3, was recently proposed as Unified Integrated Circuit Antenna (UNICA) and promises a more seamless and direct integration than AIAs [9–11]. An example of an antenna-circuit integration is shown in Figure 6.2(a), in which impedance matching and power-combining capabilities have been integrated into the antenna. Such an integration can allow the formation of large array structures as shown in Figure 6.2(b) while minimizing the number of passive components. Moreover, the reduced device sizes at millimeter-wave and terahertz frequencies along with rapid scaling of semiconductor technologies have the potential to enable integration of active devices within the antenna to realize a complete front-end module in a single unified design space.

6.3  Specialized Radios and Implantable Applications Although on-chip antennas have radically reduced system sizes and the resulting interconnection losses, they still have a long way to go before becoming the primary choice for conventional wireless communication applications. This is because AoCs are outperformed by their off-chip counterparts in terms of radiation efficiency and communication range, which are essential for wireless applications. However, due to their small size and seamless integration with onchip circuits, they are ideal for low-power and short-range radio transceivers. One such prominent application is in-vivo wireless biomedical microsystems. These devices can be used for a myriad of monitoring, diagnostic, and therapeutic applications ranging from cardiac pacemakers and defibrillators to emerging methods such as visual prosthesis, brain computer interfaces, and biomedical telemetry. Although the design requirements of such devices are application-specific, they share the common constraints of size, power, and functionality.



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Figure 6.2  Unified IC antenna with on-antenna impedance matching and power combination: (a) unit cell and (b) antenna array with amplifying components.

The primary considerations of antenna design for in vivo applications include operating frequency, antenna size, and losses due to tissue absorption. For devices to be effectively implanted in living tissue, the total system size should be extremely small. Therefore, compared to other applications of AoC technology, biomedical implants demand a much higher level of miniaturization and specialized packaging. Similarly, the performance requirements of implantable

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AoCs are also quite stringent as they should be able to operate in the presence of highly absorptive living tissues. An implication of the area constraints is that many of the gain-improving techniques (lenses, DRAs) commonly used in other AoC applications cannot be adopted in implantable devices making the task of achieving high gain, all the more challenging. In addition, implantable systems need to comply with strict safety requirements compared to other applications. For this reason, biocompatibility of the sensor, specific absorption rate (SAR), and intersubject variability shall become an integral part of the AoC design process in the coming years. Few such systems have already been demonstrated with real-life applications such as a single chip glaucoma monitoring transceiver that could be inserted into the eye of a patient to measure intraocular pressure as illustrated in Figure 6.3 [12, 13].

6.4  Energy-Harvesting AoCs An avenue of research that can benefit greatly from compact integrated antennas is the zero-power self-sustainable on-chip circuits. Based on the concept of RF energy harvesting, there has been considerable progress in this direction over the last decade. Devices fulfilling their power requirements through energy harvested from specified sources or the ambient environment have been demonstrated. However, most of these devices harvest energy through antennas fabricated on a separate substrate and attached to the chip through wire-bonding, thus resulting in larger volume of the implant or sensor, increased cost, and decreased reliability. Integration of the energy-harvesting antennas on the die is an elegant solution for low-cost, compact, reliable, and mass-producible, singlechip circuits. This level of integration offers significant clinical and laboratory advantages, especially for in-vivo devices where power supply and maintenance are critical issues. Other applications include but are not limited to agricultural,

Figure 6.3  Glaucoma-monitoring CMOS SoC for intra-ocular pressure measurement



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environmental, and industrial sensors that are not easily reachable for maintenance. This capability was demonstrated in a battery-less, millimeter-sized SoC device designed for mapping and localization of hydraulic fractures in pipelines [14]. Miniaturization is an imperative step towards achieving ubiquitous sensor nodes and imposes serious challenges on energy harvesting and data communication. With the current state of the semiconductor technology, integrated electronic circuits occupy only a fraction of chip space and the overall dimension of the chip is dominated by the size of antennas and energy storage components. A reduction in size of the antenna leads to degradation in power transfer efficiency and a consequent decrease in harvested power and operating range. To date, very few designs have managed to achieve a range-to-size ratio that could meet IoT application requirements. To realize robust, self-sustainable SoCs, an interplay between antenna size and performance will be the key challenge. An essential part of energy-harvesting systems is the power management module (PMM), which employs storage components such as large on-chip capacitors. Mitigation of unwanted coupling is already a key concern in AoC design and the presence of large storage capacitors in close proximity to the antenna can potentially disrupt the radiation pattern. Therefore, well-thought-out component placement and layout in energy harvesting on-chip antenna systems presents another design challenge. Although on-chip energy harvesting helps to get rid of batteries and the large form factor associated with them, the inclusion of a separate antenna for energy-harvesting functionality leads to a larger chip size. In a simple energyharvesting transceiver design, the total number of AoCs would be 3, with at least two antennas for transmission and reception and one for energy harvesting. A good strategy is to reuse the receiving antenna to harvest power as well as receive data, thereby reducing the number of antennas to two. To further minimize chip space, designers will need to focus on ways to use the same on-chip antenna for multiple purposes while combating associated interference and coupling issues.

6.5  Miniaturization of Low-Frequency AoCs While the higher-frequency bands such as millimeter-wave and terahertz show a promising future in terms of AoC-based imaging and radar applications, utilization of on-chip antennas at lower frequencies (