Analog electronics with LabVIEW 9780130470652, 0-13-047065-1

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Copyright Libr a r y of Congr e ss Ca t a login g- in - Pu blica t ion D a t a Ashley, Kennet h L. Analog elect ronics wit h LabVI EW / Kennet h L. Ashley. p. cm . — ( Nat ional I nst rum ent s virt ual inst rum ent at ion series) I ncludes bibliographical references and index. I SBN 0- 13- 047065- 1 ( pbk. : alk. paper) 1. Elect ronics. 2. Elect ronic circuit s—Com put er- aided design. 3. LabVI EW. I . Tit le. I I . Series. TK7816 .A84 2002 621.381- - dc21 2002072656 Edit orial/ product ion supervision: Pat t i Guerrieri Cover design direct or: Jerry Vot t a Cover designer: Nina Scuderi Manufact uring m anager: Alexis R. Heydt - Long Publisher: Bernard Goodwin Edit orial assist ant : Michelle Vincent i Market ing m anager: Dan DePasquale © 2003 Pearson Educat ion, I nc. Publishing as Prent ice Hall PTR Upper Saddle River, NJ 07458 Prent ice Hall books are widely used by corporat ions and governm ent agencies for t raining, m arket ing, and resale. For inform at ion regarding corporat e and governm ent bulk discount s please cont act : Corporat e and Governm ent Sales ( 800) 382- 3419 or corpsales@pearsont echgroup.com All product s or services m ent ioned in t his book are t he t radem arks or service m arks of t heir respect ive com panies or organizat ions. All right s reserved. No part of t his book m ay be reproduced, in any form or by any m eans, wit hout perm ission in writ ing from t he publisher. Print ed in t he Unit ed St at es of Am erica 10 9 8 7 6 5 4 3 2 1 Pearson Educat ion LTD. Pearson Educat ion Aust ralia PTY, Lim it ed Pearson Educat ion Singapore, Pt e. Lt d. Pearson Educat ion Nort h Asia Lt d. Pearson Educat ion Canada, Lt d.

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National Improvements | Virtual Instrumentation Series Ke n ne t h L. Ash le y Analog Elect ronics wit h LabVI EW Je ffr e y Y. Be yon Hands- On Exercise Manual for LabVI EW Program m ing, Dat a Acquisit ion, and Analysis Je ffr e y Y. Be yon LabVI EW Program m ing, Dat a Acquisit ion, and Analysis M a h e sh L. Ch uga n i, Abha y R. Sa m a nt , M ich a e l Ce r r a LabVI EW Signal Processing N e sim i Er t ugr u l LabVI EW for Elect ric Circuit s, Machines, Drives, and Laborat ories Ra h m a n Ja m a l · H e r be r t Pich lik LabVI EW Applicat ions and Solut ions Sha h id F. Kh a lid Advanced Topics in LabWindows/ CVI Sha h id F. Kh a lid LabWindows/ CVI Program m ing for Beginners H a ll T. M a r t in · M e g L. M a r t in LabVI EW for Aut om ot ive, Telecom m unicat ions, Sem iconduct or, Biom edical, and Ot her Applicat ions Br u ce M ih ur a LabVI EW for Dat a Acquisit ion Jon B. Ola nse n · Er ic Rosow Virt ual Bio- I nst rum ent at ion: Biom edical, Clinical, and Healt hcare Applicat ions in LabVI EW Ba r r y Pa t on Sensors, Transducers, and LabVI EW Je ffr e y Tr a vis LabVI EW for Everyone, second edit ion Je ffr e y Tr a vis I nt ernet Applicat ions in LabVI EW

Preface This book present s a st udy of analog elect ronics as a st and- alone course or as a course t o be augm ent ed by one of t he m any com plet e undergraduat e t ext books on t he subj ect . Theory and closely coupled laborat ory proj ect s, which are based ent irely on com put er- based dat a acquisit ion, follow in a sequent ial form at . All analyt ical device charact erizat ion form ulat ions are based exact ly on SPI CE. I n addit ion t o t radit ional curricula in elect rical engineering and elect ronics t echnology, t he course is suit able for t he pract icing engineer in indust ry. For t he engineer wit h a general undergraduat e elect ronics background, for exam ple, t he course of st udy can provide an upgrade in basic analog elect ronics. Under t hese or sim ilar circum st ances, it can be t aken as self- paced or wit h m inim um supervision. Two course sequences are possible, depending on t he em phasis desired: •

•

For a course t hat st resses MOSFET charact erizat ion and circuit s, beginning wit h Unit 1 and following t he sequence is recom m ended. A brief review of relevant circuit analysis and t he m ost rudim ent ary basics of elect ronics are present ed init ially, wit h associat ed proj ect s. The proj ect s include an int roduct ion t o LabVI EW program m ing along wit h t he m easurem ent s of basic circuit s. The program m ing aspect s are direct ly relevant t o t he t hrust of t he course; t hey em phasize t he m easurem ent of analog elect ronics circuit s. The st udent is t hus provided wit h a basic underst anding of LabVI EW concept s used t hroughout t he proj ect s. I f, on t he ot her hand, int erest is direct ed m ore t oward LabVI EW and com put er dat a acquisit ion, device charact erizat ion, and circuit sim ulat ion, t he appropriat e beginning sequence is Unit s A t hrough C. The associat ed proj ect s are Proj ect A, Proj ect s B, Proj ect C1, and Proj ect C2. Proj ect A is a program m ing and m easurem ent exercise t hat em phasizes and explores t he use of LabVI EW DAQ soft ware, t he discret e nat ure of analog- t o- digit al and digit al- t o- analog conversions, LabVI EW- based volt m et ers wit h aut oranging, ac volt m et ers, and sim ult aneous sending and receiving of waveform s init iat ed wit h a funct ion generat or. This is followed wit h proj ect s on t ransist ors and t ransist or circuit s, which are based on t he bipolar j unct ion t ransist or. Alt hough t he BJT is losing ground as t he m ost im port ant t ransist or in elect ronics ( com pared t o t he MOSFET) , it s inherent ly m ore com plex behavior provides for a rich array of circuit sim ulat ion form ulat ions and design challenges. The proj ect s include t he m ix of NPN and PNP devices in a single am plifier. The t ransist ors recom m ended are t he com plem ent ary pair NTE 186 ( 2N6288) and NTE 187 ( 2N62xx) . The t ransist ors are rat ed at 3 A and are t herefore alm ost indest ruct ible. At t he m uch lower current levels of t he proj ect s, device heat ing is negligible, which is im port ant , as all m easurem ent s assum e t hat t he circuit is at room t em perat ure. Also, highlevel m odel effect s are avoided, whereas low- level effect s abound.

Wit h bot h approaches, all t he m easurem ent LabVI EW program s are provided. Many of t he ext raordinary feat ures provided by LabVI EW are included in t he program s. The program s t herefore m ay serve addit ionally as a t ut orial in advanced aspect s of LabVI EW. The basics of operat ional am plifiers and t heir applicat ions are t reat ed in t wo unit s and t wo proj ect s. The book form at consist s of one or m ore unit s of background m at erial for each laborat ory proj ect . A given set of t heoret ical unit s and t he associat ed proj ect have a relat ed Mat hcad problem s file ( Problem xx.m cd) and Mat hcad exercise file ( ExerciseXX.m cd) , relat ing t o t he t heory and proj ect , respect ively. The files are also in a pdf form at ( Problem XX.pdf, ExerciseXX.pdf) . A Mat hcad file ( Proj ect XX.m cd) for evaluat ing t he result s of t he proj ect s is included wit h each proj ect . Accom panying each Mat hcad proj ect file are SPI CE sim ulat or files based on PSPI CE. The SPI CE m odels for t he sim ulat ions use, in each case, t he param et ers for t he devices obt ained in laborat ory proj ect s. Since t he Mat hcad proj ect s use t he exact SPI CE

form ulat ions, t he result s from Mat hcad and SPI CE are ident ical in t he case of t he use of basic sim ulat ion levels. Sam ples of all of t he proj ect s have been com plet ed and are included. These provide for eit her dem onst rat ions or sim ulat ed result s wit hout act ually running t he program s wit h circuit s. The m easured dat a are st ored in LabVI EW graphics and can be ext ract ed t o obt ain dat a files in t he sam e m anner as act ually m aking t he m easurem ent s. I n som e cases, t he sim ult aneous t aking of dat a, plot t ing and curve fit t ing is sim ulat ed. Unit s 13 and 14 are t heoret ical only but each has Mat hcad problem s on t he t opic of t hese respect ive unit s. Special feat ures of t he lab experience are as follows: •

• •

•

The lab proj ect s are based ent irely on com put er dat a acquisit ion using LabVI EW and a Nat ional I nst rum ent s dat a acquisit ion card ( DAQ) in t he com put er for int erfacing wit h t he circuit board. Each device cat egory has an associat ed proj ect for evaluat ing SPI CE param et ers in which device m odel param et ers are obt ained. Subsequent am plifier proj ect s use t he param et ers in perform ance assessm ent . No ext ernal inst rum ent at ion is required. The funct ion generat or, volt m et ers, and oscilloscopes are virt ual and provided by LabVI EW and a DAQ card in t he com put er. The proj ect s on t he current - m irror load com m on- source am plifier and t he operat ional am plifier require an ext ernal power supply. Circuit s are const ruct ed on a special circuit board. The board is connect ed t o t he com put er DAQ card t hrough a Nat ional I nst rum ent s shielded 68- pin cable. The circuit board allows expedient , error- free const ruct ion of t he circuit s, as connect or st rips for t he respect ive out put and input channels and ground are available direct ly on t he board.

Topics included in t his course t reat m any of t he m ost relevant aspect s of basic m odern analog elect ronics wit hout st raying int o peripheral areas. The course essent ially st ream lines t he st udy of analog elect ronics. There is not a unit on, for exam ple, feedback per se, but m ost basic t ypes of feedback are addressed at som e point . The role t hat t he device plays in frequency response is om it t ed. This is consist ent wit h t he fact t hat t o a large ext ent , t he int ension is t hat t heory and m easurem ent s can be connect ed. St udent s of elect rical engineering or elect ronics engineering of t oday have a vast array of subj ect s t o at t em pt t o m ast er; it is not reasonable t o expect t hem t o labor t hrough a classical ext ensive st udy of t he subj ect of analog elect ronics, alt hough som e basic knowledge should be required. Specializat ion can com e at a lat er st age, if desired.

As mentioned, many LabVIEW features are utilized in the projects. To some extent, the goal of demonstrating the extensive array of the capabilities of LabVIEW influences the design of the various projects. This includes sending voltages (including waveforms), receiving voltages (including autoscaling), scanning, graphics, reading data files, writing data files, computations such as extraction of harmonic content of a signal, assembling data in a composite form, along with a host of array manipulation processes and data curve fitting.

References CMOS analog circuit s including applicat ions ( advanced) : Allen P., and R. Holberg. CMOS Analog Circuit Design, 1st Ed. Holt , Reinhart and Winst on, New York, 1986. Allen P., and R. Holberg. CMOS Analog Circuit Design, 2nd Ed. Oxford Universit y Press, New York, 2002. Ext ensive coverage of analog circuit s, which includes a com prehensive discussion of feedback and frequency response ( advanced) : Gray, P., P. Hurst , S. Lewis, and R. Meyer. Analysis and Design of Analog I nt egrat ed Circuit s, 4t h Ed. Wiley, New York, 2001. CMOS analog circuit s ( wit h som e BJT circuit s) wit h ext ensive coverage of applicat ions ( advanced) : Johns D., and K. Mart in. Analog I nt egrat ed Circuit Design. Wiley, New York, 1997. Present at ion of t he physical and em pirical associat ion bet ween sem iconduct or devices and t heir m odels, MOSFETs and BJTs: Massobrio G., and P. Ant ognet t i. Sem iconduct or Device Modeling wit h SPI CE. McGraw- Hill, New York, 1993. General t ext book on elect ronics ( basic) : Millm an J., and A. Grabel. Microelect ronics, 2nd Ed. McGraw- Hill, New York, 1987. Physical descript ion of sem iconduct or devices: Muller R., and T. Kam ins. Device Elect ronics for I nt egrat ed Circuit s, 2nd Ed. Wiley, New York, 1986. General t ext book on elect ronics ( basic) : Sedra, A.S., and K.C. Sm it h. Microelect ronic Circuit s, 4t h Ed. Oxford Universit y Press, Oxford, 1998. General t reat m ent of analog circuit s including applicat ions ( basic t o advanced) : Soclof, S. Design and Applicat ions of Analog I nt egrat ed Circuit s, Prent ice Hall, Upper Saddle River, N.J., 1991.

Hardware and Software Requirements Circuit connect ions t o t he DAQ require a cable and a facilit y for connect ing t o individual pins. An efficient syst em is based on a Nat ional I nst rum ent s Connect or Block ( CB- 68LP) and a basic circuit board as shown here.

Connect ions t o t he circuit board from t he connect or block are m ade one t im e. The t wo resist ors of t he circuit are connect ed t o out put channels 0 and 1, respecively. Thus, for exam ple, Chan0_out , as not ed, is dedicat ed t o t he t op st rip on t he circuit board. The bot t om t op st rip is associat ed wit h Chan0_in, and so fort h. All of t he proj ect LabVI EW files are program m ed t o be consist ent wit h t he plus bus ( rail) , Chan0_out , and t he m inus bus ( rail) , Chan1_out . Therefore, it is int uit ively helpful t o have t he out put channels physically connect ed in t his fashion. The proj ect exam ples included wit h t he book were conduct ed on a special circuit box t hat connect s direct ly t o t he shielded 68- pin connect or. This bypasses t he connect or block. A shielded cable is st rongly recom m ended in any event . Many of t he proj ect s involve t he m easurem ent of relat ively low volt age signals. I n addit ion, t he lab proj ect s included in t he book require t he following ( or equivalent ) : •

•

•

•

•

Pent ium PC ( or equivalent ) . Nat ional I nst rum ent s DAQ PCI - MI O- 16E- 4. LabVI EW 6.0i St udent Edit ion or LabVI EW 6.0i or lat er version. Mat hcad Professional 2001 or lat er version. Nat ional I nst rum ent s Shielded 68- pin Cable.

Se m icondu ct or D e vice s a n d Com pone n t s ( Re com m e nde d) 6- Transist or ( 3- gat e) CMOS Array – CD4007 [ * ] CMOS Opam p – SGS- Thom son TS271 [ * * ] NPN - Medium - Power NPN BJT – NTE186 [ * * * ]

PNP - Medium - Power PNP BJT – NTE187 [ * * * * ] Capacit ors Resist ors

Conn e ct or Block Pin s ( AT- M I O- E or PCI - E Se r ie s) Chan0_out Pin 21 Chan0_in Pin 68 Gnd – Pin 34 Chan1_out Pin 22 Chan1_in Pin 33 Gnd – Pin 66 Out put Channel Gnd Pin 55 Chan2_in Pin 65 - plus Pin 31 - m inus I nput Channel Gnd Pin 67 I nput and out put grounds are connect ed.

+ 5 V Supply Volt age Pin 14

[* ] The CD4007 chip cont ains t hree CMOS inv ert ers or t hree PMOS and t hree NMOS t ransist ors. Since t hey are invert ers, NMOS and PMOS pairs hav e Hardware and Soft ware Requirem ent s int ernally connect ed gat es. How ever, t his does not prevent hav ing a sufficient num ber of t he indiv idual t ransist ors in t he analog laborat ory proj ect s. [* * ]

The TS271 is chosen as it has sim ple ext ernal resist or biasing. Thus, st udent s can gain an int uit iv e feel for t he relat ion bet ween t he charact erist ics of t he CMOS opam p and bias current w it h st raight forward exchange of bias resist ors. I n t he case of a group of st udent s, for exam ple, each st udent can select a different bias current , such t hat all of t he result s can be assem bled t o plot t he opam p charact erist ics, such as gain and frequency response versus bias current . I n addit ion, t he circuit ry of t he opam p is st raight forward and m ay be underst ood w it hin t he scope of t he book. Ext ensive experience in our laborat ory w it h dev ices has dem onst rat ed t hat t his opam p can wit hst and considerable abuse w it hout failing ev en t hough it is a MOSFET chip. I t is how ever, st rongly adv ised t hat t he power supply nev er be t urned on unt il t he power- supply pins, input pins and out put pin are connect ed in t he circuit . [* * * ]

The NTE186 is a rugged npn BJT t hat is invest igat ed at current levels w ell below t he norm al operat ing range. Heat ing of t he dev ice is t hus m inim ized and for t he m easurem ent s, it can be assum ed t o be at room t em perat ure. Also, various highlevel inj ect ion effect s, which render t he basic SPI CE param et er set inv alid, are avoided. [* * * * ]

Com plem ent ary paired w it h t he NTE186.

LabVIEW VI Libraries and Project and Problem Folders and Files Each proj ect has a folder, which cont ains t he LabVI EW library plus any relat ed Mat hcad files for t hat proj ect . Mat hcad files include t hose for t he exercises and result s analysis ( proj ect files) . The proj ect folder also has circuit - sim ulat or subfolders for Schem at ics and Capt ure. A LabVI EW VI library is included for each proj ect . These are LabVI EW files wit h ext ension llb. The LabVI EW files wit hin a library have ext ension vi. A given proj ect library will cont ain m ost of t he LabVI EW virt ual inst rum ent s for t hat proj ect . The addit ional VI s are in t he User.lib folder, which is in t he LabVI EW a pplica t ion folder. The User.lib folder cont ains all t he LabVI EW libraries and ot her LabVI EW files t hat are not included in t he individual proj ect libraries. The folders are Read_Rit e, Dat _File, Funct Gen, and Subvi. Each problem folder has a set of problem s associat ed wit h t he unit wit h t he sam e num ber. Each problem set has a pdf file ( Word) , a Mat hcad solut ions file, a pdf version on t he Mat hcad file and a circuit - sim ulat or subfolder. There are also pdf files for t he com posit e of t he problem s ( WordProb.pdf) , Mat hcad problem solut ion files ( Mat hcadProb.pdf) , proj ect exercises ( Mat hcadExer.pdf) , proj ect Schem at ics exercises ( Schem at icsExer.pdf) , and proj ect Capt ure exercise ( Capt ureExer.pdf) . The procedure for inst allat ion of t he libraries from t he CD ont o t he com put er is described in t he Readm e files.

Unit 1. Elementary Circuit Analysis for Analog Electronics I n t his unit , we present a basic review of segm ent s of circuit analysis which recur repeat edly in elect ronic circuit s. A firm grasp on t hese is essent ial t o developing an underst anding of t he analysis and design of basic elect ronic circuit s. A t ransist or is included in t he circuit s t o show a correlat ion bet ween circuit analysis and elect ronics. Only st eady- st at e circuit sit uat ions are considered here. This includes dc and sinusoidal. Som e t ransient analysis is considered in connect ion wit h operat ional am plifier applicat ions wit h capacit ors.

1.1 Resistor Voltage Divider and MOSFET DC Gate Voltage Figure 1.1( a) shows a basic NMOS am plifier st age. This is t he dc ( or bias) port ion of t he circuit , which excludes t he signal part . The t erm inals of t he t ransist or are designed G ( gat e) , D ( drain) and S ( source) . The design calls for a dc volt age VG, wit h respect t o t he zero reference volt age, which is obt ained by dividing t he supply volt age VDD bet ween bias resist ors RG1 and RG2 . Since t he gat e t erm inal has zero current , t he volt age, VG, at t he gat e can be assessed wit h t he resist or net work separat ed from t he circuit as in Fig. 1.1( b) . The goal is t o relat e t he node volt age VG t o t he values of RG1 and RG2 and VDD. The result is t he basic resist or volt age- divider relat ion.

Figu r e 1 .1 . ( a ) D c cir cu it for t h e ba sic N M OS a m plifie r . ( b) Cir cu it for de t e r m in in g t h e ga t e volt a ge , V G.

Not e t hat since VDD is given wit h respect t o t he reference zero volt s, t he VDD designat ion at t he t op node is equivalent t o t he supply volt age, also referred t o as VDD. The current I RG is

Equ a t ion 1 .1

The volt age across t he resist or RG2 is VG ( since VG is wit h respect t o t he zero reference) and t his is

Equ a t ion 1 .2

I t can be concluded t hat t he gat e volt age is t he value of RG2 divided by t he sum of t he t wo gat e- bias resist ors.

1.2 Output Circuit and DC Drain Voltage For t he dc circuit in Fig. 1.1, t he drain volt age is det erm ined from

Equ a t ion 1 .3

As illust rat ed in Fig. 1.2, for t he purpose of a solut ion t o ( 1.3) , t he t ransist or can be replaced by a current source as shown in Fig. 1.2. Drain current I D is a funct ion of VG; t hat is, I D = f( VG) . Thus, in a design, t he value of VG det erm ines t he value of VD . I D is relat ed t o VG according t o

Equ a t ion 1 .4

Figu r e 1 .2 . Cir cu it for illu st r a t in g t h e de t e r m in a t ion of t h e dr a in volt a ge , V D .

This relat ion and param et ers Vt no and k n are discussed in Unit 2.

1.3 Frequency Response of the Amplifier Stage Capacit ance associat ed wit h am plifiers m ay cause t he out put t o fall off at low and high frequencies. This effect is referred t o as t he frequency response of t he am plifier. A generalizat ion of possible capacit ance is shown in t he circuit of Fig. 1.3. Capacit or Cg is an ext ernal capacit ance, which is included t o at t ach a sine- wave signal source, consist ing of Vsig ( e.g., sine- wave peak) and Rs, wit hout int errupt ing t he dc bias circuit ry. Sim ilarly, t here could be an out put capacit ance, which couples t he signal out put volt age t o an ext ernal load resist or. Capacit or CT is associat ed wit h t he int ernal capacit ance of t he t ransist or. I t m ay be regarded as an equivalent effect ive capacit ance t hat represent s all of t he capacit ance of t he t ransist or.

Figu r e 1 .3 . Am plifie r in clu din g possible cir cu it ca pa cit a n ce .

Generally, t he frequency range over which a given capacit or is effect ive is m uch different for t he t wo capacit ors. Capacit or Cg affect s t he out put at low frequencies, while t he effect of CT is realized at t he high end of t he spect rum . Thus, t heir effect s can be considered separat ely if, as assum ed in t he following, t he high and low ends of t he response funct ion are widely separat ed in frequency, t hat is, by several orders of m agnit ude. Figure 1.4 shows t he signal circuit s for t he t wo cases of low ( a) and high ( b) frequencies. As discussed in Unit 2, t he signal circuit is form ulat ed from t he com plet e circuit by set t ing all dc volt ages t o zero. This includes, for t his am plifier, t he power supply and dc volt age across t he capacit or Cg . Not e t hat t he t ransist or plays no apparent role in t he frequency response in t he equivalent circuit . I t is, of course, crit ically im port ant in dict at ing t he value of CT.

Figu r e 1 .4 . Cir cu it s for low ( a ) a n d h igh ( b) fr e qu e n cie s.

The t wo circuit s, ( a) and ( b) , are t echnically high- pass and low- pass circuit s, respect ively. I n com binat ion, t hey have a m idband range, which is t he norm al range of frequency for operat ion of t he am plifier. As m ent ioned above, if t he m idband separat es t he low and high port ions by a

sufficient range of frequency, t he effect s m ay be considered separat ely, as suggest ed in Fig. 1.4. The response funct ion is obt ained by considering t he frequency dependence of t he node volt age Vg ( f) for t he const ant - m agnit ude sine- wave source volt age, Vsig . ( Since t he only volt ages under considerat ion in t he circuit s of Fig. 1.4 are t hose associat ed wit h signals, lowercase subscript is used. This is discussed furt her in Unit 2.) The frequency response is first considered for t he low end of t he spect rum and involves Cg only, as in t he circuit of Fig. 1.4( a) . We can ut ilize t he volt age- divider relat ion obt ained above as ( 1.2) . For t his case t his is

Equ a t ion 1 .5

where RG = RG1 | | RG2 . Using t he definit ions

Equ a t ion 1 .6

and

Equ a t ion 1 .7

t he result is condensable t o

Equ a t ion 1 .8

The m agnit ude is

Equ a t ion 1 .9

At f = f lo , . This, by definit ion, is t he response m agnit ude for t he 3- dB frequency, f 3dB, for t he low- frequency end of t he response funct ion. That is, in general, f 3dB is t he frequency at which t he response falls t o ( for decreasing frequency) from t he m axim um , asym pt ot ic value. Thus, for t he sim ple case here of one capacit or, f 3dB = f lo . The equat ion for t he response funct ion associat ed wit h CT is sim ilar t o ( 1.8) and is

Equ a t ion 1 .1 0

where

Equ a t ion 1 .1 1

The frequency f 3dB for t his case is j ust f hi . The frequency response of circuit s of t he t ype of Fig. 1.4 is m easured in Proj ect 1. I n t he design of t he proj ect circuit s, capacit ors and resist ors are select ed t o give widely different f lo and f hi values.

1.4 Summary of Equations Resist or- circuit volt age divider.

Drain current and gat e volt age relat ion.

Low- frequency frequency- response funct ion.

High- frequency frequency- response funct ion.

Midband m agnit ude of t he signal gat e volt age.

1.5 Exercises and Projects Proj ect Mat hcad Files

Exercise01.m cd - Proj ect 01.m cd

La bor a t or y Pr oj e ct Basic Circuit Analysis for Elect ronic Circuit s and 1 Program m ing Exercises P1.1

Resist or Volt age- Divider Measurem ent s

P1.2

Resist or Volt age Divider wit h Current Measurem ent

P1.3

Resist or Volt age Divider wit h Resist or Measurem ent

P1.4

Resist or Volt age Divider wit h a Sine- Wave Source Volt age

P1.5

Frequency Response of a Resist or- Capacit or Circuit

Unit 2. Transistors and Voltage Amplification Radio t ransm it t ers and receivers have exist ed since before t he end of t he ninet eent h cent ury. A pract ical form of wireless t elegraph, at t ribut ed t o G. Marconi, appeared in 1895, and successful t ransm ission across t he At lant ic Ocean was achieved in 1901. However, in t he early part of t he t went iet h cent ury, syst em s were lim it ed by t he lack of a m eans of volt age am plificat ion. The appearance of a volt age am plificat ion device, t he vacuum t ube, dram at ically im proved t he concept , as m icrovolt signals could be boost ed for receiving and t ransm it t ing. I n t he m iddle of t he t went iet h cent ury, t he t ransist or appeared. The idea of t ransist ors based on a sandwich of pn j unct ions ( BJT) and a field- effect t ransist or based on pn j unct ions ( JFET) and on a m et al – oxide – sem iconduct or ( MOS) st ruct ure ( basically, a capacit or) were all underst ood at t he t im e. However, pn- j unct ion devices becam e a pract ical realizat ion m uch sooner t han t he MOS st ruct ure, due t o fabricat ion com plicat ions in producing t he MOS device as well as perhaps a perceived lack of need. The JFET served as an int erim field- effect t ransist or unt il t he MOS t echnology evolved. I t provided for a t ransist or wit h very high input resist ance and was used ext ensively as t he input t ransist ors for BJT opam ps. A t ext book on radio, Elem ent s of Radio, published in 1948 ( Marcus and Marcus, 1948) , m akes no m ent ion of t ransist ors. A 1958 t ext , ( Millm an, 1958) , Vacuum - Tube and Sem iconduct or Elect ronics, gives equal weight t o vacuum t ubes and BJTs in elect ronic circuit s but m akes no m ent ion of t he field- effect t ransist or. Slight ly lat er ( Nanavat i, 1963) , in An I nt roduct ion t o Sem iconduct or Elect ronics, as t he t it le suggest s, vacuum t ubes are dropped com plet ely and t he only reference t o a field- effect t ransist or is in one sect ion of t he last chapt er and t his refers t o a j unct ion field- effect t ransist or. I n 1965, in his t ext book Analysis and Design of Elect ronic Circuit s, Chirlian devot es a sm all port ion of t he book t o vacuum t ubes, but m ost of t he em phasis is on circuit s based on t he BJT ( Chirlian, 1965) . No m ent ion is m ade of t he fieldeffect - t ransist or. An exam ple of a book in which BJTs and field- effect t ransist ors of bot h t ypes were finally given balanced t reat m ent was published in 1979 ( Millm an, 1979) . Text books t end t o lag t he indust ry a bit , and during t he 1970s, MOSFET circuit s were em erging rapidly, driven by t he sim ult aneous developm ent of int egrat ed circuit s. The four edit ions of a t ext on analog circuit s by Gray and Meyer, ( 1977, 1984, 1993) and Gray, et al. ( 2001) serve well as a series t hrough which we observe a t ransit ion from m ost ly BJT t o, in t he last t wo edit ions, m ore- orless equal t reat m ent of BJT and MOSFET devices. A recent t ext book on t he subj ect of analog int egrat ed circuit s ( Johns and Mart in, 1997) t akes t he approach t hat such circuit s are now t ot ally dom inat ed by MOSFETS but includes som e BJT applicat ions. BiCMOS, a com binat ion of MOSFET and BJT devices on t he sam e int egrat ed circuit , is growing in popularit y as m ore ways of t aking advant age of t he superior propert ies of t he t wo t ransist or t ypes are developed. Since t he earliest t ransist ors, t here has been persist ent com pet it ion bet ween BJT and MOS t ransist ors. I t has been, t o a large ext ent ( along wit h m any ot her considerat ions) , a m at t er of power consum pt ion versus speed; t he BJT has been fast er but is associat ed wit h high power consum pt ion. The MOSFET has gradually t aken over as t he m ost im port ant t ransist or, wit h increased em phasis on int egrat ed circuit s and im proved speeds.

2.1 BJT and MOSFET Schematic Symbols, Terminal Voltages, and Branch Currents The BJT can be eit her a pnp or an npn. The MOSFET sim ilarly can be a pm os or an nm os. The equivalent s are npn and nm os and pnp and pm os. The following discussion is based on t he npn and nm os, as shown in Fig. 2.1. ( All polarit ies and current direct ions are reversed for t he pnp and pm os. This provides for im port ant versat ilit y in applicat ions.)

Figu r e 2 .1 . BJT n pn a n d M OSFET n m os t r a n sist or s. Th e t e r m in a l con figu r a t ion s a r e de sign a t e d com m on e m it t e r a n d com m on sou r ce .

The BJT t erm inals are designat ed collect or, base, and em it t er while t hose of t he MOSFET are drain, gat e, and source. The t erm inal configurat ions in Fig. 2.1 are, for t he BJT, t he com m on em it t er, and for t he MOSFET, t he com m on source, in am plifier- st age parlance. This suggest s t hat bot h t he input ( left side) and out put ( right side) are referred t o t he com m on t erm inal. For exam ple, for t he BJT, t he input t erm inal volt age is VBE and t he out put t erm inal volt age is VCE. Sim ilarly, for t he MOSFET, we have VGS and VDS. Not e t hat in t he convent ion of subscript s in elect ronics, t he first subscript is assigned posit ive. This m at ches t he assignm ent s in t he diagram , and t he plus and m inus signs are superfluous. Not e also t he convent ion for sym bols for all current s and volt age. Tot al volt age and current : v XY, i X Dc, bias, quiescent , or operat ing point : VXY, I X Signal or ac ( RMS, peak) : Vxy , I x General inst ant aneous signal: v x , i x The volt age and current sym bols in Fig. 2.4 are t herefore for dc. For a volt age, a single subscript m eans t hat t his t erm inal ( or node) volt age is referred t o t he com m on t erm inal. For exam ple, in t he npn case above, VCE = VC.

Figu r e 2 .4 . Ba sic N M OS a m plifie r w it h r e sist or ga t e bia sin g a n d in pu t sign a l V s. ( a ) Com ple t e cir cu it . ( b) Sign a l ( or a c or in cr e m e n t a l) cir cu it . Th e sign a l cir cu it is obt a in e d by se t t in g t h e pow e r su pply ( dc) n ode t o ze r o volt s. ( c) Lin e a r signa l cir cu it r e pla ce s t h e lin e a r sch e m a t ic r e pr e se n t a t ion .

The input t erm inals v BE and v GS are t he cont rol t erm inals; t hat is, t hey cont rol t he out put current s i C and i D . I n bot h cases, t he t erm inal pairs possess ext rem ely nonsym m et rical volt age – current behavior. Wit h t he polarit ies as shown, t he current s flow readily, whereas wit h t he opposit e polarit ies, t he out put current s are cut off or are, for m ost purposes, essent ially zero. The basic ( sim plified) general relat ions bet ween t he current s and volt ages are:

Equ a t ion 2 .1

Equ a t ion 2 .2

I S, VT, k n , Vt n , and VT are device m odel param et ers or physical const ant s. I n linear circuit applicat ions, for exam ple, as am plifier st ages, t he t ransist ors are provided wit h a circuit configurat ion t hat set s up dc, or bias, current s and t erm inal volt ages ( som et im es referred t o as t he Q- point , for quiescent , or in SPI CE, t he operat ing point ) . I n t he am plifier applicat ion, a signal volt age is applied t o t he input , t hat is, superim posed on t he dc m agnit ude, which m ust be m uch sm aller t han t he dc volt age if t he signal input - out put relat ion is t o be linear. This is apparent from ( 2.1) and ( 2.2) , which are nonlinear relat ions. All of t he current s and t erm inal volt ages will change in response t o t he input signal, and all of t hese increm ent al changes m ust be sm all com pared t o any of t he dc current s or volt ages, in order for t he linear relat ionships t o be valid. I n circuit applicat ions, bot h t ypes of t ransist ors are operat ed in all t hree possible t erm inal configurat ions. This provides for a wide variet y of am plifier- st age charact erist ics, including gain and input and out put im pedance.

2.2 Fundamentals of Signal Amplification: The Linear Circuit The m ost fundam ent al propert y of a useful elect ronic volt age am plificat ion device is t hat it possess a t ransconduct ance t hat leads t o t he possibilit y of volt age gain. Transconduct ance is defined as t he rat io of t he signal ( ac, increm ent al) current out , iout δi OUT, and t he applied input signal volt age, v in δv I N. That is, t ransconduct ance g m is

Equ a t ion 2 .3

For t he BJT, i OUT i C and v I N v BE, while for t he NMOS, i OUT i D and v I N v GS. Thus, ( 2.1) and ( 2.2) can be used for t he BJT and MOSFET, respect ively, t o obt ain an expression for g m . The result s are

Equ a t ion 2 .4

and

Equ a t ion 2 .5

I C and I D are t he dc ( bias) current s of t he t ransist ors, so for com parison t hey can be m ade equal. At room t em perat ure, t he t herm al volt age is VT = 26 m . For t he MOSFET, VGS is t he gat e – source bias volt age and Vt n is t he t ransist or t hreshold volt age. The difference, as in t he denom inat or of t he t ransconduct ance expression, could t ypically be about VGS – Vt n = 500 m V. The expression ( 2.3) suggest s t he linear m odel given in Fig. 2.2. I ncluded in t he m odel is an input resist ance, r in , which account s for t he fact t hat t here can be an increm ent al current flowing int o t he input t erm inal for an increm ent of input volt age. The m odel applies in general t o am plifying devices, including t he vacuum t ube ( VT) , BJT, JFET, and MOSFET. There exist s a wide range of m agnit ude of t ransconduct ance and input resist ance bet ween t he devices. The input resist ance, t hough, affect s only t he loading of t he input signal source; ot herwise, t he relat ion of ( 2.3) applies in all cases, and t he t ransconduct ance is t he key t o t he gain for a given device t ype. The input resist ance is essent ially infinit e for t he vacuum t ube and t he MOSFET ( com m on source) but can be as low as a few ohm s in som e configurat ions for t he BJT ( e.g., com m on base) .

Figu r e 2 .2 . Ba sic lin e a r m ode l of a volt a ge a m plifica t ion de vice . M ode l pa r a m e t e r s a r e g m a n d r in .

I t is int erest ing t o com pare t he t ransconduct ance of t he BJT and MOSFET along wit h t he vacuum t ube. We will m ake a com parison at I D = I C = 10 m A ( suit able for a vacuum t ube) even t hough t ransist ors would not usually be operat ed at such high current s, especially in an int egrat ed circuit . Consult ing a source of inform at ion for a t riode 6SN7 ( perhaps one of t he m ost com m on t ubes of all t im e) , one deduces from a graphical analysis t he plat e charact erist ics t hat , for exam ple, g m ( VT) = 3 m A/ V. From ( 2.4) and ( 2.5) , we obt ain g m ( BJT) = 385 m A/ V and g m ( MOSFET) = 40 m A/ V wit h VGS – Vt n = 500 m V. The BJT is decidedly superior in t his respect , and t his is one of t he fact ors cont ribut ing t o t he sust ained life of t he t ransist or in indust ry. That is, t he BJT am plifier st age can pot ent ially have a m uch higher volt age gain. The vacuum t ube is clearly inferior t o bot h t ransist ors and point s t o t he reason for t he need for so m any am plificat ion st ages in som e VT am plifiers. The out put volt age of am plifiers based on any of t he devices will depend on t he value of t he load resist ance, RL, which is added t o t he circuit of Fig. 2.2 in Fig. 2.3. Not e t hat , in general, RL is not necessarily an act ual resist or but could be an effect ive resist ance, as dict at ed by t he am plifier circuit ry t hat is connect ed t o t he out put of a given st age, com bined wit h a bias resist or. The out put volt age induced across RL will be

Equ a t ion 2 .6

Figu r e 2 .3 . Ba sic lin e a r m ode l of a volt a ge a m plifica t ion de vice w it h loa d R L con n e ct e d.

The m inus sign is a result of t he current flowing up t hrough RL. The signal volt age gain is t he increm ent al out put volt age divided by t he increm ent al input volt age such t hat t he gain can readily be obt ained from ( 2.6) as

Equ a t ion 2 .7

Thus, t he gain is direct ly relat ed t o t he param et er g m for a given t ransist or. I n general, av can be posit ive or negat ive, depending on t he t erm inal configurat ion. For exam ple, t he com m on base ( BJT) and com m on gat e ( MOSFET) are posit ive ( noninvert ing) gain am plifiers.

2.3 Basic NMOS Common-Source Amplifier An exam ple of t he applicat ion of t he t ransconduct ance relat ion for t he t ransist or is t he basic circuit in Fig. 2.4. Set t ing dc volt ages ( in t his case, VDD) equal t o zero in Fig. 2.4( a) leads t o t he signal ( or ac) circuit [ Fig. 2.4( b) ] . This follows from t he fact t hat t he signal circuit involves only increm ent al variables ( changes) and VDD is a const ant . The schem at ic sym bol for t he t ransist or in t he signal circuit associat es t he out put current wit h t he input volt age according t o t he linear relat ion of ( 2.3) . For linear circuit analysis, t he linear equivalent circuit of Fig. 2.2 ( Fig. 2.4( c) ) replaces t he linear schem at ic- sym bol represent at ion [ Fig. 2.4( b) ] . For t he MOSFET, r in is infinit e and t herefore om it t ed. The overall gain from t he signal source t o t he out put is a v = Vo / Vs, which is

Equ a t ion 2 .8

where Vo/ Vg is ( 2.7) and Vg / Vs is provided by t he sim ple resist or- divider relat ion given in ( 1.2) .

2.4 Transistor Output Resistance and Limiting Gain The linear- equivalent circuit of Fig. 2.2 includes an idealizat ion in t hat t he out put is a pure current source. I n real t ransist ors, t he collect or ( BJT) or drain ( MOSFET) current increases wit h increasing VCE or VDS. This is account ed for by including an out put resist ance, r out , in t he linear m odel, as added t o t he circuit in Fig. 2.5. For t he BJT and MOSFET, respect ively, t he value of r out is

Equ a t ion 2 .9

Equ a t ion 2 .1 0

Figu r e 2 .5 . Ba sic lin e a r cir cu it w it h t r a n sist or lin e a r m ode l. Cir cu it in clu de s sign a l sou r ce volt a ge a n d loa d R L, Tr a nsist or m ode l n ow in clu de s out pu t r e sist a n ce r ou t .

where VA is t he charact erizing t ransist or param et er. Not e t hat t his volt age dependence is not included in ( 2.1) and ( 2.2) ; t hese equat ions are consist ent wit h t he sim plified circuit m odel of Fig. 2.2. Sim ilarly, t he volt age dependence will alt er g m from t he sim ple form s of ( 2.4) and ( 2.5) . This is discussed in Unit 4. The act ual gain, wit h a load RL, which includes t he out put resist ance, can be obt ained from m odificat ion of ( 2.7) t o include r out in parallel wit h RL as in Fig. 2.5. The result is

Equ a t ion 2 .1 1

The param et er VA of bot h t ransist ors can t ypically be about 100 V. ( I n MOSFETs, t he param et er is usually referred t o as λ, which is t he reciprocal, λ = 1/ VA.) A useful com parison bet ween t he devices is t he m axim um lim it ing gain of t he com m on- em it t er and com m on- source . The gain in t his case is am plifier volt age gains, which applies for t he case of RL

Equ a t ion 2 .1 2

Using ( 2.4) , ( 2.5) , ( 2.9) , and ( 2.10) , we obt ain for t he lim it ing gain:

Equ a t ion 2 .1 3

Equ a t ion 2 .1 4

Using sam ple num bers from above, t he com parison gives av lim ( BJT) –4000 and a v –400. The vacuum t ube, t ype 6SN7, has a t ypical out put resist ance r out r p lim ( MOSFET) 7KΩ ( p for plat e) , which leads t o a lim it ing gain m agnit ude of about 21. ( This is referred t o as t he µ of t he t ube.) You have t o respect t he am plifier designers of t he vacuum - t ube era when considering what was accom plished despit e t he lim it at ions of t hese am plifying devices. I n m odern int egrat ed circuit s, it is possible t o im plem ent load circuit s, which have an effect ive RL > > r out such t hat t he lim it ing gain can be achieved. This is part icularly im port ant in MOSFET am plifiers t o m ake up for t he relat ively low value of g m .

2.5 Summary of Equations BJT t ransfer funct ion and t ransconduct ance relat ion.

MOSFET t ransfer funct ion and t ransconduct ance relat ion.

General volt age- gain relat ion from t he t ransist or input .

Gain relat ion from t he signal source.

General relat ion for t he t ransist or out put resist ance.

Volt age gain, including t he effect of t he t ransist or out put resist ance.

2.6 Exercises and Projects Proj ect Mat hcad Files Exercise02.m cd - Proj ect 02.m cd La bor a t or y Pr oj e ct 2

Basic NMOS Com m on- Source Am plifier wit h Program m ing Exercises P2.1

NMOS Com m on- Source Circuit wit h Drain Current Measurem ent P2.2

NMOS Com m on- Source Am plifier wit h Resist or Gat e Bias Circuit P2.3

Am plifier wit h Signal and Gain Measurem ent

2.7 References to the Electronics Book Sequence Chirlian, P. M. Analysis and Design of Elect ronic Circuit s. McGraw- Hill, New York, 1965. Gray, P. R., and R. G. Meyer. Analysis and Design of Analog I nt egrat ed Circuit s, 1st , 2nd, and 3rd eds. Wiley, New York, 1977, 1984, and 1993. Gray, P. R., P. J. Hurst , S. H. Lewis, and R. G. Meyer. Analysis and Design of Analog I nt egrat ed Circuit s, 4t h ed. Wiley, New York, 2001. Johns, D., and K. Mart in. Analog I nt egrat ed Circuit s. Wiley, New York, 1997. Marcus, A., and W. Marcus. Elem ent s of Radio, 2nd ed., Prent ice- Hall, New York, 1948. Millm an, J. Vacuum - t ube and Sem iconduct or Elect ronics. McGraw- Hill, New York, 1958. Millm an, J. Microelect ronics. McGraw- Hill, New York, 1979. Nanavat i, R. P. An I nt roduct ion t o Sem iconduct or Elect ronics. McGraw- Hill, New York, 1963.

Unit 3. Characterization of MOS Transistors for Circuit Simulation I n t his unit , t he basic ( Level 1 SPI CE) dc MOSFET charact erist ic equat ions are int roduced. The am plifier exercises and proj ect s use t he result s for design and analysis. Circuit solut ions are com pared wit h m easured result s from t he circuit t o m ake an assessm ent of t he degree t o which t he t ransist or m odels for t he MOSFET represent act ual device behavior. The param et ers for t his unit are present ed in Table 3.1. Not e t hat in t he case of KP, we can only m easure K and would be able t o ext ract KP only if gat e widt h W and lengt h L were known. TABLE 3 .1 SPI CE Nam e VTO

Mat h sym bol Vt no , Vt po

KP

Descript ion Zero- bias t hreshold volt age. Transconduct ance param et er.

Gam m a

γn , γp

Body- effect param et er.

Phi

2ΦF

Surface inversion pot ent ial.

Lam bda

λn , λp

Channel lengt h m odulat ion.

3.1 Physical Description of the MOSFET A diagram m at ic NMOS is shown in Fig. 3.1. The device consist s of a t hree- layer st ruct ure of m et al–oxide–sem iconduct or ( MOS) . A t wo- t erm inal MOS st ruct ure ( connect ions t o m et al and sem iconduct or) is essent ially a parallel- plat e capacit or. I n t he sam e m anner as for a norm al capacit or, when a posit ive gat e volt age, VG, is applied wit h respect t o t he p- t ype body ( for NMOS) [ i.e., wit h respect t o t he m et al cont act on t he underside of t he p- t ype sem iconduct or body ( or subst rat e) ] , negat ive charges are induced under t he oxide layer in t he sem iconduct or. When VG ( wit h respect t o t he sem iconduct or body) exceeds t he t hreshold volt age, Vt no , a channel of free- carrier elect rons form s under t he oxide; t hat is, t he onset of t he channel occurs when VG = Vt no . The subst rat e is n t ype for t he PMOS and t he channel is m ade up of free- carrier holes.

Figu r e 3 .1 . M OS t r a n sist or con sist in g of a m e t a l – ox ide – se m icon du ct or la ye r e d st r u ct u r e ( plu s a m e t a l body con t a ct on t he bot t om ) . A posit ive ga t e volt a ge , V G > V t n o , in duce s a con du ct in g ch a n n e l u n de r t h e ox ide , w h ich con n e ct s t h e t w o n r e gion s, sou r ce a n d dr a in . All volt a ge s a r e w it h r e spe ct t o V B, t h a t is, t he body ( su bst r a t e ) of t h e t r a n sist or . ( a ) N o ch a n n e l; ( b) u n ifor m ch a n n e l; ( c) ch a n n e l is j u st pin ch e d off a t t h e dr a in e n d of t h e cha n n e l; ( d) ch a n n e l le n gt h is r e du ce d du e t o dr a in pn - j u n ct ion de ple t ion r e gion e x t e n din g ou t a lon g t h e ch a n n e l.

An n- channel MOSFET device is t hen com plet ed by fabricat ing n regions, source and gat e, for cont act ing t he channel on bot h ends of t he channel. For VG < Vt no [ Fig. 3.1( a) ] t here is no channel under t he oxide, and t he t wo n regions are isolat ed pn j unct ions. When VG > Vt no and source volt age, VS, and drain volt age, VD , are bot h zero ( all wit h respect t o t he body) [ Fig. 3.1( b) ] a uniform - t hickness n- t ype channel exist s along t he lengt h of t he oxide layer and t he source and drain regions are connect ed by t he channel. Thus, t he channel is a volt agecont rolled resist or where t he t wo ends of t he resist or are at t he source and drain and t he cont rol volt age is applied at t he gat e.

I n elect ronic circuit applicat ions, t he t erm inal volt ages are referred t o t he source; gat e and drain volt ages are designat ed as VGS and VDS ( NMOS) . I n analog circuit s, VGS > Vt no ( in order for a channel t o exist ) , VDS is posit ive, and a drain current flows t hrough t he channel and out by way of t he source ( and t he gat e current is zero) . On t he drain end of t he channel, t he volt age across t he oxide layer is VGD = VGS – VDS. The channel at t he drain end j ust shut s off when VGD = Vt no . VDSsat = VGS – Vt no [ Fig. 3.1( c) ] is defined for t his condit ion as t he sat urat ion volt age. The t ransist or is referred t o as in t he linear ( or t riode) region or act ive region for VDS < VDSsat and VDS > VDSsat , respect ively. For VDS > VDSsat ( act ive m ode of operat ion) , t he channel lengt h decreases from L t o L' as t he reverse- biased deplet ion region of t he drain pn j unct ion increases along t he channel ( along t he oxide – sem iconduct or int erface) [ Fig. 3.1( d) ] . The increm ent VDS – VDSsat drops across t he deplet ion region of t he drain pn j unct ion. I n long- channel devices, t he reduct ion of channel lengt h is relat ively sm all com pared t o t he channel lengt h. I n t his case, t he lengt h is roughly a const ant and t he channel resist ance, for a given VGS, is independent of VDS. From a circuit point of view, for VDS > > VDSsat , by Ohm 's law,

Equ a t ion 3 .1

where Rchan ( VGS) is t he resist ance of t he channel and is a funct ion of VGS. Assum ing t hat L' L, for a given VGS, Rchan ( VGS) , and t hus I D , is approxim at ely a const ant for VDS VDSsat . Thus, t he drain, in circuit t erm s, appears like a current source. I n m any m odern MOSFET devices, t his is only m arginally valid. I n t he following, t he definit ion Veffn VDSsat = VGS – Vt no will be used. ( The subscript is an abbreviat ion for effect ive.) The PMOS has a count erpart , Veffp VSDsat = VSG – Vt po . Veffp is a frequent ly recurring t erm in device and circuit analyt ical form ulat ions.

3.2 Output and Transfer Characteristics of the MOSFET The equat ions used in t he following t o charact erize t he MOSFET t ransist or are from t he SPI CE Level 1 m odel. SPI CE also has m ore det ailed m odels in Level 2 and Level 3. These can be specified when running SPI CE. However, t he num ber of new m odel param et ers, in general, in circuit sim ulat ion is pract ically boundless. Level 1 is chosen here as it is t he m ost int uit ive, t hat is, t he m ost suit able for an int roduct ory discussion of device behavior. Som e new m odels, for exam ple, which focus on frequency response at very high frequencies, can include pages of equat ions. I n addit ion, Level 1 is suit able and adequat e for m any exam ples of circuit sim ulat ion. The basic com m on- source NMOS circuit configurat ion is repeat ed in Fig. 3.2. Here it serves as a basis for discussing t he dc SPI CE param et ers of t he MOSFET t ransist or. I n t he exam ple, VDS = VDD. The out put charact erist ic is a plot of I D versus VDS for VGS = const . A represent at ive exam ple is shown in Fig. 3.3. As m ent ioned, t he low- volt age region is referred t o as t he linear region, t riode region, or presat urat ion region. Out side t his region for higher volt ages is t he act ive ( sat urat ion) region. This is referred t o here as t he act ive region t o avoid confusion wit h t he fact t hat t he nom enclat ure is j ust t he opposit e in t he case of t he BJT; t hat is, t he lowvolt age region is called t he sat urat ion region. As discussed in Unit 3.1, t he linear and act ive regions are delineat ed by Veffn VDSsat = VGS – Vt no .

Figu r e 3 .2 . Com m on - sou r ce cir cu it con figu r a t ion for discu ssion of t h e dc m ode l pa r a m e t e r s of t h e N M OS t r a nsist or . Th e t h r e e - t e r m in a l t r a n sist or sym bol im plie s t h a t t he body a n d sou r ce a r e con n e ct e d.

Figu r e 3 .3 . M a t h ca d- ge n e r a t e d ou t pu t ch a r a ct e r ist ic for t h e N M OS t r a n sist or . Th e plot illu st r a t e s t h e lin e a r a n d a ct ive r e gion s. The lin e a r r e gion is a lso ca lle d t h e t r iode r e gion or pr e sa t u r a t ion r e gion . Cu r r e n t is in m icr oa m pe r e s a n d V e ffn = 0 .8 V. Also plot t e d is t he ide a l ch a r a ct e r ist ic w it h ze r o slope in t h e a ct ive r e gion .

The out put - charact erist ic equat ion in t he linear region corresponds t o VDS ranging from t he condit ion of Fig. 3.1( b) t o t hat of Fig. 3.1( c) . As VDS increases from zero, t he channel begins t o close off at t he drain end ( i.e., t he channel becom es progressively m ore wedge shaped) . The result is an increase in t he resist ance of t he channel as a funct ion of VDS, and t herefore a sublinear current – volt age relat ion develops. When VGS > Vt no , t he elect ron charge in t he channel can be relat ed t o t he gat e volt age by Qchan = Cox ( VGS – Vt no ) ( per unit area of MOSFET looking down at t he gat e) , where Cox is t he parallelplat e capacit ance ( per unit area) form ed by t he MOS st ruct ure. This provides a sim ple linear relat ion bet ween t he gat e volt age and t he charge in t he channel.

The conduct ivit y in t he channel is σchan = µn Qchan / t chan , where µn is t he m obilit y of t he elect rons in t he channel and t chan is t he t hickness of t he channel int o t he sem iconduct or. Thus, in t he 0) , t he channel conduct ance is case of a uniform channel ( i.e., for VDS

Equ a t ion 3 .2

where

Equ a t ion 3 .3

and where KPn = µn Cox is t he SPI CE t ransconduct ance param et er ( t he n subscript is t he equat ion sym bolic not at ion for t he NMOS; t he param et er in t he device m odel is j ust KP) , W is t he physical gat e widt h, and L, again, is t he channel lengt h. Param et er KPn is relat ed t o t he elect ron m obilit y in t he channel and t he oxide t hickness. Therefore, it is very specific t o a given MOSFET device. As VDS increases, but is less t han Veffn [ t ransit ion from Fig. 3.1( b) t o 3.1( c) ] , t he wedge- shaped effect on t he channel is reflect ed funct ionally in t he channel conduct ance relat ion as

Equ a t ion 3 .4

This leads t o an out put charact erist ic equat ion for t he linear region, which is

Equ a t ion 3 .5

The derivat ion leading t o ( 3.4) and ( 3.5) is given in Unit 3.4. The linear- region relat ion, ( 3.5) , is applicable for VDS up t o VDS = Veffn , which is t he boundary of t he linear and act ive regions. The act ive- region equat ion is t hen obt ained by subst it ut ing int o ( 3.5) , VDS = Veffn , giving

Equ a t ion 3 .6

This act ive- region current corresponds t o t he zero- slope ideal curve in Fig. 3.3. As discussed in Unit 3.1, t he drain current is not act ually const ant in t he act ive region ( in t he sam e m anner as for a BJT) , due t o t he fact t hat t he physical lengt h of t he channel is reduced for increasing VDS beyond VDS = Veffn . The reduct ion in t he channel lengt h has t he effect of slight ly reducing t he resist ance of t he channel. This is t aken int o account using t he fact t hat k n 1/ L, from ( 3.3) , where L is t he effect ive physical lengt h bet ween t he source and drain regions. For VDS > Veffn , a

reduced lengt h L' = L( 1 – λn VDS) is defined which leads t o a new effect ive

,

Equ a t ion 3 .7

where λn is t he SPI CE channel- lengt h m odulat ion param et er ( Lam bda) . Subst it ut ing ( 3.6) produces

for k n in

Equ a t ion 3 .8

( Not e: A preferred form would be I D = k n Veffn 2 [ 1 + λn ( VDS – Veffn ) ] because t he channel- lengt h effect only begins for VDS > Veffn and k n could be defined properly for effect ive lengt h L at VDS = Veffn . Level 1 SPI CE uses ( 3.8) .) Level 1 SPI CE also applies t his channel- lengt h reduct ion fact or t o t he equat ion in t he linear region, ( 3.5) . To m at ch t he linear- region equat ion t o t he act ive- region equat ion, ( 3.5) becom es, at t he edge of t he act ive – linear regions,

Equ a t ion 3 .9

and, in general

Equ a t ion 3 .1 0

[ Again, t he fact t hat t he channel lengt h is not reduced wit h t he t ransist or in t he linear region would suggest t he use of ( 3.9) t hroughout t he linear region. Level 1 SPI CE uses ( 3.8) and ( 3.10) .] I n general, Vt n is a funct ion of t he source- body volt age, VSB. We assum e for t he m om ent t hat VSB = 0. This applies, for exam ple, t o t he com m on- source circuit in Fig. 3.2, since t he body will always be at zero volt s, and t he source in t his case is grounded as well. For t his case, Vt n = Vt no , as used above. I n laborat ory proj ect s we m easure t he out put charact erist ic from which param et er λn can be obt ained. This is based on ( 3.8) . The I – V slope in t he act ive region is

Equ a t ion 3 .1 1

From t he dat a m easured, a st raight - line curve fit det erm ines t he slope and t he zero VDS int ercept ( I D at VDS = 0) . These are used in ( 3.11) t o obt ain λn from λn = slope/ int ercept . The int ercept is t he ext ension of t he act ive region of Fig. 3.3 ( dashed line) t o t he I D axis. When applying t he equat ions of t his developm ent t o t he PMOS, t he volt age bet ween t he gat e and source is defined as posit ive wit h respect t o t he source, t hat is, VSG. To be consist ent , t he t hreshold volt age for t he PMOS, Vt p , is also posit ive. I n t he SPI CE m odel, however, t he t hreshold volt age is assigned negat ive because posit ive is t aken for bot h t ypes of devices wit h respect t o t he gat e ( VGS is negat ive for t he PMOS) , and t he t hreshold volt age for t he PMOS is negat ive. The t ransfer charact erist ic is obt ained by holding VDS const ant and varying VGS. I n t he MOSFET param et er- det erm inat ion experim ent s of Proj ect s 3 and 4, we plot VGS versus t ransist or biased int o t he act ive region. The equat ion is

for t he

Equ a t ion 3 .1 2

where

is ( 3.7)

The slope in ( 3.12) is and t he zero int ercept is expect ed t o be Vt no . LabVI EW obt ains t he slope and int ercept from a st raight - line fit t o t he dat a. The m easured t ransfer charact erist ic t hus yields t he t wo param et ers

and Vt no .

I n Proj ect 4, param et er λn is obt ained from finding on

at t wo different VDS values. This is based

Equ a t ion 3 .1 3

where t he

values are m easured and λn is t he only unknown.

3.3 Body Effect and Threshold Voltage I n Fig. 3.4 is shown an exam ple of a circuit in which t he body and source cannot be at t he sam e volt age. We now use t he four- t erm inal sym bol for t he NMOS, which includes t he body cont act . I n m ost applicat ions, t he body would be t ied t o t he lowest pot ent ial in t he circuit ( NMOS) , in t his case, VSS ( e.g., VSS = –5 V) . But by t he nat ure of t he circuit , t he source volt age is VS = VSS + I D RS, such t hat t he source- body volt age is VSB = I D RS.

Figu r e 3 .4 . N M OS t r a n sist or cir cu it w it h a r e sist or , R S, in t h e sou r ce br a n ch . W it h t h e body a t t a ch e d t o V SS, V SB = I D R S.

I n MOSFET devices, t he t hreshold volt age depends on VSB and in SPI CE is m odeled according t o ( NMOS)

Equ a t ion 3 .1 4

SPI CE param et ers cont ained in t he equat ion are Vt no ( VTO) , γn ( Gam m a) , and 2ΦF ( Phi) ( Table 3.1) . Typically, γn 0.5 V1/ 2 and 2ΦF 0.6 V. Therefore, for exam ple, for VSB = 5 V, t he body effect adds 0.8 V t o Vt no . I n t he case of t he CMOS array I Cs of our lab proj ect s ( CD4007) , t he body effect for t he PMOS is significant ly less pronounced t han for t he NMOS ( γp < γn ) , but t he param et er for t he channellengt h- m odulat ion effect is m uch sm aller for t he NMOS t han for t he PMOS ( λn < λp ) . The com binat ion suggest s t hat t he chip is a p- well configurat ion; t hat is, t he NMOS devices are fabricat ed in " wells" of p- t ype sem iconduct or t hat are fabricat ed int o an n- t ype subst rat e. The PMOS devices reside direct ly in t he n- t ype subst rat e m at erial. As far as our m easurem ent s are concerned, t he ext rem es in param et ers are an advant age, as we are int erest ed in observing t he effect s of t he various param et ers. I n Proj ect 4, a num ber for γn is obt ained by m easuring Vt n as a funct ion of VSB. The result s are

plot t ed as Vt n versus . LabVI EW calculat es t he X variable. The dat a plot t ed should give a st raight line wit h slope γn . The effect iveness of SPI CE m odeling for represent ing t he behavior of t he t ransist or in a circuit is invest igat ed in Proj ect 4. The t ransfer charact erist ic, VGS versus I D , is m easured for a circuit of t he t ype shown in Fig. 3.4, where t he circuit has VSB = I D RS. I n t he proj ect , VSS is swept over a range of values t o produce a range of I D of about a decade. From ( 3.14) , t he t hreshold volt age charact erist ic t hat includes t he body effect is

Equ a t ion 3 .1 5

The input circuit loop equat ion ( Fig. 3.4) is

Equ a t ion 3 .1 6

I ncluding t he body effect , VGS is now [ from ( 3.12) ]

Equ a t ion 3 .1 7

where, for t his special case, VDS = VGS ( VD = 0, VS = 0) . A solut ion is obt ainable t hrough com bing ( 3.14) , ( 3.16) , and ( 3.17) for I D and VGS. These equat ions cont ain every param et er from t his discussion of MOSFET SPI CE param et ers along wit h RS. I n a proj ect Mat hcad file, Proj ect 04.m cd, a solut ion is obt ained t o provide a com parison wit h t he m easured VGS versus I D for t he circuit . The Mat hcad it erat ion form ulat ion is, from ( 3.16) ,

Equ a t ion 3 .1 8

and, from ( 3.15) and ( 3.17) ,

Equ a t ion 3 .1 9

I D and VGS are found for t he range of VSS corresponding t o t hat used in t he m easurem ent , which is 2.5 < | VSS| < 10 V.

3.4 Derivation of the Linear-Region Current – Voltage Relation The volt age along t he channel is defined as Vc( x) ( Fig. 3.5) , wit h t he range 0 at x = 0 ( source) t o Vc( L) = VD ( drain) . The device is in t he linear- region m ode, t hat is, VD < Veffn . The charge in t he channel at x is

Equ a t ion 3 .2 0

where t he charge at t he source is Qchan = Cox ( VGS – Vt no ) , as in t he case of ( 3.2) .

Figu r e 3 .5 . D ia gr a m m a t ic N M OS t r a n sist or bia se d in t o t h e lin e a r r e gion .

A generalizat ion of ( 3.2) for t he increm ent al conduct ance, dGchan ( x) , at x over a lengt h dx is

Equ a t ion 3 .2 1

The volt age drop across t he lengt h dx, for a drain current I D , is

Equ a t ion 3 .2 2

where Rchan ( x) = 1/ Gchan ( x) . Using ( 3.21) , t he increm ent al volt age across dx is

Equ a t ion 3 .2 3

Rearranging t he equat ion and int egrat ing gives

Equ a t ion 3 .2 4

which leads t o t he result ( 3.5) , repeat ed here

3.5 Summary of Equations Equat ions for NMOS. For PMOS, reverse t he order of subscript s and define I D out of t he drain. Current – volt age relat ion for t he linear region.

Current – volt age relat ion for t he act ive region.

Threshold- volt age dependence on source- body volt age.

3.6 Exercises and Projects Proj ect Mat hcad Files Exercise03.m cd - Proj ect 03.m cd - Exercise04.m cd, Proj ect 04.m cd La bor a t or y Pr oj e ct 3

Charact erizat ion of t he PMOS Transist or for Circuit Sim ulat ion P3.4

Low- Volt age Linear Region of t he Out put Charact erist ic P3.5

PMOS Param et ers from t he Transfer Charact erist ic P3.6

PMOS Lam bda from t he Transfer Charact erist ic P3.7

PMOS Out put Charact erist ic P3.8

PMOS Lam bda La bor a t or y Pr oj e ct 4

Charact erizat ion of t he NMOS Transist or for Circuit Sim ulat ion P4.4

NMOS Param et ers from t he Transfer Charact erist ic P4.5

NMOS Lam bda from t he Transfer Charact erist ic P4.6

NMOS Gam m a SubVI P4.7

NMOS Gam m a P4.8

NMOS Circuit wit h Body Effect

Unit 4. Signal Conductance Parameters for Circuit Simulation The basic low- frequency linear m odel for a MOS t ransist or has t hree conduct ance param et ers: t he t ransconduct ance param et er, g m , t he body- effect param et er, g m b , and t he out put conduct ance param et er g ds. They are t he proport ionalit y const ant s bet ween increm ent al variables of current and volt age. For t he linear m odel t o be valid, t he increm ent m ust be sm all com pared t o t he dc ( bias) value of t he variable. To qualify as sm all, t he increm ent m ust be sufficient ly sm all, in each case, as t o avoid unaccept able degrees of nonlinearit y in t he variable relat ionships. The condit ions are explored in Unit 5 in connect ion wit h linearit y of an am plifier gain funct ion. I n t he following, t he t hree conduct ance param et ers are explored, and in each case, an expression for obt aining t he circuit value is developed. The discussion is based on a st andard am plifier st age t o provide for an associat ion wit h elect ronic circuit s.

4.1 Amplifier Circuit and Signal Equivalent Circuits To serve as an illust rat ion of t he ut ilit y of t he param et ers, t he discussion of t he linear m odel and g param et ers will be accom panied by a signal- perform ance evaluat ion of an NMOS t ransist or in t he m ost general am plifier configurat ion ( Fig. 4.1) . The circuit includes drain and source resist ors, and input is at t he gat e t erm inal. As shown in Fig. 4.1( b) , out put can be at t he drain ( com m on- source am plifier) or source ( source- follower am plifier) .

Figu r e 4 .1 . ( a ) I de a l N M OS in a ba sic com m on - sou r ce a m plifie r cir cu it ( ou t pu t , V ocs) . D c supply n ode s of Fig. 4 .1 ( a ) a r e se t t o ze r o volt s t o obt a in t h e sign a l cir cu it s of Fig. 4 .1 ( b) a n d ( c) . An a lt e r n a t ive ou t pu t is V oe f [ sh ow n in ( b) ] , w h ich is t he sou r ce - follow e r a m plifie r st a ge . Volt a ge va r ia ble V g is t h e in put for bot h ca se s.

Figure 4.1 shows t he dc ( bias) circuit ( a) and signal circuit ( b) . Replacing all dc nodes wit h signal ground and replacing t he dc variables wit h signal variables as in Fig. 4.1 produces t he signal circuit . I t will be assum ed t hat t he schem at ic sym bol for t he t ransist or in signal circuit ( b) is equivalent t o t he ideal, int rinsic linear m odel of t he t ransist or. The t ot al drain current of t he m odel is I d = g m Vgs, as, for exam ple, in t he basic circuit of Fig. 2.4. The linear equivalent m odel is t hat of Fig. 4.1( c) . The sym bolic t ransist or in Fig. 4.1( b) is m ore int uit ively represent at ive in t erm s of t he overall circuit perspect ive t han t hat of Fig. 4.1( c) . For t his reason, t he Fig. 4.1( b) version is chosen for use in all of t he following discussions of MOSFET circuit s. All ot her det ails of t he t ransist or m odel, as discussed in t his unit , will be added ext ernally. Signal Vg = Vi is applied t o t he gat e ( input ) and, in response, a signal volt age, Vo , appears at t he drain ( or source) . We would like t o analyze t he signal perform ance in t erm s of volt age gain, a v = Vo / Vi = Vd / Vg ( or a v = Vs/ Vg ) , of t he circuit based on a linear ( sm all- signal) analysis. I n any case, t he volt age gain is a v = Gm Rx , where Gm is t he circuit t ransconduct ance ( as opposed t o t he t ransist or t ransconduct ance) and x = D ( com m on source) or x = S ( source follower) . Thus, t he goal will be t o obt ain a relat ion for Gm for a given linear m odel of t he t ransist or. Circuit t ransconduct ance is det erm ined in t he following for m odels wit h t he various param et ers included.

4.2 Transistor Variable Incremental Relationships As illust rat ed previously diagram m at ically, for exam ple, in Fig. 3.2, t he MOSFET is a fourt erm inal device. The four- t erm inal version of t he schem at ic sym bol is repeat ed here in Fig. 4.2. The t erm inals again are t he source, drain, gat e, and body. The drain current and t he t hree t erm inal- pair volt ages are all int erdependent such t hat i D = f( v DS, v GS, v SB) . Use of t he t hreet erm inal schem at ic sym bol for t he t ransist or, as in Fig. 4.1, conveys t he assum pt ion t hat t he body and source are connect ed. For an applied increm ent al Vgs, for exam ple, t here will be, in response, increm ent al drain current I d and increm ent al volt ages Vds and Vsb . The linear m odel is based on relat ing t he current t o t he t hree volt ages. This is

Equ a t ion 4 .1

Figu r e 4 .2 . Fou r - t e r m in a l N M OS sch e m a t ic sym bol in a com m on sou r ce con figu r a t ion .

The linear- m odel represent at ion is shown in Fig. 4.3. Figure 4.3( a) shows a current - source version. The body- effect param et er, g m b , is defined as posit ive. The m inus sign is required as t he part ial derivat ive in ( 4.1) is negat ive. I n Fig. 4.3( b) t he body- effect current source is reversed t o elim inat e t he m inus sign, and t he current source associat ed wit h g ds is replaced wit h a resist ance. The lat t er is possible as t he volt age- dependent current source is bet ween t he sam e nodes as t he volt age.

Figu r e 4 .3 . ( a ) Lin e a r m ode l t h a t in clu de s a ll con t r ibu t ion s t o t h e sign a l dr a in cu r r e n t , I d , a s give n in ( 4 .1 ) . Th e body- e ffe ct pa r a m e t e r , g m b , is a posit ive n u m be r su ch t ha t cu r r e n t fr om t he cu r r e n t sou r ce is in t he dir e ct ion opposit e t h e a r r ow . ( b) Cu r r e n t sou r ce of body e ffe ct is r e ve r se d t o e lim in a t e t he m in u s sign , a n d a r e sist or r e pla ce s t h e g ds cu r r e n t sou r ce .

I n t he following unit s, using t he det ailed funct ions ( 3.8) and ( 3.14) , which relat e t he four variables, expressions, as used in SPI CE, will be obt ained for t he t hree proport ionalit y const ant s: t ransconduct ance param et er, g m , out put conduct ance param et er, g ds, and bodyeffect t ransconduct ance param et er, g m b . The result s will be used t o obt ain num erical result s for t he circuit t ransconduct ance, Gm , for various cases.

4.3 Transconductance Parameter The t ransconduct ance param et er, g m , was int roduced in Unit 2 in t he t reat m ent on t he rudim ent ary elect ronic am plifier; it is t he proport ionalit y const ant of t he linear relat ionship bet ween t he out put ( responding) current and t he input ( cont rol) volt age [ ( 2.3) ] . For t he MOSFET, NMOS, or PMOS, I d = g m Vgs, where I d is int o t he drain for bot h t ransist or t ypes. An ideal t ransist or can be m odeled wit h t his alone. A sim ple m odel, which includes no ot her com ponent s, would oft en be adequat e for m aking est im at es of circuit perform ance. To obt ain an expression for g m as a funct ion of t he general form i D = f( v GS, v DS, v SB) [ e.g., ( 3.8) ] , we use t he definit ion [ from ( 4.1) ]

Equ a t ion 4 .2

Using ( 3.8) t o express i D , t he result ing relat ion for g m is

Equ a t ion 4 .3

where [ ( 3.7) ] and Veffn = VGS – Vt no . Not e t hat t he use of VDS is consist ent wit h t he part ial derivat ive t aken wit h respect t o v GS, t hat is, Vds = 0. Also, t he use of Vt no im plies t hat v SB = 0. I n general, VSB could be nonzero, alt hough in t he definit ion of g m , Vsb m ust be zero. For t he case of nonzero VSB ( bias) , one subst it ut es for Vt no a const ant Vt n ( VSB) in t he g m expression. Alt ernat ive form s for t he g m expression can be obt ained from ( 3.8) , which is, solving for Veffn ,

Equ a t ion 4 .4

Using ( 3.8) , ( 4.3) , and ( 4.4) , g m t akes on alt oget her t hree form s:

Equ a t ion 4 .5

Usually, in init ial design, k n replaces penalt y in accuracy.

t o elim inat e t he VDS dependence wit hout a serious

Using t he sim ple linear t ransist or m odel, an expression for t he circuit t ransconduct ance, Gm , for t he circuit of Fig. 4.1 will now be obt ained. The input loop equat ion for an applied gat e signal volt age, Vg , is

Equ a t ion 4 .6

which is, wit h Vgs = I d / g m ,

Equ a t ion 4 .7

and

Equ a t ion 4 .8

The far right - hand side uses ( 4.5) . For exam ple, for a 1- V drop across RS and Veffn = 0.5 V, Gm = g m / 5. Not e t hat t he rat io of t he signal volt age drop across RS and signal volt age Vgs is g m RS: 1. The Gm concept is ut ilized rout inely in MOSFET circuit s ( and BJT circuit s) , which gives t he effect ive reduced t ransconduct ance, referred t o Vg , in t he presence of t he source resist or.

4.4 Body-Effect Transconductance Parameter For circuit s in which t he signal Vsb is nonzero, t here will be an addit ional com ponent of I d , g m b Vsb . An exam ple is t he circuit of Fig. 4.1 but wit h body t erm inal connect ed t o ground. This feat ure is added t o t he circuit as shown in Fig. 4.4. The proport ionalit y const ant for t his case, g m b , is t he body- effect t ransconduct ance. I t is defined as

Equ a t ion 4 .9

Figu r e 4 .4 . Sign a l cir cu it w it h t h e a ddit ion of a cu r r e n t sou r ce du e t o t h e body e ffe ct . I n t h is e x a m ple , V b = 0 V a n d V sb = I d R S.

which is [ wit h ( 3.8) and ( 3.14) for i D and Vt n ]

Equ a t ion 4 .1 0

The m inus sign is consist ent wit h a current source in t he opposit e direct ion from t hat of Fig. 4.4 ( as shown in Fig. 4.3) as i D is defined as posit ive int o t he drain. The preference is t o t urn t he current source around as in Figs. 4.3 and 4.4 and use posit ive g m b . The result for g m b is a fact or, η, t im es g m , t hat is

Equ a t ion 4 .1 1

For γn = 0.5 V1/ 2 , VSB = 5 V, and 2ΦF = 0.7 V, g m b = 0.1g m ( η = 0.1) . Not e t hat g m b is not zero even wit h t he source connect ed t o t he body [ i.e., wit h VSB = 0 in ( 4.11) ] . However, signal Vsb is zero in such a case, such t hat g m b does not have t o be t aken int o account . I n general, even

wit h VSB 0 it is possible for Vsb 0, in which case, g m b m ust be included in t he m odel ( e.g., in Proj ect 8 on t he st udy of t he source- follower st age, at t he low end of t he bias current scan) .

4.5 Output Conductance Parameter The out put conduct ance account s for t he finit e slope of t he out put charact erist ic, an exam ple of which is shown in Fig. 4.5. The plot for t he SPI CE form ulat ion [ ( 3.8) ] of t he act ive region is also shown ( applicable t o t he device for VDS > Veffn ) . Bot h plot s are for VGS = const ant ( i.e., Vgs = 0 and g m Vgs = 0) .

Figu r e 4 .5 . Ou t pu t ch a r a ct e r ist ics illu st r a t in g n on z e r o a ct ive - r e gion slope . Also sh ow n is t h e SPI CE for m u la t ion for t h e a ct ive r e gion . For t h e plot s, λn = 1 / 1 0 V. A possible bia s poin t w it h I D a n d V D S is in clu de d.

I n t he ideal case, for any v DS in t he act ive region, t he current is t he sam e for a given VGS, and t he drain current is sim ply I d = g m Vgs. The real case, t hough, obviously possesses a current dependence on v DS. The linear m odel t reat s g m as a const ant ( calculat ed at t he bias values) and includes t he effect of t he nonzero slope wit h t he out put conduct ance, g ds, such t hat I d = g m Vgs + g dsVds ( wit hout or neglect ing t he body effect ) . The circuit shown in Fig. 4.6 includes t he g ds com ponent .

Figu r e 4 .6 . Sign a l cir cu it t ha t in clu de s a ddit ion of t h e out pu t con du ct a n ce . Th e e qu iva le n t r e sist a n ce h a s m a gn it u de 1 / g ds.

An expression for t he out put conduct ance is obt ained from t he definit ion

Equ a t ion 4 .1 2

Again using ( 3.8) , t he result is

Equ a t ion 4 .1 3

where Veffn = VGS – Vt no is const ant and where I D is t he dc ( bias) current . The last t erm ( on t he right - hand side) is t he form t hat is generally used in pract ice for an init ial design, as it does not require a value for VDS. Not e t hat g ds is not a conduct ance in t he physical sense but has t he correct dim ensions and behaves in t he circuit like a conduct ance. We will now obt ain t he circuit t ransconduct ance for t he case where t he effect of g ds is included. Upon applicat ion of an input signal, Vg , a signal drain current , I d , will flow in t he out put circuit . This causes a signal volt age t o appear across RS and RD , which is equal t o t he volt age t o Vds. That is,

Equ a t ion 4 .1 4

The associat ed current t hrough t he out put resist ance is t hus

Equ a t ion 4 .1 5

The effect is t o reduce t he current t hrough RS and RD and t hus reduce t he circuit t ransconduct ance of t he com m on- source am plifier st age. The out put current wit h t he current of ( 4.15) subt ract ed from t he basic g m Vgs is

Equ a t ion 4 .1 6

which is, when solved for Vgs,

Equ a t ion 4 .1 7

Again using ( 4.6) , which is Vg = Vgs + I d RS, t he new circuit t ransconduct ance is

Equ a t ion 4 .1 8

Wit h a 1 - V drop across RS and a 5 - V drop across RD , and wit h λn = 1/ 50 V, t he new Gm is g m / 5.12, com pared wit h g m / 5 when neglect ing g ds [ ( 4.8) ] . I n general, t he com plet e circuit includes, in addit ion, t he body- effect t ransconduct ance current source of Figs. 4.3 and 4.4. The om ission of t his current source in Fig. 4.6 im plies t hat Vsb = 0 because t he source and body are connect ed. This connect ion is possible t o im plem ent in special cases such as in som e of our MOSFET lab proj ect s where only one t ransist or on t he chip is used or for t he case of a different ial st age where t he source of t wo t ransist ors is at t he sam e node. I t is also possible t o elim inat e t he body- effect current source by bypassing t he source resist or wit h a bypass capacit or. The capacit or places t he source at signal ground. However, in t his case, t he dc t hreshold volt age is st ill affect ed by VSB = I D RS. I n Unit 8, t he circuit t ransconduct ance equivalent t o ( 4.8) and ( 4.18) , but which includes t he body effect [ ( 8.49) ] , is given as

where η is defined in ( 4.11) . For g ds = 0 and η = 0, ( 4.19) reduces t o ( 4.8) . Not e t hat including t he body effect will in general have m ore effect on Gm t han including g ds, as η can be on t he order of 0.2. I n all cases where we can calculat e t he circuit t ransconduct ance, Gm , t he m agnit ude of t he volt age gain is obt ainable from –Gm RD ( com m on- source st age) and Gm RS( source- follower st age) .

4.6 Graphical Perspective of Output Characteristics and the Load Line The t ransist or out put charact erist ics from Unit 3 and t he variable increm ent s along wit h t heir linear relat ionships are illust rat ed in Fig. 4.7. This would be applicable, for exam ple, t o t he am plifier of Fig. 2.4. ( As in t hat circuit , no body effect is included.) The circuit is biased wit h drain – source volt age VDS and drain current I D . A posit ive signal Vg is applied t o t he gat e t erm inal. I n response, t here appears drain signal volt age –Vd , due t o t he rise in drain current . Signal volt ages are wit h respect t o t he source or ground.

Figu r e 4 .7 . Tr a n sist or ou t pu t ch a r a ct e r ist ics w it h out a n d w it h in put sign a l, V g . A solut ion for t h e dr a in cu r r e n t a n d dr a in – sou r ce volt a ge in bot h ca se s is t h e in t e r se ct ion be t w e e n t h e r e spe ct ive ch a r a ct e r ist ics a n d t h e loa d lin e of t h e a m plifie r cir cu it .

The t wo out put charact erist ic curves correspond t o bias VGS only and wit h gat e volt age VGS + Vg . I n bot h cases, t he solut ion t o t he drain current and volt age is t he int ersect ion bet ween t he t ransist or charact erist ic curve and t he load line, which is a plot of t he out put circuit loop equat ion. This is ( wit h reference, for exam ple, t o Fig. 2.4)

Equ a t ion 4 .1 9

The solut ion is always const rained t o t his st raight - line equat ion. The solut ion for v DS wit h and wit hout signal is based on ( 4.19) and ( 3.8) , which is

The com bined cont ribut ions t o I d associat ed wit h t he t wo g param et ers is

Equ a t ion 4 .2 0

By t he nat ure of t he load- line funct ion, t he t wo t erm s will always have opposit e signs; when Vg is negat ive, Vd will be posit ive.

4.7 Summary of Equations Transconduct ance.

where

Approxim at e t ransconduct ance.

where

Am plifier circuit t ransconduct ance wit h a source resist ance. Body- effect t ransconduct ance.

Out put conduct ance. g ds = λn I D

Approxim at e out put conduct ance. Am plifier circuit t ransconduct ance wit h g ds included.

Subscript s are for NMOS. All equat ions are t he sam e for PMOS wit h " p" subscript subst it ut ion and subscript - order reversal for bias- volt age variables.

Unit 5. Common-Source Amplifier Stage Two t ypes of com m on- source am plifiers will be invest igat ed in lab proj ect s. One is wit h t he source grounded and t he ot her is wit h a current - source bias ( dual power supply) . I n Unit s 5.1 and 5.2 we discuss various aspect s of t he com m on- source st age wit h grounded source, in Unit 5.3 we t ake up circuit - linearit y considerat ions, and in Unit 5.4 we cover t he basics of t he dualpower- supply am plifier. Bot h am plifiers are based on t he PMOS, as in t he proj ect s. The first t wo unit s are m ost ly a review of t he basic am plifier as present ed in previous unit s, t o reinforce t he basic concept s. The PMOS replaces t he NMOS ( Unit s 2 and 4) in t his unit , t o provide fam iliarit y wit h t he opposit e polarit y in bias considerat ions and t o illust rat e t hat t he linear m odel applies in t he sam e m anner for bot h t ransist or t ypes.

5.1 DC (Bias) Circuit Dc circuit s for t he grounded- source am plifier are shown in Fig. 5.1 ( PMOS) . The circuit in ( a) is based on a single power supply, and t he gat e bias is obt ained wit h a resist or volt age- divider net work. The circuit in ( b) is for a laborat ory proj ect am plifier. Bot h VGG and VSS are negat ive, since t he source is at ground. There is no volt age drop across RG since t here is negligible gat e current . RG is necessary only t o prevent short ing t he input signal, Vi . The bias current I D for a given applied VSG will respond according t o ( 3.8) , which is I D = k p ( VSG – Vt po ) 2 ( 1 + λp VSD)

Figu r e 5 .1 . Ba sic PM OS com m on - sou r ce a m plifie r s. Sin gle - pow e r su pply a m plifie r ( a ) a n d la bor a t or y a m plifie r ( b) w it h V SG ( = V GG) a n d V SS con t r olle d by D AQ out pu t ch a n n e ls. N ot e t ha t e it he r e nd of t h e cir cu it of ( a ) ca n be a t gr ou n d.

The t wo circuit s are equivalent , as VGG and RG of Fig. 5.1b are t he Thévenin equivalent of t he bias net work of t he Fig. 5.1( a) . I n t he proj ect on t he am plifier, t hey are act ually a volt age and a resist or. This is not a bias- st able circuit , as a slight change in VSG or t he t ransist or param et ers can result in a significant change in I D . The dual- power- supply circuit of Unit 5.4 is considerably bet t er in t his respect .

5.2 Amplifier Voltage Gain This dc ( bias) circuit becom es an am plifier now sim ply by adding a signal source at t he gat e as in Fig. 5.2. This requires a coupling capacit or, as shown here in t he com plet e circuit , t o prevent dist urbing t he bias upon connect ing t he input signal t o t he circuit .

Figu r e 5 .2 . A signa l sou r ce is con n e ct e d t o t h e ga t e t hr ou gh a cou plin g ca pa cit or . Th e ca pa cit or is n e ce ssa r y t o isola t e t h e dc cir cu it fr om t h e sign a l sou r ce .

I n t he am plifier of Proj ect 5, t he signal will be superim posed on t he bias volt age at t he node of VGG. This can be facilit at ed wit h LabVI EW and t he DAQ. A capacit or, as in an act ual am plifier, is t herefore not required. The requirem ent for having LabVI EW cont rol over bot h VGG and VSS, and t he lim it at ion of t wo out put channels, dict at es t his configurat ion. I n Proj ect 5 we m easure t he gain as a funct ion of bias current , I D . For a SPI CE com parison, we need an expression for t he gain. For t he ideal case, which neglect s t he out put conduct ance, g ds, t he out put current is relat ed t o t he input volt age by ( 4.1) , which is I d = g m Vgs = g m Vi The out put signal volt age is, in general,

Equ a t ion 5 .1

The convent ion used here for subscript order for signal ( linear) variables is com m on t o t he NMOS and PMOS. This is consist ent wit h t he fact t hat t he linear m odel does not dist inguish bet ween t he t wo t ypes. Thus, for exam ple, t he dc t erm inal volt age for a PMOS is VSG, but t he signal equivalent is Vgs ( Fig. 5.3) and t he signal input volt age is posit ive at t he input t erm inal ( com m on- source, gat e input ) . For t he PMOS, i D is defined as posit ive out of t he drain, but t he signal out put current is int o t he drain ( as in t he NMOS) . We not e t hat a posit ive Vgs ( Vgs = – Vsg ) corresponds t o a decrease in t he t ot al gat e – source volt age, v SG, which is consist ent wit h a decrease of i D and posit ive I d .

Figu r e 5 .3 . Sign a l- e qu iva le n t ve r sion of t he a m plifie r st a ge . D c n ode s a r e se t t o ze r o volt s ( cir cu it r e fe r e n ce ) . Th e r e a ct a n ce of Cg is a ssu m e d t o be ze r o.

Thus, t he negat ive sign in ( 5.1) is consist ent wit h t he flow of current I d up t hrough t he resist or ( Fig. 5.3) for posit ive Vi = Vgs. The com m on- source st age is an invert ing am plifier and has an inherent 180° phase shift . From ( 4.1) and ( 5.1 ) , t he gain is

Equ a t ion 5 .2

where bot h Vi = Vgs and Vo = Vds are wit h respect t o ground or t he source t erm inal for t he com m on- source st age. I f t he out put resist ance, 1/ g ds, cannot be neglect ed ( which is t he case for t he proj ect on PMOS am plifiers) , t he t ransist or current , g m Vi , is shared bet ween t he out put resist ance and RD . The port ion t hat flows t hrough RD is ( Fig. 5.4)

Equ a t ion 5 .3

Figu r e 5 .4 . Com m on - sou r ce a m plifie r st a ge sign a l cir cu it , w it h a ll dc n ode s se t t o ze r o volt s. Th e t ra n sist or m ode l in clu de s ou t pu t r e sist a n ce 1 / g ds, w h ich a ppe a r s dir e ct ly in pa r a lle l w it h R D w it h t h e sou r ce gr ou n de d.

Not e again t hat t he signal schem at ic t ransist or represent s a current source wit h value g m Vi , as est ablished in connect ion wit h Fig. 4.1. The addit ional feat ure of t he t ransist or m odel is included wit h t he addit ion of 1/ g ds. This resist ance is act ually part of t he t ransist or and is

bet ween t he drain and source of t he t ransist or, but t he circuit as given is equivalent , as t he source is at ground. Since t he out put volt age is Vo = –I RD RD , t he new gain result is

Equ a t ion 5 .4

Not e t hat t his form evolves from ideal t ransist or current , g m Vgs, flowing t hrough t he parallel com binat ion of t he out put resist ance and RD . To facilit at e an int uit ive grasp of t he m agnit ude of t he effect of g ds, we use t he expression for g ds ( 4.13) in ( 5.4) , t o obt ain

Equ a t ion 5 .5

Not e t hat I D RD is t he volt age drop across RD . For exam ple, for a –10- V power supply, we choose I D RD 5 V. A m easurem ent of λp for our devices will show t hat λp 1/ 20 V, which result s in λp I D RD 1/ 4. Thus, t he effect of g ds ( = λp I D ) for t his case is significant . Finally, we can get an overall current dependence for a v wit h t he elim inat ion of g m , using( 4.5) wit h

k p , which result s in

Equ a t ion 5 .6

Using an alt ernat ive form for g m ( = 2I D / Veffp ) , also ( 4.5) , t he gain expression is

Equ a t ion 5 .7

where

For sim plicit y, approxim at e form s of ( 4.5) and ( 4.13) of g m and g ds are used here, which are independent of VSD. For reference, t he " exact " and approxim at e form s of ( 4.5) and ( 4.13) , respect ively, are repeat ed here:

and

The " exact " equat ions of g m and g ds are used in conj unct ion wit h t he am plifier proj ect s t o com pare t he com put ed gain wit h t he m easured gain plot t ed against I D . This is done in bot h LabVI EW and Mat hcad. Param et ers k p and Vt po ( t o get Veffp ) will be ext ract ed from t he m easured dc dat a, and λp will be used as an adj ust able param et er t o fit t he SPI CE and m easured gain dat a.

5.3 Linearity of the Gain of the Common-Source Amplifier The connect ion bet ween I d and Vgs is linear provided t hat Vgs is sm all enough, as considered in t he following unit s. Use of t he linear relat ions also assum es t hat t he out put signal rem ains in t he act ive region ( i.e., neit her in t he linear region nor near cut off) . This is discussed below. NMOS subscript s are used. The result s are t he sam e for t he PMOS, wit h a " p" subscript subst it ut ed for " n" and t he subscript order reversed for all bias- volt age variables.

5.3.1 Nonlinearity Referred to the Input The general equat ion again is ( 3.8)

Then using I d = i D – I D and v GS = VGS + Vgs, t he equat ion for t he increm ent al drain current becom es

Equ a t ion 5 .8

which leads t o a nonlinear ( variable) t ransconduct ance,

, given by

Equ a t ion 5 .9

Therefore, t he condit ion for linearit y is t hat Vgs < < 2Veff , wit h Veffn = VGS = Vt no and using . Wit h t his condit ion not sat isfied, an out put signal is dist ort ed. However, for t he purpose of m easuring t he am plifier gain, our signal volt m et er will t ake t he average of t he posit ive and negat ive peaks, which is

Equ a t ion 5 .1 0

I n t he parabolic relat ionship, t he squared t erm s cancel ent irely. I n general, t hough, t he out put signal cont ains harm onic cont ent ( dist ort ion) when Vgs is t oo large com pared t o Veffn .

5.3.2 Nonlinearity Referred to the Output The discussion above of lim it s im posed on Vgs assum es t hat t he t ransist or rem ains in t he act ive m ode. To clarify t his point , reference is m ade t o t he out put charact erist ics of Fig. 5.5. The

graph has plot s of t he out put charact erist ic for t hree values of v GS in addit ion t o t he load line. The charact erist ic plot in t he m idrange is for no signal. Operat ing point variables are VDS 2.5 V and I D 40 µA. Wit h a large, posit ive Vgs, t he charact erist ic m oves up t o t he high- level plot ( i Dhi ) and t he opposit e occurs for a large but negat ive Vgs ( i Dlo ) . The high- level plot is shown for when t he t ransist or is about t o m ove out of t he act ive region and int o t he linear region. At t em pt s t o force v DS t o lower values will creat e considerable dist ort ion in t he out put signal volt age. The lower curve suggest s t hat t he posit ive out put signal is on t he verge of being cut off ( clipped) for an addit ional increase in t he negat ive- input signal volt age.

Figu r e 5 .5 . Com m on - sou r ce a m plifie r st a ge ou t pu t ch a r a ct e r ist ics. Ou t pu t ch a r a ct e r ist ics a r e fr om t op t o bot t om , la r ge h igh - cu r r e n t sign a l sw in g, i D h i , dc bia s, I D , low - cu r r e n t sign a l sw in g, i D lo . Also show n is t h e loa d lin e . Th e cu r r e n t – volt a ge cir cu it solu t ion is a lw a ys t h e in t e r se ct ion be t w e e n a give n ch a r a ct e r ist ic a n d t h e loa d lin e .

According t o t he discussion above, t he negat ive signal out put volt age is lim it ed t o

Equ a t ion 5 .1 1

Technically, Veffn is from t he high- current signal st at e, but for sim plicit y, a reasonable est im at e can be m ade from t he dc case; t hat is, Veffn = VGS – Vt no . The posit ive signal lim it is

Equ a t ion 5 .1 2

The act ual out put - signal lim it is dict at ed by t he sm aller of t he t wo for a sym m et rical periodic signal such as a sine- wave. I n t he exam ple shown in Fig. 5.5, Veffn 0.5 V, VDS 2.5 V, and VDD = 5 V. The plus and m inus signal- volt age lim it s are about 2.5 V and 2.0 V, respect ively. Depending on t he dc bias, t he lim it could be dict at ed by one or t he ot her. I n t he am plifier proj ect s, t he gain will t ypically be m easured over a range of dc bias current for a fixed resist or. This m eans t hat for t he low- current end of t he scan, t he signal will be lim it ed by t he m agnit ude of I D RD and, by design, t he plus and m inus swings will be m ade t o be about equal at t he highest dc current . Dist ort ion associat ed wit h t he nonlinear I d – Vgs relat ion and t hat due t o signal lim it s at t he out put m ay be t aking place sim ult aneously. This is seen from t he gain expression ( 5.7) ( g ds = 0)

where a v Vds/ Vgs and where t he approxim at ion is for t he case of neglect ing t he λn fact or. Thus, for a given Vds, Vgs is

Equ a t ion 5 .1 3

I f, for exam ple, Vds is pushed t o t he posit ive out put - signal lim it , t hen Vds VRD . According t o ( 5.13) , Vgs = Veffp / 2, and Vgs exceeds t he condit ion for a linear I d – Vgs relat ion as given in ( 5.9) ,

5.4 Current-Source Common-Source Amplifier: Common-Source Amplifier with a Source Resistor The bias circuit of t he current - source bias am plifier, shown in Fig. 5.6, has a dual power supply. One advant age of t his is t hat t he input is at zero dc volt s such t hat t he signal can be connect ed direct ly wit hout int erfering wit h t he bias. The dc circuit equat ion for set t ing up t he bias is

Equ a t ion 5 .1 4

where

.

This circuit is m ore bias st able t han t he grounded source am plifier, as slight changes in VSG ( due t o device param et er variat ions or t em perat ure) are usually sm all com pared t o VDD. Not e t hat Vt p is used in lieu of Vt po as VBS 0. The chip ( CD4007) used in t he proj ect s is a p- well device ( as not ed in Unit 3) , wit h t he NMOS t ransist ors in t he well. The well is connect ed t o VSS, while t he body of t he chip is connect ed, as in Fig. 5.6, t o VDD. The pn j unct ion form ed by t he well and t he bulk is t hus reverse- biased wit h a volt age | VSS| + VDD.

Figu r e 5 .6 . D c cir cu it of t h e du a l- pow e r - su pply com m on - sou r ce a m plifie r . Th e ga t e is a t gr ou n d pot e n t ia l, a llow in g t h e signa l t o be con n e ct e d dir e ct ly t o t h e ga t e . R G is n e ce ssa r y on ly t o pr e ve n t sh or t in g ou t t h e in put signa l.

I n t he am plifier proj ect s, however, we have t he lat it ude t o connect t he body and source as t here is only one t ransist or in t he circuit and t he body can float along wit h t he source. Thus we can assum e t hat Vt p = Vt po . As shown in Fig. 5.7, t he signal circuit requires t he addit ion of a bypass capacit or, Cs. This places t he source at signal ground provided t hat t he capacit or is large enough. The crit erion for t his is discussed in Unit 6. The volt age- gain equat ion is t he sam e as in t he am plifier, wit h t he source act ually grounded.

Figu r e 5 .7 . Am plifie r cir cu it w it h a bypa ss ca pa cit or a t t a ch e d be t w e e n t h e sou r ce a n d gr ou n d t o t ie t h e sou r ce t o sign a l gr oun d. Sign a l in pu t

is a t t a ch e d dir e ct ly t o t h e ga t e . Body a n d sou r ce a r e con n e ct e d in t e r n a lly in t h e pr oj e ct ch ip for t he t r a n sist or u se d in t h e a m plifie r .

Wit hout t he bypass capacit or, RS is in t he signal circuit and a fract ion of t he applied signal volt age at t he gat e is dropped across t he resist or. The signal circuit for t his case is shown in Fig. 5.8. The circuit t ransconduct ance of t he am plifier wit h RS was discussed init ially in Unit 4. This is reviewed in t he following. An applied input signal, Vi = Vg , divides bet ween t he gat e – source t erm inals and t he source resist or according t o [ ( 4.6) ] Vg = Vgs + I d Rs

Figu r e 5 .8 . Sign a l cir cu it for du a l- pow e r su pply com m on - sou r ce a m plifie r . I n pu t sign a l volt a ge , V i , is divide d be t w e e n V gs, t h e con t r ol volt a ge , a n d t h e sou r ce r e sist or a ccor din g t o t he r a t io 1 : g m R S.

When com bing t his wit h I d = g m Vgs, we obt ain [ ( 4.7) ]

The circuit t ransconduct ance, Gm , is t hen [ ( 4.8) ]

The gain for t his case is t hus ( neglect ing g ds)

Equ a t ion 5 .1 5

I n one of t he am plifier proj ect s, RS = RD , and t he gain wit hout t he bypass capacit or is act ually less t han unit y.

5.5 Design of a Basic Common-Source Amplifier Unlike in t he laborat ory environm ent , an act ual pract ical com m on- source am plifier would have a single power supply for t he base and collect or circuit bias. Also, t he circuit design requires a t olerance t o a wide range of param et er variat ion, including t hat due t o t em perat ure change. I n t his unit , t he design process for a possible com m on- source am plifier is discussed. Em phasis is on dc bias st abilit y, t hat is, on t olerance t o device param et er and circuit com ponent variat ions. The com m on- source am plifier t o be designed is shown in Fig. 5.9. Source resist or, RS, is included for bias ( and gain) st abilizat ion. The goal is for t he circuit t o funct ion properly for any NMOS t ransist or, which has device param et ers k n and Vt no t hat fall int o a wide range of values, as is norm ally expect ed. Tolerance t o com ponent variat ion, such as resist or values, could also be built int o t he design.

Figu r e 5 .9 . N M OS com m on - sou r ce a m plifie r w it h R S for bia s a n d ga in st a biliza t ion . Ga t e bia s is pr ovide d by a volt a ge - divide r n e t w or k con sist in g of R G1 a nd R G2 . Th e body a n d sou r ce t e r m in a ls a r e con n e ct e d.

Gat e volt age VG is provided by t he volt age divider, consist ing of resist ors RG1 and RG2 . Since t here is no gat e current , t he gat e bias volt age is [ ( 1.2) ]

Volt age VG is t hus relat ively st able and can be considered const ant . Once VG has been est ablished, t he drain current will be dict at ed by

Equ a t ion 5 .1 6

Since t he gat e – source volt age is given by

Equ a t ion 5 .1 7

t he drain current , I D , m ay be expressed in t erm s of t he device param et ers as

Equ a t ion 5 .1 8

This result reveals t he dependence of I D on t he m agnit udes of k n and Vt no . ( Again, for sim plicit y, as in t he am plifier proj ect s, we will assum e t hat t he body and source are connect ed such t hat Vt n = Vt no .) Bias current I D is assum ed t o be a given. The init ial design t hen is conduct ed for t he NMOS nom inal, average values for k n and Vt no . Any com binat ion of VG and RS t hat sat isfies ( 5.18) will provide t he design I D . Specific values for VG and RS will be dict at ed by st abilit y requirem ent s. Suppose t hat k n is expect ed t o fall wit hin k no ± δk n and Vt no wit hin Vt noo ± δVt no , where k no and Vt noo are t he nom inal values of t he original design. Assum e t hat t he design bias current associat ed wit h k no and Vt noo is I Do . At t he ext rem es for t he param et ers, t he low and high current s will be

Equ a t ion 5 .1 9

Resist or RS, for t he given VG and design drain current , is

Equ a t ion 5 .2 0

VGSo is obt ained from ( 5.17) , using t he nom inal param et er values. The low and high current lim it s t end t o converge on VG/ RS as VG becom es large. That is, in t he lim it , VG dom inat es t he volt ages in t he num erat or of ( 5.19) , t hus rendering t he expression insensit ive t o t he m inor cont ribut ions from changes in k n and Vt no . An im port ant design considerat ion is drain – source volt age, VDS, as t his dict at es t he out put signal range. This is calculat ed from

Equ a t ion 5 .2 1

I n t he design of t he am plifier, drain resist or RD is norm ally select ed for equal posit ive and negat ive peak- signal m axim um s. This configurat ion is illust rat ed in Fig. 5.10, which shows t he out put charact erist ic of t he t ransist or in t he circuit . The signal is lim it ed by VDD – VRS and Veffno

= VGSo – Vt no at t he high and low ends of t he volt age range, respect ively. Therefore, nom inal bias should be set at

Equ a t ion 5 .2 2

Figu r e 5 .1 0 . Ou t pu t ch a r a ct e r ist ic of t he t r a n sist or of t h e a m plifie r w it h bia s V D S se t a ppr ox im a t e ly a ccor din g t o ( 5 .2 2 ) . Th e sign a l is r e st r ict e d w it h in t h e r a n ge V D D – V RS a n d a ppr ox im a t e ly v e ffn . The ch a r a ct e r ist ic cu r ve s a r e for n o sign a l ( solid plot ) a nd for t h e sign a l a t a m a x im u m ( da sh e d plot ) , a s lim it e d by t h e t r a n sist or goin g in t o t h e in a ct ive ( lin e a r ) r e gion . The loa d lin e s a r e dc ( solid lin e ) a n d sign a l ( a c, da sh e d lin e ) .

For sim plicit y, it is assum ed t hat v effn Veffno . Veffno , VDDo , and I Do are t he bias values at t he nom inal param et er values. The bias drain volt age is VDSo plus t he drop across RS, t hat is,

Equ a t ion 5 .2 3

Knowing VDo t hen provides for t he calculat ion of RD from

Equ a t ion 5 .2 4

where VDo and I Do are for t he init ial design wit h k no and Vt noo .

An opt im izat ion design sequence plot s t he lim it s for a range of VG and for specified δVt no and δk n . An exam ple is shown in Fig. 5.11. The plot of VDSo corresponds t o t he nom inal k no and Vt noo . The curve slopes downward as I SRS increases for increasing VG at const ant nom inal bias current , I Do . VDShi is for t he com binat ion of δVt no and δk n , which gives t he m axim um posit ive deviat ion from t he nom inal, and VDSlo is t he opposit e. The exam ple of Fig. 5.11 is for VDD = 10 V and design bias current of I Do = 100 µA and nom inal param et ers k no = 300 µA/ V2 , Vt noo = 1.5

V, δVt no = 0.1 V, and δk n = 100 µA/ V2 . Experience wit h t he CMOS chip of our am plifier proj ect ( Proj ect 7) indicat es t hat t hese are represent at ive.

Figu r e 5 .1 1 . Com pu t e d h igh a n d low r a n ge of V D S a s a fu n ct ion of ga t e bia s volt a ge V G. Th e com pu t a t ion is w it h k n o = 3 0 0 µA/ V 2 , V t n oo = 1 .5 V , δV t n o = 0 .1 V, a nd δk n = 1 0 0 µA/ V 2 .

Figure 5.12 shows plot s of t he com put ed posit ive and negat ive signal- peak lim it s. Due t o t he increasing VRS wit h increasing VG, t he signal range decreases, as shown by t he plot s. Thus, t he signal- peak lim it s have a m axim um , as is evident in t he graph. The design of t he am plifier uses VG at t he m axim um of t he lower curve. The value of VG is consist ent wit h t he m axim um VDSlo in t he plot of Fig. 5.11. I n t he exam ple, VG 3V.

Figu r e 5 .1 2 . Com pu t e d m a x im u m s for n e ga t ive a n d posit ive ou t pu t volt a ge sign a l pe a k s a s a fu n ct ion of V G: V dplu s, posit ive m a x im u m ; V dm in u s, n e ga t ive m a x im u m .

Once VG is det erm ined, t he select ion of RG1 is m ade from ( 1.2) , which is

where RG is t he parallel com binat ion

RG can be select ed som ewhat arbit rarily but could be dict at ed by t he coupling capacit or, CG, requirem ent . Associat ed wit h t he coupling capacit or is t he 3 - dB frequency ( 6.2) , which is

RG2 is t hen calculat ed from

The gain equat ions for t he circuit of Fig. 5.9, wit h and wit hout a bypass capacit or, are ( 5.2) and ( 5.15) , respect ively. These are a v = –g m RD and

I n t he design procedure out lined in t his unit , em phasis is on st abilit y and t he gain falls out . This would t ypically be t he case for t his t ype of am plifier. We not e t hat due t o t he charact erist ically sm all g m of MOSFETs, t he volt age gain is relat ively sm all. Gain can be im proved considerably t hrough t he use a current - source load, as in t he am plifier of Unit 10.

5.6 Summary of Equations a v = –g m RD

Com m on- source am plifier- st age volt age gain. Com m on- source am plifier gain including out put resist ance, PMOS. ( Sam e for NMOS wit h λn .) Nonlinear t ransconduct ance for large input signals. ( Sam e for PMOS wit h Veffp .)

Vdsm inus = VDS - Veffn

Negat ive out put signal lim it , NMOS.

Vdsm inus = VSD - Veffn

Negat ive out put signal lim it , PMOS.

Vdsplus = VDD - VDS = I D RD

Posit ive out put signal lim it , NMOS.

Vdsplus = | VSS| - VSD = I D RD

Posit ive out put signal lim it , PMOS.

Volt age gain of com m on- source st age wit h source resist or.

Circuit t ransresist ance of com m on- source st age wit h source resist or.

5.7 Exercises and Projects Proj ect Mat hcad Files Exercise05.m cd - Proj ect 05.m cd La bor a t or y Pr oj e ct 5

PMOS Com m on- Source Am plifier P5.2

PMOS Com m on- Source Am plifier DC Set up P5.3

Am plifier Gain at One Bias Current P5.4

Am plifier Gain versus Bias Current

Unit 6. Coupling and Bypass Capacitors and Frequency Response As not ed in Unit 1, due t o t he ext ernal capacit ors t hat are at t ached t o t he circuit for configuring t he signal circuit , t he gain of t he am plifiers will t end t o fall off at t he low- frequency end of t he frequency spect rum . The design basis for choosing t he capacit ors for a given applicat ion is considered in t he following. The gain- frequency dependence due t o t he input coupling capacit or, t he source- resist or bypass capacit or, and t he load coupling capacit or is discussed. A discussion of response roll- off on t he high end of t he spect rum is deferred t o Unit 11.

6.1 Grounded-Source Amplifier: Coupling Capacitor A version of t he circuit s of Fig. 5.2, as given in Fig. 6.1, is generalized t o include a resist ance, Rs, as part of t he input signal source. The input signal at t he gat e ( and t hus t he out put ) will fall off for decreasing frequencies as t he m agnit ude of react ance of t he capacit or increases. The value of t he capacit or is select ed such t hat t he react ance will be sm all com pared t o t he value of t he sum of t he resist ors, at t he lowest operat ing frequency.

Figu r e 6 .1 . Cir cu it w it h cou plin g ca pa cit or . Ca pa cit or block s t h e sign a l a t low fr e qu e n cie s. Cg a nd R G = R G1 | | R G2 m u st be se le ct e d for | X Cg | < < R s + R G a t t h e ga in m e a su r e m e n t fr e qu e n cy.

I n t his am plifier, all t he gain- frequency dependence is bet ween Vg and Vs. The relat ion bet ween t he gat e signal, Vg , and source signal, Vs, based on a volt age- divider relat ion is

Equ a t ion 6 .1

wit h

Equ a t ion 6 .2

where RG = RG1 | | RG2 . Wit h Rs included, t he f 3dB expression applies t o an act ual am plifier. I n Proj ect 6, t he signalsource volt age is applied direct ly t o t he gat e. We select a com binat ion of RG and Cg t o obt ain a suit ably low f 3dB. This m ust be m ore t han a fact or of 10 lower t han t he gain m easurem ent frequency assure t hat t he capacit or is not influencing t he m easurem ent s. I n Proj ect s 5 and 7, no capacit or is used at t he input as t he signal is superim posed on t he dc gat e volt age. This is t o facilit at e t he need for bot h DAQ out put channels t o provide t he bias. However, Proj ect 6, one channel provides t he bias, as in Figs. 5.1( a) and 6.1, and t he ot her channel is used for t he signal wit h connect ion t o t he input t hrough a coupling capacit or.

6.2 Current-Source Bias Amplifier: Bypass Capacitor The PMOS com m on- source am plifier circuit wit h t he bypass capacit or is shown in Fig. 6.2. At som e low frequency, t he effect of t he capacit or is absent , and t he gain is com put ed from ( 5.15) , which is

Figu r e 6 .2 . D u a l- pow e r - su pply com m on - sou r ce a m plifie r st a ge w it h bypa ss ca pa cit or . Th e obj e ct is t o de t e r m in e t h e fr e qu e n cy for w h ich t h e sou r ce is e ffe ct ive ly a t sign a l gr ou n d.

Over a range of frequencies, t he gain evolves from ( 5.15) t o ( 5.2) , a v = –g m RD ( neglect ing t he out put resist ance of t he PMOS) . The frequency- dependent t ransit ion region is det erm ined by replacing RS in ( 5.15) wit h t he im pedance of RS in parallel wit h t he react ance of Cs. This is

Equ a t ion 6 .3

or

Equ a t ion 6 .4

wit h

Equ a t ion 6 .5

and

Equ a t ion 6 .6

Not e t hat t he " RC" fact or has an " R," which is RS in parallel wit h 1/ g m , t he lat t er being t he out put resist ance looking int o t he source of t he t ransist or. The t wo frequencies f s and f z are t echnically t he pole and zero of t he response funct ion. We not e t hat g m RS = 2I D RS/ Veffp . Since Veffp could be as low as Veffp som e cases. The corner frequency, f 3dB, occurs at

0.2 V, t hen g m RS > > 1 in

Equ a t ion 6 .7

which gives

Equ a t ion 6 .8

such t hat

Equ a t ion 6 .9

where t he far- right - hand t erm applies for g m RS > > 1. This is t ypically only m arginally sat isfied in MOSFET circuit s. The derivat ion carried out here was init iat ed from ( 5.15) , which neglect s t he out put resist ance of t he t ransist or. I n t he case of t he MOSFET devices of our proj ect s, t he sim plificat ion is valid for t he NMOS t ransist or but m arginal for t he PMOS t ransist or. This is because λp > > λn . The result ( 6.9) st ill serves t o est im at e t he required value for Cs, even for t he case of t he PMOS. Nevert heless, a m ore det ailed derivat ion is carried out in t he next unit . This perm it s com parisons, in a proj ect , of SPI CE and Mat hcad solut ions wit h am plifier gains and frequency response.

6.3 Precision Formulation of the Low-Frequency Gain and Characteristic Frequencies I n Unit 8, t he gain of a com m on- source st age wit h source resist or, which includes t he effect of t he out put resist ance, is shown t o be [ ( 8.36) ]

This is designat ed here as a volo t o em phasize t hat it is t he const ant low- frequency asym pt ot ic gain. I f t he source- branch im pedance is subst it ut ed for RS, t his becom es

Equ a t ion 6 .1 0

where f z is ( 6.5) . This can be rearranged in t he form of ( 6.4) , which is

Equ a t ion 6 .1 1

where t he new pole frequency is

Equ a t ion 6 .1 2

and a volo is ( 8.36) .

6.4 Load Coupling Capacitor The com plet e pract ical am plifier includes a load, RL, at t he out put . This requires an addit ional coupling capacit or. The am plifier wit h an at t ached load is shown in Fig. 6.3. We will assum e t hat t he effect of t he out put resist ance, r ds, can be neglect ed. The t ransist or appears as a current source of m agnit ude I d . The equivalent signal circuit at t he out put can be represent ed as shown in Fig. 6.4( a) and ( b) . I n Figure 6.4( b) , t he current source and drain resist or are replaced wit h a volt age- source equivalent . From Fig. 6.4( b) , t he out put volt age is

Equ a t ion 6 .1 3

Figu r e 6 .3 . Am plifie r w it h ca pa cit ive ly cou ple d loa d r e sist or , R L. The ca pa cit or m u st be la r ge e nou gh n ot t o a t t e n u a t e t h e ou t pu t be t w e e n t h e dr a in a nd loa d r e sist or .

The expression wit h t he high- frequency asym pt ot ic value and frequency dependence is

Equ a t ion 6 .1 4

which is

Equ a t ion 6 .1 5

where

Equ a t ion 6 .1 6

Figu r e 6 .4 . ( a ) Equ iva le n t cir cu it con sist in g of a cu r r e n t sou r ce a n d t h e loa d com pon e n t s. ( b) Con ve r sion of cur r e n t sou r ce t o volt a ge sou r ce .

Current source I d is not dependent on frequency ( at t he low end of t he spect rum ) when no ot her capacit ors are considered. However, in general, wit h bot h Cd and Cs at t ached, t he com bined response is

Equ a t ion 6 .1 7

where f d is ( 6.16) , f z is ( 6.5) , f s is ( 6.6) , and is RD in parallel wit h RL. Wit h Cd = Cs, usually f d < < f s such t hat ( 6.9) is t he approxim at e f 3dB for t he circuit wit h bot h capacit ors connect ed. Com bining t he frequency- dependent t erm s t o obt ain ( 6.17) assum es t hat current source I d is independent of com ponent s Cd , RD , and RL. This is a correct assum pt ion as long as t he out put resist ance of t he t ransist or is neglect ed. When bet t er precision is required, t he derivat ion st art s wit h t he general form of t he circuit t ransconduct ance, as deducible from ( 8.36) , and replaces bot h RD and RS wit h t he im pedance in t hose respect ive branches, Z D and Z S. This gives

Equ a t ion 6 .1 8

The gain follows from m ult iplying t he t ransconduct ance by t he load at t he drain, Z D , and m ult iplying by t he volt age divider, Vo / Vd = RL/ ( RL + 1/ j 2πfCd ) . The result is

Equ a t ion 6 .1 9

6.5 Summary of Equations MOSFET coupling capacit or corner- frequency equat ion. Zero and pole equat ions for bypass capacit or response funct ion.

Com put at ion of f 3dB frequency wit h one pole and one zero. Approxim at e f 3dB frequency for capacit or Cs.

Pole frequency f s wit h g ds included in t he derivat ion. Load coupling capacit or corner- frequency equat ion. Not e: Any one of t he frequencies, f g , f s ( approxim at e) , or f d is t he f 3dB ( corner) frequency if it is t he dom inant ( high) frequency. Ot herwise, t he corner frequency is som e com binat ion.

6.6 Exercises and Projects Proj ect Mat hcad Files

Exercise06.m cd - Proj ect 06.m cd - Exercise07.m cd, Proj ect 07_1.m cd Proj ect 07_2.m cd.

La bor a t or y Pr oj e ct 6

PMOS Com m on- Source Am plifier St age wit h Current - Source Biasing

P6.3

PMOS Current - Source Am plifier DC Set up

P6.4

Am plifier Gain

P6.5

Am plifier Frequency Response

La bor a t or y Pr oj e ct 7

NMOS Com m on- Source Am plifier St age wit h Source- Resist or Bias

P7.2

NMOS Com m on- Source Am plifier DC Evaluat ion

P7.3

Am plifier Gain at Opt im um Bias for Linear Out put

P7.4

Opt im um Bias St abilit y Test

P7.5

Am plifier Frequency Response

Unit 7. MOSFET Source-Follower Buffer Stage High- gain st ages in am plifiers are usually som e form of different ial st age or com m on- source st age. These are inherent ly high- out put - resist ance st ages and are not suit able for lowim pedance loads. The solut ion for a requirem ent t o drive low- im pedance loads is t o insert a buffer st age bet ween t he out put of t he com m on- source st age and t he load. The buffer will be a source- follower st age. The nam e follower com es from t he fact t hat t o a good approxim at ion, t he out put volt age follows t he input volt age; t hat is, it has an open- circuit gain of unit y and low out put resist ance. Alt hough t he out put volt age/ input volt age relat ion is som et im es loosely referred t o as t he gain, it would be m ore accurat e t o label it t he volt age t ransfer funct ion, as t he " gain" is less t han 1. The t ransfer funct ion is explored in t he following for various possibilit ies of degrees of approxim at ion in t he linear circuit .

7.1 DC (Bias) Circuit The circuit diagram shown in Fig. 7.1 uses for t he t ransist or a sym bol t hat includes t he body connect ion. This is t o em phasize t he fact t hat t he out put ( source) of t he source follower is generally ( and usually) at different dc and signal pot ent ials from t he body. I n Proj ect 8 we m easure t he gain for bot h t he connect ion shown ( which we can m ake for t his special case of one t ransist or on t he chip being used) and wit h t he body connect ed t o VSS, which is signal ground. The lat t er dem onst rat es t he ext ent of t he influence t hat t he body effect has on t he gain when it is not possible t o connect t he body and source t oget her as shown in Fig. 7.1.

Figu r e 7 .1 . Sou r ce - follow e r ( com m on - dr a in ) st a ge ( N M OS t r a n sist or ) w it h t he input a t t he ga t e a n d t h e ou t pu t a t t h e sou r ce . I n t h is e x a m ple , t h e sou r ce is con n e ct e d t o t h e body. Usu a lly, in a cir cu it , t h e body w ill be a t t a ch e d t o t h e pow e r su pply V SS ( N M OS) .

The design of t he st age will oft en consist of set t ing t he dc out put at VO = 0 V ( for a dual power supply) , as t his will be t he final ( out put ) st age. Therefore, RS will be select ed based on t he design drain current from RS = | VSS| / I D . I t is t hen necessary t o det erm ine VGS in order t o det erm ine t he VG = VGS required ( which will be set by t he dc circuit ry of t he preceding circuit ) . For t he usual pract ical applicat ion, body volt age, VB = VSS. Wit h VS = 0 V, VSB = | VSS| . Thus, t he t hreshold volt age, including body effect , will be

Equ a t ion 7 .1

and t he gat e bias volt age will be obt ainable from

Equ a t ion 7 .2

I f t he source and body are connect ed, as in Fig. 7.1, Vt n is replaced wit h Vt no .

7.2 Source-Follower Voltage Transfer Relation A signal circuit is shown in Fig. 7.2, where t he dc supplies have been replaced wit h ground. Also, t he int ernal resist ance, r ds = 1/ g ds, of t he t ransist or has been included in t he signal circuit . Not e t hat it is in parallel wit h RS since t he drain is t ied t o signal ground. Assum e for now t hat source and body are connect ed as in Fig. 7.1.

Figu r e 7 .2 . Sign a l cir cu it of t h e sou r ce follow e r . Body e ffe ct is a bse n t sin ce t h e sou r ce a n d body a r e a ssu m e d con n e ct e d.

Regardless of t he t erm inal configurat ion, for infinit e out put resist ance and wit h t he body and source connect ed, t he relat ionship bet ween t he drain current and gat e – source cont rol volt age of t he t ransist or is ( 4.1) wit h g ds = g m b = 0, which is [ ( 2.5) ]

I n t he source- follower circuit , t he out put resist ance of t he t ransist or can be included in t he source- follower load and ( 2.5) effect ively applies. The t ransconduct ance for t he circuit configurat ion wit h a source resist or was shown in Unit 4 t o be [ ( 4.8) ]

where, for t his case, resist ance and is

Equ a t ion 7 .3

Then using

Equ a t ion 7 .4

is t he source- follower load, which includes t he t ransist or out put

t he " gain" ( t he t ransfer funct ion is less t han unit y) is det erm ined t o be

Equ a t ion 7 .5

I deally, t his is a unit y gain, as would be t he case for . I n bipolar t ransist ors, t his condit ion is closely approached. However, in MOSFET source followers, t he ideal case is in general not reached. As we will see below, t his deficiency is enhanced when t he body effect is included. Not e t hat a v is

Equ a t ion 7 .6

This is t he expression for a sim ple volt age divider. Thus t he source follower is t he equivalent of a unit y- gain circuit wit h load and out put resist ance 1/ g m . We can conclude t hat t he t ransist or viewed from t he source has an out put resist ance of 1/ g m . Finally, wit h

separat ed int o it s com ponent part s, t he source- follower gain becom es

Equ a t ion 7 .7

I n general, t he g ds param et er can be dropped. The rat io of g m / g ds is

Equ a t ion 7 .8

7.3 Body Effect and Source-Follower Voltage Transfer Relation Suppose now, as in Fig. 7.3, t hat t he body t erm inal is connect ed t o VSS, which is signal ground. Following t he definit ion of t he body- effect t ransconduct ance, g m b , t he com ponent of I d due t o source- body volt age Vsb is [ from ( 4.1) ]

Equ a t ion 7 .9

Since t he body is at zero pot ent ial ( signal) , t his is

Equ a t ion 7 .1 0

This com ponent of current can be included in t he circuit , as shown in Fig. 7.3, wit h an addit ional resist ance in parallel wit h RS of value 1/ g m b . That is, t he body- effect cont ribut ion t o t he drain current is a volt age- dependent current source, where t he volt age is t he sam e as t hat across t he current source.

Figu r e 7 .3 . Sou r ce - follow e r sign a l e qu iva le n t cir cu it w it h body con n e ct e d t o V SS, w h ich is signa l gr ou n d. Th e body e ffe ct is t a k e n ca r e of for t his ca se w it h a r e sist a n ce of m a gn it u de 1 / g m b pla ce d in pa r a lle l w it h R S a lon g w it h r ds = 1 / g ds.

Wit h t he body- effect addit ion, t he source- follower gain expression is m odified t o t he following:

Equ a t ion 7 .1 1

The body- effect param et er is relat ed t o g m by [ ( 4.11) ] g m b = ηg m wit h

Wit h t he subst it ut ion of ( 4.11) in ( 7.11) , t he gain is

Equ a t ion 7 .1 2

I n m odern int egrat ed circuit s, resist or RS will be replaced wit h a current - source out put resist ance, which is significant ly great er t han RS. The source- follower gain is, in t his case, approxim at ely ( wit h no ext ernal load)

Equ a t ion 7 .1 3

Param et er η will t ypically be in t he range 0.1 < η < 0.2. Not e t hat t he body effect degrades t he " gain" significant ly below t he ideal unit y. I n t he proj ect on t he source- follower circuit , we m easure t he volt age t ransfer funct ion of t he source follower for a range of dc drain current wit h body and source connect ed and wit h t he body connect ed t o VSS. Τηε ρεσυλτινγ χυρϖεσ ωιλλ βε χοµπαρεδ το δεµονστρατε τηε βοδψ εφφεχτ ον τηε τρανσφερ φυνχτιον. Α χυρϖε φιτ οφ τηε ΣΠΙΧΕ εθυατιον το µεασυρεδ δατα ωιλλ προϖιδε φορ αν αλτερνατιϖε δετερµινατιον οφ πα ραµετερ γn . This value should be close t o t he value obt ained from dc m easurem ent s.

7.4 Summary of Equations Threshold volt age VS = 0 zero volt s and negat ive power supply VSS.

Source- follower volt age gain wit h Vsb = 0.

Source- follower volt age gain wit h Vsb = I d Rs. g m b = ηg m Body- effect t ransconduct ance.

Source- follower body- effect degradat ion fact or.

7.5 Exercises and Projects Proj ect Mat hcad Files

Exercise08.m cd - Proj ect 08.m cd

La bor a t or y Pr oj e ct 8 NMOS Source- Follower St age P8.2

Source- Follower DC Evaluat ion

P8.3

Source- Follower Volt age Transfer Relat ion

P8.4

Source- Follower Volt age Transfer Relat ion wit h Body Effect

Unit 8. MOSFET Differential Amplifier Stage The MOSFET different ial am plifier st age is a relat ively high- gain st age wit h grounded dc input s, which requires no bypass capacit or. The st age also has t he im port ant advant age of having t wo input s, one invert ing and one noninvert ing. This is essent ial in operat ional am plifiers where one or t he ot her ( or bot h) is used, depending on t he applicat ion. The t wo input s also provide for operat ing t he st age in t he different ial m ode, where t he input is not referenced t o ground. The different ial am plifier st age discussed here is an all- resist or circuit wit h source and drain resist ors. I n a m odern int egrat ed circuit , t hese are replaced wit h t ransist or current sources. However, t he principle of operat ion is t he sam e, and t he resist or version can be im plem ent ed in our laborat ory proj ect . Various segm ent s of t he different ial am plifier com prise am plifier st ages from all t hree t erm inal configurat ions: t he com m on source, t he com m on gat e, and t he source follower ( com m on drain) . I n t his unit , a det ailed t heoret ical analysis of all t hree st ages is undert aken ( based on Level 1 SPI CE) . The linear m odels used include, progressively, t he out put conduct ance, g ds, and t he body- effect t ransconduct ance, g m b .

8.1 DC (Bias) Circuit The equat ion for t he dc circuit ( Fig. 8.1) is t he sam e as for t he current - source com m on- source st age except t hat t he bias resist or has current 2I D as t he current from bot h t ransist ors is flowing t hrough t his resist or. For now, t he st age will be assum ed t o be perfect ly balanced such t hat I D1 = I D2 = I D . The bias equat ion is

Equ a t ion 8 .1

Figu r e 8 .1 . D c cir cu it for diffe r e n t ia l- a m plifie r st a ge w it h r e sist a n ce bia s. Sou r ce a n d body a r e n or m a lly a t diffe r e n t pot e n t ia ls. I n t h e pr oj e ct w it h t h is cir cu it , w e a t t a ch t h e t w o sou r ce s t o t h e t r a n sist or body, w h ich is a llow e d in a sim ple cir cu it .

Not e t hat t he t hreshold volt age is t hat for VSB 0 V. The solut ion can be obt ained wit h t he inclusion of t he t hreshold volt age equat ion, also a funct ion of I D ,

Equ a t ion 8 .2

I n t he proj ect on t he different ial am plifier, we can connect t he sources and bodies of t he t wo t ransist ors. This is because only NMOS t ransist ors are used in t he circuit , and bot h t ransist ors have t he source connect ed t o t he sam e node. I n t his case, Vt n = Vt no .

8.2 DC Imbalances

I n a real t ransist or, param et ers k n , Vt no , and λn can be slight ly different such t hat , in general, I D1 I D2 . The rat io of t he current s is given by

Equ a t ion 8 .3

where, in t he circuit wit h t he gat e of M1 grounded, VGS1 = VGS2 = VGS. For t he specific case of t he proj ect on t he am plifier, we can assum e t hat VDS1 VDS2 such t hat

Equ a t ion 8 .4

To sim plify t he relat ion, it is advant ageous t o express param et ers in t erm s of increm ent s. For exam ple, t hreshold volt age will be expressed as a m ean value

Equ a t ion 8 .5

and a difference bet ween t he t hreshold volt age of t he t wo t ransist ors

Equ a t ion 8 .6

such t hat

Equ a t ion 8 .7

and

Equ a t ion 8 .8

Using t hese definit ions along wit h Veff = VGS – Vt no , we have

Equ a t ion 8 .9

or, approxim at ely,

Equ a t ion 8 .1 0

I n t he different ial am plifier proj ect ( PMOS) , we m easure t he drain current s along wit h VSG over a range of drain current values. These are used t o obt ain, in t he Mat hcad proj ect file, k n1 , k n2 , and t he t hreshold volt ages and t hus, v t . This will provide a com parison bet ween t he m easured drain- current rat ios and ( 8.10) as a funct ion of Veff and drain current .

8.3 Signal Voltage Gain of the Ideal Differential Amplifier Stage This init ial assessm ent of t he gain of t he different ial am plifier neglect s t he effect s of t he bias resist or, Rbias, and of t he out put resist ance of t he t ransist ors as well as t he body effect . These effect s are considered below. To generalize t he discussion t o include t he possibilit y of invert ing and noninvert ing m odes of operat ion, we base t he discussion on t he circuit ( Fig. 8.2) wit h a drain resist or for bot h t ransist ors. The invert ing and noninvert ing m odes t ake, respect ively, t he out put s at Vd1 = Vo1 ( a v1 ) and Vd2 = Vo2 ( a v2 ) . Also, t his is t he configurat ion t hat is st udied in t he proj ect on t he different ial am plifier. Not e t hat t he input could arbit rarily be m oved t o t he gat e of M2 , in which case t he out put t aken at Vd1 becom es t he noninvert ing m ode, and so fort h.

Figu r e 8 .2 . Cir cu it for our pr oj e ct on t h e diffe r e n t ia l a m plifie r . Th e cir cu it h a s r e sist or s in bot h dr a in br a n che s for com pa r in g t h e ga in fr om t he n on in ve r t in g a n d inve r t ing out pu t s a n d for se n sin g t he bia s dr a in cu r r e n t s.

Assum e for t he present t hat t he am plifier is perfect ly sym m et rical such t hat , for exam ple, I D1 = I D2 and g m 1 = g m 2 . A signal volt age Vi is applied t o t he gat e of M1 as shown in t he diagram . The volt age divides bet ween t he t wo t ransist ors ( from gat e 1 t o gat e 2) t o give

Equ a t ion 8 .1 1

Since Vgs1 = | Vsg2 | ( due t o t he sym m et ry of t his case) , t hen

Equ a t ion 8 .1 2

The negat ive Vgs2 result s from t he fact t hat t he t ot al v GS2 is reduced from bias VGS2 upon t he applicat ion of a posit ive signal volt age, Vi , at t he gat e of M1 ( i.e., v GS2 = VGS2 – Vi / 2) . I t follows t hat t ot al i D2 decreases, which leads t o a posit ive signal volt age at t he drain, Vd2 . Thus, t he am plificat ion is noninvert ing.

As always, t he relat ion bet ween t he signal drain current and t he signal drain- source volt age is ( 4.1) , which is ( wit h g ds = g m b = 0) I d = g m Vgs Elim inat ing Vgs in ( 4.1) , applied t o M2 , wit h ( 8.12) , t he drain current for M2 is relat ed t o t he input volt age, Vi , by

Equ a t ion 8 .1 3

Com bining ( 8.13) wit h Vo2 = –I d2 RD2 , t he out put volt age is relat ed t o t he input volt age by

Equ a t ion 8 .1 4

such t hat t he gain is

Equ a t ion 8 .1 5

Not e t hat t here is no m inus in t he relat ion; t hat is, t his is t he noninvert ing am plifier m ode. Also not e t hat t he gain for t his am plifier is one- half of t hat for t he com m on- source am plifier. This is a reasonable price t o pay for not having a bypass capacit or. The am plificat ion can be viewed as a source- follower st age in cascade wit h a com m on- base st age, neit her of which is an invert ing st age. The invert ing m ode of t he am plifier is for t he out put t aken at t he drain of M1 . For t his case, Vo1 = –I d1 RD1 , and from ( 8.12) and ( 4.1) applied t o M1 , I d1 = g m 1 Vg / 2 and t he volt age relat ionship is

Equ a t ion 8 .1 6

This leads t o t he invert ing gain, which is

Equ a t ion 8 .1 7

8.4 Effect of the Bias Resistor on Voltage Gain The result s above ignore t he effect of resist ance, Rbias. When it is included, it is no longer valid t o assum e t hat Vgs1 = Vsg2 , even wit h I D1 = I D2 . The bias- resist or effect is exam ined here based on a signal equivalent circuit of Fig. 8.3. The resist ance at t he source of M1 consist s of t he bias resist or and t he linear- m odel resist ance 1/ g m 2 ( which neglect s 1/ g ds2 ) , looking int o t he source of M2 .

Figu r e 8 .3 . Sou r ce cir cu it a s vie w e d fr om M 1 . Sou r ce r e sist a n ce in clu de s a ct u a l r e sist or R bia s in pa r a lle l w it h in put r e sist a n ce a t sou r ce of M 2 , w h ich is 1 / g m 2 for t he con dit ion s of t his u n it .

For t he noninvert ing m ode, t he circuit t ransconduct ance, Gm 2 = I d2 / Vi , is

Equ a t ion 8 .1 8

Param et er g m 2 is t he t ransconduct ance I d2 / Vs2 ( i.e., from t he source of M2 t o t he out put Vo2 ) . Not e t hat t he fract ion is j ust a volt age divider, Vs2 / Vi , since t he out put resist ance at t he source of M1 is 1/ g m 1 , as not ed in connect ion wit h ( 7.6) . Wit h g m 1 = g m 2 , t he m ult iplying fract ion assum es t he value of ½ for very large Rbias. The noninvert ing gain, which includes t he effect of t he bias resist or, is

Equ a t ion 8 .1 9

where t he right - hand side uses g m 1 = g m 2 . The gain result is t echnically t hat of t he cascade of a source- follower st age ( M1 ) and a com m on- gat e st age, g m 2 RD2 ( M2 ) . The m ult iplying fract ion is < ½. The gain for t he invert ing side can be obt ained by using ( 5.15) , which is for a com m on- source am plifier wit h source resist or. This gives for t he invert ing- m ode gain

Equ a t ion 8 .2 0

where t he right - hand side again uses g m 1 = g m 2 . The m ult iplying fract ion is > ½ . Not e t hat for bot h invert ing and noninvert ing gains, t he effect of Rbias can be neglect ed for m ost purposes, as t he m ult iplying fract ions in ( 8.19) and ( 8.20) are bot h close t o ½ . The choice of t he input at gat e 1 is arbit rary and all of t he result s obt ained here apply equally t o t he input t aken at gat e 2. The invert ing out put is always at t he side of t he input , and t he noninvert ing out put is always at t he opposit e side.

8.5 Differential Voltage Gain Suppose t hat an input volt age, Vg12 = Vg1 – Vg2 , is applied bet ween t he input s. Due t o sym m et ry, t he volt age m agnit udes at t he input s wit h respect t o ground are Vg1 = Vg12 / 2 and Vg2 = –Vg12 / 2, respect ively. The noninvert ing out put , Vd2 , for t his case is, by superposit ion,

Equ a t ion 8 .2 1

The gains for t he cont ribut ions from Vg1 and Vg2 are ( 8.19) and ( 8.20) , respect ively. This is t he case of a pure different ial input wit h result ing gain

Equ a t ion 8 .2 2

A sim ilar approach applied t o obt ain t he gain for t he out put t aken as Vd1 produces

Equ a t ion 8 .2 3

Assum e, for a num erical exam ple, t hat I D = 100 µA, RD1 = 50 KΩ, and g m = 200 µA/ V ( Veffn = 0.5 V) . I n t his case t he gain is avd1 = –10. This would be consist ent wit h VDD = | VSS| = 10 V. The gain for t he case of t he different ial out put , a vd12 = ( Vd1 – Vd2 ) / ( Vg1 – Vg2 ) , can be obt ained from ( Vd1 – Vd2 ) = –( 1/ 2) g m 1 RD1 Vg12 – ( 1/ 2) g m 2 RD2 Vg12 and is

Equ a t ion 8 .2 4

where g m 1 = g m 2 and RD1 = RD2 = RD . Not e t hat ( 8.22) and ( 8.23) are t he sam e as ( 8.15) and ( 8.17) . However, ( 8.15) and ( 8.17) are t he lim it ing form s of ( 8.19) and ( 8.20) for Rbias , whereas ( 8.22) and ( 8.24) apply for a finit e Rbias.

8.6 Common-Mode Voltage Gain The com m on- m ode gain is defined for t he sam e volt age applied sim ult aneously t o bot h input s. The out put m ust be t he sam e at eit her out put t erm inal ( again assum ing t hat g m 1 = g m 2 and RD1 = RD2 ) . For exam ple, for t he out put Vd2 , t he gain can be det erm ined by a superposit ion of gains, invert ing ( input , Vg2 ) and noninvert ing ( input , Vg1 ) , wit h RD2 in bot h equat ions. Using ( 8.19) ( noninvert ing) and ( 8.20) ( invert ing) , t he gain for finit e Rbias is, accordingly,

Equ a t ion 8 .2 5

which is

Equ a t ion 8 .2 6

The result is t hat of a com m on- source st age wit h source resist ance 2Rbias. This is int uit ively correct as t aken from t he half- circuit viewpoint , where t he circuit is com plet ely sym m et rical. The input from eit her side looks at a com m on- source st age except t hat t he opposit e side is cont ribut ing an equal am ount of source current, t hus giving an effect ive source resist ance equal t o t wice t he act ual value. A valid approxim at e form for well- designed circuit s ( in t erm s of com m on- m ode gain) is

Equ a t ion 8 .2 7

The sam e result applies t o t he case of t he out put t aken at t he opposit e drain, wit h t he subst it ut ion of RD1 for RD2 . Using t he circuit values following ( 8.23) plus Rbias = 85 kΩ, a vcm – 0.3. Not e t hat t his result in com binat ion wit h t he gain from ( 8.23) would indicat e t hat t his is not a part icularly good design. The goal is for avd > > a vcm .

8.7 Voltage Gains Including Transistor Output Resistance I n Proj ect 9 we m easure t he gain of a " balanced" st age wit h drain resist ors for bot h t ransist ors. The am plifier is t he PMOS version of t he NMOS am plifier of Fig. 8.2. We obt ain an exact Level 1 SPI CE solut ion for t he gains for bot h out put s. The exam ple is used t o explore t he use of a sim ulat or for obt aining precision result s t o com pare wit h sim ple hand calculat ions. For larger λn values ( NMOS) , t he out put resist ance can influence t he gain and com plicat e t he gain expressions considerably. Here we consider t he effect due t o g ds1 and g ds2 while ret aining t he effect of Rbias. I n t he following, t he gain of t he invert ing input , a v1 , is obt ained again as a com m on- source st age wit h source resist ance. The effect of g ds2 on t he effect ive source resist ance is included ( input at t he source of M2 ) . The effect s due t o g ds1 are also t aken int o considerat ion. The gain of t he noninvert ing case, a v2 , is obt ained by considering t he cascade of t he source follower st age ( M1 ) and t he com m on- gat e st age ( M2 ) , as, in effect , was done in t he developm ent of ( 8.19) . The source- follower gain t akes int o account effect s from g ds1 and g ds2 , and t he gain of t he com m on- gat e st age depends on g ds2 .

8.7.1 Gain of the Common-Source Stage with Transistor Output Conductance and Source Resistor The circuit t ransconduct ance for a com m on- source st age wit h source resist or, wit h t he inclusion of g ds, was developed in Unit 4 [ ( 4.18) ] . This will be reviewed and reinforced here in t he form of a slight ly different approach t o t he result . The signal circuit for t his case is again given in Fig. 8.4. Using t he variables of Fig. 8.4, t he circuit t ransconduct ance is Gm 1 = I d1 / Vi . The obj ect is t hus t o obt ain a relat ion bet ween t hese t wo variables.

Figu r e 8 .4 . Cir cu it for obt a in ing t h e ga in for t h e in ve r t in g out pu t w it h t h e t r a n sist or out pu t r e sist a n ce in clu de d. R s in clu de s a ll r e sist a n ce con t r ibu t ion s a t t h e sou r ce .

The fract ion of t he current produced by t he int rinsic t ransist or, g m 1 Vgs1 , which flows int o Rs is

Equ a t ion 8 .2 8

This is t he port ion of current source g m 1 Vgs1 , shared bet ween 1/ g ds and RD + Rs, which flows t hrough RD + Rs, t hat is, I d1 . Not e t hat RD + Rs and 1/ g ds1 are in parallel and shunt t he t ransist or current source. A relat ion for Vgs1 in t erm s of I d1 follows, which is

Equ a t ion 8 .2 9

The input Volt age is t he sum of Vgs1 and t he drop across Rs. That is,

Equ a t ion 8 .3 0

Using ( 8.29) in ( 8.30) gives

Equ a t ion 8 .3 1

or

Equ a t ion 8 .3 2

The circuit t ransconduct ance follows as

Equ a t ion 8 .3 3

The gain for t his case is t hen

Equ a t ion 8 .3 4

A discussion of Rs as affect ed by g ds2 follows.

8.7.2 Common-Gate Amplifier Stage The circuit diagram of Fig. 8.5 is for t he M2 port ion of t he different ial am plifier. The input is applied at t he source, Vs2 , and t he out put is t aken at t he drain, Vd2 = Vo2 , while t he gat e is grounded. This is a com m on- gat e configurat ion. Here we analyze t he input resist ance, for evaluat ing t he effect on Rs, and gain of t he com m on- gat e st age.

Figu r e 8 .5 . Cir cu it t ha t in clu de s t h e out pu t r e sist a n ce of M 2 . Th e cir cu it is for obt a in in g in pu t r e sist a n ce a t t h e sou r ce of M 2 a n d t h e ga in of t h e com m on - ga t e st a ge of M 2

Wit hout g ds2 , t he input resist ance at t he source is j ust 1/ g m 2 . Wit h g ds2 in place, t here is a posit ive feedback from t he drain out put t o t he source input . This causes t he input resist ance t o increase. Wit h g ds2 , t he current int o t he source t erm inal is

Equ a t ion 8 .3 5

I t is not ed t hat t he g ds2 t erm reduces t he input current , which has t he effect of increasing t he input resist ance. From ( 8.35) , t he result ing input resist ance at t he source, Ris2 = Vs2 / I d2 , is

Equ a t ion 8 .3 6

The input resist ance goes t o 1/ g m 2 , as not ed above, for g ds2 = 0. The expression for t he equivalent Rs is now Rs = Rbias | | Ris2 , where Ris2 is ( 8.36) . I n m odern int egrat ed circuit s, RD2 m ay be replaced wit h a high- resist ance t ransist or current source, and t he input resist ance is t his case can be m uch great er t han 1/ g m 2 . The gain of t he com m on- gat e st age is obt ained as follows: The out put volt age is

Equ a t ion 8 .3 7

which gives

Equ a t ion 8 .3 8

Not e t hat for g ds2 = 0, t he gain has t he sam e m agnit ude as t he sim ple case for t he com m onsource st age.

8.7.3 Voltage Gain for the Noninverting Output The noninvert ing am plifier gain is based on a cascade of a source- follower st age ( M1 ) and a com m on- gat e st age ( M2 ) . The source- follower t ransconduct ance, I d1 / Vi , is ( 8.33) . Using t his wit h Vs1 = I d1 Rs gives

Equ a t ion 8 .3 9

Not e t hat t he m agnit ude is about ½ . Overall gain is t he product of ( 8.38) and ( 8.39) , which is

Equ a t ion 8 .4 0

The equat ions from t his unit are sum m arized below in Unit 8.11. Recall from t he discussion of MOSFET m odel param et ers t hat g ds is given by ( 4.13) , which is

Thus, t he gain expression depends on param et er λ, and especially if λ is som ewhat large. I n Proj ect 9 we m easure t he gains from t he t wo drains and use t he result s t o find t he value of λ t hat m akes t he t heory fit t he m easurem ent s. I n t his way, we are get t ing a signal- derived experim ent al num ber t o com pare wit h t hat obt ained in t he param et er- det erm inat ion proj ect . This will be done using t he PMOS configurat ion since t he value of λp is large and t he effect is significant . All of t he gain expressions, which are based on NMOS t ransist ors, apply exact ly t o t he PMOS st age wit h subst it ut ion of subscript s; change n t o p ( param et ers) and reverse t he order for dc volt age variables. For hand calculat ions, approxim at e form s m ust reasonably be used. This applies t o approxim at e form s for device param et ers and gain. The basic gain equat ions are, again, , sim ply, as given by ( 8.15) and ( 8.17) , assum ing t hat g ds = 0 and Rbias =

wit h RD1 = RD2 and g m 1 = g m 2 . I n t he different ial am plifier proj ect , we will com pare t hese wit h t he m ore precision form s.

8.8 Body Effect and Voltage Gain I n Proj ect 9 we are able t o connect t he sources of t he t ransist ors t o t he chip body. Cert ainly, in general t his cannot be done such t hat t here is a body effect associat ed wit h t he different ialam plifier- st age t ransist ors. The necessary alt erat ions t o t he gain equat ions are det erm ined in t he following. At t he end of t his unit , we will have t he com plet e, precision- gain calculat ion equat ions of Level 1 SPI CE. I t will be inform at ive t o consider num erical result s t hat are based on various degrees of approxim at ions, and t his is done below.

8.8.1 Common-Source Stage and Body Effect Wit h t he body effect present , a com ponent of current , g m b1 Vs ( Fig. 8.6) , is subt ract ed from g m 1 Vgs1 such t hat ( 8.28) for t his case is m odified t o becom e

Equ a t ion 8 .4 1

Figu r e 8 .6 . Cir cu it for obt a in ing t h e in ve r t in g ga in of t h e diffe r e n t ia l st a ge w it h body e ffe ct in clu de d. Body e ffe ct is a ccou n t e d for by t h e cu r r e n t sou r ce a dde d t o t he t r a n sist or sign a l ( lin e a r ) e qu iva le n t cir cu it .

Addit ionally using Vs = I d1 Rs and Vgs1 = Vi – I d1 Rs ( 8.30) ] in ( 8.41) , a relat ion bet ween I d1 and Vi is obt ained, which is

Equ a t ion 8 .4 2

Solving for I d1 , t he circuit t ransconduct ance is, for t he body- effect case,

Equ a t ion 8 .4 3

I t follows t hat t he gain for t he invert ing m ode, wit h t he addit ion of body effect , is

Equ a t ion 8 .4 4

The effect of ηn in t he denom inat or t ends t o m ake t he gain sm aller. However, t he body effect , as shown below, will decrease Rs such t hat t he t wo effect s t end t o cancel one anot her.

8.8.2 Common-Gate Stage and Body Effect The volt age applied t o t he com m on- gat e st age is Vs2 = Vsg2 ( Fig. 8.7) . Recall t hat in t he g m odel for t he t ransist or, as discussed for t he com m on- source m ode, current sources g m b Vsb and g m Vgs are in parallel but in opposit e direct ions. Thus, t he current sources g m Vsg and g m b Vsb are, for t he com m on- gat e m ode, in t he sam e direct ion since Vsb = Vsg = –Vgs; t he com m ongat e has an effect t ransconduct ance of ( 1 + η) g m . I t follows t hat t he input resist ance of t he com m on- gat e st age is as obt ained before t he body effect was included [ ( 8.38) ] , except for t he addit ion of ηn , as in t he following:

Equ a t ion 8 .4 5

Figu r e 8 .7 . Cir cu it t ha t in clu de s t h e volt a ge - de pe n de n t cu r r e n t sou r ce du e t o body e ffe ct a ssocia t e d w it h M 2 . Body e ffe ct a ffe ct s t h e in pu t r e sist a n ce in t o t h e sou r ce of M 2 a n d t h e ga in of t h e com m on - ga t e st a ge of M 2 .

Sim ilarly, t he com m on- gat e gain, ( 8.38) , is readily m odified wit h t he addit ion of t he m ult iplying fact or ( 1 + ηn ) . This is

Equ a t ion 8 .4 6

Not e t hat in t he absence of g ds2 , t he gain for t he com m on- source st age reduces t o a vcd = g m 2 ( 1 + ηn ) RD2 , where, wit h body effect , t he effect ive t ransconduct ance is, again, ( 1 + ηn ) g m 2 .

8.8.3 Source-Follower Stage with Body Effect The t ransconduct ance relat ion obt ained for t he com m on- source st age given by ( 8.43) also applies t o t he source- follower st age. Com bining t his wit h Vs1 = I d1 Rs leads t o t he sourcefollower gain associat ed wit h M1 , which is

Equ a t ion 8 .4 7

The overall gain is again a v2 = a vsf a vcg Not e t hat t he body effect for t he source- follower st age increases t he denom inat or of ( 8.49) while it increases t he num erat or in t he com m on- gat e result , ( 8.48) . These t end t o cancel, as in t he case of t he invert ing gain.

8.9 Amplifier Gain with Differential and Common-Mode Inputs For input s at eit her or bot h gat es, t here exist s a com m on- m ode and different ial- m ode volt age. These are, for applied volt ages Vg1 and Vg2 , com m on m ode

Equ a t ion 8 .4 8

and different ial m ode

Equ a t ion 8 .4 9

Based on t hese definit ions, t he out put , for exam ple, Vd1 , for a given set of input s is

Equ a t ion 8 .5 0

where a vd1 and a vcm are ( 8.23) and ( 8.26) ( wit h RD1 ) , respect ively. For t he out put Vd2 , a vd2 is subst it ut ed for a vd1 . Vdm is a pure different ial input and is not wit h respect t o ground; t he effect from t he bias resist or is account ed for in t he com m on- m ode gain. For t he case of a single- ended input , for exam ple, Vg1 = Vi and Vg2 = 0, t he out put is

Equ a t ion 8 .5 1

This is ident ical t o ( 8.20) . The com m on- m ode cont ribut ion can be significant , for exam ple, in a resist ance feedback am plifier ( Unit 11) . I n t his case, Vdm in ( 8.50) can be very sm all com pared t o Vcm .

8.10 Comparison of Numerical Gain Results

Gain calculat ions were m ade using k n = 1000 µA/ V2 , λn = 0.05 V–1 , RD = 150 kΩ, Rbias = 100kΩ, ηn = 0.15, I D = 50 µA, and VDS = 5 V. The values are given in Table 8.1. For t he com parison, g m was calculat ed wit h t he precision form [ ( 4.5) ] ( λn 0) for all cases. Possibly a m ore valid consist ency ( hand calculat ion versus precision calculat ion) would be achieved wit h t he use of t he approxim at e form for g m up t o λn 0. This would reduce som e of t he difference in t he result s. For exam ple, for t he first case, a v1 = –a v2 = –33.5, wit h t he approxim at e form 0) . for g m ( λn TABLE 8 .1 Gain Magnit udes

a v1

a v2

37.5

37.5

plus Rbias = 100KΩ

37.9

37.1

plus λn = 0.05V–1

29.21

28.48

plus ηn = 0.15

29.17

28.53

Rbias =

, λn = 0, ηn = 0

I t is not able t hat t he various fact ors do not have a m aj or effect on t he result s, even t hough t he value of λn is relat ively large. This is especially t rue for t he different ial am plifier wit h resist ive load, as considered here. The conclusion can be m ade t hat for init ial hand- calculat ion purposes, t he sim plest form is sat isfact ory. Precision result s can be obt ained wit h a sim ulat or.

8.11 Summary of Equations Different ial- st age bias equat ion.

Threshold volt age for wit h VB = VSS and t hus VSB = 2I D Rbias. Approxim at e relat ion for drain- current im balance due t o k n1 k n2 and Vt no1 Vt no2 .

,

I deal volt age gain, Rbias = gm 2 = gm .

and g ds = 0, g m 1

Gain Vd2 / Vg1 = Vo2 / Vi for noninvert ing out put wit h finit e Rbias. Gain Vd1 / Vg1 = Vo1 / Vi for invert ing out put wit h finit e Rbias. Gain Vd1 / Vg1 = Vo1 / Vi for invert ing out put for source resist ance, Rs, wit h g ds 0. Rs = Ris2 | | Rbias I nput at t he source of M2 wit h g ds

0.

Gain Vd2 / Vs2 = Vo2 / Vs2 for com m on- gat e st age of M2 for g ds 0. Gain Vs1 / Vg1 = Vs1 / Vi of source- follower wit h input at gat e of M1 and out put at source of M1 . Gain Vd2 / Vg1 = Vo2 / Vi for noninvert ing out put and g ds 0. a vd12 = –g m RD

Gain for different ial input , different ial out put wit h RD1 = RD2 and g m 1 = g m 2 . Com m on- m ode gain.

Different ial- st age bias equat ion.

I nvert ing- input gain Vd1 / Vg1 = Vo1 / Vi , including body effect .

Rs = Ris2 | | Rbias I nput at t he source of M2 , including body effect and g ds 0. Com m on- gat e gain Vd2 / Vs2 = Vo2 / Vs2 of M2 , including body effect . Source- follower gain Vs1 / Vg1 = Vs1 / Vi of M1 , including body effect . a v2 = a vsf a vcg

Gain Vd2 / Vg1 = Vo2 / Vi , including body effect , g ds 0.

8.12 Exercises and Projects Proj ect Mat hcad Files

Exercise09.m cd - Proj ect 09.m cd

La bor a t or y Pr oj e ct 9

MOSFET Different ial Am plifier St age

P9.2

DC Evaluat ion of t he Single- Power- Supply Different ial Am plifier

P9.3

Det erm inat ion of t he PMOS Param et ers

P9.4

Am plifier Gain Measurem ent

P9.5

Transist or Param et ers and DC I m balance

P9.6

Com m on- Mode Gain Measurem ent

Unit 9. MOSFET Current Sources Wit h t he evolut ion of int egrat ed circuit s, it was necessary t o reduce t he num ber of resist ors in t he circuit , and t he solut ion was t he t ransist or current source. An added bonus was t hat t he circuit was generally great ly im proved as well. Here, t he basic principle is int roduced, followed by a discussion of t he st andard m et hod of increasing t he current out put resist ance wit h source degenerat ion. The applicat ion of a current - source configurat ion for balancing a different ial am plifier st age is discussed.

9.1 Basic Current Source An exam ple of a current source based on PMOS t ransist ors is shown here in Fig. 9.1. I t consist s of t he reference circuit , consist ing of t ransist or M3 and bias resist or Rbias. The reference- circuit t ransist or is diode connect ed. The induced VSG3 = VSD3 is applied t o t he current - source t ransist or M2 . Thus, t he drain current , or current - source current of M2 is t he m irror of t he reference current . I n an int egrat ed circuit , any num ber of current sources can be referenced t o t he reference current or volt age. Current rat ios are im plem ent ed wit h t he select ion of t he relat ive gat e widt hs of t he t ransist ors.

Figu r e 9 .1 . PM OS cu r r e n t sou r ce . Th e cu r r e n t se t u p by t he r e fe r e n ce cir cuit of M 3 a n d R bia s is m ir r or e d a s t h e cu r r e n t of M 2 .

The design of t he reference circuit is based on a dc solut ion t o t he reference current , I D3 . The solut ion is obt ained from t he loop equat ion

Equ a t ion 9 .1

and t ransist or equat ion

Equ a t ion 9 .2

The current in M2 is

Equ a t ion 9 .3

where

and

W 2 and W 3 are t he t ransist or gat e widt hs of M2 and M3 , respect ively, and L is t he channel lengt h. I n general, t he rat io of current s is

Equ a t ion 9 .4

where t he approxim at ion can oft en be used for sim plicit y wit h long- channel devices. This avoids t he necessit y of knowing t he source – drain volt ages. The signal out put resist ance at t he drain of M2 is

Equ a t ion 9 .5

I n t he proj ect of t he current source, we will scan VSD2 and com pare t he source current wit h t he reference current .

9.2 Current Source with Source Degeneration I t is norm ally desirable t o have t he out put resist ance of a current source as large as possible. I t can be im proved over t he circuit of Fig. 9.1 by adding resist ance in t he source branch, as shown in Fig. 9.2, t o est ablish source degenerat ion ( negat ive feedback) . I n t he discussion of t he signal circuit , it is necessary t o represent t he diode- connect ed t ransist or wit h it s linear equivalent , which is j ust a resist ance of m agnit ude, 1/ g m . This can be seen by inspect ion of t he circuit of Fig. 9.3. The volt age, Vd , is applied direct ly t o t he gat e such t hat Vgs = Vd and t he drain current is I d = g m Vd . Thus t he resist ance of t he diode is j ust Vd / I d = 1/ g m . The result is t he sam e for t he PMOS and NMOS as is always t rue for signal linear m odels.

Figu r e 9 .2 . Cu r r e n t - sou r ce cir cu it w it h sou r ce r e sist or s t o im pr ove ou t pu t r e sist a n ce a t dr a in of cur r e n t - sou r ce t r a nsist or , M 2 .

Figu r e 9 .3 . Sign a l cir cu it for diode - con n e ct e d N M OS.

The new out put resist ance at t he drain of M2 for t he current - source circuit wit h source resist ors ( Fig. 9.2) can be derived based on t he signal circuit s shown in Fig. 9.4. The out put resist ance is defined as Ro = Vo / I o , where I o is t he drain current flowing in conj unct ion wit h t he applicat ion of t he t est volt age Vo . Figure 9.4( b) replaces M3 wit h t he signal m odel equivalent and M2 wit h t he ideal, int rinsic t ransist or m odel ( current source) along wit h out put resist ance,1/ g ds2 . The

t ransist or sym bol represent s t he ideal t ransist or wit h out put current g m 2 Vsg2 , posit ive in t he direct ion shown.

Figu r e 9 .4 . ( a ) Sign a l cir cu it of Fig. 9 .2 . ( b) Re fe r e n ce t r a n sist or cir cu it r e pla ce d w it h t h e lin e a r m ode l. Th e e ffe ct ive r e sist a n ce a t t h e ga t e of t h e cu r r e n t sou r ce t r a nsist or pla ys n o r ole ot h e r t ha n t o r e t ur n t he ga t e t o gr ou n d sin ce I g2 = 0 .

The current I o flowing t hrough t he t ransist or and up t hrough t he resist or, RS2 , develops a volt age across t he resist or, VRS2 = I o RS2 . Since I g2 = 0, an input circuit loop equat ion is sim ply Vgs2 = –I d RS2 . The t ransist or linear- m odel current source, g m 2 Vgs2 , t hus is down, as shown in t he signal- circuit diagram of Fig. 9.4( b) . The sum of current s t hrough 1/ g ds is

Equ a t ion 9 .6

The volt age Vo is t hus

Equ a t ion 9 .7

and t he out put resist ance is

Equ a t ion 9 .8

This m agnit ude can be assessed wit h t he use of ( 4.5) , which is g m = 2I D / Veffp . Elim inat ing g m in ( 9.8) result s in

Equ a t ion 9 .9

I f t he m agnit ude of t he volt age across RS2 is several volt s, t hen Ro is m uch great er t han 1/ g ds2 , since Veff2 is t ypically a fract ion of a volt . I n int egrat ed circuit s, RS m ay be replaced wit h an addit ional current source, in which case t he expression becom es

Equ a t ion 9 .1 0

where t he out put resist ance of t he added current source is approxim at ely 1/ I D2 λp [ ( 4.13) ] .

9.3 Differential Amplifier Balancing Circuit The principle of t he balancing of t he different ial- am plifier st age ( e.g., in an opam p) is oft en based on a circuit sim ilar t o t hat in Fig. 9.2, as shown in Fig. 9.5. I m balance could be due, for exam ple, t o Vt po1 Vt po2 and k p1 k p2 . Balancing is im plem ent ed by adj ust ing R1 R2 , where R1 = RS1 / / Rx and R2 = RS2 | | Ry .

Figu r e 9 .5 . Ba la n cin g cir cu it . Volt a ge V D 2 is con t r olle d by se le ct in g t h e r e la t ive va lu e s of R x a nd R y .

The relat ionship am ong t he current s, param et ers, and resist ors is obt ained by writ ing t he loop equat ion around t he source resist ors and t he gat e – source t erm inals, which is

Equ a t ion 9 .1 1

A solut ion for VSD2 can be obt ained from ( 9.11) for a given set of param et ers, resist ors, and bias variables; on t he ot her hand, Rx and Ry are adj ust ed t o obt ain a cert ain VSD2 . For t he special case of I D1 = I D2 = I D , t he difference bet ween t he resist ors in ( 9.11) is

Equ a t ion 9 .1 2

For a num erical exam ple, suppose t he goal is t o set ( 9.12) ,

Equ a t ion 9 .1 3

. By design, in

Any slight possible difference in λp is neglect ed. I n a pract ical opam p wit h t his balancing configurat ion, t he source nodes are connect ed t o ext ernal pins. These pins are connect ed t hrough ext ernal resist ors Rx and Ry t o VDD as shown in Fig. 9.5. For adequat e adj ust m ent sensit ivit y, Rx and Ry are great er t han RS1 RS2 by at least a fact or of 10. I n pract ice, t he ext ernal resist ances are im plem ent ed wit h a pot ent iom et er. Assum e t hat t he t ransist or param et er values are Vt po1 = 1.49 V, Vt po2 = 1.51 V, k p1 = 345 µA/ V2 , k p2 = 335 µA/ V2 , and λp = 0.02 V–1 . Also assum e t hat t he bias current I D = 100 µA. We select RS1 = RS2 = RS = 3 kΩ ( Volt age I D Rs = 0.3 V) and we use Rx + Ry = Rpot = 25 kΩ; t he t wo resist ors are segm ent s of a 25- kΩ pot ent iom et er. The segm ent s of t he pot ent iom et er are t hen det erm ined from a solut ion t o

Equ a t ion 9 .1 4

where δR is obt ained from ( 9.12) wit h VSD2 = VSG1 as obt ained from ( 9.13) . The resist or values are Rx = 16 kΩ and Ry = 9 kΩ t o give R1 = 2.53 kΩ and R2 = 2.25 kΩ.

An evaluat ion of VSD2 wit hout t he balancing circuit can be m ade by set t ing δR = 0 in ( 9.12) and for solving VSD2 t o obt ain

Equ a t ion 9 .1 5

VSG1 is again obt ained from ( 9.13) .

Wit h t he num bers from t he exam ple above, VSD2 = 7.87 V. We not e t hat wit h λp = 0.01 V–1 , t he solut ion is VSD2 = 13.2 V and t he circuit m ight well have exceeded t he power- supply lim it s. I f Vt po1 = 1.45 V, Vt po2 = 1.55 V, and λp = 0.02 V–1 t hat is, for an ext rem e case of t he difference of t hreshold volt age, t he balancing circuit will st ill funct ion but now Rx = 21.8 kΩ and Ry = 3.24 kΩ wit h a sm all R2 = 1.56 kΩ.

9.4 Summary of Equations Reference current , I D3 , and current - source current , I D2 , relat ion.

Out put resist ance of current - source wit h source degenerat ion.

Out put resist ance of current - source wit h source degenerat ion and g m = 2I D / Veffp .

Relat ion for set t ing VD2 in balancing circuit wit h R1 = RS1 / / Rx and R2 = RS2 | | Ry .

δR = R1 – R2

Relat ion for VD2 = VD1 for I D1

I D2 = I D .

VSD2 for unbalanced circuit wit h δR = 0 and I D1 = I D2 = I D .

Unit 10. Common-Source Amplifier with Current-Source Load The am plifier in t his part is t he sam e, in principle, as t he basic com m on- source am plifiers of Figs. 2.4 and 5.1. However, now t he act ual resist or RD is replaced wit h a current - source load as shown in t he circuit of Fig. 10.1. As not ed in Unit 9, a benefit of replacing bias resist ors wit h current sources is a reduced requirem ent for resist ors in t he circuit ; t he reference volt age associat ed wit h M3 can be used elsewhere in a t ypical circuit . Addit ionally, as will be shown, t he gain of t he com m on- source st age is subst ant ially im proved over t hat wit h act ual bias resist or RD . The specific circuit of Fig. 10.1 is t hat for t he proj ect am plifier. The bias and gain of t he am plifier are evaluat ed in t he following.

Figu r e 1 0 .1 . Com m on - sou r ce a m plifie r w it h dr ive r t r a n sist or M 1 a n d cu r r e n t - sour ce loa d fr om dr a in of M 2 . I n t he a m plifie r pr oj e ct , a n ou t pu t ch a n n e l se t s V G1 for a give n cu r r e n t a n d a n ot h e r ou t pu t ch a n n e l w ill se a r ch for t h e V SS t o se t u p bia s V O = V D D / 2 . For t h e sign a l m e a su r e m e n t s, a sign a l volt a ge is su pe r im pose d on t he dc V G1 .

10.1 DC (Bias) Circuit The bias circuit is crit ical in t erm s of get t ing t he dc out put volt age at a value near t he proj ect design value of VO = VDD/ 2 ( for m axim um out put m agnit ude and linearit y) . The relat ion, from t he dc circuit analysis, for obt aining t his condit ion is based on I D1 = I D2 . This is, in t erm s of t he t ransist or charact erist ic equat ions, ( 3.8) ,

Equ a t ion 1 0 .1

Not e t hat t he source- gat e volt age of M2 is referenced t o M3 . A cert ain com binat ion of VGS1 and VSS will sat isfy Vo = VDD/ 2. I n t he proj ect on t he am plifier, a LabVI EW VI sends out a VG1 = VGS1 t o set up a given I D1 = I D2 and t hen adj ust s VSS t o obt ain t he desired bias out put volt age. Figure 10.2 shows a SPI CE plot of t he current for t he PMOS and NMOS t ransist ors as a funct ion of VDS1 . The source – drain volt age for t he PMOS is VSD2 = VDD – VDS1 . Bot h t ransist ors have a specific gat e – source volt age. The solut ion for t he out put volt age for t his case is about 3 V. A slight decrease in VGS1 or a slight increase in VSG2 is required t o bring VDS1 t o 5 V, t he design result in t his exam ple. The increase in VSG2 would be im plem ent ed by m aking VSS m ore negat ive t o increase t he reference current . The st eeper slope in t he act ive region of t he PMOS device is consist ent wit h λp > λn , as in t he proj ect am plifier.

Figu r e 1 0 .2 . Plot of dr ive r a n d loa d t r a n sist or ou t pu t ch a r a ct e r ist ics on com m on volt a ge sca le . Sin ce I D 1 = I D n = I D 2 = I D p , V D S1 = V O is w h e r e cu r r e n t s int e r se ct . Th e cu r r e n t fr om t h e cu r r e n t sou r ce loa d n e e ds, in t h is e x a m ple , t o be sligh t ly in cr e a se d t o se t V D S1 = V O , w it h V D D = 5 V.

10.2 Signal Voltage Gain The expression for t he gain of t he basic com m on- source am plifier, ( 5.4) , which includes t he out put resist ance of t he driver t ransist or, is

I n t he signal circuit , as shown in Fig. 10.3, RD is replaced by 1/ g ds2 . The new equat ion for t his circuit is

Equ a t ion 1 0 .2

Figu r e 1 0 .3 . Lin e a r cir cu it of t h e com m on - sou r ce a m plifie r . The loa d is n ow t h e ou t pu t r e sist a n ce of t h e cu r r e n t sou r ce loa d, 1 / g ds2 .

or wit h g m = 2I D / Veff , ( 4.5) , and g ds

I D λ, ( 4.13) ,

Equ a t ion 1 0 .3

The result shows t hat t he gain increases for decreasing Veffn1 . This is lim it ed by t he fact t hat t he MOSFET ceases t o behave in t he norm al m anner at som e lower lim it on Veffn . Using gain. This is

Equ a t ion 1 0 .4

an alt ernat ive form is obt ained, which reveals t he I D1 dependence of t he

I ncreasing gain is achieved wit h decreasing t he level of bias current . The lower lim it is, as not ed above, associat ed wit h a lower lim it on Veffn . Also, t here is an approxim at e inverse t radeoff bet ween frequency response lim it at ions, on t he high end of t he spect rum , and gain. The gain, t hough, for t he am plifier wit h current source load, will generally be several t im es as large as t hat wit h t he resist ive load. An am plifier wit h even higher gain can be obt ained by replacing t he current source load wit h one wit h source degenerat ion as discussed in Unit 9.2, and as discussed ext ensively for t he case of t he BJT in Unit C.

10.3 Summary of Equations Out put drain- current balance equat ion. Volt age- gain equat ion. Volt age- gain equat ion in t erm s of λ's and Veffn1 . Volt age- gain equat ion in t erm s of λ's and I D .

10.4 Exercises and Projects Proj ect Mat hcad Files

Exercise10.m cd - Proj ect 10.m cd

La bor a t or y Pr oj e ct 10

Current Mirror and Com m on- Source Am plifier wit h Current Source Load

P10.2

Evaluat ion of t he Current - Source Circuit

P10.3

Evaluat ion of t he Mirror- Current Circuit

P10.4

Evaluat ion of t he Bias Set up

P10.5

Measurem ent of t he Am plifier Gain versus Drain Current

Unit 11. Operational Amplifiers with Resistor Negative Feedback I n t he following unit s we consider t he operat ional am plifier in t he basic resist ive feedback am plifier configurat ions. We discuss gain, dc offset , and frequency response. I n proj ect s, t he opam p is im plem ent ed in t he noninvert ing am plifier m ode t o evaluat e volt age again, opam p offset , bias st abilizat ion, and am plifier and opam p frequency response.

11.1 Operational Amplifiers with Resistance Feedback I n t his unit , t he gain charact erist ics of t he operat ional am plifiers wit h resist ive feedback are discussed. These are dc am plifiers t hat are configured for specific gain and input and out put resist ance charact erist ics. The operat ional am plifier wit hout feedback is in t he open- loop m ode. The dc ( bias) configurat ion is shown in Fig. 11.1. Due t o im balances in t he am plifier circuit , which are a result of variat ions in t he param et ers of t he t ransist ors and circuit com ponent s from t he values used in t he design, t he out put will probably be lat ched at eit her t he plus or m inus power supply.

Figu r e 1 1 .1 . Ope n - loop a m plifie r . I n pu t s, ou t pu t , a n d pow e r - su pply pin s a r e con n e ct e d. Cir cu it w ill be bia s u n st a ble . D c V O is lik e ly t o be la t ch e d a t n e a r V D D or V SS.

The circuit can be set int o a st able, act ive m ode wit h t he out put approxim at ely at zero volt s by providing resist ive negat ive feedback as shown in t he circuit diagram of Fig. 11.2.

Figu r e 1 1 .2 . Opa m p r e sist or n e t w or k , in clu din g fe e dba ck r e sist or for bia s st a biliza t ion . Sign a l ou t pu t volt a ge is V o = a vo V .

The resist or connect ed bet ween t he out put , VO, and t he invert ing ( m inus) input effect ively applies t he out put volt age t o t he opam p input and it is of such a polarit y as t o drive t he out put t oward zero volt s, where it t ends t o st ay. That is, at t aching t he resist or com plet es t he negat ive feedback loop from V t o VRy . The quant it at ive aspect s of st abilizat ion wit h t he feedback resist or are discussed in Unit 11.6. This circuit becom es a dc am plifier by inst alling a signal at eit her input . These t wo possibilit ies are discussed in t he following unit s.

11.1.1 Voltage Gain of the Noninverting Resistor Feedback Amplifier I n t he circuit diagram of Fig. 11.3, an input signal volt age Vs is at t ached t o resist or Rx . By definit ion, t he out put t erm inal volt age is posit ive for a plus input . Hence, t his is t he noninvert ing am plifier. Here we obt ain t he relat ionship bet ween t he am plifier gain, a vo = Vo / Vs, and t he open- loop gain ( opam p gain) , a vo = Vo / V , and t he circuit resist ors.

Figu r e 1 1 .3 . N on - in ve r t in g or volt a ge a m plifie r ( se r ie s- sh u n t ) . The in pu t r e sist a n ce is e sse n t ia lly in fin it e .

Wit h a signal applied t o t he plus input t erm inal, t he responding out put volt age is fed back t o t he resist or Ry . The volt age across Ry , Vf , and Vo ( signal) are relat ed by

Equ a t ion 1 1 .1

This is j ust t he volt age- divider relat ion, which applies in t his case, as negligible current flows int o t he input t erm inals of t he opam p. Variable Vf is used in lieu of VRy t o dist inguish it from t he dc value of t he volt age across Ry . This use is also consist ent wit h t he fact t hat Vf is t echnically a signal feedback volt age. The input signal volt age Vs adds up t o

Equ a t ion 1 1 .2

where ( 11.1) is used t o elim inat e Vf . ( The volt age drop across Rx is essent ially zero.) This leads direct ly t o t he relat ion for am plifier gain, which is

Equ a t ion 1 1 .3

wit h ( ideal noninvert ing gain) .

Equ a t ion 1 1 .4

AvNI is t he lim it ing form of t he noninvert ing am plifier gain for a vo . This is consist ent wit h 0 and Vs = VRy . Thus, t he out put and input volt ages are sim ply t he fact t hat in t he lim it , V relat ed by t he volt age- divider relat ion. The result , ( 11.3) , indicat es t hat for a vo > > AvNI , t he volt age gain can sim ply be expressed in t erm s of t he resist ors and t herefore is very predict able. I f we m ake, for exam ple, Rf = 10Ry , AvNI = 11, and ( 11.3) gives Av = 10.998, wit h a vo = 40,000. The value for t he opam p gain is t ypical for our proj ect opam p. Not e t hat due t o t he high resist ance at t he opam p input t erm inals, Rx has no influence on t he gain. The noninvert ing am plifier has a very high input resist ance and a low out put resist ance, as discussed in Unit 11.4. The am plifier t echnically falls int o t he cat egory of a series – shunt feedback configurat ion or a volt age am plifier.

11.1.2 Voltage Gain of the Inverting Resistor Feedback Amplifier To obt ain t he invert ing am plifier, t he signal is applied t o t he negat ive or invert ing t erm inal as shown in Fig. 11.4. A posit ive signal result s in a negat ive out put volt age. The gain expression can be obt ained wit h t he loop equat ion from out put t o input :

Equ a t ion 1 1 .5

Figu r e 1 1 .4 . I n ve r t in g or t r a n sr e sist a n ce a m plifie r ( shunt – shunt ) . Th e in pu t r e sist a n ce is e qu a l t o t h e sign a l- sou r ce r e sist a n ce , R y .

and t he loop equat ion at t he input ( volt age drop across Rx is zero)

Equ a t ion 1 1 .6

Elim inat ing I s bet ween ( 11.5) and ( 11.6) gives

Equ a t ion 1 1 .7

This expression can be m anipulat ed t o give t he gain as

Equ a t ion 1 1 .8

which is

Equ a t ion 1 1 .9

where

Equ a t ion 1 1 .1 0

AvI is t he gain of t he ideal invert ing am plifier. The ideal gain, as in t he case of t he noninvert ing am plifier, depends only on resist or values. 0, in which case t he negat ive The approxim at e form is based on t he approxim at ion V = input t erm inal is at virt ual ground. Thus, | v o | and Vs are proport ional t o Rf and Ry , respect ively. The invert ing- am plifier gain result includes t he fact t hat t he current int o t he negat ive t erm inal is zero. The circuit is a shunt – shunt feedback configurat ion or a t ransresist ance am plifier.

11.2 Output Resistance of the Resistor Feedback Amplifier The negat ive feedback of t he am plifiers will alt er t he out put resist ance of t he circuit . I n t he case of series – shunt feedback ( noninvert ing am plifier) and t he shunt – shunt ( invert ing am plifier) , t he out put resist ance will be reduced from t hat of t he open- loop am plifier. This can be explained wit h t he use of t he circuit of Fig. 11.5, which shows a linear- m odel circuit for t he am plifiers of Figs. 11.3 and 11.4, wit h t he input s set t o zero.

Figu r e 1 1 .5 . Lin e a r e qu iva le n t cir cu it for de r ivin g opa m p ou t pu t r e sist a n ce . Te st volt a ge , V o , is a pplie d a t t h e opa m p ou t pu t . Th e in put s a r e gr ou n de d for de r ivin g t h e ou t pu t r e sist a n ce .

For t he present purposes, a volt age- dependent volt age source equivalent circuit for t he opam p is chosen. The param et er r o is t he out put resist ance of t he open- loop opam p. For exam ple, t he out put resist ance would be about 1/ g m in a CMOS opam p wit h a source- follower st age- out put st age. A t est volt age, Vo , is applied at t he out put t erm inal wit h t he input grounded. This result s in an input t o t he opam p of m agnit ude V = Vo / AvNI . The volt age- dependent volt age source of t he opam p is t hus ( a vo / AvNI ) Vo . The t ot al current , I o , flowing from t he t est volt age is t hen

Equ a t ion 1 1 .1 1

Therefore, t he out put resist ance is

Equ a t ion 1 1 .1 2

where T = a vo / AvNI ( i.e., t he loop gain of t he feedback am plifier) . The approxim at e form com es from t he expect at ion t hat r o < < Ry + Rf ; it neglect s t he current t hrough t he feedback resist ors. r o / T is a valid approxim at ion in m ost cases and Ro < < r o . For exam ple, for AvNI 10 and Ro a vo 40,000, T = 4000, and Ro r o / 4000.

11.3 Operational Amplifier Offset I deally, an opam p is balanced such t hat t he dc out put is zero ( wit h dual power supply) wit h zero input volt age ( as in Fig. 11.1) . I n pract ice, t his is not realized, due t o t he variat ion of param et ers bet ween sim ilar t ransist ors and com ponent s. As m ent ioned above, t he opam p configurat ion of Fig. 11.1 will probably be locked at near t he posit ive or negat ive rail volt age. Thus, a given opam p requires an input volt age Vin t o set t he out put t o zero. The m agnit ude of t his volt age is defined as offset volt age Voff . An equivalent circuit t hat includes t he offset volt age is given in Fig. 11.6. The im perfect ions of t he am plifier are reflect ed int o t he offset volt age and t he opam p is ideal. I f Vi is m ade equal t o Voff , t he out put VO will be zero. Suppose t hat Vi = 0. I n t his case we have t he equivalent of Voff applied t o t he input and t he out put is driven t oward t he plus or m inus power- supply volt ages ( depending on t he polarit y of Voff ) . Voff is usually large enough t o cause t he am plifier t o be driven out of t he act ive m ode. For exam ple, a t ypical Voff is Voff = 1 m V. Thus, if a vo = 40,000, t he out put will at t em pt t o becom e –40 V, which is probably great er t han t he supply volt age value; t he out put is set at t he negat ive lim it . I n our proj ect opam p, t his will be roughly VSS + 50 m V if driven negat ive or VDD –1V if driven t oward t he posit ive supply.

Figu r e 1 1 .6 . I de a l opa m p w it h offse t volt a ge . W it h dc in put volt a ge V i V D D or V SS w it h = V off , V O = 0 . W it t V i = 0 ( gr ou n de d in pu t ) , V O | a vo V off | > V D D or | V SS| for V off n e ga t ive or posit ive , r e spe ct ive ly.

11.4 DC Stabilization with the Feedback Resistor The dc out put volt age can be set close t o zero wit h negat ive feedback for norm al operat ion as a linear am plifier as illust rat ed in Fig. 11.7. A port ion of t he out put volt age is applied back t o t he input as t he volt age across Ry . This is

Equ a t ion 1 1 .1 3

Figu r e 1 1 .7 . Opa m p dc st a bilize d w it h fe e dba ck r e sist or n e t w or k . Th e ou t pu t volt a ge is a pplie d ba ck t o t h e in pu t t o t h e n dr ive t h e ou t pu t t ow a r d a sm a lle r va lu e . The volt a ge a cr oss R y w ill be a bou t e qu a l t o V off a n d V O is for ce d t o n e a r ze r o.

( Dc VO is used, as t his is a no- signal or bias st at e under considerat ion.) This volt age will cancel m ost of Voff , such as t o drive VO close t o zero if Rf is sm all enough com pared t o Ry . The value of VO for a given Rf can be obt ained as follows: A loop equat ion at t he input side ( Fig. 11.7) gives

Equ a t ion 1 1 .1 4

The opam p circuit is a dc am plifier. Therefore, t he input – out put relat ion holds for dc as well as for signals. Thus, V = VO/ a vo such t hat

Equ a t ion 1 1 .1 5

and

Equ a t ion 1 1 .1 6

where t he approxim at ion usually applies and is equivalent t o V = 0. –0.1 V. This would be a very sat isfact ory For exam ple, wit h Voff = 1 m V and AvNI = 100, Vo dc st at e for using t he circuit as an am plifier. Also, t he approxim at ion of t he right - hand side of ( 11.16) is quit e valid. Not e t hat wit hout t he feedback net work, VO = –a vo Voff = –40,000 · 1 m V = –40 V. Assum ing t hat t he power- supply volt age is, for exam ple, ± 15 V, t he out put is locked at VO –15 V and t he linear gain relat ion does not apply. I n our proj ect wit h t he opam p, we det erm ine Voff from a m easurem ent of VO and t he applicat ion of ( 11.16) .

11.5 Frequency Response of the Operational Amplifier and Resistor Feedback Amplifier The MOSFET has a num ber of capacit ances, including t hose associat ed wit h t he gat e st ruct ure and source and drain pn j unct ions as well as ot her parasit ic capacit ors of t he t ransist or and t he circuit . Therefore, t he open- loop opam p will t end t o be unst able due t o t he poles and zeros associat ed wit h t he capacit ors. Opam ps are usually st abilized wit h t he addit ion of a capacit or. The added pole is well below t he lowest nat urally occurring pole. This pole will dom inat e t he frequency response of t he opam p. I n a lab proj ect , t he pole frequency will be m easured. We will obt ain t he frequency response of t he feedback am plifier based on t he single- pole response. The form of t he response of t he open- loop opam p is

Equ a t ion 1 1 .1 7

The response funct ion has value a vo at low frequencies and has m agnit ude at f = f 3dB opam p , where f 3dB opam p is t he charact erist ic frequency of t he opam p. This is indirect ly, f 3dB opam p = GBP/ a vo , where GBP is t he gain – bandwidt h product of t he opam p as given in t he dat asheet . Dat asheet value a vo is also given ( Avd , large- signal volt age gain) . The noninvert ing feedback am plifier has a gain as given by ( 11.3) . That expression is used here along wit h ( 11.17) in place of a vo . The frequency response of t he feedback am plifier is t hus

Equ a t ion 1 1 .1 8

which is

Equ a t ion 1 1 .1 9

This can be sim plified t o

Equ a t ion 1 1 .2 0

where Avo is t he am plifier gain at low frequencies and where

Equ a t ion 1 1 .2 1

Frequency param et er f BW is t he bandwidt h of t he am plifier for a specific AvNI · Param et er f BW, by definit ion of bandwidt h, is also f 3dB of t he am plifier. Adding feedback by reducing Rf always increases bandwidt h at t he expense of gain. Not e t hat for Rf very sm all, f BW can be relat ively high and t he frequency response is com plicat ed by t he fact t hat ot her poles of t he opam p com e int o play. Given in Table 11.1 is a segm ent from t he m anufact urer's dat asheet for t he opam p ( TS271C) used in our proj ect . As m ent ioned above, t he param et er for large- signal volt age gain is designat ed as Avd and is ident ical t o a vo . The GBP indicat ed is 700 kHz. Thus for a lowfrequency am plifier gain of, for exam ple, Av = 5000, t he bandwidt h is f BW = 700 kHz/ 5K = 140 Hz, which can be readily m easured using LabVI EW and t he DAQ in t he com put er. TABLE 1 1 .1 TS271C/ AC/ BC Sym bol Avd

GBP

Param et er

Min. Typ. Max

Unit

50

V/ m V

0.7

MHz

Large Signal Volt age Gain VO = 1 V t o 6 V, RL = 100 kΩ, Vic = 5 V

30

Tm in. < Tam b < Tm ax.

20

Gain Bandwidt h Product ( Av = 40dB, RL = 100 KΩ, CL = 100pF, f in = 100 KHz)

Not e t hat for t he lim it ing case of Rf , t he bandwidt h of t he open- loop am plifier is only f 3dB = 700 kHz/ 50K = 14 Hz, where t he t ypical ( Typ.) num ber, Avd = 50 k has been used.

11.6 Summary of Equations Noninvert ing feedback am plifier volt age gain.

I deal noninvert ing am plifier volt age gain.

I nvert ing feedback am plifier volt age gain.

I deal invert ing am plifier volt age gain.

Out put resist ance of t he resist ance- feedback opam p am plifier.

T = a vo / AvNI

Loop gain of resist ance- feedback opam p am plifier. Out put volt age of resist ance- feedback opam p wit h offset volt age, Voff .

Frequency- response funct ion of resist ance- feedback opam p am plifier.

Bandwidt h ( corner frequency) of opam p am plifier wit h opam p open- loop corner frequency, f 3dB.

11.7 Exercises and Projects Proj ect Mat hcad Files

Exercise11.m cd - Proj ect 11.m cd

La bor a t or y Pr oj e ct 11

Operat ional Am plifier wit h Resist or Feedback

P11.2

Bias Circuit Set up

P11.3

Opam p Offset Volt age

P11.4

Evaluat ion of t he Bias Balancing Circuit

P11.5

Evaluat ion of t he Gain and Signal Lim it s wit h Swept I nput

P11.6

Evaluat ion of t he Gain wit h Sine- Wave and Square- Wave Signals

P11.7

Det erm inat ion of t he Opam p Frequency Response

Unit 12. Operational Amplifier Applications with Capacitors I n t his unit we consider t he m ost com m on applicat ions of operat ional am plifiers where t he circuit uses a capacit or as t he key com ponent . I ncluded are t he opam p int egrat or and a basic opam p square- wave oscillat or. Bot h form s are invest igat ed in proj ect s.

12.1 Operational Amplifier Integrator The noninvert ing or invert ing resist ance- feedback am plifier can be convert ed int o an int egrat or wit h t he addit ion of a feedback capacit or, Cf , as shown in Fig. 12.1. Specifically, t he feedback resist or is replaced wit h Cf , except t hat t he resist or Rf m ust rem ain for dc st abilizat ion purposes.

Figu r e 1 2 .1 . Opa m p in t e gr a t or . Th e r e sist or R f in sh u n t w it h Cf is for opa m p st a biliza t ion pu r pose s.

The operat ion of t he int egrat or can be explained as follows. For t he init ial discussion, assum e t hat Rf is infinit e. Upon applicat ion of a const ant volt age Vs, a current is induced in Ry , which is

Equ a t ion 1 2 .1

The approxim at ion relies on t he fact t hat V volt age is

0, which can be expect ed. The result ing out put

Equ a t ion 1 2 .2

To a good approxim at ion, v o ( t ) is proport ional t o t he int egral of t he input . Perform ing t he int egrat ion, t he result is

Equ a t ion 1 2 .3

I f Vs is t he m agnit ude of a square- wave, t he out put will be a t riangular wave. I n t he int egrat or proj ect we explore t he int egrat or by using it t o generat e a t riangular wave. The proj ect design calls for a peak of t he t riangular wave equal t o a few volt s, t hat is, a significant port ion of t he power- supply volt age. The t im e of int egrat ion for t he plus or m inus segm ent of t he squarewave input is T/ 2, where T is t he period and T = 1/ f, t hat is, t he inverse of t he square- wave frequency. The peak of t he t riangular wave t hen is based on

Equ a t ion 1 2 .4

The 2 Vopeak is due t o t he fact t hat t he int egrat ion is from m inus Vopeak t o plus Vopeak . The volt age drop across Ry has been neglect ed in t he out put . Suppose we choose Cf as t he design param et er where Vs, T, Vopeak , and Ry ( from Unit 11) are given. The capacit or is t hen select ed according t o

Equ a t ion 1 2 .5

For exam ple, for Vs = 1 m V, Vopeak = 5 V, Ry = 220 Ω and T = 1 m S ( f = 1 kHz) , Cf = 23 nF. I n t he int egrat or proj ect , a sine- wave source is used. The int egrat ed out put for t his case is

Equ a t ion 1 2 .6

The sine t erm can be neglect ed and t he result ing form ulat ion can be used t o predict t he peak of t he cosine for a given Cf and peak Vs. A m ore general solut ion for t he out put volt age for t he noninvert ing int egrat or includes t he current t hrough t he resist or Rf . I f we neglect t he volt age across Ry , ( 12.2) becom es, for t his case ( const ant input or square- wave input )

Equ a t ion 1 2 .7

The solut ion is

Equ a t ion 1 2 .8

Replacing t he exponent ial wit h t he first t hree t erm s of an infinit e series gives

Equ a t ion 1 2 .9

This dem onst rat es t hat for t he circuit t o funct ion properly as an it egrat or, t he choice of Rf should sat isfy Rf Cf > > T/ 2. I n t he above exam ple, Cf = 23 nF. Wit h t his capacit or and Rf = 1 MΩ, for exam ple, Rf Cf = 23 m s, com pared wit h T/ 2 = 0.5 m s. The m agnit ude of Rf m ust also sat isfy t he requirem ent of sust aining t he operat ional am plfier in t he act ive m ode. The solut ion for t he periodic square- wave input , giving an approxim at e t rianglar- wave out put , unlike ( 12.8) , includes t he fact t hat t he t ransient does not st art at zero volt s. This case is considered in Exercise12.m cd, Part 2. The out put volt age funct ion equivalent t o ( 12.2) for t he invert ingm ode int egrat or is

Equ a t ion 1 2 .1 0

This would apply t o t he circuit of Fig. 12.1 wit h t he plus input grounded and t he source, Vs, at t ached at t he grounded end of Ry .

12.2 Operational Amplifier Oscillator The opam p can serve as a square- wave oscillat or by adding posit ive feedback wit h R1 and R3 and replacing Ry wit h a capacit or Co , as shown in Fig. 12.2. The frequency of t he operat ion can be com put ed on t he basis of t he following derivat ion. Wit h posit ive feedback, t he circuit is unst able and t he out put volt age is eit her Vop or –Vom , t hat is, t he posit ive or negat ive lim it . The lim it s are close t o VDD or VSS. These volt age values are applied t o t he input t hrough t he posit ive feedback net work such t hat t he plus input t erm inal is eit her at

Equ a t ion 1 2 .1 1

or

Equ a t ion 1 2 .1 2

Figu r e 1 2 .2 . Opa m p oscilla t or . Th e fr e qu e n cy is de t e r m in e d by t h e va lu e of r e sist or s a n d t h e ca pa cit or .

where Vom is posit ive. However, t he negat ive- feedback circuit consist ing of Rf and Co will cause t he capacit or t o charge up t oward t he volt age at t he out put . For exam ple, suppose t hat for an int erval of t im e, VDD. Also assum e t hat R3 = R1 such t hat t he plus input is at Vop / 2. When t he v o ( t ) = Vop capacit or charges up t o and j ust beyond Vop / 2, t he opam p input V changes sign and t he out put will swit ch over t o v o ( t ) = –Vom . At t his point , t he capacit or begins charging t oward t he opposit e polarit y, and so fort h. For a given out put , t he t im e- dependent capacit or volt age is a sim ple RC t ransient . For exam ple, for v o ( t ) = Vop,

Equ a t ion 1 2 .1 3

wit h a st eady- st at e value of Vop . As an oscillat or, t he capacit or volt age will never reach t he st eady- st at e value; t he t ransient t erm inat es at t he value given by ( 12.11) . The out put is swit ching back and fort h from Vop t o –Vom . Therefore, t he init ial value of t he capacit or volt age in ( 12.13) is

Equ a t ion 1 2 .1 4

Using t his t o obt ain a com plet e solut ion for ( 12.13) result s in

Equ a t ion 1 2 .1 5

We define t = Tplus as t he posit ive t im e segm ent of t he square- wave period. As not ed, t his corresponds t o t he t im e where t he out put swit ches t o –Vom ; t hat is,

Equ a t ion 1 2 .1 6

Using ( 12.16) in t he left - hand side of ( 12.15) gives an equat ion for Tplus as follows:

Equ a t ion 1 2 .1 7

Then, solving for Tplus result s in

Equ a t ion 1 2 .1 8

Following t he reasoning t hat led t o ( 12.15) , t he falling capacit or- volt age t ransient is

Equ a t ion 1 2 .1 9

The t ot al t im e int erval ( negat ive segm ent of t he square- wave period) of t he falling t ransient , t = Tm inus, corresponds t o t he capacit or volt age, decreasing t o

Equ a t ion 1 2 .2 0

Using ( 12.20) in ( 12.19) gives t he equat ion for Tm inus, which is

Equ a t ion 1 2 .2 1

This leads t o

Equ a t ion 1 2 .2 2

A special case is for R1 = R3 , where ( 12.18) and ( 12.22) becom e

Equ a t ion 1 2 .2 3

and

Equ a t ion 1 2 .2 4

The oscillat or period is T = Tplus + Tm inus or, for t his special case,

Equ a t ion 1 2 .2 5

A good est im at e com es from t he approxim at ion Vop

Vom . The result is

Equ a t ion 1 2 .2 6

Not e t hat alt hough Tm inus and Tplus can be significant ly different [ from ( 12.18) and ( 12.22) ] , t he sum is well represent ed by ( 12.26) . Not e also t hat t he waveform is st rict ly a square- wave only if Vop = Vom . LabVI EW uses ( 12.25) t o calculat e t he act ual value of t he capacit or used in t he proj ect on t he oscillat or. I n t he proj ect , period T is a m easured value. Shown in Fig. 12.3 is a proj ect result of t he m easurem ent of t he out put volt age and capacit or volt age for t he oscillat or. Power- supply volt ages were set at plus and m inus eight volt s and R1 = R3 .

Figu r e 1 2 .3 . Oscilla t or v o ( t ) a n d v co ( t ) ve r su s t ( m s) . N ot e t h a t t h e sw it ch in g t a k e s pla ce w h e r e t h e ca pa cit or volt a ge r e a ch e s a bou t on e h a lf of t he squ a r e - w a ve pe a k m a gn it u de . Th is is for R 1 = R 3 .

12.3 Summary of Equations Opam p- int egrat or equat ion for det erm ining t riangularwave peak am plit ude for applied square- wave wit h peak Vs and period T. Opam p- int egrat or equat ion for det erm ining out put waveform for sine- wave input wit h peak Vs and period T. Equat ion for t he opam p- oscillat or period, for t he case of R1 = R3 . Equat ion for opam p- oscillat or period, for t he case of R1 = R3 and equal posit ive and negat ive peak m agnit udes.

12.4 Exercises and Projects Proj ect Mat hcad Files

Exercise12.m cd - Proj ect 12.m cd

La bor a t or y Pr oj e ct 1 2

Operat ional Am plifier I nt egrat or and Oscillat or

P12.2

Opam p I nt egrat or

P12.3

Opam p Oscillat or

Unit 13. Cascaded Amplifier Stages The cascade elect ronic circuit configurat ion is t hat form ed by connect ing t he out put of one st age t o t he input of t he one following. I n analog am plifiers, such as t he operat ional am plifier, high gain is achieved t hrough cascading a num ber of st ages. Mixing NMOS and PMOS circuit s provides t he m aj or advant age of direct coupling bet ween st ages. The am plifier invest igat ed is t he cascade of a different ial st age and a com m on- source st age. Circuit bias st abilit y is explored as an exam ple of problem s in general wit h direct st age coupling.

13.1 Combining NMOS and PMOS Circuits in Cascade The circuit of Fig. 13.1 illust rat es t he concept of com bining NMOS circuit s wit h PMOS circuit s for enabling direct coupling of t he st ages. The added feat ure of a dual power supply is included, which provides for having t he input and out put s at ground pot ent ial. One of t he im port ant advant ages of t his is t hat connect ing input sources and out put loads does not affect t he bias.

Figu r e 1 3 .1 . Ca sca de of a diffe r e n t ia l st a ge a n d a com m on - sou r ce st a ge . N o cou plin g ca pa cit or s or bypa ss ca pa cit or s a r e r e qu ir e d. Th is is t h e r e for e a dc a m plifie r .

The input can be set equal t o zero volt s, as it is t he gat e of a different ial am plifier st age in a dual- power- supply configurat ion. The out put can be set equal t o zero volt s by select ing t he drop across t he bias resist or RD3 t o be equal t o | VSS| . This flexibilit y is provided by t he PMOS as t he out put st age; it is approxim at ely a current course wit h t erm inat ion at t he negat ive power supply. Wit h VO = 0, t he available out put signal range is nearly equal t o t he m agnit ude of t he power- supply volt age; t he drain volt age of M3 can swing anywhere from near VDD down t o VSS. Not e t hat t his would not be possible if t he com m on- source st age t ransist or were based on an NMOS. The out put from M2 of t he different ial- am plifier st age is used arbit rarily. Since t he com m onsource st age is an invert ing st age, t he gat es of M1 and M2 are t he invert ing ( –) and noninvert ing ( + ) input s, respect ively. A dc st abilizat ion resist or would be connect ed bet ween t he out put ( drain of M3 ) and t he input at t he gat e of M1 . This t ype of feedback would, of course, represent an addit ional load on t he out put st age.

13.2 Amplifier Gain of Differential Amplifier and Common-Source Stage in Cascade I n t he exam ple of Fig. 13.1, a different ial st age and a com m on- source st age are connect ed in a cascade configurat ion; t he input of t he com m on- source st age is t he out put of t he different ial st age. The overall volt age gain is defined as a v = v o / v i = v d3 / v g1 . But this is also

Equ a t ion 1 3 .1

Therefore, t he gain can be calculat ed by using t he separat e expressions considered previously for t he different ial am plifier st age [ ( 8.15) ] and t he com m on- source st age [ ( 5.5) ] . This leads t o

Equ a t ion 1 3 .2

or using, from ( 4.5) , g m = 2I D / Veff ,

Equ a t ion 1 3 .3

Throughout t his unit , t he assum pt ion is m ade t hat g m 1 = g m 2 and v effn1 = Veffn2 . The gain expression neglect s t he t ransist or out put resist ance in t he different ial am plifier gain for sim plicit y wit hout a great loss of accuracy, due t o t he relat ively sm all value of RD2 . I t also neglect s t he effect on t he gain of t he different ial st age of Rbias. [ Rbias and t he out put resist ance are included in gain result ( 8.40) , for com parison.] For a calculat ion of a num erical value of a represent at ive gain, assum e t hat Veffn1 = Veffp3 = 0.3 V, Vt no = Vt po = 1.0 V ( giving VRD2 = 1.3 V) , VRD3 = 5 V ( for Vss = –5 V) and λp = 0.05 V–1 . The volt age- gain m agnit ude is | a v | = 4.33 · 26.7 = 116. We com pare t his below wit h an am plifer t hat has bet t er bias st abilit y but which loses gain in a t rade- off.

13.3 Stabilization of Signal Gain and Bias Current with a Source Resistor The am plifier of Fig. 13.1 is not a good design in t erm s of bias st abilit y. Bias current I D3 ( of M3 ) in t he circuit of Fig. 13.1 is very sensit ive t o t he volt age across RD2 , which, in a relat ive sense, is only m arginally predict able, given t he norm al variat ion in device param et ers and circuit com ponent s. Also, as in t he bias- st abilit y discussion of Unit 5.5 on t he design of t he NMOS com m on- source am plifier, for a const ant VGS3 , bias current I D3 is sensist ive t o changes in t ransit or param et ers. ( Not e t hat t he different ial- am plifier- st age bias current is relat vely st able, as it is a current - source bias current .)

13.3.1 Gain and Gain Stabilization As not ed, it was shown in Unit 5.5 t hat a degree of bias st abilit y is provided wit h a source resist or as in t he circuit of Fig. 13.2 ( in t his case, RS3 ) . This is an addit ional exam ple of providing som e st abilizat ion wit h t he addit ion of ac and dc negat ive feedback in a circuit . The addit ion of t he resist or result s in an increase in t he gain of t he different ial am plifier st age but a decrease in t he gain of t he com m on- source st age. The net result is a reduct ion of gain as a t rade- off bet ween t he gain and bias st abilit y.

Figu r e 1 3 .2 . Am plifie r cir cu it w it h t he a ddit ion of a sou r ce r e sist or , R S3 , w h ich se r ve s t o im pr ove t h e ga in a n d bia s st a bilit y. Th is a ga in de m on st r a t e s a ge n e r a l pr in ciple , oft e n u se d in e le ct r on ic cir cu it s, w h e r e in a lin e a r com pone n t is in st a lle d t o dom in a t e t h e volt a ge of volt a ge s in se r ie s.

The gain expression for t he circuit wit h RS3 is

Equ a t ion 1 3 .4

where ( 5.15) is now used for t he gain of t he com m on- source st age. I t is useful again t o express t he result in t erm s of Veffn and Veffp and t he volt ages across resist ors t o m ake a quant it at ive assessm ent of t he gain. Using g m = 2I D / Veff [ ( 4.5) ] , t he gain expression is

Equ a t ion 1 3 .5

For exam ple, we set VRS3 = 1 V, wit h a new VRD2 = 2.3 V. The gain m agnit ude is now | a v | = 7.67 · 4.35 = 33.3, com pared wit h 116 for t he circuit of Fig. 13.1. Not e t hat t he cont ribut ion from t he different ial st age increases from 4.3 t o 7.7. The out put - resist ance effect on t he gain of t he com m on- source st age is neglect ed [ as in ( 5.15] . This is j ust ified as t he out put resist ance at t he drain of M3 is increased significant ly wit h RS3 . [ Precision gain equat ion ( 8.34) gives 4.21 com pared wit h 4.35 using ( 5.15) ] . This is discussed furt her below in conj unct ion wit h t he com m on- source am plifier wit h source resist or from t he viewpoint of a feedback circuit . I f resist or VRS3 is sufficient ly large, g m 3 RS3 > > 1. I n t his lim it t he gain is

Equ a t ion 1 3 .6

The m agnit ude of gain given by ( 13.6) is about 38, a fair approxim at ion t o t he value of 33 from ( 13.5) . I t is apparent from t he form of ( 13.6) t hat a significant degree of gain st abilizat ion has been achieved, as t he gain depends prim arily only on t he bias current s I D1 = I D2 , which is quit e st able in t he different ial am plifier circuit .

13.3.2 Transistor Parameter Variation and ID3 Bias Stability The benefit t o I D3 bias st abilit y associat ed wit h t ransist or param et er variat ion can be assessed by a considerat ion of ( 5.18) applied t o t his case, which is

For a quant it at ive exam ple, suppose t hat I D3 = 100 µA. To be consist ent wit h t he num bers used in Unit 13.2, k p3 = 1110 µA/ V2 wit h Veffp3 = 0.3 V. Assum e t hat VRD2 = I D2 RD2 is const ant . Now m ake k p3 5% larger and Vt po3 50 m V sm aller. For t he VRD2 = 2.3 V, we have a new I D3 = 105 µA for VD3 = 0.25 V, which is an accept able bias value. For t he circuit of Fig. 13.1, and t he sam e param et er changes, t he new bias current is I D3 = 143 µA for VD3 = 2.15 V, significant ly away from t he design zero volt s.

13.3.3 Bias Stability of ID3 Due to Changes in ID2 The act ual different ial- st age bias current will vary from t he basic design due t o t he variat ion in circuit com ponent s, t ransist or param et ers, and power- supply volt age. Suppose t hat in lieu of t he value of VRD2 = 2.3 V as in t he exam ple above, VRD2 is 5% higher or 2.42 V. Assum e t hat t he t ransist or param et ers of t he com m on- source st age are at t he original design values.

An est im at e of t he new out put volt age ( different from 0V) can be m ade using t he linear relat ion bet ween t he input and out put of t he com m on- source st age, t hat is, t he com m onsource cont ribut ion of ( 13.4) . The " signal" is t he change of volt age across RD2 , which is –0.12 V. ( The gat e volt age v G3 decreases.) The com m on- source gain from ( 13.4) for t he original param et ers associat ed wit h M3 is –4.35. The out put bias volt age is now ( –4.35) ( –0.12V) = 0.5 V ( inst ead of 0 V) . Therefore, t he circuit is reasonably bias st able. The gain of t he unst abilized circuit of Fig. 13.1 is –27, which leads t o an out put volt age, for t he sam e change of volt age across RD2 , of 3.2 V, using t he linear approxim at ion. Not e t hat t he linear approxim at ion is m arginally valid only for such a large value of t he com m on- source input " signal" volt age, as in t his case of no source resist or. ( A dc calculat ion gives a bias out put volt age of 4.8 V.)

13.4 Common-Source Stage as a Series – Series Feedback Circuit The circuit of Fig. 13.2 wit h t he source resist or is t echnically a feedback circuit . I t falls int o t he cat egory of series – series feedback, or t he feedback net work sam ples t he out put current and feeds back a volt age in series ( and t he sam e polarit y, negat ive feedback) wit h t he input t o t he com m on- source st age, t hat is, Vgs3 . The series – series feedback am plifier is referred t o as a t ransconduct ance am plifier. The noninvert ing and invert ing opam p configurat ions are series – shunt ( volt age am plifier) and shunt – shunt ( t ransresist ance am plifier) , respect ively. An addit ional alt ernat ive is shunt – series ( current am plifier) . An exam ple of t his t ype of feedback am plifier is discussed in Unit 13.5. I n Unit 9.9, an expression for t he out put resist ance of t he current source ( drain current ) wit h source degenerat ion was obt ained [ ( 9.9) ] . This is

The perspect ive of t he com m on- source am plifier in a series – series feedback m ode is shown in Fig. 13.3. The circuit configurat ion is for det erm ining t he out put resist ance. A volt age Vo is applied at t he out put t erm inals wit h t he input grounded. I n t his series – series circuit , a feedback volt age, Vf , which is proport ional t o t he current I o , is induced as indicat ed in t he circuit diagram . Wit h t he input grounded, volt age Vf is applied t o t he input t erm inals of t he t ransist or. The loop equat ion at t he out put is t hen

Equ a t ion 1 3 .7

Figu r e 1 3 .3 . Lin e a r cir cu it for de r ivin g t h e ou t pu t r e sist a n ce for t h e se r ie s – se r ie s fe e dba ck cir cu it . Th e fe e dba ck volt a ge is pr opor t ion a l t o t h e ou t pu t cu r r e n t .

By com parison of t he feedback circuit of Fig. 13.3 wit h t he circuit of Fig. 13.2, Vf = I o RS3 . Thus,

Equ a t ion 1 3 .8

This produces ( 9.9) from Ro = Vo / I o and wit h r ds = 1/ g ds. I nt uit ively, t he feedback is such as t o cause a m uch larger current t hrough r ds t han I o , and t herefore a m uch larger Vo is required for a given I o . Dropping t he RS as in t he right - hand side of ( 13.8) renders t he result equivalent t o t he ideal series – series feedback am plifier, as shown in Fig. 13.4. I n t he ideal series – series am plifier, t he sense funct ion has zero resist ance; t hat is, t he out put volt age is direct ly across r ds. Wit h g m / g ds > > 1, t he ideal circuit provides a very good approxim at ion t o t he act ual circuit . For exam ple, wit h Veffn = 0.5 V and λn = 1/ 50 V, t he rat io is 100.

Figu r e 1 3 .4 . An ide a l se r ie s – se r ie s fe e dba ck a m plifie r . V o is a pplie d dir e ct ly a cr oss t h e ou t pu t r e sist a n ce a n d V f is a pplie d t o t he gr ou n de d input .

For bot h feedback am plifier t ypes wit h series as t he second t erm ( series – series and shunt – series) , t he out put resist ance is increased by a fact or ( 1 + T) , where T is t he loop gain, as in t he discussion of t he opam p feedback am plifiers in Unit 11. The loop gain for t he com m onsource circuit of Fig. 13.2 is, by definit ion, T = Vf / Vgs3 . By inspect ion of ( 9.9) we conclude t hat T = g m 3 RS3 . I n t erm s of T, t he out put resist ance is t hen

Equ a t ion 1 3 .9

13.5 Shunt – Series Cascade Amplifier The cascading of t wo com m on- source am plifier st ages will now be explored. This will expand t he discussion on feedback am plifiers t o include t he shunt – series ( current ) am plifier. As shown in Fig. 13.5, t he current I o is sensed, wit h t he feedback net work consist ing of RS2 and Rf , and a fract ion of I o is sum m ed at t he gat e input node along wit h t he input source current . Gat e resist or RG1 provides for an addit ion bias design variable but ot herwise is sim ply com bined wit h t he source resist ance, Rs, in t he am plifier perform ance analysis or design.

Figu r e 1 3 .5 . Sh u n t - se r ie s fe e dba ck a m plifie r . Th is is a cu r r e n t a m plifie r w it h fe e dba ck a m plifie r ga in , A i = I o / I i .

13.5.1 DC Design For t he design, assum e t hat a choice has been m ade for I D1 and I D2 and VG2 = VD1 . The lat t er m ust be such t hat VG2 > VGS1 + VGS2 . Then, for RD1 , use

Equ a t ion 1 3 .1 0

As will be indicat ed below, t he ideal current gain is

Equ a t ion 1 3 .1 1

Use t his, based on t he feedback- am plifier design current gain goal, t o obt ain a relat ion bet ween Rf and RS2 . This gives

Equ a t ion 1 3 .1 2

Now det erm ine t he value of RS2 which st at isfies t he design value of I D2 . This is obt aned from

Equ a t ion 1 3 .1 3

where 13.12 has been used for Rf and where VS2 = VG1 – VGS2 and

Equ a t ion 1 3 .1 4

and

Equ a t ion 1 3 .1 5

Finally, select RG1 t o sat isfy t he VGS1 requirem ent from

Equ a t ion 1 3 .1 6

13.5.2 DC Stability The feedback net work provides significant bias st abilizat ion and t he effect can be assessed by t he sam e form ulat ion as for t he opam p. I n Unit 11.4, it was shown t hat t he out put volt age for a given offset volt age is [ ( 11.16) ]

As applied t o our shunt – series circuit ( by equivalency) , AVNI = 1 + Rf / RG1 , and a vo is t he volt age- gain m agnit ude ( m inus t erm inal equivalent ) from t he gat e, Vg1 , t o t he source Vs2 , t hat is, t he gain of t he case of a com m on- source st age ( M1 ) and a source- follower st age ( M2 ) . Also, for t his case, ∆Vo ∆VS2 . Not e t hat for t his case, ∆Vo is a bias- volt age change, whereas for t he opam p, it is t he out put volt age ( different from zero volt s) . Suppose t hat t he dc ( bias) is at a set st at e. Then t he bias is alt ered such as by a change of a t ransit or param et er ( eit her by t em perat ure change or subst it ut ing one t ransist or for a new one) . For exam ple, a change in Vt no of M1 is equivalent t o inst alling an offset volt age, and [ ( 11.16) ] can be applied direct ly t o t his case. Make RG1 = Rf for AVNI = 2. Also assum e a t ypical a vo = 40 ( com m on- source st age) . For a change of δVt no –Voff = –0.1 V, ∆VO 2 · 0.1 V = 0.2 V. Not e t hat based on a vo = 40, wit h no feedback st abilzat ion, t he change in out put would be approxim at ely a vo δVt no = 4 V.

13.5.3 Signal Current Gain We first com put e t he open- loop t ransconduct ance and t hen t he open- loop current gain. This is done, for a good approxim at ion, by disconnect ing t he right side of Rf from t he souce of M2 and connect ing it t o ground. ( This disables t he shunt – series feedback and ot herwise alt ers t he circuit only slight ly.) The result is

Equ a t ion 1 3 .1 7

where Ri = Rs| | RG1 | | Rf . ( This assum es t hat Rf > > RS2 which is consist ent wit h AiI > > 1.) Transconduct ance Gm is for t he com plet e cascade circuit ( open loop) , t hat is,

Equ a t ion 1 3 .1 8

Not e t hat t he series – series feedback effect is ret ained in t he open- loop com put at ion and t hat RS2 has been used as an approxim at ion for RS2 | | Rf . This once again assum es t hat Rf > > RS2 . The loop gain is

Equ a t ion 1 3 .1 9

Following t he discussion in Unit 11, which led t o ( 11.3) , t he current gain wit h feedback is t hen

Equ a t ion 1 3 .2 0

where ( ideal current gain of t he feedback am plifier)

Equ a t ion 1 3 .2 1

As a design exam ple, suppose t he design goal is AiI = 10. Assum e t hat t he t ransist ors have Vt no = 1 V, k n1 = 1000 µA/ V2 , and k n2 = 2000 µA/ V2 . We select I D1 = 100 µA, I D2 = 200 µA, VDD = 10 V, and VG2 = 3.5 V. From ( 13.12) and ( 13.13) we obt ain RS2 = 11.4 kΩ and Rf = 103 kΩ. Based on ( 13.16) , t he value of RG1 is RG1 = 156 kΩ. To sat isfy t he drain volt age requirem ent s, RD1 = 65 kΩ and RD2 = 25 kΩ. The lat t er is based on VD2 = VDD/ 2. Also, we assum e t hat Rs = 100 kΩ.

The open- loop t ransconduct ance is Gm = 3372 µA/ V and Ri = 38 kΩ for a i = 129. Loop gain T = 12.9 such t hat Ai = 9.28. We not e t hat since Ai AiI = 10, t he current gain is very predict able, despit e bias and param et er variat ions.

13.6 Summary of Equations Gain of cascade of different ial st age and com m on- source st age, including out put resist ance of M3 . Gain of cascade circuit for case of com m onsource st age wit h source resist or.

,

Approxim at e form for gain which assum es t hat g m 3 RS3 > > 1.

Bias equat ion for t ransist or M3 .

Shunt – series am plifier dc design equat ions.

Shunt – series am plifier dc st abilit y relat ion.

Shunt – series am plifier open- loop current gain relat ions.

Feedback am plifier current - gain relat ions.

Unit 14. Development of a Basic CMOS Operational Amplifier I n t his unit , we st art wit h t he basic com ponent s of am plifiers t hat have been discussed and progress, st epwise, t oward an act ual int egrat ed- circuit operat ional am plifier. The final am plifier consist s of t wo gain st ages and a buffer st age. The gain st ages are t he equivalent of t he cascade of a different ial st age and a com m on- source st age of Unit 13, except wit h im provem ent s consist ing of current - source bias in place of bias resist ors.

14.1 Current-Source Bias for the Differential Amplifier Stage The drain- current bias resist or, Rbias, of t he basic different ial am plifier st age as int roduced in Fig. 8.1 will now be replaced by a current source as shown in t he circuit of Fig. 14.1. The bias resist or is replaced by t wo t ransist ors, M10 and M11 , and one resist or, R1 . This seem s like an unfavorable exchange but it is not . This is because t he reference volt age VGS10 form ed by t he reference circuit of R1 and M10 can be used for addit ional current sources in t he com plet e circuit , t hereby elim inat ing t he need for a num ber of ot her bias resist ors.

Figu r e 1 4 .1 . D iffe r e n t ia l a m plifie r st a ge w it h bia s r e sist or , R bia s ( Fig. 1 3 .1 ) , r e pla ce d w it h a cu r r e n t sou r ce . Bia s cir cu it con sist s of R 1 , M 1 0 , and M11.

Resist ors in an int egrat ed circuit cost m uch m ore in chip space t han do t ransist ors. Also, t he out put resist ance of a current - source t ransist or, M11 , will be m uch higher t han t he resist or equivalent , leading t o im proved am plifier charact erist ics, as discussed below. Following t he discussion of t ransist or current sources in Unit 9, t he rat io of t he reference current and t he current - source current is

Equ a t ion 1 4 .1

The rat io of t he gat e widt hs will t hus be select ed t o sat isfy t he design of t he different ial- st age bias. The current rat io will deviat e from t he sim ple rat io due t o t he λn t erm s, but t his is not crit ical, as t he design will not call for an exact value for I D1 I D2 .

14.2 Current-Source Output Resistance and CommonMode Gain As discussed in Unit 8, t he com m on- m ode gain is t he gain for t he sam e signal being applied t o bot h input s. I n Unit 8.6 t he com m on- m ode volt age gain expression, ( 8.26) , was obt ained for t he bias resist or, Rbias. This is

To apply t he com m on- m ode gain equat ion t o t he circuit of Fig. 14.1, resist or Rbias is replaced by r ds11 . The result for t he com m on- m ode gain is

Equ a t ion 1 4 .2

The approxim at e form is consist ent wit h neglect ing t he change of t he gat e – source volt age com pared t o t he change of volt age at t he drain of t he current - source t ransist or, M11 . , t ransist or M11 , is a pure current source, and i D1 I nt uit ively, ( 14.2) indicat es t hat for r ds11 = i D2 = I D1 = I D2 regardless of t he m agnit ude of com m on volt age applied t o bot h gat es. I n t his case, signals I d1 = I d2 = 0 for any ( realist ic) com m on- m ode input signal. Com m on- m ode input s can be a form of noise, and t herefore t he ideal opam p would rej ect t hese signals ent irely. An im port ant considerat ion is t he ext ent of rej ect ion based on t he com m on- m ode gain relat ive t o t he different ial am plifier gain. This is quant it at ively assessed wit h t he com m on- m ode rej ect ion rat io, which is t he rat io of t he different ial am plifier gain wit h different ial out put divided by t he com m on- m ode gain, ( 14.2) . The gain for t his case was obt ained in Unit 8.5 as ( 8.24) , which is a vd12 = –g m RD . Using ( 8.24) and ( 14.2) , t he com m on- m ode rej ect ion rat io is

Equ a t ion 1 4 .3

Wit h g m 1 = 2I D1 / Veffn1 [ ( 4.5) ] , and for t he out put resist ance of M11 , r ds11 t he com m on- m ode rej ect ion rat io is

Equ a t ion 1 4 .4

By com parison, for resist or bias, t he equivalent result is

Equ a t ion 1 4 .5

1/ λn 2I D1 [ ( 4.15) ] ,

where Rbias is t he bias resist or of, for exam ple, t he circuit s of Figs. 13.1 and 13.2.

14.3 Current-Source Load for the Common-Source Stage We now add t o t he different ial st age t he com m on- source st age t o obt ain a t wo- st age am plifier as in Unit 13 ( Fig. 14.2) . Transist or M12 , which replaces bias resist or RD3 , provides a current source load as in t he circuit of Fig. 10.1. Not e t hat current I D12 m irrors I D10 and no addit ional resist ors are required wit h t he addit ion of t he com m on- source st age. That is, M11 and M12 bot h use t he reference volt age provided by t he diode- connect ed M10 .

Figu r e 1 4 .2 . Ca sca de of t h e diffe r e n t ia l a m plifie r st a ge a n d com m on sou r ce st a ge . M 1 2 pr ovide s a cu r r e n t - sou r ce loa d for t h e com m on sou r ce st a ge . Th is cir cu it r e m a in s in a de qu a t e in t e r m s of dc bia s st a bilit y of I D 3 . This is im pr ove d in t h e m odifica t ion t ha t follow s.

The bias design for t he com m on- source st age consist s of picking W 12 t o obt ain a specified I D12 relat ive t o I D10 and m aking I D3 = I D12 . Param et er W 12 is det erm ined from

Equ a t ion 1 4 .6

The approxim at ion is sufficient , as t he current m agnit ude, again, is not crit ical. The circuit is adj ust ed t o m ake I D3 = I D12 by equat ing t he relat ions for t he t wo current s. This is

Equ a t ion 1 4 .7

A m uch sim pler equat ion replaces t his rat her com plicat ed one when RD2 is finally replaced by a t ransist or as well. Veff12 is known from Veff12 = Veff10 . Thus, t he current balance can be obt ained by a select ion of t he various rem aining param et ers. The load on t he com m on- source st age is now r ds12 = 1/ g ds12 . The gain is, including t he out put resist ance of M3 .

Equ a t ion 1 4 .8

The overall am plifier gain, a v = Vo / Vi , is now

Equ a t ion 1 4 .9

This can be evaluat ed wit h

Equ a t ion 1 4 .1 0

Using t he num bers from t he previous calculat ion for t he am plifier of Fig. 13.1 wit h RD3 , and adding λn = λp , t he gain m agnit ude for t he circuit of Fig. 14.2 is 289. This com pares wit h t he value of 116 for t he cascade am plifier of Fig. 13.1. I n t he next unit , t he different ial st age will be m odified t o include a current source load wit h a considerable addit ional im provem ent in gain.

14.4 Current-Source Load for the Differential Stage The load resist or ( or bias resist or) of t he different ial st age will now be replaced wit h a current source load. I n addit ion t o elim inat ing t he need again for a resist or, it provides for m uch bet t er dc st abilit y and a significant gain im provem ent , including t he elim inat ion of t he fact or of ½ associat ed wit h t he different ial st age gain as in ( 8.15) and ( 8.17) . As shown in t he new circuit in Fig. 14.3, t he resist or RD2 is replaced by t ransist ors M4 and M5 . Transist or M5 provides a current - source load for t ransist or M2 . The diode- connect ed t ransist or, M4 , provides t he dc reference volt age for M5 . The reference current is I D1 = I D4 .

Figu r e 1 4 .3 . D iffe r e n t ia l a m plifie r st a ge w it h cu r r e n t - sou r ce loa d.

The dc out put volt age ( of t he different ial st age) is set aut om at ically at VDD – VSG4 due t o t he relat ion VSD4 = VSG4 = VSG5 = VSD5 . This is an idealizat ion t hat assum es t hat t he param et ers of t ransist ors M4 and M5 and M1 and M2 are ident ical and t hat I D1 = I D2 . Recall t hat in t he different ial st age wit h drain resist or, RD2 , t he noninvert ing out put signal volt age was induced across RD2 due t o t he signal current I d2 . I n t he new circuit , t he out put current is t he com posit e of signal current s I d2 and I d5 . That is, signal current I d1 is m irrored at t he out put as I d5 . This is a result of t he coupling from M1 t hrough M4 t o t he gat e of M5 . The circuit from t he gat e of M1 t o t he drain of M5 can be regarded as a cascade of t wo com m onsource st ages ( M1 and M5 ) wit h a shunt resist or bet ween t hem of m agnit ude 1/ g m 4 ( t he signal resist ance of t he diode- connect ed t ransist or) . The gain for t his circuit can be explained st art ing from t he t ransconduct ance for t he t wo current s I d2 and I d5 . Assum e for a m om ent t hat t he out put volt age is held const ant at t he dc bias value. This is equivalent t o a signal short circuit at t he out put . As in t he case of t he resist or- bias different ial am plifier st age, we have

Equ a t ion 1 4 .1 1

where t he effect of t he out put resist ance of M11 is neglect ed. But also, as in t he resist or- load case,

Equ a t ion 1 4 .1 2

But I d1 = –I d4 and I d4 is m irrored as I d5 , which leads t o I d5 = –I d1 . This assum es t hat M4 and M5 are ident ical. Thus,

Equ a t ion 1 4 .1 3

All signal drain current s are defined as posit ive int o t he respect ive drains. The out put current s sum m ed at t he out put node, Vo , are ( defined posit ive int o t he node)

Equ a t ion 1 4 .1 4

The result is valid for v O = VO or Vo = 0, as st ipulat ed above. One could im agine at t aching a dc supply exact ly equal t o VO at t he out put node. I n t his case, t he out put current could readily flow int o t he node according t o ( 14.14) . For t he opposit e ext rem e of having an open circuit at t he out put , as in Fig. 14.3, t he current s I d2 and I d5 are dependent on v D2 = v D5 = v O. The deviat ion of I o from ( 14.14) is, as usual, t aken care of by including t he effect of t he out put resist ance at t he out put node. The out put resist ance is som ewhat com plicat ed by feedback effect s, which are inherent in t his circuit . For assessing t he circuit out put resist ance, a signal circuit is shown in Fig. 14.4 wit h a t est volt age, Vo , applied at t he out put wit h bot h input s grounded. Result ing current s I d2 and I d5 will be considered separat ely and will be superim posed.

Figu r e 1 4 .4 . Sign a l ( line a r ) cir cu it for de t e r m ining t h e ou t pu t r e sist a n ce a t t h e dr a in s of M 2 a n d M 5 . Cu r r e n t s sh ow n a r e a ssocia t e d w it h t h e a sse ssm e n t of t h e out pu t r e sist a n ce a ssocia t e d w it h M 2 only. Th e bia s t r a n sist or ( M 1 1 ) ou t pu t r e sist a n ce is n e gle ct e d.

The current s indicat ed in Fig. 14.4 are for t he case of I d2 of M2 . Looking back int o t he drain of M2 , t he out put resist ance is affect ed by em it t er degenerat ion because of t he resist ance 1/ g m 1 bet ween t he em it t er of M2 and ground. That is, t he resist ance looking back int o t he em it t er of M1 is 1/ g m 1 . Thus, t he resist ance looking only back int o M2 is 2r ds2 . However, I d2 feeds t hrough and around t he loop com posed of M2 , M1 , M4 , and M5 such t hat t he t ot al current flowing int o

t he node ( exclusive of t he separat e I d5 cont ribut ion) is 2I d2 . The t est volt age is Vo = I d2 2r ds2 , due t o current I d2 flowing down int o t he resist ance 2r ds2 of t he drain of M2 . The out put resist ance associat ed wit h t he drain of M2 , RoM2 , is based on a t ot al current of 2I d2 such t hat it is

Equ a t ion 1 4 .1 5

The drain resist ance 2r ds2 com bined wit h a t est current of 2I d2 result s in an effect ive drain resist ance r ds2 despit e t he em it t er degenerat ion. Separat ely, by superposit ion, for applied Vo , a current I d5 of value I d5 = Vo / r ds5 flows int o t he drain of M5 such t hat t he out put resist ance associat ed wit h M5 is RoM5 = r ds5 = 1/ g ds5 . This is based on t he fact t hat t he out put resist ance is t hat of a com m on- source st age wit h grounded source. The t wo cont ribut ions are in parallel such t hat finally, t he out put resist ance is

Equ a t ion 1 4 .1 6

Com bining t his wit h t he effect ive am plifier t ransconduct ance obt ained above, ( 14.14) , t he gain is

Equ a t ion 1 4 .1 7

or

Equ a t ion 1 4 .1 8

An ext ernal load, RL, appears in parallel wit h Ro . Hence wit h an ext ernal load, t he gain is

Equ a t ion 1 4 .1 9

I n t he discussion leading t o ( 14.14) , it was not ed t hat t he out put current given by ( 14.14) is for a short - circuit condit ion at t he out put , and t he effect of finit e Vd2 = Vd5 is t aken care of t hrough t he concept of t he out put resist ance of t he circuit . A clarificat ion of t his st at em ent is provided by t he analyt ical form ulat ion, which includes a load, RL, given by

Equ a t ion 1 4 .2 0

where v D5 = v D2 , as t hey are t he sam e node. The linear form is

Equ a t ion 1 4 .2 1

and t his leads t o ( 14.19) , where, again, av2 = Vd2 / Vg1 . A volt age source at t ached t o t he out put is equivalent t o RL 0, in which case Vd2 0 and v D2 VD2 = VO, t hat is, t he bias value. The finit e out put current m agnit ude int o t he short circuit is consist ent wit h Vd2 / RL| vds, RL 0 = g m 1 Vg1 .

14.4.1 Common-Mode Gain of the Differential Stage with Current-Source Load As m ay be deduced from t he com m on- m ode gain equat ion, ( 14.2) , in Unit 14.2, t he com m onm ode t ransconduct ance for t he different ial st age wit h current - source biasing is Gm = g m 1 / ( 1 + g m 1 2r DS11 ) . The increm ent al load at t he drain of M1 for t he case of t he circuit shown in Fig. 14.3, however, is t he resist ance of t he diode- connect ed t ransist or M4 of Fig. 14.3, which is 1/ g m 4 . Due t o sym m et ry, t his is also t he effect ive load at t he drain of M2 . The com m on- m ode gain is t hus

Equ a t ion 1 4 .2 2

and t he com m on- m ode rej ect ion rat io is, from ( 4.17) ( for single- ended out put ) and ( 14.22) ,

Equ a t ion 1 4 .2 3

This is great er t han ( 14.3) by t he fact or g m 4 / ( g ds2 + g ds5 )

[ Veff4 ( λn + λp ) ] –1 .

14.5 Two-Stage Amplifier with Current-Source Biasing The cascade am plifier t hat includes all feat ures discussed up t o t his point is given in Fig. 14.5. Not e t hat t he only ( int ernal) resist or is t hat of t he reference- current circuit . Bias current s for t his circuit can be set up using gat e- widt h proport ions. We not e t hat I D3 I D5 since M3 and M5 have a com m on bias volt age, VSG4 . Thus

Equ a t ion 1 4 .2 4

Figu r e 1 4 .5 . Tw o- st a ge a m plifie r w it h cu r r e n t - sou r ce bia sin g. R 1 is t he on ly r e sist or in t h e in t e r n a l cir cu it . R G is e x t e r n a lly con n e ct e d.

Also, M11 and M12 are referred t o t he sam e reference volt age such t hat

Equ a t ion 1 4 .2 5

Using I D3 = I D12 and I D11 = 2I D5 , we obt ain

Equ a t ion 1 4 .2 6

Com bining ( 14.24) and ( 14.26) leads t o

Equ a t ion 1 4 .2 7

Assum e t hat W 11 has been picked t o sat isfy t he design I D11 . W 12 is t hen select ed t o give t he design I D12 using I D12 / I D10 = W 12 / W 10 . W 5 is select ed on t he basis of signal considerat ions. This leaves t he com put at ion of W 3 [ from ( 14.27) ] . A precision calculat ion includes t he lam bda effect s and is from

Equ a t ion 1 4 .2 8

The sim ple form should norm ally suffice. The dc out put volt age VO is very sensit ive t o som e of t he param et ers and t he approxim at e calculat ion from ( 14.27) will not result in VO = 0. However, uncert aint ies in t ransist or param et ers preclude t he j ust ificat ion of using ( 14.28) in pract ice. The overall signal gain is now obt ainable using ( 14.17) for t he different ial st age and ( 14.8) for t he com m on- source st age wit h a current - source load. The result is

Equ a t ion 1 4 .2 9

A useful form for m aking a quant it at ive gain assessm ent is

Equ a t ion 1 4 .3 0

Based on t he sam e param et ers as used previously for gain calculat ions ( λn = λp = 1/ 20 V and Veffn = Veffp = 0.3 V) , t he gain m agnit ude is 4440. The value com pares wit h 116 for t he allresist or circuit for Fig. 13.1 and 289 for t he circuit of Fig. 14.3. I n t his special case, bot h st ages cont ribut e t he sam e value.

14.6 Output Buffer Stage I t is evident from t he gain result , ( 14.29) , t hat t he high gain depends on having a high resist ance at t he out put ; a relat ively sm all load resist or can reduce t he gain subst ant ially. For exam ple, suppose t hat t he am plifier is t o be used as a resist ance feedback am plifier as shown in Fig. 14.6. The input is at t he gat e of M2 , and t he feedback resist or is connect ed back t o t he gat e of M1 . The load at t he out put is Rf + R2 | | RO.

Figu r e 1 4 .6 . Opa m p w it h fe e dba ck r e sist or R f . Th e fe e dba ck cir cu it a dds loa d R f + R 2 in pa r a lle l w it h e x t e r n a l loa d, R O , a t t he ou t pu t .

For a specific exam ple, assum e t hat RO > > Rf > > R2 such t hat t he load is approxim at ely Rf . Wit h t he addit ional load, t he gain ( 14.30) becom es

Equ a t ion 1 4 .3 1

which is t he result of Rf being in parallel wit h t he out put resist ance of t he com m on- source st age. Suppose t hat Rf = 10 kΩ and I D3 = 100 µA. I n t his case t he gain would drop t o about 400 ( from about 4400) , which would be unaccept able, as proper operat ion of opam ps assum es a very high gain. This loading problem is subst ant ially elim inat ed wit h t he addit ion of a buffer st age t o isolat e t he load from t he out put node of t he com m on- source st age, as shown in t he circuit of Fig. 14.7. The source- follower buffer st age is m ade up of M6 and M13 . The current - source bias t ransist or M13 also uses t he reference volt age provided by M10 . The load on t he com m onsource st age of M3 is now infinit e. The feedback net work is included in t he circuit for com paring wit h t he diagram m at ic version of t he circuit of Fig. 14.6.

Figu r e 1 4 .7 . Thr e e - st a ge a m plifie r w it h t h e a ddit ion of t he sou r ce follow e r ( bu ffe r ) st a ge .

The gain expression of t he source follower requires t hat t he body effect be t aken int o considerat ion, as t he body of M6 will be at signal ground. [ The body of M6 will be at t ached t o t he negat ive supply volt age ( not shown) .] From Unit 7 it was shown t hat t he source- follower st age gain, wit h resist or bias [ ( 7.12) ] for t his case is

For t he present case of current - source bias for t he source- follower st age, t he gain expression becom es, wit h inclusion now of t he feedback net work and t he ext ernal load resist ance of Fig. 14.7,

Equ a t ion 1 4 .3 2

To obt ain a quant it at ive sense of t he body effect on t he gain of t he source follower, suppose , a vsf = 0.87. This is t he best possible result , t hat η = 0.15. Thus, in t he lim it for g m 6 given t he body effect . For a m ore general assessm ent , we can subst it ut e t he relat ions g m = 2I D / Veff , [ ( 4.5) ] , and g ds = I D λn [ ( 14.15) ] int o ( 14.32) t o obt ain

Equ a t ion 1 4 .3 3

We not e t hat t he t erm s associat ed wit h g ds6 and g ds13 are negligible. Minim izat ion of t he resist ance t erm requires m aking g m 6 [ ( Rf + R2 ) | | RO] > > 1 ( m aking t he out put resist ance of t he source follower m uch less t han t he load resist ance) . This involves a com binat ion of a large I D6 and k n6 .

Suppose t hat I D6 = 400 µA, W 6 = 500 µm , KPn = 100 µA/ V2 , and t hat t he gat e lengt h is L = 10 µm . Recalling t hat k n = ( KPn / 2) ( W/ L) ( Table 3.1) , we obt ain k n = 2500 µA/ V2 and 1/ g m 6 = 500 Ω. Thus, for exam ple, for RO = 10 kΩ, Rf = 10 kΩ, and Rf > > RG, a vsf = 0.80, com pared wit h t he lim it ing value of a vsf = 0.87. Thus t he source follower funct ions very well t o isolat e t he load from t he high- gain com m on- source st age. Finally, we writ e t he overall gain expression, including a general load resist ance, RL, by com bining ( 14.29) and ( 14.32) as

Equ a t ion 1 4 .3 4

A good approxim at ion for t he case of a sufficient ly large g m 6 is

Equ a t ion 1 4 .3 5

14.7 Output Resistance of the Feedback Amplifier and Effect on Gain from Loading The out put resist ance of t he resist ance feedback am plifier was considered in Unit 11.4. There it was shown t o be Ro = r o / ( 1 + T) [ ( 11.12) ] , where r o is t he out put resist ance of t he open- loop am plifier and T is t he loop gain of t he feedback am plifier. Therefore, wit h t he expect at ion t hat T > > 1, t he out put resist ance of t he feedback am plifier is very sm all. For exam ple, consider t he am plifier of Fig. 14.7, wit h no ext ernal load on t he out put and neglect ing t he effect of t he feedback resist ors. The open- loop out put resist ance is

Equ a t ion 1 4 .3 6

The out put resist ance of t he feedback am plifier is

Equ a t ion 1 4 .3 7

where t he loop gain is T = a vo RG/ ( RG + Rf ) . Suppose t hat in order t o get a high gain from t he am plifier, we redesign t he MOSFETs t o have λp = λn = 0.01 V–1 for a new a v = 96,000 [ from ( 14.35) , no loading] . Also, let Rf = 10 kΩ and RG = 100 Ω. Using t he sam e num bers as in t he calculat ion of a sam ple source- follower st age gain [ ( 14.33) ] , r o = 435 Ω and Ro = 0.45 Ω. The gain of t he feedback am plifier is ( 11.3) , which is

wit h ( 11.4)

Here, gain Av is for t he case of no ext ernal load ( including t he om ission of t he load from t he feedback resist ors) . The value is Av = 100.9 for AvNI = 101.

Now we include an ext ernal load of RO = 100 Ω and com bine t his in parallel wit h Rf = 10 kΩ for load RL = 99 Ω. The loading effect reduces t he open- loop gain t o av = 18,000. The reduct ion is all at t ribut ed t o t he loading on t he source- follower st age. The am plifier gain [ from ( 11.3) ] is now AvLoad = 100.4. However, wit h Ro known, an alt ernat ive m eans of obt aining t he gain wit h loading is t o use

Equ a t ion 1 4 .3 8

Av and Ro are calculat ed once, using ( 14.35) and ( 14.37) , respect ively. Thus, t he effect of loading can be obt ained wit h one calculat ion using ( 14.38) . As in t he sam ple calculat ion above for t he am plifier gain wit h loading included, AvLoad = 100.4.

14.8 Output Circuit of the TS271 Opamp The TS271 operat ional am plifier is designed t o operat e at very low current levels. This would include t he current of t he source follower of t he out put st age. I n t his case, t he out put resist ance of an am plifier wit h a sim ple source- follower st age for an out put st age, such as in Fig. 14.7, would be unaccept ably high. I n t he TS271 operat ional am plifier, t he 9- t ransist or circuit of Fig. 14.8 replaces t he sim ple source- follower st age consist ing of M6 and M13 of Fig. 14.7. Not e t hat t he circuit of Fig. 14.8 uses different t ransist or designat ors. I n Fig. 14.7, M6 and M13 are equivalent t o M1 and Mn1 of Fig. 14.8.

Figu r e 1 4 .8 . Th e ou t pu t st a ge of t h e TS2 7 1 opa m p. Th e n e w sou r ce follow e r con sist in g of M 1 a n d M n 1 is e qu iva le n t t o t he st a ge of M 6 a n d M 1 3 of t h e a m plifie r of Fig. 1 4 .7 .

The circuit of Fig. 14.8 has an addit ional source- follower st age consist ing of M2 and Mn2 . The out put from t he com m on- source st age ( drain of M3 of Fig. 14.7) is applied t o t he gat es of bot h source- follower st ages. The sources ( out put s) of M1 and M2 are connect ed t o t he input s of t he different ial- st age gat es of M3 and M4 , respect ively. There is no load at t he source of M1 such t hat t he gain of t he source follower can be considered unit y. Thus, Vg3 Vg2 = Vg1 ( increm ent al volt ages) . By cont rast , t he source of M2 is connect ed t o RL such t hat , in general, Vo = Vs2 < Vg2 . From anot her perspect ive, suppose Vg2 = 1V, t hat is t he source- follower gat es are raised by 1V above t he bias level. Wit h a load, RL, t he current increase will be great er for M2 com pared t o M1 . This will cause t he source volt age of M2 t o be slight ly lower ( t han t hat of M1 ) such t hat t he input t o t he different ial am plifier is nonzero and t he out put volt age ( drain of M3 ) will drop. The result is a reduct ion of t he gat e volt age of Mn2 and t hus a reduct ion of t he drain current in Mn2 . The increm ent al drain current of Mn2 provides m ost of t he current t hrough t he load; t he load current is dom inat ed by t he change in t he current of Mn2 inst ead of M2 . Fig. 14.9 is a reasonable equivalent , increm ent al, circuit . The different ial st age ( M3 , m inus, M4 , plus, and t he drain of M3 as t he out put ) is represent ed by an opam p sym bol.

Figu r e 1 4 .9 . Equ iva le n t cir cu it of t h e ou t pu t st a ge of Fig. 1 4 .8 . Th e opa m p sym bol r e pr e se n t s t h e diffe r e n t ia l- a m plifie r st a ge of M 3 a n d M 4 .

Since t he source follower of M1 has a t ransfer funct ion of nearly unit y, increm ent al Vg2 ( = Vg1 ) is m oved direct ly t o gat e of M3 ( m inus input of t he different ial am plifier) as in Fig. 14.9. Thus

Equ a t ion 1 4 .3 9

where a vda is t he gain of t he opam p and t he out put of t he opam p is Vgsn2 . The am plifier ( out put st age) out put volt age is t herefore

Equ a t ion 1 4 .4 0

where we now assum e t hat g m 2 = g m n2 . I t follows t hat t he relat ion bet ween Vgs2 and Vo is

Equ a t ion 1 4 .4 1

Com bining t his wit h

Equ a t ion 1 4 .4 2

gives t he t ransfer funct ion, input t o out put , as

Equ a t ion 1 4 .4 3

where

Equ a t ion 1 4 .4 4

The out put resist ance of t he circuit of Fig. 14.8 is 1/ Gm . The out put resist ance of t he circuit of Fig. 14.8 is t hus reduced by a fact or of about 1/ avda com pared t o t he circuit of Fig. 14.7 for t he sam e g m of t he source follower t ransist ors. From ( 14.18) , t he gain of t he different ial- am plifier st age is

This would t ypically be on t he order of 100. Thus a significant benefit over t he sim ple sourcefollower st age out put is realized wit h t he circuit of Fig. 14.8. I t is also significant t hat t here is no body effect associat ed wit h Mn2 .

14.9 Summary of Equations Bias equat ion for different ial am plifier st age.

Different ial- st age com m on- m ode gain equat ion for case of drain bias resist or, RD2 . CMRR = 1 + g m 1 2r ds11

Com m on- m ode rej ect ion rat io for case of drain bias resist or, RD2 . Bias equat ion for com m on- source st age.

Com m on- source st age gain wit h current - source load. Am plifier gain for case of different ial- st age drain bias resist or, RD2 , and com m on- source st age gain wit h current - source load. Out put resist ance of different ial st age wit h current source load. Different ial- st age gain wit h current - source load and ext ernal load resist or, RL.

Relat ion t o det erm ine M3 gat e widt h, W 3 .

Precision relat ion t o det erm ine M3 gat e widt h, RD2 .

Gain for t wo- st age am plifier, bot h st ages wit h current - source loads. Gain of t he source- follower st age for t he case of load Rf + RG | | RO ( feedback resist ors and ext ernal load, Ro ) . Out put resist ance of source- follower st age.

Out put resist ance of resist ance feedback am plifier

Bias equat ion for different ial am plifier st age.

TS271 out put resist ance, where g m 2 is for t he source- follower st age and a vda is t he gain of t he different ial am plifier st age.

Unit A. Communicating with the Circuit Board: LabVIEW Programming and Measurement Exercises Com m unicat ing bet ween t he com put er and a circuit board ( sending and receiving volt ages from t he com put er) is accom plished wit h t he dat a acquisit ion card ( DAQ) . The DAQ is norm ally connect ed from t he com put er t o t he circuit board wit h a 68- pin cable. I n general, all 68 pins are used for such t hings as analog input s and out put s, t riggering, digit al input s and out put s, a 5- V dc supply, and count ers. I n our proj ect s, we use, for t he m ost part , only analog input s and out put s. A digit al out put could also be used if we required an addit ional out put , which of course is lim it ed t o on or off. Since t he analog input s and out put s involve digit al- t o- analog and analog- t o- digit al conversions, special considerat ion m ust be given t o t he discret e nat ure of t he conversion relat ions. These are discussed in t he following along wit h a series of basic program m ing and m easurem ent exercises. A sequence of VI s ( virt ual inst rum ent s) is program m ed. I n Unit A.2 and beyond, preprogram m ed VI s are used. The LabVI EW library, Proj ect A.llb, of Proj ect A cont ains t he preprogram m ed VI s, along wit h sam ples of all of t he VI s in t he exercises. Proj ect A com plem ent s t his unit . I t is recom m ended t hat t he part s of Proj ect A be com plet ed at t he end of a given program m ing segm ent in t he unit . The appropriat e proj ect part is flagged as wit h t he following: Pr oj e ct PA.x ( Tit le of Proj ect Segm ent )

A.1 Basics of Sending and Receiving Circuit Voltages The following is based on a Nat ional I nst rum ent s PCI - MI O- 16E- 4 DAQ card ( or equivalent ) . The sam ple rat e is not crit ical. The DAQ card has eight different ial analog input channels and t wo analog out put channels. We generally use only channels 0, 1, and 2 for receiving in our proj ect s. LabVI EW provides som e preprogram m ed VI s for readily sending volt ages t o t he circuit board and sam pling a signal for reading int o a LabVI EW program . The m ost im port ant of t hese for analog circuit m easurem ent s are AI Acqu ir e W a ve for m .vi and AO Upda t e Cha nn e l.vi. Som e m easurem ent s will be m ade next using t hese t wo VI s. As t he nam e suggest s, t he VI , AI Acqu ir e W a ve for m .vi sam ples t he st ipulat ed volt age a num ber of specified t im es. For dc m easurem ent s, t he sam ples are sim ply averaged. This provides for a m ore precision m easurem ent t han from a single sam ple. LabVI EW has a singlepoint DAQ funct ion, AI Sa m ple Ch a n ne l.vi. This funct ion does not t ake advant age of com put er- based dat a acquisit ion.

A.1.1 Programming Exercise: Installing, Sending, and Receiving VIs in the Program Open a new VI in LabVI EW and save it wit h a personal nam e. Here t he VI is referred t o as M e a su r e .vi. The VI has a Front Panel and a Diagram . The Diagram is shown in Fig. A.1. Moving from t he Diagram t o t he Front Panel or t he opposit e can be perform ed under m enu Window> > Show Diagram ( or Ct rl/ E) and Window> > Show Panel ( or Ct rl/ E) . The input s and out put s, including graphics, appear in t he Front Panel and t he program is set up in t he Diagram . For program m ing, t hree palet t es are used: Tools Palet t e, Cont rols Palet t e, and Funct ions Palet t e. The m et hods for get t ing t hese palet t es are out lined in Table A.1.

Figu r e A.1 . La bVI EW D ia gr a m w it h icon for AI Acqu ir e W a ve for m .vi. To pla ce t h e icon in t h e D ia gr a m , Righ t Click on t h e D ia gr a m t o ge t Fu n ct ions. Click t h e st ick pin . Th e n follow t h r ou gh t he se qu e n ce :> > D a t a Acqu isit ion > > An a log I npu t > > AI Acqu ir e W a ve for m .vi. Go t o Opt ion s in t he Fu n ct ions Tool Ba r t o Cha n ge Pa le t t e Se t if de sir e d.

Place AI Acqu ir e W a ve for m .vi in t he Diagram of M e a su r e .vi. I t is locat ed in t he Funct ions Palet t e and under Dat a Acquisit ion> > Analog I nput ( Fig. A.1) . Not e t hat t he Funct ions Palet t e has various Opt ions, t hat is, m ore or less feat ures. To get t he version shown in Fig. A.1 ( if is not already in t his form ) , go t hrough Opt ions in t he Funct ions Tool Bar ( Fig. A.1) . TABLE A.1 Diagram Tools Palet t e Funct ions Palet t e Or Menu Sequence: Shift / Right Click Right Click – St ickpin t o hold Window> > Show Funct ions Palet t e

Front Panel Tools Palet t e Cont rols Palet t e Or Menu Sequence: Shift / Right Click Right Click – St ickpin t o hold Window> > Show Cont rols Palet t e When inst alled, AI Acqu ir e W a ve for m .vi appears as in Fig. A.1. Now Double Click on t he icon ( or Right Click and Open Front Panel) t o bring up t he Front Panel of AI Acquir e W a ve for m .vi. I t will appear sim ilar t o t he exam ple shown in Fig. A.2, which has som e cosm et ic changes.

Figu r e A.2 . Fr on t Pa n e l of La bVI EW VI AI Acqu ir e W a ve for m .vi. D igit a l Con t r ols pr ovide for va r ious inpu t s in clu din g t he n u m be r of sa m ple s t o be t a k e n , in t his e x a m ple , 1 0 0 0 . Th e ou t pu t is t h e de sign a t e d w a ve for m a n d is a n a r r a y of sa m ple va lu e s of in de x 0 t h r ou gh 9 9 9 in t h is ca se .

The Digit al Cont rols in t he Front Panel of AI Acqu ir e W a ve for m .vi provide for inst alling t he m achine device num ber ( e.g., 1) , t he input channel, num ber of sam ples, and sam ple rat e in addit ion t o t he ADC ( analog- t o- digit al convert er) Digit al Cont rols high lim it and low lim it . The default , 0 V, as in t he exam ple, is equivalent t o 10 V and –10 V for high lim it and low lim it , respect ively. The device num ber of t he DAQ card is set using t he Nat ional I nst rum ent s Measurem ent & Aut om at ion ut ilit y. Go t o St art > > Program s> > Nat ional I nst rum ent s> > Measurem ent & Aut om at ion. This opens a window called Max. Then under My Syst em , locat e Devices and I nt erfaces and Right Click on t he nam e of t he DAQ card t o bring up Propert ies. The device num ber can be set from t he Propert ies window. The sam ple program s in Proj ect A.llb use Device 4 ( or as set on your PC) . Close Max. We will want t o send out som e volt ages t o be read by t he input channel. For t his, add out put channel funct ion AO Upda t e Cha n ne l.vi t o t he Diagram of your VI . I t is under Funct ions> > Dat a Acquisit ion> > Analog Out put . I nst all t his VI in your VI diagram as shown in Fig. A.3. Posit ion t he icons wit h t he Posit ioning Tool ( arrow) . I t is obt ained by cycling t hrough t he Tools by st riking t he Tab key or Space Bar, or, again, get t he Tools Palet t e wit h Shift / Right

Click from t he Front Panel or Diagram .

Figu r e A.3 . La bVI EW VI D ia gr a m w it h t he a ddit ion of out put cha nne l VI AO Upda t e Ch a n n e l.vi. Th e t w o VI s r e pr e se n t e d by t h e icon s ca n be ope n e d w it h Right Click a nd ope n Fr ont Pa ne l or w it h D ouble Click .

Pr oj e ct PA.1 Sending and Receiving Volt ages wit h t he Sending and Receiving VI s ( Measure.vi, version 1)

A.1.2 Programming Exercise: Using a Sequence Structure The t wo VI s represent ed by t he icons of t he Diagram are subVI s of M e a su r e .vi. That is, t hey will r u n when we r u n M e a su r e .vi. I n t his case, it is necessary t hat t hey execut e in t he proper order. For exam ple, we would want t o send out t he volt age before reading t he response. For ensuring proper execut ion order, inst all a Sequence St ruct ure as shown in Fig. A.4. Obt ain t he Sequence St ruct ure from t he Diagram under t he m enu series Funct ions> > St ruct ures> > Sequence. Recall t hat t o obt ain t he Funct ions Palet t e, Right Click on t he Diagram .

Figu r e A.4 . La bVI EW VI D ia gr a m w it h Se qu e n ce St r u ct u r e . This St r u ct u r e e x e cu t e s in or de r of in de x a t t h e t op of t h e Fr a m e s. Fr a m e 1 sh ow n con t a in s t h e VI for r e a ding volt a ge . Fr a m e 0 con t a in s t he VI for se n din g volt a ge . Click on a r r ow s t o m ove t h r ou gh Fr a m e s. Also sh ow n is t h e St r u ct u r e s Pa le t t e u n de r Fu n ct ion s a nd t h e pr oce ss of a ddin g a fr a m e .

I nit ially, t he Sequence St ruct ure is t oo sm all. To enlarge, get t he Posit ioning Tool ( arrow) by pressing t he Space Bar, by sequencing t hrough t he Tools wit h Tab, or by using Shift / Right Click t o bring up t he Tools Palet t e. Posit ion t he Tool at t he lower- right - hand corner of t he Sequence St ruct ure, Left Click, and drag t o enlarge t he St ruct ure. Right Click on t he edge of t he Fram e of t he Sequence St ruct ure and go t o Add Fram e Aft er ( Fig. A.4) . The result will be t wo Fram es wit h index 0 and index 1. Now place ( e.g., drag) t he send and receive VI s int o Fram e 0 and Fram e 1, respect ively. Left Click on t he left and right arrows at t he t op of t he Sequence St ruct ure t o m ove bet ween Fram es. The result will be as shown in Fig. A.4. The Diagram shows Fram e 1. The program will execut e t he VI in num erical Fram e order. Thus, t he out put volt age will always be sent before t he input channel at t em pt s t o read.

A.1.3 Programming Exercise: Digital Controls and Digital Indicators The Front Panel of M e a su r e .vi will now be configured t o perm it assigning t he volt age t o be sent out and reading t he input volt age from t he Front Panel. The Front Panel of t he new configurat ion is shown in Fig. A.5. From t he Front Panel and t hen from t he Cont rols Palet t e, go t o Cont rols> > Num eric ( Fig. A.5) , and from t his select ion, get a Digit al Cont rol and a Digit al I ndicat or. You m ight want t o color t he Front Panel. For t his, Shift / Right Click and get t he Coloring Tool from t he bot t om of t he Palet t e. Then, wit h t he Coloring Tool, Right Click on t he Front Panel and pick a color. You can also color t he Diagram . Change t he labels over t he Digit al Cont rol and Digit al I ndicat or using t he Edit Text Tool ( Fig. A.5) . Obt ain t he Tools Palet t e wit h Shift / Right Click and t he Edit Text Tool. The labels are default ed as Num eric. Use t he Edit Text Tool from t he Tools Palet t e t o relabel as in t he exam ple ( or sim ilar) .

Figu r e A.5 . Fr ont Pa n e l w it h a ddit ion of D igit a l Con t r ol ( se n d) a n d D igit a l I n dica t or ( r e ce ive ) . Th e se a r e obt a in e d w it h a Right Click on Fr on t Pa n e l for Con t r ols Pa le t t e a n d t he n N u m e r ic a n d D igit a l Con t r ol a n d D igit a l I ndica t or . Also sh ow n is t h e Edit Te x t Tool for ch a n gin g t h e la be ls on t h e Con t r ols fr om t h e de fa u lt N u m e r ic.

Now go t o t he Diagram ( under Menu Window> > Show Diagram or use Ct rl E) for wiring t he program in t he diagram . This will include Term inals and Num erics and St rings. St art by connect ing t he sending VI icon ( Fram e 0) value t o t he Digit al Cont rol t erm inal ( Fig. A.6) . To locat e t he t erm inal for t he Digit al Cont rol, go back t o t he Front Panel, Right Click t he Digit al Cont rol for Send Volt s, and m ove t he point er t o Find Term inal. The Diagram will open and t he proper t erm inal will be highlight ed. Not e t hat t he t erm inal for Digit al Cont rol is darker t han t hose for Digit al I ndicat or. This provides for an alt ernat ive m eans of locat ing t he proper t erm inal.

Figu r e A.6 . Top D ia gr a m s: Loca t in g t he va lu e t e r m in a l on t he icon a n d m ovin g t h e W ir in g Tool t o t h e D igit a l Con t r ol t e r m in a l. Bot t om D ia gr a m s: Com ple t e d w ir in g for Fr a m e 0 a n d Fr a m e 1 . Com ple t ion of Fr a m e 1 is discu sse d be low .

Get t he Wiring Tool ( appears like a roll of solder) by st riking t he Space Bar. To wire, first find t he correct t erm inal on t he icon. There are t hree in t his case. The t erm inal for t his connect ion, value, is t he bot t om t hird of t he icon. To locat e t he region of t he connect ion, sweep t he Wiring Tool over t he icon and find t he value. A given t erm inal displays a black- and- whit e blinking while t he Wiring Tool is in cont act wit h t his t erm inal. Now, wit h t he Wiring Tool, Left Click on t he value connect ion region, Release, and m ove t he Wiring Tool t o t he t erm inal of t he Digit al Cont rol. Left Click again t o finish. For an alt ernat ive view of where t he connect ions are m ade, you can Right Click on t he icon, and get Visible I t em s> > Term inals. Recall again t hat t he Digit al Cont rol t erm inal is darker t han t he Digit al I ndicat or t erm inal. This adds addit ional clarificat ion as t o t he correct t erm inal. Com plet e t he connect ions t o t he icon wit h a Num eric Const ant for t he device ( Right Click, t hen Funct ions> > Num eric> > Num eric Const ant ) and a St ring Const ant for t he channel ( Right Click, t hen Funct ions> > St ring> > St ring Const ant ) . Use t he Point ing Tool ( finger) t o writ e in t he const ant values. Obt ain t he various Tools by st riking t he Tab key. Now sequence t o Fram e 1 t o connect t o t he AI Acquir e W a ve for m .vi icon. ( Click on t he arrows at t he t op of t he Sequence St ruct ure.) Com plet e all wiring, as shown in Fig. A.6, except for t he waveform t erm inal ( connect ion on t he right side of t he icon in Fram e 1) . This includes device ( num eric const ant , 4) , channel ( st ring const ant , 0) , num ber of sam ples ( num eric const ant , 100) , high lim it ( num eric const ant , 10) , and low lim it ( num eric const ant , 0) . The low lim it can be set t o 0 because no negat ive num bers are t o be read. As a rem inder for using t he Wiring Tool: I n t he Diagram , use Shift / Right Click t o get t he Tools Palet t e and obt ain t he Wiring Tool. The Wiring Tool is also obt ainable by pressing t he Space Bar, while t he Diagram is t he act ive window, t o sequence bet ween t he Wiring Tool and t he Posit ioning Tool. Left Click on t he t erm inal t o be wired ( do not hold) and m ove t he Tool t o t he ot her t erm inat ion and Left Click again.

A.1.4 Programming Exercise: Using the Array Average Value VI from Probability and Statistics for Averaging the Samples Received

To com plet e connect ions t o t he t erm inals associat ed wit h Fram e 1, we m ust add t he VI M e a n .vi ( Fig. A.7) . I t is used t o obt ain t he average of all of t he num ber of sam ples ( as select ed) in t he reading ( receiving) funct ion. Not e t hat M e a n .vi is connect ed bet ween t he waveform t erm inal of t he AI Acqu ir e W a ve for m .vi and t he Digit al I ndicat or t erm inal. The out put from AI Acqu ir e W a ve for m .vi ( waveform ) in t his case is a clust er of inform at ion including a dat a array. I n t he Diagram , a m uch broader line t han t hat for a single dat a point represent s t he connect ion.

Figu r e A.7 . D ia gr a m sh ow in g Fr a m e 1 . Th e VI M e a n .vi h a s be e n a dde d t o a ve r a ge t h e da t a sa m ple s.

M e a n .vi is obt ainable from t wo different locat ions in t he Funct ions palet t e: Funct ions> > Analyze> > Mat hem at ics> > Probabilit y and St at ist ics> > M e a n .vi;Funct ions> > Mat hem at ics> > Probabilit y and St at ist ics> > M e a n .vi. Connect t he waveform of t he Fram e 1 icon t o M e a n.vi t o t he Digit al I ndicat or Term inal. Connect t he out put in M e a n .vi, m ean, t o t he Term inal of t he Digit al I ndicat or. This m easurem ent , which is t he average of a large num ber of sam ples, is superior t o obt aining a single point t hat m ight very well fluct uat e due t o noise. Pr oj e ct PA.2 Sending and Receiving Volt ages from t he Front Panel ( M e a su r e .vi, version 2)

A.1.5 Programming Exercise: Installing and Using the Waveform Graph A given dc volt age is sent out via an out put channel ( e.g., fram e 0 of Fig. A.7) . A circuit node response is m easured, in our proj ect s, by sam pling t he volt age a num ber of t im es. Wit h LabVI EW, we can easily obt ain a graphical present at ion of t he sam ple dat a point s t o provide an indicat ion of t he noise t hat exist s on t he dc volt age being m easured and in t he m easurem ent syst em . For t his, obt ain a new VI by saving a Save As copy and giving it a new nam e. Here it is nam ed Plot Sa m ple s.vi. The new VI will init ially appear som et hing like t hat in Fig. A.8.

Figu r e A.8 . Fr ont Pa n e l w it h a ddit ion of a W a ve for m gr a ph . Th e gr a ph is obt a in a ble fr om t h e Fr ont Pa n e l u n de r Con t r ols> > Gr a ph > > W a ve for m Gr a ph .

To inst all t he Waveform graph, in t he Front Panel, Right Click and get Cont rols> > Graphs> > Waveform Graph and place it on t he Front Panel. Shift / Right Click on t he face of t he graph t o get t he Coloring Tool and pick a color for your graph background field and Fram e. Figure A.8 shows a new graph inst allat ion wit h som e color changes. A new inst allat ion of a graph has t he Plot Legend open ( Plot 0 in t he exam ple) . I n general, t his feat ure and ot hers can be hidden or m ade t o appear by a Right Click anywhere on t he graph and t hen select ing Visible I t em s as shown in t he exam ple of Fig. A.9.

Figu r e A.9 . Va r iou s gr a ph fe a t u r e s a r e obt a in e d u n de r V isible I t e m s a s sh ow n . Th is in clu de s t h e Plot Le ge n d for se t t in g u p t h e plot st yle .

I n t he box of t he Plot Legend, Right Click, go t o Color and pick a color for t he plot t ing point s or lines. Also, select Point s under Com m on Plot s. Hiding t he Plot Legend m ight be in order, now alt hough t his is opt ional. ( Right Click on t he graph face and select Visible I t em s> > Plot Legend.) For t he present applicat ion, it is preferred t o have no grid. To accom plish t his, Right Click on a num ber on t he Y- scale of t he Fram e of t he graph, go t o Form at t ing... and Grid Opt ions ( Fig. A.10) . Select t he no grid ( Left Click) condit ion as illust rat ed in Fig. A.10. Repeat for t he X- axis. Not e t hat a given axis can be select ed from t he Form at t ing window at t he t op under Select Scale.

Figu r e A.1 0 . Y- sca le For m a t t in g show in g t h e se ct ion of n o gr id fr om Gr id Opt ions. Se le ct ion of D igit s of Pr e cision is a lso m a de in t h is w in dow .

Now use t he Edit Text Tool t o edit t he X and Y designat ors. Then Right Click on t he graph face and get Find Term inal. Com plet e t he wiring t o t he graph t erm inal as in Fig. A.11. The final Front Panel ( Fig. A.11) has t he label hidden and t he X- and Y- axis designat ors edit ed t o be Sam ple Value( V) and Tim e ( sec) . The graph dat a are from a sam ple m easurem ent from Proj ect A.

Figu r e A.1 1 . Com ple t e d Fr on t Pa n e l a n d D ia gr a m sh ow in g con n e ct ion t o t h e t e r m in a l of t h e W a ve for m gr a ph .

Pr oj e ct PA.3 Plot t ing Measured Sam ples ( Plot Sam ples.vi)

A.2 ADC and the Autoranging Voltmeter Very oft en in m easuring circuit charact erist ics, it is necessary t o plot som e volt age response over a wide range of input - volt age st im ulat ion. An aut om at ic m eans of adj ust ing t he volt m et er sensit ivit y t hrough t he sweep is t hus required. When set for t he full m easurem ent range ( lim it ) , t he 12- bit analog- t o- digit al conversion ( ADC) in t he DAQ has eit her a 2.44 m V ( unipolar, 10 V full range) or a 4.88 m V ( bipolar, 20 V full range) resolut ion. However, t he range of t he DAQ is soft ware select able. So, for exam ple, suppose t hat in t he sweep we are m easuring 5 m V and only posit ive volt ages. The DAQ can be program m ed for a high lim it of, for exam ple, 100 m V and a low lim it of 0 V ( unipolar) , such t hat t he resolut ion is 24.4 µV. The Proj ect A LabVI EW library, Pr oj e ct A.llb, cont ains a preprogram m ed VI for set t ing aut om at ically t he range. The Diagram of t he VI , Volt m e t e r .vi, is shown in Fig. A.12. As indicat ed, t he range is set t hrough t he high- and low- lim it input s t o AI Acquir e W a ve for m .vi, for exam ple, 10 V ( high lim it ) and 0 V ( low lim it ) in t he diagram of our aut oranging volt m et er as shown in Fig. A.12.

Figu r e A.1 2 . D ia gr a m of a u t or a n ging dc volt m e t e r , Volt m e t e r .vi. The W h ile Loop r u n s u n t il t he com pa r ison fin ds t h e m e a su r e d va lu e le ss t h a n t h e low e st possible lim it .

The aut oranging volt m et er is program m ed as follows. First , a copy of AI Acquir e W a ve for m .vi is Saved As..., m odified for dc only and renam ed as AI Acquir e Avg.vi. The m odificat ion consist s of t aking t he average of t he array of sam ples and providing for a singlepoint out put of t he average value of t he sam ples. AI Acqu ir e Avg.vi is program m ed t o operat e in select able bipolar or unipolar m ode. Thus, t his feat ure is included in Volt m e t e r .vi. This VI is t hen used as a subVI in t he aut oranging dc volt m et er. Upon running Volt m e t e r .vi, t he execut ion st art s wit h t he subVI AI Acqu ir e Avg.vi on t he left ; t he high lim it set at 10 V, and wit h t he bipolar m ode, t he lower lim it is –10 V. Thus t he volt age being m easured is first sam pled wit h m inim um sensit ivit y but t his is sufficient t o obt ain an approxim at e value of t he volt age. The init ial m easurem ent value is t hen processed t hrough a select ion schem e t o decide which lim it should be set int o t he final m easurem ent subVI t hat is again AI Acquir e Avg.vi. The lim it choices are given in Table A.2. These are st ored in an Array Digit al Cont rol as seen

on t he left in t he diagram . The While Loop com pares t he m easured value wit h each lim it value st art ing at t he t op. The loop halt s when t he com parison finds t he sm allest possible lim it . Bipolar or unipolar are set according t o t he sign of t he init ially m easured value. A fact or of 2 of im proved resolut ion is available wit h t he unipolar case. As not ed, t he valid lim it set t ings and associat ed resolut ions are shown in Table A.1. Wit h t he aut oranging volt m et er, during a sweep, t he resolut ion is m aint ained, t hrough t he sweep, at roughly a fixed percent age of t he value of t he num bers being m easured. TABLE A.2 Unipolar

Range

Resolut ion

0 t o + 10 V

Bipolar

Range

Resolut ion

2.44 m V

- 10 t o + 10 V

4.88 m V

0 to + 5 V

1.22 m V

-5 to + 5 V

2.44 m V

0 to + 2 V

488 µV

-2 to + 2 V

1.22 m V

0 to + 1 V

244 µV

-1 to + 1 V

488 µV

0 t o + 500 m V

122 µV

- 500 t o + 500 m V

244 µV

0 t o + 200 m V

48.8 µV

- 200 t o + 200 m V

122 µV

0 t o + 100 m V

24.4 µV

- 100 t o + 100 m V

48.8 µV

- 50 t o + 50 m V

24.4 µV

Figure A.13 shows a m easurem ent of a sine- wave from a funct ion generat or. This was obt ained in LabVI EW using t he ac volt m et er t hat is discussed in a following unit . The volt age waveform is sam pled at t he t wo lim it set t ings, 100 m V ( a) and 2 V ( b) . The peak of t he sinewave is 10 m V. I t is clear t hat t he resolut ion is not adequat e at t he higher lim it set t ing. I n an aut oranging version of t he ac volt m et er, t he best lim it set t ing is aut om at ically assigned.

Figu r e A.1 3 . La bVI EW m e a su r e m e n t of a sin e - w a ve volt a ge w it h pe a k of 1 0 m V. Th e sin e w a ve is sa m ple d a t t w o lim it se t t in gs of ( a ) 1 0 0 m V a n d ( b) 2 V. Th e r e solu t ion s a r e ( a ) 4 8 .8 µV a n d ( b) 1 .2 2 m V.

Pr oj e ct PA.4 Using t he Aut oranging Volt m et er

A.3 LabVIEW Oscilloscope and Voltmeter (ac) An exam ple of an oscilloscope is shown in Fig. A.14. This special version displays t hree waveform s. These are t he t ot al waveform ( ac + D) , t he sine- wave m inus t he dc ( average value) and t he absolut e value of t he sine- wave ( | ac| ) .

Figu r e A.1 4 . Fr ont Pa n e l for a possible La bVI EW oscilloscope . D igit a l Con t r ols pr ovide for in pu t s of Fr e qu e n cy, Cou n t ( n u m be r of sa m ple s) , a n d # cycle s. D igit a l I n dica t or s sh ow Sa m ple s/ Se c, Se c/ Sa m ple , VD C, a n d Va c Pe a k . Th e lim it s a r e se t in t h e D ia gr a m .

The volt m et er is designed t o m easure peak or RMS values for periodic waveform s, t hus, t o be an ac volt m et er. Tot al sam pling t im e m ust occur in exact m ult iples of cycles. This provides for obt aining t he waveform ( sine- wave) peak or RMS value based on an average of all t he sam ples. The required sam ple rat e, SR, is obt ained from

The values for all t he num bers on t he right - hand side are set in Digit al Cont rols on t he Front Panel ( Fig. A.14) . The # Sam ples is also referred t o as t he Count . SR and # Sam ples are t hen sent t o t he subVI , AI Acquir e W a ve for m .vi. For exam ple, assum e t hat t he # Cycles is 4 and t he # Sam ples is 256. Once cycle will be sam pled 64 t im es. Assum e also t hat f = 1000 Hz. Sam ple rat e SR will be 64000 sam ples/ sec or about 16 µsec/ sam ple. The t ot al sam pling t im e is T · # Cycles, where T is t he period and is T = 1/ f. I n t his exam ple t his is 4m sec. Digit al I ndicat ors in t he Front Panel display t he dc volt age, VDC, and t he peak, Vac Peak. Vac peak is calculat ed as t he average value of | ac| m ult iplied by π/ 2. The program m ing sequence for obt aining t he t hree waveform s is shown in Fig. A.15. I n t he Sequence Fram e is also shown t he program m ing configurat ion for connect ing t o t he graph on t he Front Panel and t he com put at ion of t he peak value, Vac Peak.

Figu r e A.1 5 . Fr a m e of Se qu e n ce St r u ct u r e sh ow in g se r ie s of e ve n t s for obt a in in g a c pe a k va lu e . Th e m e a n is su bt r a ct e d fr om t h e a r r a y w it h t h e r e su lt con ve r t e d t o t h e a bsolu t e va lu e , a n d t h e a ve r a ge is m u lt iplie d by π/ 2 .

Pr oj e ct PA.5 Observing t he Oscilloscope Out put Graph

A.4 Measuring the Discrete Characteristics of Sending and Receiving Voltages I n t he discussion above of t he aut oranging volt m et er, t he discret e nat ure of t he ADC and DAC was dem onst rat ed. LabVI EW VI s t hat plot t he input volt age versus out put volt ages for bot h ADC and DAC dem onst rat e t he effect furt her. Figure A.16 shows t he Front Panel of t he VI D iscr e t e .vi. This VI is for dem onst rat ing t he discret e nat ure of t he sending and receiving funct ions. We first consider t hat of t he sending funct ion, as in t he case of D iscr e t e .vi in Fig. A.16.

Figu r e A.1 6 . D AC in t he bipola r m ode . Plot of t h e pr ogr a m m e d volt a ge se n t ou t ( 0 .1 - m V st e ps) ve r su s m e a su r e d a ct u a l ou t pu t volt a ge . The gr a ph on t h e r igh t is a plot of t h e in put volt a ge sa m ple s for a sin gle ou t pu t sw e e p.

The graph on t he left shows t he volt age act ually sent out ( Y- axis) for a quasi- cont inuous range of request ed ( program m ed) volt age t o be sent out ( X- axis) . I n t he exam ple, t he program called for t he out put volt age t o be swept over a range from –10 t o 10 m V in st eps of 100 µV. The act ual volt age sent out is discret e in st eps of 4.88 m V; t hus only four st eps over t he ent ire range are sent out . The graph on t he right is a plot of t he input volt age sam ples from one ( t he last ) m easurem ent . The plot illust rat es t he inherent scat t er in t his t ype of m easurem ent . Pr oj e ct PA.6 Discret e Out put Volt age from The DAQ I n Fig. A.17 is shown t he result of m easuring a high- resolut ion out put sweep wit h a less precision input m ode of m easurem ent . The high resolut ion is obt ained wit h a resist ance volt age divider. The graph on t he left shows t he discret e nat ure of t he receiving funct ion for a low- resolut ion m ode. For t he lim it set t ings, t he receiving resolut ion is 4.88 m V.

Figu r e A.1 7 . Th e fu ll r a n ge of t h e out pu t sw e e p is 1 0 m V. ( Th e X- a x is is be for e t he 1 0 0 :1 volt a ge division .) Th e in pu t ch a n n e l h a s low r e solu t ion , a s r e ve a le d by t h e st e ps in t h e plot .

The t ransit ion regions are nonabrupt due, t o t he bit uncert aint y ( due t o noise) in t hese regions. I n Fig. A.18 is shown input volt age sam ples ( for one out put volt age) for a point in a plat eau region ( a) and for a point in t he t ransit ion region ( b) . Not e t hat t he plot in t he graph on t he right in Fig. A.17 is for a plat eau region ( last point in t he sweep in t he plot on t he left ) and shows no scat t er.

Figu r e A.1 8 . ( a ) Ch a n 0 _ in sa m ple s for a volt a ge in a pla t e a u r e gion in t h e plot of Fig. A.1 7 . ( b) Sa m ple s for a volt a ge fr om t h e t r a n sit ion r e gion .

Pr oj e ct PA.7 Discret e I nput Volt age from t he Circuit Board

A.5 Sending and Receiving Waveforms Measuring circuit response t o waveform input signals requires sim ult aneous sending and receiving dat a wit h t he DAQ. An exam ple was dem onst rat ed above wit h t he oscilloscope m easurem ent proj ect ( Fig. A.14) . The funct ion generat or VI used for t hat m easurem ent is FG_ A.vi. The m ain subVI of t he funct ion generat or VI is SR_ A.vi. The Front Panel and Diagram of t he VI are shown in Fig. A.19. The VI sends and receives volt age arrays from one out put channel and one input channel.

Figu r e A.1 9 . Th e Fr on t Pa n e l a n d D ia gr a m of SR_ A.vi. La bVI EW AO W r it e r e ce ive s t h e a r r a y of t h e n u m e r ica l va lu e s of t he w a ve for m a n d se n ds t h e m ou t on t he ou t pu t ch a n n e l. The oscilloscope is la u n ch e d in se qu e n ce a n d m e a su r e s t h e r e spon se volt a ge of t he in pu t ch a n n e l w h ile t he out pu t a r r a y is st ill be in g e x e cu t e d.

I nform at ion supplied from t he t op VI , FG_ A.vi, includes sine- wave ( or square- wave) frequency ( Frequency) , num ber of cycles ( Cycles) , and num ber of sam ples per cycle ( Sam ples/ Cycle) . The inform at ion is used t o facilit at e t he com put at ion Sam ple Rat e = Frequency · Sam ple/ Cycle and t he size of t he waveform dat a array ( Cycle · Sam ples/ Cycle) . The subVI , SR_ A.vi, receives t his inform at ion along wit h t he waveform dat a array, as required by t he funct ions in t he Diagram of SR_ A.vi ( Fig. A.19) . The waveform dat a array is calculat ed by a subVI , Sin e - w a ve .vi ( on t he sam e level as SR_ A.vi) . ( An alt ernat ive waveform , Squa r e W a ve .vi, is select able from FG_ A.vi) . The execut ion sequence is AO Config.vi, AO W r it e .vi, AO St a r t .vi, Oscilloscope A.vi, AO W a it .vi, and AO Cle a r .vi. The Num ber of Cycles is adj ust ed aut om at ically in t he t op VI and increases for higher frequencies. The increase provides assurance t hat t he out going waveform is st ill execut ing

during t he oscilloscope m easurem ent phase. The durat ion of t he waveform sent out is Cycles · T. Pr oj e ct PA.8 Using t he Sim ult aneous Sending/ Receiving Funct ion

A.6 Summary of Programming Projects PA.1

Sending and Receiving Volt ages wit h t he Sending and Receiving VI s

PA.2

Sending and Receiving Volt ages from t he Front Panel

PA.3

Plot t ing Measured Sam ples

PA.4

Using t he Aut oranging Volt m et er

PA.5

Observing t he Oscilloscope Out put Graph

PA.6

Discret e Out put Volt age from t he DAQ

PA.7

Discret e I nput Volt age from t he Circuit Board

PA.8

Using t he Sim ult aneous Sending/ Receiving Funct ion

Unit B. Characterization of the Bipolar Junction Transistor for Circuit Simulation The inclusion of t ransist ors in circuit sim ulat ion requires a m odel for t he t ransist or. That is, t he sim ulat or needs t o know how t he t ransist or behaves. Specifically, t he sim ulat or requires knowledge of t he t erm inal charact erist ics of t he t ransist or. For exam ple, for a given dc volt age VBE applied bet ween t erm inals B ( base) and E ( em it t er) , what will be t he current int o B ( I B) ? The m at hem at ical relat ions are obt ained from t heory or experim ent al observat ion. Oft en, t he t heory is very com plicat ed, but m uch m ore sim ple relat ions serve very well as good approxim at ions. TABLE B.1 SPI CE Nam e

Mat h Sym bol

Descript ion

IS

IS

Descript ion

I SE

I SE

Sat urat ion current .

BF

βF

Base – em it t er leakage sat urat ion current .

VAF

VAF

I deal m axim um forward current gain.

BR

βR

Forward Early volt age.

NF

nF

Reverse- current gain.

NE

nE

Forward- current em ission coefficient .

The param et ers for t he BJT, which are t o be det erm ined in t he proj ect s as described in t he following, are given in Table B.1. The param et ers are obt ained by fit t ing t he m at hem at ical expressions as used by SPI CE t o m easured current – volt age relat ions.

B.1 Fundamentals of Bipolar Junction Transistor Action A bipolar j unct ion t ransist or is m ade up of a sandwich of t wo sem iconduct or pn j unct ions. Transist ors are eit her npn or pnp. I n t he act ive- m ode t ransist or st at e, one j unct ion, t he input j unct ion, is forward biased, and t he opposit e j unct ion, t he out put j unct ion, is reverse biased. The behavior of t he individual pn j unct ion diode will first be considered t o clarify forward and reverse bias. A sem iconduct or pn- j unct ion diode in diagram m at ic form is shown in Fig. B.1. The current and volt age of an ideal pn- j unct ion diode are relat ed by

Equ a t ion B.1

Figu r e B.1 . D ia gr a m m a t ic pn - j u n ct ion diode . Applie d volt a ge V D is sh ow n for for w a r d bia s for w hich cu r r e n t fr e e ly flow s. Opposit e pola r it y is r e ve r se bia s, w h e r e t h e diode is e sse n t ia lly cu t off a n d I D = – I S.

where VD is t he volt age applied bet ween t he p and n regions ( posit ive at t he p t erm inal) , I D is t he responding current , and I Sd is t he sat urat ion current . The t herm al volt age, VT, is defined as VT = kT/ q, where T is t he t em perat ure, k is t he Bolt zm ann const ant and q is t he elect ron charge. At 27°C, V T 26 m V. VD is posit ive for forward bias and negat ive for reverse bias. As illust rat ed by t he arrows in t he j unct ion of Fig. B.1, for forward bias, t he diode current consist s of inj ect ion of holes from t he p region ( posit ive free carriers) int o t he n region and inj ect ion of elect rons from t he n region ( negat ive free carriers) int o t he p region. The exponent ial fact or in ( B.1) is associat ed wit h t he st at ist ics of t he free carriers, holes and elect rons, and t he effect on t he lowering of t he barrier t o free- carrier flow of t he applicat ion of t he posit ive applied volt age. The m agnit ude of I Sd is dependent on sem iconduct or elect ronic propert ies such as doping levels and free- carrier lifet im e and m obilit y. The m agnit ude of current flow for a given VD is dict at ed by a com binat ion of t he barrier- lowering fact or ( in t he exponent ial) and t he rat e of free- carrier recom binat ion; t hat is, carriers are annihilat ed by recom bining wit h t he opposit e t ype of carrier on t he opposit e side of t he j unct ion from which t hey are inj ect ed. A t ypical value for sat urat ion current , I Sd , is 10 –11 m A, such t hat , for exam ple, for VD = 0.6 V, 0.1 m A and increases by an order of m agnit ude for each addit ional increm ent of δVD 60 ID m V ( at room t em perat ure) . The equat ion would suggest t hat for negat ive VD and | VD | > > VT, I D = –I Sd and t herefore is very sm all com pared t o t he current under forward bias. I n real pn-

j unct ion diodes, t he current is larger and is not independent of t he value of t he reverse applied volt age. Nonet heless, it is st ill very sm all com pared t o t he value of current for norm al forward bias. As m ent ioned above, t he bipolar j unct ion t ransist or is m ade up t o t wo j unct ions, which share a com m on region. A pnp exam ple is shown in Fig. B.2. The individual pn j unct ions of a t ransist or also exhibit diode charact erist ics, and t he j unct ion current s are relat ed t o t he j unct ion volt ages by equat ions sim ilar t o ( B.1) . There is an essent ial difference t hat can be explained for t he case of one j unct ion being forward biased while t he ot her j unct ion is zero or reverse biased. Specifically, suppose t hat t he t ransist or is a pnp ( t he ot her possibilit y being t he npn) and t he pn j unct ion on t he left ( input j unct ion) is forward biased and t he pn j unct ion on t he right ( out put j unct ion) , is m ade t o have zero bias by connect ing a wire across t his j unct ion, as shown in Fig. B.2.

Figu r e B.2 . D ia gr a m m a t ic se m icon du ct or pn p t r a nsist or . Th e in pu t j u n ct ion on t h e le ft h a s for w a r d bia s volt a ge V D , a n d t h e out pu t j u n ct ion on t h e r igh t is sh or t e d for ze r o bia s. Th e in pu t pn - j u n ct ion diode cu r r e n t I D cou ple s w it h t h e ou t pu t pn j u n ct ion t o flow in t o t h e ou t pu t p r e gion .

Even t hough t he forward- biased pn j unct ion on t he left shares t he n region wit h anot her pn j unct ion ( on t he right ) , it behaves like a pn- j unct ion diode such t hat t he current – volt age relat ion for t he j unct ion st ill has t he form of ( B.1) and is

Equ a t ion B.2

The sat urat ion current is now designat ed I S, since I S I Sd . [ I f t he widt h of t he n region is very large, t he holes inj ect ed int o t he n region will recom bine wit h elect rons in t he n region, and t he associat ed current will flow ent irely out t hrough t he cont act t o t he n region. I n t his lim it ing case, t he current – volt age relat ion for t he j unct ion on t he left revert s t o ( B.1) . The presence of t he p region on t he right will play no role.] I n a t ransist or, t he n- region widt h is m ade sm all and t he st at ist ical chance of an inj ect ed hole surviving t he t ransit across t his region, wit hout recom bining wit h an elect ron, is very high. Upon ent ering t he p region on t he right , t he holes are accom m odat ed by t he exit of an equal num ber of holes m oving out at t he cont act t o t his p region. ( Act ually, t hey are convert ed t o elect rons at t he int erface of t he cont act and sem iconduct or t o be consist ent wit h having only elect ron flow in t he m et al cont act and device connect ing m et al.) I n an ideal t ransist or, t his is t he only current m echanism . The various ot her current com ponent s of t he real t ransist or are discussed below. These include elect ron inj ect ion t hat would be expect ed from t he n region int o t he p region of t he forward- biased j unct ion on t he

left ( as in Fig. B.2) . I n pract ice, special fabricat ion t echniques are em ployed t o m ake t his com ponent of current very sm all. I n t he applicat ion of a t ransist or in t he act ive m ode, as for exam ple, in an analog am plifier st age, t he out put j unct ion is reverse biased, as shown in Fig. B.3. The j unct ion configurat ion now represent s a t ransist or; t he regions are accordingly designat ed as em it t er ( E) , base ( B) , and collect or ( C) . Consist ent wit h t hese assignm ent s, t he current int o t he t ransist or on t he left is t he em it t er current , I E, and t he out put current on t he right is t he collect or current , I C, and according t o t he m echanism described above for t he ideal t ransist or, I C = I E.

Figu r e B.3 . D ia gr a m m a t ic se m icon du ct or pn p t r a nsist or in a ct ive - m ode ope r a t ion . Re gion s a r e n ow de sign a t e d e m it t e r , ba se , a n d colle ct or . Th e e m it t e r – ba se j u n ct ion is for w a r d bia se d a n d t h e colle ct or – ba se j u n ct ion is r e ve r se bia se d.

Wit h forward bias ( volt age) across t he em it t er – base j unct ion and reverse bias across t he collect or – base j unct ion, t he em it t er – base current equat ion, ( B.2) , is slight ly alt ered, t o becom e

Equ a t ion B.3

Variable subscript s have been changed t o reflect t he fact t hat t he pnp st ruct ure is now specifically a t ransist or. ( The param et er I S is t he sam e in SPI CE for t he diode and t he t ransist or m odels. I Sd was used above for t his discussion alone t o different iat e bet ween t he t wo.) For reverse bias of t he collect or – base j unct ion, t he –1 of ( B.2) is elim inat ed. I n t his sim plified version of t he t ransist or, t he out put current is independent of t he collect or – base volt age. The possibilit y of infinit e volt age gain is t hus provided, because t he out put circuit behaves like a pure current source; t hat is, it will force current int o an ext ernal resist ance, which can be large wit hout lim it . This conclusion rem ains subj ect t o addit ional alt erat ions for t he real t ransist or. However, in principle, t he t ransist or m echanism as discussed is applicable short of cert ain lim it at ions. An exam ple of obt aining gain from a t ransist or in an am plifier circuit is shown in Fig. B.4. A ground has been added at t he n- region t erm inal t o est ablish a reference. Therefore, t he out put volt age, VO, is defined wit h respect t o t his reference. To t he t ransist or circuit of Fig. B.3, we have added an input signal Veb and a load resist or, RL. Not e t hat since t he input and out put are referred t o t he base, t he circuit is a com m on- base am plifier.

Figu r e B.4 . Am plifie r cir cu it incor por a t in g a pn p t r a nsist or . Th e ou t pu t volt a ge is w it h r e spe ct t o gr ou n d a t t he n - r e gion t e r m in a l. The ba se is

com m on t o t h e in pu t a n d ou t pu t a n d h e n ce , t h is is t he com m on - ba se a m plifie r con figu r a t ion .

Suppose t hat init ially, Veb = 0 and VEB is select ed t o give I C = 1 m A. This is, in an am plifier, t he bias current . The out put supply volt age is chosen t o be VCC = 12 V. We select RL = 5 kΩ giving a bias out put volt age VO = I CRL = 5 V. Not e now t hat t he collect or- base bias volt age is VBC = VCC – VRL = 7V and t he j unct ion is reverse biased. We now apply an input volt age ( signal, ac, or increm ent al volt age) Veb = 18 m V. This increm ent added t o VEB will cause I C t o double ( i.e., I C = 2 m A) . The result is a new out put volt age of v O( sig) = 10 V. Thus t he increm ent al ( or signal) out put volt age is δVO = v O( sig) – VO = Vo = 5 V. Base – collect or volt age is now v BC = VRL = 2 V and t he j unct ion rem ains in a reverse- bias st at e. The increm ent al ( ac or signal) rat io of out put and input volt age is Vo / Vbe = 5V/ 18 m V = 278. Not e t hat t he gain is power- supply lim it ed. Em ploym ent of a larger power supply perm it s t he use of a larger RL, which result s in a higher gain. We will lat er show t hat t he gain is in fact VRL/ VT based on an approxim at e linear represent at ion bet ween t he input and out put volt age. Not e t hat in t his case, t he linear approxim at ion is VRL/ VT = 192, which indicat es, for t he exam ple above, t hat t he linear relat ion provides a fair est im at e. An alt ernat ive bias arrangem ent is shown in Fig. B.5. The input t erm inal is now t hat of t he n region and t he p t erm inal is a com m on node t o t he input and t he out put . This is t he com m onem it t er configurat ion. Not e t hat t he volt age applied t o t he input j unct ion has not changed, and t he out put j unct ion now has a bias volt age of VEC – VEB and rem ains reverse biased as long as VEC> VEB.

Figu r e B.5 . Com m on - e m it t e r t r a nsist or a m plifie r con figu r a t ion . The com m on t e r m in a l is n ow t h e p- e m it t e r r e gion a n d t h e in pu t is a t t h e ba se ( n r e gion ) . Th e out pu t is be t w e e n t h e com m on e m it t e r a n d t h e colle ct or . Th is dia gr a m in clu de s a possible I B a n d t h u s I C < I E, a s is discu sse d in Un it B.3 .

I n elect ronic am plifiers, all t hree t erm inal configurat ions are possible: com m on base, com m on em it t er, and com m on collect or ( em it t er follower) . Them ost frequent ly em ployed am plifier st age is based on t he com m on- em it t er m ode, but t he ot her t wo serve im port ant roles in elect ronic am plifiers. I n all t hree, t he em it t er – base volt age is t he input cont rol- t erm inal volt age. I n t he com m on- em it t er and com m on- base, t he out put current is t he collect or current and in t he com m on collect or, it is t he em it t er current . The com m on- collect or configurat ion is usually referred t o as t he em it t er follower. I n t he subunit s t hat follow, t he det ailed SPI CE relat ions t hat generally relat e t he branch current s t o t he t erm inal volt ages are developed. This includes t he addit ion of m any aspect s of t he real t ransist or which were not included in t he discussion above of t he highly idealized t ransist or. I nit ially, t he forward- act ive m ode is explored, and t his is followed by a discussion of t he reverse- act ive m ode. The reverse- act ive m ode is where t he sit uat ion in Fig. B.3 is reversed. Thus, VCB is posit ive ( base – collect or j unct ion forward biased) , while VEB is zero or negat ive. I n t he reverse- act ive m ode, VCB becom es t he input volt age, and t he out put current is t he em it t er current , I E. Alt hough t he t ransist or is not operat ed in t he reverse- act ive m ode, t he relat ionships developed for t his case can be com bined wit h t hose from t he forward- act ive m ode. The com binat ion produces t he general equat ions for relat ing current s and t erm inal volt ages in t ransist ors for all bias possibilit ies ( i.e., where t he t ransist or is biased out of t he act ive m ode) .

B.2 Base-Width Dependence on Junction Voltage I n real t ransist ors, t he base widt h depends on t he volt age applied across a pn j unct ion. The effect is known as base- widt h m odulat ion. A diagram m at ic represent at ion of t he effect is illust rat ed in Fig. B.6. Not shown in t he diagram s in Unit B.1 of t he pnp st ruct ure are t he deplet ion regions, which are shown shaded in Fig. B.6. These are t he t ransit ion regions t hat are deplet ed of free carriers, and in which t he barrier is form ed t hat im pedes elect ron and hole flow t o t he p regions and n region, respect ively. The base widt h ( n region) is act ually t he widt h bet ween t he deplet ion regions. I n t he diagram of Fig. B.6, we define w Bo for VBC = 0 and w B for VBC > 0.

Figu r e B.6 . D ia gr a m m a t ic pn p st r u ct u r e sh ow in g t h e e ffe ct of ba se – colle ct or volt a ge on ba se w idt h .

The m agnit ude of sat urat ion current , I S, in ( B.3) is specifically defined for VBC = 0 or w Bo . I n a circuit applicat ion, t hough, VBC will in general be nonzero and t he base widt h can vary as shown; in t he exam ple of Fig. B.6, t he base widt h is w B for a given applied VBC. To a reasonable approxim at ion, t he relat ionship bet ween t he effect ive sat urat ion current wit h a nonzero VBC can be account ed for wit h t he form .

Equ a t ion B.4

where is t he effect ive sat urat ion current for a reverse- applied base – collect or volt age. The approxim at e form assum es t hat VBC < < VAF. The expression in t he denom inat or, 1 – VBC/ VAF, com es from t he fact t hat base widt h is roughly

is approxim at ely inversely proport ional t o t he base widt h, and t he

Equ a t ion B.5

The param et er VAF is called t he Early volt age for forward- act ive operat ion. I t has a count erpart for reverse- act ive operat ion, VAR. The base- widt h dependence on j unct ion volt age is included in t he nonideal fact ors t aken up in Unit B.3.

B.3 BJT Base, Emitter, and Collector Currents in the Active Mode The discussion of t he t ransist or m echanism of Unit B.1 is ext ended here t o include basecurrent m echanism s, which exist in t he real t ransist or, and t he effect of base- widt h m odulat ion as discussed in Unit B.2. I nit ially, t he case of act ive- m ode operat ion is discussed, and t his is followed by t he general- bias case, which includes t he possibilit y of bot h pn j unct ions becom ing forward biased. I n t he device m odel for t he bipolar j unct ion t ransist or, t he param et er βDC is

Equ a t ion B.6

where I B is t he com posit e of all cont ribut ions t o t he base current . ( The use of " dc" is consist ent wit h SPI CE.) This relat es t he out put current , I C, t o t he input current , I B, for t he t ransist or operat ed in t he com m on- em it t er t erm inal configurat ion. I n t he following, t he discussion is based on t he npn t ransist or, as shown now wit h t he schem at ic sym bol in Fig. B.7. The npn is chosen over t he pnp, as it is subst ant ially m ore basic t o BJTs t han t he pnp. This probably has t o do m ost ly wit h t he fact t hat a com m on- em it t er st age is consist ent wit h a posit ive power supply ( a holdover from t he vacuum - t ube days) , t hat t he npn is superior in t erm s of frequency response, and t hat it has consist ent ly been t he device of BJT digit al swit ches including t he TTL. The pnp was used in t he discussion above on t he fundam ent als of t ransist or act ion, as it is som ewhat m ore int uit ively sat isfying t o have t he current and part icle flow ( where t he illust rat ion is wit h t he hole) in t he sam e direct ion.

Figu r e B.7 . BJT ( n pn) in t h e com m on - ba se con figu r a t ion , sh ow in g t e r m in a l volt a ge s a n d br a n ch cu r r e n t s.

The assignm ent of polarit ies of volt ages VBE and VBC is consist ent wit h forward bias for bot h t he em it t er – base and collect or – base j unct ions. VBC will be negat ive in act ive- m ode operat ion. The assignm ent of VCE is st andard, as it will be posit ive in act ive- m ode operat ion. Current direct ions are assigned t o correspond t o t he act ual direct ions of t he current s in t he forwardact ive m ode. Base current s do not couple bet ween j unct ions. Rat her, as suggest ed in Fig. B.8, a given base current is associat ed wit h a given pn j unct ion. I n t he forward- act ive m ode, a base- current com ponent is added t o t he em it t er current as indicat ed in Fig. B.7. However, since t he base – collect or j unct ion is reverse biased, t he base- current cont ribut ion t o t he collect or current is negligible and ( B.3) st ill represent s t he t ot al collect or current . The collect or- current relat ion wit h t he base- widt h- m odulat ion effect ( Unit B.2) now included becom es

Equ a t ion B.7

Figu r e B.8 . D iode lik e ch a r a ct e r ist ics of t h e ba se cu r r e n t s. Th e y a r e se pa r a t e ly a ssocia t e d se pa r a t e ly w it h t h e ir r e spe ct ive pn j u n ct ion s. Th e se cu r r e n t s do n ot cou ple a cr oss t h e ba se .

The equat ion has also been generalized t o include t he SPI CE param et er n F, t he forward current em ission coefficient ( which is usually assum ed t o be 1) . The base current , for t he forward- biased base – em it t er j unct ion, is m ade up of t wo t erm s; t hese are t he ideal base current ( because it has t he sam e VBE dependence as I C) and t he leakage base current . The leakage com ponent is t ypically sm all enough t o be neglect ed and oft en is, for sim plicit y, in pract ice. I n t he absence of leakage base current , t he base current is

Equ a t ion B.8

where I SBE is t he base – em it t er sat urat ion current . I n t he act ive m ode, VBE is posit ive, and t ypically, VBE 0.6V. The exponent ial t erm is, for t his case, exp( VBE/ n FVT) 10 10 such t hat t he –1 is quit e negligible. The –1 is necessary for t he current t o go t o zero for VBE = 0. This current is due t o ( npn) inj ect ion and recom binat ion of m inorit y- carrier elect rons in t he base and inj ect ion and recom binat ion of m inorit y- carrier holes in t he em it t er. Base current could also be connect ed t o inj ect ion of holes int o t he n- t ype em it t er, which recom bine at t he em it t ercont act m et al – sem iconduct or int erface. I n any event , base – em it t er j unct ion base current is predom inant ly from inj ect ion int o t he em it t er, as opposed t o inj ect ion int o t he base. For t his case of no leakage current and for VBC = 0, t he forward- act ive current gain ( or current rat io) is defined as βDC βF. Using ( B.6) , ( B.7) , and ( B.8) ( wit h –1 neglect ed) , t his is

Equ a t ion B.9

and I SBE = I S/ βF. Consequent ly, t he ideal base current is norm ally writ t en as

Equ a t ion B.1 0

Not e t hat t he base current does not have VBC dependence as exhibit ed by t he collect or current . This is dem onst rat ed t o be valid in Proj ect B.

The param et er βF is t he SPI CE t ransist or- m odel β. I m plicit in t he assignm ent of I S ( I S) and BF ( βF) in t he SPI CE device m odel is t he assignm ent of t he ideal base- current sat urat ion I SBE = I S/ βF. That is, t here is no I SBE ( SPI CE param et er) in t he m odel. I f t he general act ive- region relat ion for I C, ( B.7) , is now used in t he βDC definit ion, we obt ain t he βDC relat ion for nonzero VBC, nam ely,

Equ a t ion B.1 1

where βF is a const ant ( SPI CE BF) and βDC = βF for VBC = 0. I n t he real t ransist or, t here is, in general, a com ponent of leakage current . I t is associat ed wit h recom binat ion of holes and elect rons in t he deplet ion region of t he base – em it t er j unct ion. I n SPI CE, t he leakage- current com ponent is charact erized wit h param et ers n E ( base – em it t er leakage coefficient ) and I SE ( base – em it t er leakage sat urat ion current ) . When added t o t he ideal com ponent , t he t ot al base current is

Equ a t ion B.1 2

( These are bot h posit ive int o t he t ransist or for t he npn.) The param et er n E is ideally 2 ( according t o early, sim plified t heories) , but in pract ice is t ypically about 1.5. When t ransist ors are operat ed in or above t he m idrange of t heir rat ed current capacit y, t he leakage com ponent becom es negligible. For a sm all power t ransist or, t he m idrange st art s at about 100 m A, such t hat t he leakage t erm would be very significant at , for exam ple, 1 m A. I n t he proj ect on t he t ransist or, which is designed t o det erm ine t he SPI CE param et ers discussed here, a low- current range of less t han about 1 m A is select ed. The low current also avoids inadvert ent rise in t he t em perat ure of t he device during evaluat ion. Sim ilar equat ions t hat apply t o t he reverse- act ive m ode can be obt ained by direct subst it ut ion of t he equivalent variables. The out put current and input volt age, are, respect ively, I E and VBC, while, for t he reverse- act ive m ode, VBE = 0 or negat ive. Based on t he equivalent subst it ut ion

Equ a t ion B.1 3

The m inus sign com es from having assigned t he current direct ion of t he em it t er current out of t he t ransist or ( Fig. B.7) . The param et er I S is com m on t o ( B.7) and ( B.13) . Equat ions ( B.7) and ( B.13) are com bined t o obt ain t he general case of VBE and VBC bot h posit ive ( forward bias) in a following unit . The reverse- operat ion base current is [ t he reverse- operat ion equivalent of ( B.12) ]

Equ a t ion B.1 4

where βR is t he dc current rat io ( reverse- act ive m ode) for t he case of no leakage com ponent of base current , and is given by βR = I E/ I B. I n pract ice, t he reverse ideal current gain is 0.1 < βR < 10, and t herefore, t he reverse- operat ed t ransist or is not a useful configurat ion in, for exam ple, analog am plifiers. However, t he reverse- act ive m ode equat ions are essent ial, as is shown below, for developing t he general equat ions for t he forward m ode. The general form includes t he possibilit y t hat t he t ransist or will be out of t he act ive m ode. Alt hough VAR ( reverse Early volt age) , I SC ( reverse leakage sat urat ion current ) and n c ( base – collect or leakage em ission coefficient ) are officially SPI CE param et ers, we will not be concerned wit h t hese as t hey would rarely be a fact or in t he st udy of analog circuit s.

B.4 Diode-Connected Transistor Circuits for Measuring Base and Collector Current The circuit shown in Fig. B.9 is used in t he param et er- det erm inat ion proj ect for m easuring t he base current wit h t he collect or open. The collect or is t ied t o t he out put channel volt age, which holds t he collect or – base j unct ion in reverse bias, and t herefore in t he act ive m ode. The configurat ion is effect ively a diode ( open collect or) wit h t wo t erm inals, base and em it t er, and t he diode current is t he base current . The base current is t hat of t he act ive- m ode t ransist or, because t he collect or – base j unct ion is m aint ained in a reverse- bias st at e. Not e t hat according t o ( B.12) , base- current m agnit ude does not ot herwise depend on t he value of t he base – collect or volt age. This is shown t o be valid in t he proj ect . ( The base current is m uch different when t he collect or t erm inal is t ied t o ground and t he base – collect or j unct ion is forward biased.)

Figu r e B.9 . Cir cu it for m e a su r in g ba se cu r r e n t in t he ope n - colle ct or diode - con n e ct e d cir cu it .

The m easurem ent circuit includes a current sensing resist or, RB. The relat ion bet ween I B and VBE for t his t erm inal configurat ion is ( B.12) , repeat ed here

As not ed above, t he base current of ( B.12) exhibit s no base- collect or volt age dependence ot her t han t he requirem ent t hat t he t ransist or be in t he act ive m ode. This is assured in t his circuit since VBC is

Equ a t ion B.1 5

where VCC

Chan0_out .

I n t he alt ernat ive diode circuit of Fig. B.10, t he base and collect or are connect ed such t hat VBC = 0 and t he equat ion for t he collect or current is ( B.7) wit h VBC = 0, or, sim ply,

Equ a t ion B.1 6

Figu r e B.1 0 . Cir cu it for m e a su r in g e m it t e r cu r r e n t . I n t h is cir cu it , V BC = 0 a n d ( B.1 6 ) a pplie s.

The m easured current in t he circuit , t hat is, sensed by t he sensing resist or, RE, is t he em it t er current , I E. This is t he sum of ( B.12) and ( B.16) , which is

Equ a t ion B.1 7

We not e t hat ( B.12) rem ains valid for VBC = 0. Current m easurem ent s from t he t wo diode circuit s provide, t herefore, I C, from I C = I E –I B. I n t he param et er m easurem ent proj ect , it is verified t hat t he base current is t he sam e for bot h m easurem ent circuit s. This is a m eans by which t he independence of base current on reverse volt age is dem onst rat ed. I n t he BJT param et er det erm inat ion proj ect , param et er ext ract ion from t he exponent ial relat ions is obt ained from plot s of current – voltage charact erist ics. The form of t he log of t he current versus volt age provides inform at ion on t he t wo param et ers of t he exponent ial from a st raight - line curve fit . For exam ple com bining t he current s from t he t wo circuit s gives, as not ed, I C = I E – I B and [ from ( B.16) ]

Equ a t ion B.1 8

The zero volt age int ercept t hus reveals I S and t he slope will show t hat n F

1.

A sim ple exponent ial represent s t he base current only approxim at ely, as it is a com binat ion of t wo exponent ials; t hat is,

Equ a t ion B.1 9

I n t he m easurem ent of t he base current , using t he circuit of Fig. B.9, t he m easured sem ilog plot will appear t o be a st raight line. This would suggest t hat t he current – volt age relat ion is a sim ple exponent ial, as in t he case of t he collect or current . However, param et ers n Eprim e and

I SEprim e vary, depending on t he given narrow range of base – em it t er volt age of t he m easurem ent . Not e t hat since n F = 1 and n E > 1, n Eprim e will be in t he range 1 < n Eprim e < n E. Sam ple m easured result s are shown in Fig. B.11, where t he current is plot t ed on a log scale. For t his plot , I C has been obt ained from I C = I E – I B. Bot h plot s are st raight lines, indicat ing t he exponent ial relat ionship bet ween current and volt age for t he t wo cases. Careful scrut iny of t he lower curve ( I B) should show a slight upward curvat ure since it is a m ixt ure of t wo exponent ial t erm s, as not ed. The st eeper slope for em it t er current is a result of t he fact t hat n F = 1 and n Eprim e > 1.

Figu r e B.1 1 . La bVI EW plot of m e a su r e d cu r r e n t s ( m A) ve r su s ba se – e m it t e r volt a ge ( V) . Th e r a t io of t h e t w o is t h e βD C of t h e t r a n sist or .

B.5 Output Characteristics of BJT in the CommonEmitter Mode The com m on- em it t er t erm inal configurat ion can be considered t he fundam ent al building block of BJT analog am plifier circuit s. The com m on base and com m on collect or are applied t o som e ext ent in m ore special- purpose roles, such as for high out put resist ance ( com m on base) and low out put resist ance ( com m on collect or) . Therefore, a st udy of t he t ransist or in t he com m onem it t er m ode is basic t o a st udy of analog circuit s. The out put charact erist ic of t he com m on- em it t er t ransist or is defined as t he out put current ( I C) as a funct ion of t he out put t erm inal volt age ( VCE) for I B ( or VBE) held const ant . I t is very im port ant t o underst and in t he design of bot h analog and digit al circuit s. The out put charact erist ic is experim ent ally explored in t he proj ect on param et er det erm inat ion. The m easurem ent circuit for obt aining t he out put charact erist ic is shown in Fig. B.12. This is also t he circuit for m easuring βDC versus I C, which is discussed below.

Figu r e B.1 2 . Cir cu it for m e a su r in g t r a n sist or ou t pu t ch a r a ct e r ist ic a n d βD C ve r su s I C.

The equat ions present ed in Unit B.2 are in t erm s of t erm inal volt ages VBE and VBC. The com m on- em it t er configurat ion has input volt age VBE but out put volt age VCE. Therefore, it is preferable t o elim inat e VBC in t he equat ions in favor of VCE, using VBC = VBE – VCE. When plot t ing t he out put charact erist ic, for exam ple, from 0 < VCE < 5 V, t he range of VBC is VBE < VBC < –( 5 – VBE) . Since VBE 0.5 V, VBC covers t he full range from st rongly forward biased ( out of t he forward- act ive m ode) t o clearly reverse biased ( forward- act ive m ode) . This requires t hat t he I C [ ( B.7) ] and I B [ ( B.12) ] equat ions be m odified t o include all possibilit ies. To obt ain an equat ion for I C under general biasing condit ions, we st art wit h t he fundam ent al equat ion of t ransist or act ion of t he BJT. This is

Equ a t ion B.2 0

This is a com posit e of ( B.7) and ( B.13) in which t he base- m odulat ion effect s are neglect ed. Bot h of t hese equat ions are for I C and I E in t he ideal t ransist or. ( I n t his unit and beyond, we assum e t hat n F = 1.) Som et im es referred t o as t he linking- current equat ion, t his is

sym m et rical in I C and I E and neglect s all com ponent s of base current and dependence of t he base widt h on VBC and VBE. To add an addit ional degree of applicabilit y t o t he real t ransist or, base- widt h m odulat ion m ust be added. We are int erest ed in a relat ion bet ween current s and volt ages for t he t ransist or in t he forward- act ive m ode. I n t his case, VBE is fixed at 0.4 < VBE < 0.6 V. On t his basis, basewidt h m odulat ion of t he em it t er – base j unct ion can be neglect ed. On t he ot her hand, t he relat ion m ust apply for a VBC range, which includes relat ively large negat ive values. Therefore, t he effect of base- widt h m odulat ion of t he collect or – base j unct ion m ust be included in a m odificat ion of ( B.20) . I f base- widt h m odulat ion due t o t he dependence of base widt h on VBC is added and t he subst it ut ion VBC = VBE – VCE is now m ade, ( B.20) becom es:

Equ a t ion B.2 1

The general equat ion m ust include any significant base current t hat cont ribut es t o collect or current , t hat is, for when t he base – collect or j unct ion becom es forward biased. For t his we use ( B.14) wit h base leakage current neglect ed. ( Leakage current is neglect ed t hroughout t his unit .) This is

Equ a t ion B.2 2

The –1 t erm has been ret ained in order for t he equat ion t o apply at all possible polarit ies and values for VBC = VBE – VCE, including zero where t his cont ribut ion of collect or current is zero. We not e t hat t his base current is in a loop ( Fig. B.8) t hrough t he base – collect or j unct ion and is posit ive out of t he collect or t erm inal; I C of ( B.21) is posit ive int o t he collect or t erm inal as in Fig. B.7. Thus, t he com ponent of base current from ( B.22) subt ract s from t he collect or current t o give

Equ a t ion B.2 3

Again, for sim plicit y, t his equat ion neglect s t he leakage current associat ed wit h t he collect or – base j unct ion [ I SC t erm ( B.14) ] , which is only a fair approxim at ion for t he level of I C at which we will obt ain an out put charact erist ic in t he param et er ext ract ion proj ect on t he BJT. A plot of t his equat ion for I C as a funct ion of VCE can be obt ained for const ant VBE or const ant I B. For t he lat t er, VBE is also a variable such t hat t he plot requires, in addit ion, a solut ion for VBE as a funct ion of VCE for const ant I B. I n t he proj ect on t he out put charact erist ic, t he m easured dat a and a SPI CE solut ion are com pared during t he m easurem ent . The input circuit provides a m ore or less const ant I B. However, t he SPI CE solut ion, which is com put ed by LabVI EW, is exact . I t allows for a variable I B and associat ed variable VBE. The SPI CE solut ion form ulat ion used by LabVI EW is out lined below in Unit B.7. The SPI CE solut ion is also explored in t he proj ect Mat hcad file.

Aft er m easuring t he out put charact erist ic, t he segm ent of t he result ing dat a array from t he act ive region ( VCE > VBE) is ext ract ed. From t hese dat a, a st raight - line curve fit is obt ained by LabVI EW, which produces a num ber for t he slope. From ( B.23) , we obt ain an equat ion for t he act ive region from let t ing VCE > VBE, wit h t he result

Equ a t ion B.2 4

The slope for t he act ive- region equat ion is slope = dI Cact / dVCE = I C/ VAF. Thus, VAF can be calculat ed from VAF = I C/ slope, where I C is t he value t aken from t he dat a array for VCE = VBE. For t he special case of VCE = VBE, one can obt ain a value for I S from t he relat ion

Equ a t ion B.2 5

Aft er VAF and I S have been obt ained, an it erat ion on βR will produce a final curve fit t o t he out put charact erist ic, t hereby providing a num ber for βR. I n t his m anner, all t hree param et ers of t his unit are obt ained: I S, βR, and VAF. An exam ple of a SPI CE out put charact erist ic ( calculat ed in Mat hcad) , which uses t he m easured t ransist or- m odel param et ers, is shown in Fig. B.13. Also shown is t he calculat ed act ive- region plot .

Figu r e B.1 3 . M a t h ca d ca lcu la t e d plot of t h e com ple t e ou t pu t ch a r a ct e r ist ic, ( B.2 3 ) , a nd t h e a ct ive - r e gion se gm e n t , ( B.2 4 ) . The sa t u r a t ion r e gion [ ( B.3 4 ) ] is gr a ph ica lly r e ve a le d w h e r e t h e plot s se pa r a t e .

The low- volt age region where I C < I Csat is called t he sat urat ion region. The volt age and current in t his region are VCEsat and I Csat . I n t he derivat ion of t he general equat ion for I C, ( B.23) , t he leakage current of t he base – collect or j unct ion was neglect ed. I f t his is not valid, t he reverse βR, which is det erm ined t hrough curve fit t ing, is som ewhat art ificial. For exam ple, suppose t hat t he leakage current t ot ally dom inat es t he collect or – base current . For t his case, t he general I C equat ion is

Equ a t ion B.2 6

where a new definit ion of a sort of βR is defined in t he relat ion I SC = I S/ βRleak . A curve fit t o t he m easured out put charact erist ic would give βRleak . However, because n C > 1, t he result depends on t he level of collect or current at which t he m easurem ent is m ade. I f, in a given m easurem ent , t he βRleak is int erpret ed as βR, it would funct ion as βR in SPI CE ( when assigning BR t o t he m odel) , but it would only be valid in a sim ulat ion for collect or current s close t o t hat of t he m easurem ent .

B.6 SPICE Solution for IC versus VCE of the Measurement Circuit All com ponent s of base current are t hose from ( B.12) ( forward m ode) and ( B.14) ( reverse m ode) . These are sum m ed t oget her t o obt ain t he following expression for t he general bias case:

Equ a t ion B.2 7

I n t he m easurem ent circuit of t he proj ect on t he out put charact erist ic of t he BJT, t he circuit will provide a current source at t he input and I B ( t o a good approxim at ion) will be a const ant . However, in t he event t hat a precision solut ion for I B and VBE is required, it can be obt ained by equat ing ( B.27) t o I B from t he input circuit equat ion ( Fig. B.12) , which is

Equ a t ion B.2 8

I n t he Mat hcad proj ect file, a solut ion for VBE as a funct ion of VCE is obt ained ( using a root finder) for a given VBB and RB. The result for VBE ( at a given VCE) is used in ( B.23) for a solut ion for I C, and hence t he out put charact erist ic is obt ained. For t his, t he leakage com ponent s of base current are neglect ed. I n t he LabVI EW out put charact erist ic m easurem ent proj ect , a SPI CE solut ion is obt ained along wit h t he m easurem ent . The solut ion is obt ained wit h LabVI EW using an it erat ive solut ion. The equat ions are ( B.28) and ( B.27) ( wit hout t he leakage t erm s) solved for VBE. This is

Equ a t ion B.2 9

The it erat ive m et hod consist s of guessing an init ial VBE and solving for I B from ( B.28) . This is used in ( B.29) , wit h t he given VCE, t o obt ain a bet t er value for VBE. The new VBE is t hen put back int o t he circuit equat ion, ( B.28) , and so on, unt il VBE st ops changing significant ly. This VBE is t hen used in ( B.23) for a solut ion for I C at t he specified VCE. For t he com plet e out put charact erist ic, t he solut ion is repeat ed in increm ent s of VCE for a range from zero up t o a specified m axim um . This is accom plished in LabVI EW wit h a Form ula Node in a While Loop. The analyt ical form ulat ion is explored in t he proj ect Mat hcad file. From ( B.29) , we not e t hat over t he full range of 0 < VCE < 5 V, for exam ple, t he lim it s of VBE are for VCE = 0,

Equ a t ion B.3 0

while for large VCE,

Equ a t ion B.3 1

The case of ( B.30) uses βF > > βR. For exam ple, for βF/ βR = 100, t he difference VBE( hi) – VBE( lo) VTln( βF/ βR) , which is about 120 m V. I n t he base circuit equat ion ( B.28) , t his change would be m inor com pared, for exam ple, wit h a base bias volt age, VBB, of 5 t o 10 V. Thus, base VBB = 5 V or current is close t o a const ant over t he full range of VCE, based on Chan1_out great er, as dict at ed by t he design goal. That is, VBB is m uch great er t han t he change in VBE as VCE m oves from ( B.30) t o ( B.31) . We not e t hat , consist ent wit h t he lim it of ( B.31) , t he solut ion for I B is from

Equ a t ion B.3 2

Therefore, I B and VBE are const ant and I C only varies wit h VCE due t o t he VCE dependence in ( B.24) . The value of t he lim it VCE is quant ified in t he next unit .

B.7 Collector-Emitter Voltage and Collector Current in the Saturation Region An equat ion for VCEsat ( VCE in t he sat urat ion region) can be obt ained using t he equat ions for I B, ( B.27) ( wit h leakage com ponent s neglect ed) , and I C, ( B.23) , t o elim inat e VBE. The approxim at e equat ion for I B is again

The equat ion for I C, ( B.23) , which neglect s t he VAF t erm ( well j ust ified at low volt age of t he sat urat ion region) , and t he –1 is

Equ a t ion B.3 3

Elim inat ing VBE bet ween t he approxim at e form of ( B.27) and ( B.33) gives

Equ a t ion B.3 4

where

Equ a t ion B.3 5

The subscript com es from " bet a forced," t he convent ional way t o define I C/ I B in t he sat urat ion region. Not e t hat by definit ion, βforced < βF, as I C < I Cact defines t he sat urat ion region.

For exam ple, we com put e VCEsat at I Csat = I C/ 2. Assum e t hat βF = 100 and βR = 1 such t hat βforced = βF/ 2 = 50. For t his case, VCEsat = 120 m V. Not e t hat t his is t he m idrange for t he validit y of ( B.30) .

I t should be not ed t hat VCEsat is not defined for βforced βF. This is because of t he neglect of t he –1 from t he equat ions. Technically, t he m axim um VCEsat is VCEsat VBE, as t his is t he m axim um VCE at which t he base – collect or j unct ion is forward biased, t he condit ion for t he onset of t he sat urat ion region. At VCE values very near VBE, t he –1 t erm s in t he current equat ions are not m at hem at ically negligible. On pract ical grounds, t hough, ( B.34) is valid for when t he out put charact erist ic is clearly in t he sat urat ion region.

A value for βR can be obt ained, using ( B.34) , from one set of dat a point s, I Csat and VCEsat from a m easurem ent , wit h βF known. I f t his proved t o vary wit h t he I Csat chosen for t he calculat ion, it would suggest t hat t he discussion at t he end of Unit B.5 applies. That is, t he leakage current is not negligible and t he effect ive βR, βRleak , is a variable t hroughout t he sat urat ion region.

B.8 DC as a Function of Collector Current bD C a s a Fu n ct ion of Collect or Cu r r e n t " h r e f= " ?x = 1 & m ode = se ct ion & sor t Ke y= t it le & sor t Or de r = a sc& vie w = & x m lid= 0 - 1 3 - 0 4 7 0 6 5 1 / ch 1 6 le v1 se c8 & ope n = t r u e & g= & ca t id= & s= 1 & b= 1 & f= 1 & t = 1 & c= 1 & u = 1 & r = & o= 1 & sr ch Te x t = " cla ss= " v2 " > SPI CE BJT βD C

B.9 Signal or Incremental Common-Emitter Current Gain

Since βDC/ I B is a variable funct ion of I C, t he increm ent al βac is, in general, different from t he dc βDC. ( The increm ent al βac is oft en referred t o as βo , but βac is consist ent wit h SPI CE.) To get an approxim at e value, we could calculat e βac from

Equ a t ion B.4 2

wit h I C1 = I C2 and where ( B.39) is used t o obt ain βDC at t he t wo current s. The definit ion of βac is from t he lim it ing case of I C2 I C1 , t hat is,

Equ a t ion B.4 3

Perform ing t his operat ion wit h t he use of ( B.39) leads t o

Equ a t ion B.4 4

The result indicat es t hat βac > βDC ( n E > 1) and t hat t he t wo converge in t he lim it for high I C. This is t he expression used in SPI CE for t he increm ent al βac, and it is used by SPI CE when NE and I SE are included in t he m odel. Ot herwise, SPI CE uses βac = βDC = βF. ( I f I S and BF are not specified in t he m odel, SPI CE will use default values, t ypically, BF = 100 and I S = 10 –16 A. For t he proj ect t ransist ors, I S is about 10 –13 A.)

B.10 Summary of Equations Com m on- em it t er dc current gain. Forward act ive- m ode out put charact erist ic relat ion. Forward base current .

Reverse base current .

Out put charact erist ic relat ion.

Collect or- em it t er volt age in sat urat ion region.

Collect or- current dependence of dc com m on- em it t er current gain.

Collect or- current dependence of increm ent al ( ac) com m on- em it t er current gain.

B.11 Exercises and Projects Proj ect Mat hcad Files

ExerciseB.m cd - Proj ect B1.m cd - Proj ect B.2.m cd - Proj ect B3.m cd

La bor a t or y Pr oj e ct Charact erizat ion of t he Bipolar Junct ion Transist or for Circuit B Sim ulat ion PB.3 PB.4

Diode- Connect ed Transist or Measurem ent s

Measurem ent of βDC versus t he Collect or Current

PB.5

BJT Out put Charact erist ic Measurem ent

PB.6

Sim ulat ion of t he Out put Charact erist ic Measurem ent

Unit C. Common-Emitter Amplifier Stage Analog am plifier st ages ( BJT) generally com prise t hree possible t erm inal configurat ions: com m on em it t er, com m on base, and com m on collect or ( em it t er follower) . As t he nam es suggest , in each case, t he input and out put are referred t o t he com m on t erm inal. The MOSFET equivalent s are com m on source, com m on gat e, and com m on drain ( source follower) , respect ively. As t he m ost fundam ent al of t ransist or am plifier building blocks, t he com m on- em it t er st age is t he logical configurat ion t o begin a st udy of signal am plifiers. The com m on- em it t er considered init ially in t his unit is obt ainable wit h a sim ple ext ension of t he dc m easurem ent circuit from Unit B ( Fig. B.12) . Based on t his circuit various aspect s germ ane t o signal am plifiers in general are discussed. I n Unit C.7, t he com m on- em it t er st age wit h act ive load is explored. Bot h t ypes of am plifiers, wit h resist ive and act ive loads, are invest igat ed ext ensively in proj ect s. The em it t er- follower st age is discussed in Unit C.9 along wit h a general t reat m ent of t he various effect s on t he com m on- em it t er st age wit h an em it t er- branch resist or. An ent ire unit ( Unit C.7) is devot ed t o t he source- follower st age, t he MOSFET equivalent of t he em it t erfollower st age. The com m on- gat e st age, t he MOSFET equivalent of t he BJT com m on- base st age, is considered ext ensively in conj unct ion wit h t he role it plays in t he different ial am plifier st age ( Unit 8) .

C.1 DC (Bias) Analysis The t wo com m on- em it t er am plifier- st age configurat ions st udied in proj ect s are shown in Fig. C.1. We not e t hat t he dc circuit of Fig. C.1( a) is t hat of Fig. B.12. Am plifier perform ance analysis can be perform ed wit h t he t wo out put channels available from t he DAQ in t he following m anner: Fig. C.1( a) uses separat e channels for t he input and out put bias circuit s and superim poses t he input signal on t he input bias. I n Fig. C.1( b) we add a signal- source resist or and coupling capacit or and use one channel for t he input signal and one channel for bias. The capacit or is required t o prevent t he connect ion of t he signal source from affect ing t he dc ( bias) operat ion of t he circuit . The lat t er represent s t he classical pract ical com m on- em it t er am plifier st age. The signal- source resist or provides for a current - source input signal and hence linear am plificat ion.

Figu r e C.1 . ( a ) Ba se cu r r e n t bia s ( dc) a n d in pu t sign a l a pplie d t o t h e sa m e n ode . Colle ct or cir cu it h a s a se pa r a t e pow e r su pply. ( b) Am plifie r w it h sign a l cou plin g ca pa cit or a n d sin gle pow e r supply for bia s.

I n t he experim ent al proj ect on t he com m on- em it t er am plifiers, we m easure t he volt age gain as a funct ion of t he collect or current and com pare t he result s wit h SPI CE. The bias collect or current is swept from 0.1 t o 1 m A. The m easurem ent uses t he circuit in Fig. C.1( a) . A DAQ out put channel ( VBB) set s t he bias current s. Anot her out put channel ( VCC) set s t he design bias VCE at each bias current . The gain of t he circuit of Fig. C.1( b) is also m easured wit h part icular em phasis on t he bias solut ion and t he frequency response.

C.1.1 DC (bias) Formulation A form ulat ion for obt aining t he collect or current for a given VBB [ Fig. C.1( a) ] is based on t he following: From t he input loop equat ion,

Equ a t ion C.1

The t wo relevant t ransist or charact erizat ion equat ions are ( B.6) ,

and base – em it t er dc volt age equat ion, from ( B.7) , set t ing VBC = 0 for sim plicit y,

Equ a t ion C.2

The equat ion set above has t hree unknowns, I C, I B, and VBE. The equat ions can be com bined t o obt ain a funct ion for I C,

Equ a t ion C.3

A good est im at e can be obt ained wit h using VBE

0.6 V, giving sim ply

Equ a t ion C.4

The sim ple expression is sufficient , for exam ple, for select ing a value for RB in t he circuit of Fig. C.1( a) in t he BJT am plifier proj ect . We have also neglect ed t he dependence of βDC on VBC of ( B.11) . This is a reasonable approxim at ion for est ablishing t he nom inal values for t he m easurem ent circuit com ponent s. The collect or – em it t er volt age, VCE, is t hen est ablished wit h

Equ a t ion C.5

I n designing a proj ect circuit for a current sweep, RB and RC are select ed for t he highest current s and highest DAQ out put volt age. I n t he am plifier proj ect , t he circuit of Fig. C.1( b) uses t he resist ors from t he circuit of Fig. C.1( a) . I t t hus has a unique bias variable and VCC solut ion for a given design VCE requirem ent . This is based on ( C.3) and ( C.5) and is

Equ a t ion C.6

I n t he am plifier proj ect , t he proj ect Mat hcad file is used t o find t he solut ion for VCC [ wit h an educat ed guess for VBE, as in ( C.4) ] . I f t he result has VCC > 10 V, t he lim it from t he DAQ, it is necessary t o decrease RC or increase RB. This m ay be necessary, as t he t ransist or βDC is not known wit h precision at t he point of t he select ion of t he resist or values. Aft er m easuring t he act ual VCC, t he result is used in t he Mat hcad file t o com put e a value for βDC from a circuit solut ion.

C.2 Linear or Signal Model for the BJT The prim ary funct ion of a t ransist or in analog circuit s is t o produce a signal out put current in response t o a signal input volt age. I n t he case of t he com m on- em it t er circuit s of Fig. C.1, t he t ransist or input volt age is Vbe and t he responding out put current is t he collect or current I c. ( Variable subscript convent ions are covered in Unit 2. Uppercase sym bols wit h lowercase subscript s denot e RMS or peak m agnit ude of periodic signals.) The linear relat ion bet ween t he t wo variables is t he t ransconduct ance, g m . By definit ion, for t he BJT

Equ a t ion C.7

I n som e sim ple am plifier circuit s, t his would be all t hat would have t o be known about t he t ransist or t o perform a design or analysis. More generally, however, t he m odel also includes input and out put resist ances, r i = r b + r π and r o , respect ively. The t ransist or linear m odel, which includes t hese com ponent s and a load resist or ( in t his case, bias resist or, RC) , is shown in Fig. C.2. Applied input volt age Vbe and responding I c are indicat ed.

Figu r e C.2 . Lin e a r sign a l m ode l for t h e BJT. M ode l pa r a m e t e r s a r e r b , r π, g m , a n d r o . Adde d t o t h e m ode l a r e cir cu it com pon e n t s R C a n d a pplie d volt a ge V be .

The input resist ance relat es t he input signal base current I b t o t he signal em it t er – base volt age, Vbe, t hat is

Equ a t ion C.8

Param et er r b is t he act ual physical resist ance t hrough which t he base current m ust flow t o arrive at t he t rue, int ernal physical base – em it t er j unct ion. The signal volt age across t he int ernal base – em it t er j unct ion is

. Param et er r π is t he linear relat ion bet ween I b and

and is not a physical resist ance. We assum e in t he following discussion t hat r π > > r b . This is especially t rue in t he low current range of our BJT t ransist or proj ect s. As will be seen below, r π is inversely proport ional t o bias collect or current , I C, whereas r b is close t o a const ant and could be significant at current s corresponding t o m idrange or higher for t he t ransist or. ( As a rule, r b m ust be t aken int o considerat ion when t he m odel is applied in very high frequency applicat ions.) Not e t hat neglect ing r b com pared t o r π is equivalent t o

, as assum ed below.

The out put - resist ance param et er, r o , account s for t he fact t hat t ot al collect or current , i C, increases wit h increasing t ot al collect or – em it t er volt age, v CE. According t o t he out put resist ance param et er relat ionship, t he current t hrough t his resist ance is

Equ a t ion C.9

I ncluding r o , t he current t hrough t he load, in t his case bias resist or, RC, is

Equ a t ion C.1 0

This current flows up t hrough RC such t hat Vce is negat ive for posit ive Vbe. Thus, t he current associat ed wit h r o subt ract s from g m Vbe t o reduce t he current t hrough RC. For a posit ive Vbe, t here is an increase in t he t ot al v BE, t hus causing t he t ot al collect or current t o increase. The result is a decrease in t he t ot al v CE and hence a negat ive increm ent al Vce. The t wo com ponent s of ( C.10) are illust rat ed graphically in Fig. C.3. The out put charact erist ics are for t wo values of base – em it t er volt age: bias only, VBE, and bias plus base – em it t er signal volt age, VBE + Vbe. They are designat ed Bias and Signal. The solut ion t o i C and v CE is const rained t o t he " load line," which is i Rc = i C = VCC/ RC – v CE/ RC [ ( C.5) ] .

Figu r e C.3 . Tr a n sist or ou t pu t ch a r a ct e r ist ic w it h n o sign a l a n d sign a l. Also plot t e d is t h e R C loa d lin e . Th e solu t ion for i C a n d v CE is a lw a ys t h e in t e r se ct ion .

At a const ant v CE = VCE, t he change in t he current - source current for t he applied Vbe is g m Vbe [ ( C.7) ] . The net collect or current change ( signal current ) , I c, t hough, is as given by ( C.10) ; t hat is, it includes t he com ponent associat ed wit h r o . Since t he out put charact erist ic slopes downward for decreasing v CE, t he act ual t ransconduct ance decreases, but t he linear m odel t reat s t his effect wit h a const ant g m com bined wit h t he effect of t he out put resist ance, r o .

C.2.1 Determination of the Linear Model Parameters We can relat e t he values of t he t wo param et ers in ( C.10) t o t he SPI CE m odel param et ers using ( B.7) wit h t he subst it ut ion v BC = –( v CE – v BE) . This is

Equ a t ion C.1 1

Different iat ing ( C.11) wit h respect t o v BE ( wit h v CE = VCE, Vce = 0) , g m is found t o be

Equ a t ion C.1 2

The approxim at e form only ignores a t erm on t he order of I C/ VAF, where VAF > > VT. The out put resist ance is obt ained wit h v BE = VBE ( bias value) or Vbe = 0. This is

Equ a t ion C.1 3

where, from ( C.11) , I C( v CE = VBE) = I Sexp( VBE/ VT) . For sim plicit y, t he bias collect or current , from ( C.11) , I C = i C( VCE) , is usually used for t he calculat ion for r o . Finally, a relat ion for r π com es direct ly from ( C.7) , I c = g m Vbe, and ( B.41) , I c = βacI b . Equat ing t he t wo gives

Equ a t ion C.1 4

Hence, from t he definit ion r π = Vbe/ I b ( wit h

)

Equ a t ion C.1 5

Not e t hat t he right - hand side of ( C.14) is t he alt ernat ive current - dependent current source of t he linear m odel of Fig. C.2.

As discussed in Unit B.9, βac can be slight ly different from βDC, but t he dist inct ion usually need not be m ade in analysis or design. This is due t o t he fact t hat βDC t ends t o be quit e variable am ong devices and t hat m ost analog designs are based on m aking t he result s as independent

of βDC as possible. Signal param et er βac will be used in t he following, but it is underst ood t hat βDC can be used in t he calculat ions wit hout serious penalt y in precision.

C.3 Amplifier Voltage Gain Any t ransist or am plifier st age has a gain from t he input t erm inal t o it s out put t erm inal ( base and collect or, respect ively, for t his case) . But t he circuit gain, from t he source t o t he out put , t akes int o considerat ion t he possible finit e input resist ance at t he t ransist or input t erm inal. Due t o t he finit e signal- source resist ance, an at t enuat ion result s from t he signal- source t o t he t ransist or input t erm inal. The exam ple of t his case of t he com m on- em it t er am plifier st age is considered here.

C.3.1 Gain from Base of Transistor to Output at Collector The m idband ( frequency- independent ) signal version of t he circuit of Fig. C.1( b) is shown in Fig. C.4. I t is obt ained from t he general circuit by convert ing dc volt ages t o zero. This includes t he capacit or volt age, which ideally, rem ains at it s const ant dc ( bias) value. The rule followed here is t hat if t here is no increm ent al variat ion bet ween any t wo nodes wit h a signal applied at t he input , t hen t he com ponent bet ween t he t wo nodes is superfluous. I n Fig. C.4, t he out put volt age is Vo = Vce and t he signal source is designat ed Vs along wit h it s source resist ance, Rs. I n t he case of an act ual signal source, Rs is probably an equivalent rat her t han an act ual resist or. Thus, it is assigned a lowercase subscript .

Figu r e C.4 . Sign a l e qu iva le n t cir cu it for t h e a m plifie r . dc n ode s h a ve be e n gr ou n de d a n d t h e ca pa cit or h a s be e n sh or t e d.

Neglect ing t he out put resist ance, t he signal collect or current for a signal volt age applied at t he base revert s t o ( C.7) , which is

wit h g m = I C/ VT [ ( C.12) ] . I C is t he bias current wit h uppercase subscript , not t he signal, wit h lowercase subscript . ( Recall t hat signal volt age and current s can be, for exam ple, periodic peak or RMS values or inst ant aneous values, as t hese are all proport ional t hroughout t he linear circuit . To be specific, as in t he experim ent on t he com m on- em it t er am plifier, we consider t hem t o be periodic- signal peak values.) The signal volt age developed at t he collect or is ( st ill assum ing t hat r o > > RC)

Equ a t ion C.1 6

From ( C.16) and ( C.7) , t he gain of t he t ransist or in t he circuit ( input at t he base of t he t ransist or and out put at t he collect or) is

Equ a t ion C.1 7

We not e t hat t he m agnit ude of t he result is t he dc volt age drop across t he bias resist or divided by VT. For exam ple, for VRc = 5 V and VT = 26 m V ( room t em perat ure) , t he gain m agnit ude is about 200. The BJT circuit is capable of providing very subst ant ial volt age gains.

C.3.2 Overall Gain Magnitude from Signal Source Voltage to Output The circuit input resist ance looking int o t he base of t he t ransist or, Rb , is t he t ransist or input resist ance, r π ( st ill neglect ing r b ) , in parallel wit h t he bias resist or RB, t hat is,

Equ a t ion C.1 8

The gain from t he signal source t o t he out put at t he collect or of t he t ransist or is t hus

Equ a t ion C.1 9

When t he input - signal source resist ance is large ( Rs > > Rb ) , a good approxim at ion for a v is

Equ a t ion C.2 0

Furt her approxim at ion can be m ade using RB > > r π, t o obt ain

Equ a t ion C.2 1

Finally, using βac = g m r π [ ( C.15) ] ,

Equ a t ion C.2 2

This result is int uit ive on t he basis of I b I s, I s approxim at ions for t he gain m agnit ude is

Vs/ Rs, and I c = βacI b . The sequence of

Equ a t ion C.2 3

An addit ional approxim at ion is wit h βac

βDC.

Not e t hat t he requirem ent for t he volt age gain t o be great er t han unit y is t hat Rs < βacRC. Thus, for sources wit h a large Rs, an am plifier design should have a high input resist ance st age such as an em it t er- follower st age. The em it t er- follower st age is discussed in Unit C.9. I n t he Proj ect C1 t he gain of t he am plifier as a funct ion of bias current , I C, is m easured using t he circuit of Fig. C.1( a) . This is m ade possible wit h t he use of LabVI EW and t he DAQ, wit h t wo out put channels, t o provide a signal source superim posed on t he input bias volt age. I n t his case, t he overall gain from t he signal source is rest rict ed ( input bias and signal source resist or ฀βacRC/ RB. Since RB of t he circuit is roughly βDCRC, t he gain is on t he are t he sam e) and a v order of unit y.

C.4 Accuracy of Transistor Gain Measurements We want now t o consider t he m easurem ent of t he gain of t he t ransist or am plifier ( Fig. C.1) based on t he linear m odel. This m odel is not valid if t he signals are t oo large, such as t o cause an unaccept able degree of nonlinearit y. I f t he linear m odel is valid, t he signal input volt age m agnit ude, bet ween t he base and em it t er of t he t ransist or, is relat ed t o t he fract ion I c/ I C according t o [ com bining ( C.7) and ( C.12) ]

Equ a t ion C.2 4

This volt age m ust be large enough for a good m easurem ent using t he DAQ board in t he com put er ( i.e., at least a few m illivolt s) , yet sm all enough so as not t o cause subst ant ial nonlinearit y, which would invalidat e t he m easurem ent of signal gain. Again, t he signal- gain concept is based on t he linear m odel. I n t he following, we will find t he condit ions under which t he linear m odel is valid and t o what ext ent . The general expression ( act ive region) bet ween t ot al collect or current and t ot al base – em it t er volt age, v BE = VBE + Vbe, is ( neglect ing t he VAF fact or) [ from ( B.7) ]

Equ a t ion C.2 5

or

Equ a t ion C.2 6

where t he lim it form for | I c/ I C| < < 1 gives ( C.24) . The plus sign is for I c and Vbe posit ive, and vice versa. Since t he signal out put volt age is Vo = –I cRC, t he signal " gain" is

Equ a t ion C.2 7

which reduces t o t he linear form , ( C.17) , when | I c/ I C| < < 1. I n t he am plifier proj ect , t he gain is obt ained by dividing t he m easured signal Vo by t he m easured signal Vbe. The circuit has Rs ( = RB) > > r π, such t hat I c βacVs/ Rs [ as in ( C.23) ] . As a

result , for t he posit ive and negat ive peaks of Vs, t he posit ive and negat ive peak m agnit udes of I c are equal. Thus, t he fract ion | I c/ I C| is t he sam e for bot h signal polarit ies. I ncrem ent al volt age Vbe will respond nonsym m et rically according t o ( C.26) . We not e t hat t his does not const it ut e a form of dist ort ion at t he out put , as is evident from t he approxim at e form of ( C.23) ( neglect ing a very sm all effect due t o variat ion of βac) . For out put current s on t he order of, for exam ple, | I c/ I C| = 0.5, t he plus and m inus peak values of Vbe are significant ly different . I n t he am plifier- gain m easurem ent proj ect , t he ac volt m et er indicat es a peak volt age, which is t he average of t he plus and m inus peak values. To som e ext ent , in t his m anner, t he error is canceled. A com parison is m ade of t he average value of t he peaks, Vbeavg , wit h t he dist ort ion- free Vbe, as shown in Fig. C.5.

Figu r e C.5 . Plot of ca lcu la t e d m e a su r e d V be a vg a s a fu n ct ion of fr a c = I c/ I C a n d dist or t ion - fr e e V be . Th e m e a su r e d va lu e e x h ibit s a 1 0 % e r r or a t | I c/ I C| = 0 .5 a n d V be = 1 2 .9 m a n d V be a vg = 1 4 .2 m V.

I n t he am plifier proj ect , t he m easurem ent base – em it t er volt age is lim it ed t o about | I c/ I C| = 0.2. This corresponds t o Vbe 5 m V. The m easurem ent error, due t o t he dist ort ion discussed here, is only about 1% for t his case. The m easurem ent circuit is configured t o be able t o m easure t he signal volt age wit h t he dc base – em it t er volt age rem oved. Therefore, t he DAQ conversion lim it can be set at t he 5 m V. m inim um of 50 m V, where t he resolut ion is m uch less t han Vbe

As not ed, a possible nonlinearit y in βac could be a cont ribut or t o nonlinearit y in t he gain funct ion ( C.22) . The effect from including t he βac nonlinearit y in t he developm ent of ( C.27) is also, t o a degree, canceled in t he averaging process of m easuring t he gain.

C.5 Effect of Finite Slope of the Transistor Output Characteristic As discussed in Unit C.2, t he signal m odel cont ains an out put resist ance, which reflect s t he fact t hat t he out put charact erist ic of t he t ransist or has a finit e slope. This is charact erized wit h t he SPI CE param et er VAF. I t was not ed t hat t he effect of t he finit e slope is t o place a resist ance effect ively across t he out put of t he am plifier. I t is calculat ed from r o = VAF/ I C, ( C.13) . Wit h increasing bias current , r o m ay not be negligible com pared t o RC. I n t he proj ect on t he gain of t he am plifier, we will read t he experim ent al dat a int o a Mat hcad file and adj ust VAF t o m ake t he SPI CE calculat ion and m easured dat a m at ch. The gain expression t hat includes t ransist or out put resist ance is

Equ a t ion C.2 8

I n a represent at ive t ransist or, VAF 100. The circuit design could call for I CRC 5 V for a 10- V supply volt age. I n t his case, t he out put resist ance has about a 5% effect on t he gain value.

C.6 Selection of Coupling Capacitors Ext ernal capacit ors are added t o t he circuit s of t his unit for t wo purposes. One, shown in Fig. C.1( b) , is t o connect t he signal input source t o t he am plifier. The ot her is a special- purpose capacit or of t he am plifier proj ect . I t is at t ached t o facilit at e m easurem ent of t he base – em it t er volt age wit h high resolut ion. Design considerat ions for select ion of t he capacit or values are discussed in t he following.

C.6.1 Coupling Capacitor for the Common-Emitter Amplifier The linear equivalent circuit of t he am plifier of Fig. C.1( b) is shown in Fig. C.6. The select ion of t he value of t he capacit or Cb is based on t he requirem ent t hat it has negligible effect on t he signal current at any frequency at which t he am plifier will be operat ed. I ncluding t he react ance of t he capacit or, t he input signal current is

Equ a t ion C.2 9

Figu r e C.6 . Sign a l m ode l of t h e cir cu it for t h e de t e r m in a t ion t h e ch a r a ct e r ist ic fr e qu e n cy of t h e fr e qu e n cy r e spon se a ssocia t e d w it h t h e cou plin g ca pa cit or .

The input signal current m agnit ude is

Equ a t ion C.3 0

where

Equ a t ion C.3 1

Frequency f 3dB is defined as t he frequency where t he response m agnit ude is

Equ a t ion C.3 2

I t follows t hat for t his case, f 3dB = f b . Not e t hat at f = 10f 3dB,

C.6.2 Coupling Capacitor for Measuring the Base Input Voltage I n Proj ect C1 m easurem ent of t he base input voltage is m ade at t he signal side of t he coupling capacit or. This is t he node designat ed by Vx in Fig. C.6. Good m easurem ent precision is provided, as t he dc com ponent of t he base voltage is blocked by t he coupling capacit or. The m axim um volt age sensed by t he input channel is only t he signal volt age Vb Vx 5 m V, as 0.5 V. I n t his configurat ion, t he discussed in Unit C.4. This value is m uch sm aller t han dc VBE lim it set t ing for t he input channel is set at 0.1 V, for a resolut ion of about 48 µV wit h t he input channel in t he bipolar m ode. I f t he peak signal volt age is, for exam ple 5 m V, t he resolut ion is about 1% of t he m easured volt age The required capacit or, Cb , for t his case and for sam e f 3dB, is subst ant ially larger t han t hat obt ained from ( C.31) . As will be shown, at f f 3dB, t he requirem ent is t hat | XCb | r π. I t follows t hat at f near f 3dB, Rs > > | XCb | since Rs > > Rb r π. The input signal current is t hus given approxim at ely by

Equ a t ion C.3 3

This includes t he good assum pt ion t hat Rs > > Rb and t hat , by design, | XCb | ( Technically, t he pole of t he t ransfer funct ion is ignored.)

Rb for f

f 3dB.

The signal volt age, Vx ( f) , at t he input signal source side of t he capacit or is t he sum of t he volt age at t he base plus t he volt age across t he capacit or, t hat is, wit h ( C.33) ,

Equ a t ion C.3 4

The rat io Vx ( f) / Vb is t hus

Equ a t ion C.3 5

Not e t hat t he form of Vx ( f) is falling, for increasing frequencies, t o a plat eau ( Vb ) . We will define f 3dB as t he frequency where t he m agnit ude of t his rat io is

. This could qualify as a

t ype of corner frequency, as it represent s t he frequency where t he frequency response funct ion is

t im es t he asym pt ot ic value. A solut ion for f 3dB t hen com es from

Equ a t ion C.3 6

giving

Equ a t ion C.3 7

At f= 10f 3dB, Vx = 1.005Vb . Not e t hat for t his case of a current source [ ( C.33) ] , t he value of t he capacit or can be obt ained sim ply t o sat isfy | XCb | = r π.

C.6.3 Coupling Capacitor for the Base Voltage Measurement of the DC Sweep Circuit The proj ect circuit for m aking a precision m easurem ent of t he gain of t he am plifier of Fig. C.1( a) is shown in Fig. C.7. The circuit has t he addit ion of Cb and Rs for m easuring t he base signal volt age wit hout t he dc com ponent . The select ion of Rs in t he am plifier proj ect is m ade t o sat isfy if Rs > > r π such t hat t he effect on t he gain referred t o Vs is sm all. The choice is, on t he ot her side, Rs < RB, such t hat t he charging t im e of Cb is not prohibit ively long during t he bias sweeps. The f 3dB frequency at Vx for t his case is ( C.31) wit h f b = f 3dB. I n t he am plifier proj ect , t he capacit or is select ed from ( C.37) t o sat isfy t he requirem ent for t he am plifier of Fig. C.1( b) using ( C.37) . The capacit or will t hus cert ainly be adequat e for t he am plifier of Figs. C.1( a) and C.7.

Figu r e C.7 . Com m on - e m it t e r a m plifie r for m e a su r in g t h e a m plifie r ga in a s a fu n ct ion of bia s cu r r e n t . Th e sign a l ba se – e m it t e r volt a ge is m e a su r e d a t V x .

C.7 Common-Emitter Amplifier with Active Load I n t he early days of elect ronic am plifiers, t he volt age am plificat ion device was, of course, t he vacuum t ube. I t exist ed in only one polarit y configurat ion, t hat is, wit h posit ive plat e ( bus or rail) volt age. Wit h t he appearance of sem iconduct or t ransist ors cam e t he availabilit y of t he dual set of devices wit h opposit e t erm inal volt age polarit ies. This is t he case for BJTs, JFETs, and MOSFETs. ( Vacuum t ubes were im plem ent ed in class B am plifiers. The applicat ion required a pair of input s, one 180° out of phase wit h t h e ot her, norm ally derived from a t ransform er.) The dual set has provided t he versat ilit y for a wide range of elect ronic syst em applicat ions, including t he am plifier wit h act ive load shown in Fig. C.8. This can be com pared wit h t he circuit of Fig. C.1, which in place of t he pnp t ransist or, has a bias collect or resist or, RC.

Figu r e C.8 . Com m on - e m it t e r a m plifie r w it h a ct ive ( t r a n sist or ) loa d. Th e n pn is t h e dr ive r t r a n sist or a n d t h e pn p is t he loa d t r a nsist or . The in pu t sign a l sou r ce cou ld be m ove d t o t h e ba se of t h e pnp, in w h ich ca se t h e t w o t r a n sist or s pla y opposit e r olls.

Not e t hat eit her t ransist or base could serve as t he input such t hat t he opposit e t ransist or becom es t he load. I n Fig. C.8, t he npn is chosen as t he driver t ransist or and t he pnp as t he load t ransist or. A dc out put charact erist ic plot is shown in Fig. C.9. Since t he collect or current of t he individual t ransist ors is t he sam e, t he solut ion t o bias volt age VCE for t he npn is t he int ersect ion of t he t wo curves, t hat is, 5 V. This would be a good choice for a bias out put volt age for t he power supply volt age of t his case, which is 10 V. For t he plot s, VAFn = 100 V and VAFp = 20 V were used. ( I n t he discussion of t he npn – pnp am plifier, t he added subscript n or p will denot e npn or pnp, respect ively.)

Figu r e C.9 . Out pu t cha r a ct e r ist ics for t h e n pn a nd pn p t r a n sist or s. Th e pn p e m it t e r – colle ct or volt a ge is v EC = V CC – v CE, w he r e v CE is t he colle ct or – e m it t e r volt a ge of t he n pn . The bia s va r ia ble s V CE, V EC, a n d I C a r e a t t h e in t e r se ct ion of t h e t w o plot s.

A signal im pressed at t he base of t he npn causes t he npn curve t o m ove up or down while t he pnp curve rem ains in place. Not e t hat t he pnp act s like a load line of a resist ive load; however, an ext ension of t he act ive- region charact erist ic of t he pnp int ersect s t he zero- current axis at VCC + VAFp = 30 V. The pnp act ive- load t ransist or t hus provides t he equivalent of a bias resist or wit h a power supply of 30 V inst ead of t he act ual 10 V.

C.7.1 Gain of the NPN – PNP Common-Emitter Amplifier with Active Load The gain benefit for t he case of t he act ive load is apparent from t he following. The equat ion for t he gain of t he BJT com m on- em it t er am plifier wit h resist or RC, which includes t he out put resist ance of t he driver t ransist or ( in t his case, npn) , is a form of ( C.28)

Equ a t ion C.3 8

where r on is t he out put resist ance of t he npn and is given by [ generalizat ion of ( C.13) ]

Equ a t ion C.3 9

where VCE and VBE are t he t ransist or bias volt age variables and I C is t he collect bias current of t he am plifier. Param et ers VAFn and VAFp are used in t his unit for t he slope param et er for t he npn and pnp, respect ively. The out put resist ance expression is generalized here t o em phasize t hat st rict ly speaking, t he collect or current s and volt ages m ust m at ch as suggest ed in t he expression. Volt ages VBE and VCE are bias values. I n t he following, as is st andard in elect ronics circuit analysis, we approxim at e t he out put resist ance, for exam ple, for t he npn as follows:

Equ a t ion C.4 0

I t follows t hat for t he pnp

Equ a t ion C.4 1

where I C

I C( VCE) , t hat is, t he act ual bias collect or current .

For t he pnp act ive load, t he resist or RC is now replaced wit h t he out put resist ance of t he pnp, t o obt ain

Equ a t ion C.4 2

where t he far right - hand side uses g m = I C/ VT. The gains for t he resist ive load and act ive load cases can readily be com pared wit h t he subst it ut ion of g m = I C/ VT in ( C.38) ( gain wit h load RC) and ( C.40) for r on t o obt ain

Equ a t ion C.4 3

For t he exam ple of VCC = 10 V and bias VCE = 5 V, VRc = 5 V. Using VAFn = 100 V and VAFp = 20 V, t he room - t em perat ure gain m agnit udes are | a vbRc| = 4.76 V/ 0.026 V= 183 for t he am plifier wit h Rc load com pared t o an npn – pnp am plifier gain m agnit ude of | a vb | = 16.7 V/ 0.026 V= 641. I n pract ice, t he advant age will be considerably m ore, as t he value for VAFp used here is sm aller t han norm al for BJTs. The sm all num ber was used above in t he plot ( Fig. C.9) t o exaggerat e t he effect of t he slope.

C.7.2 Output Resistance at the Collector with an Emitter Resistor I n Proj ect C2 t he effect of an em it t er resist or in t he em it t er branch of t he pnp, REp , on t he out put resist ance of t he pnp will be explored. The circuit is shown in Fig. C.10. The effect of t he em it t er resist or is t o increase t he out put resist ance, due t o t he negat ive feedback effect , at t he collect or of t he pnp. This increase can be m ade t o be subst ant ial; in fact , t o a good approxim at ion, t he load on t he am plifier is only r on of t he npn.

Figu r e C.1 0 . Am plifie r w it h a n e m it t e r r e sist or in e m it t e r br a n ch of pn p t o in cr e a se t h e ou t pu t r e sist a n ce a t t h e colle ct or of t h e pnp. Also in clu de d is a ca pa cit or , Cb , for gr ou n din g ( sign a l) t h e ba se volt a ge of t h e pn p.

The generalized gain expression, which includes t he effect of t he em it t er resist or, is

Equ a t ion C.4 4

where Rop is t he out put resist ance at t he collect or of pnp, for t he circuit wit h REp . Here, we develop an expression for t he out put resist ance of a BJT wit h t he em it t er resist or. This is a funct ion of bot h REp and RBp . I n t he Proj ect C2 t he am plifier gain is m easured wit h and wit hout a base shunt capacit or, Cb . Wit h t he capacit or in place, t he base resist ance in t he signal circuit is effect ively zero, and t his alt ers Rop significant ly. The linear circuit for t he general case of a BJT com m on- em it t er am plifier wit h em it t er resist or is shown in Fig. C.11. The circuit includes a base resist or, RB.

Figu r e C.1 1 . Lin e a r cir cu it for t h e de t e r m in a t ion of t h e out pu t r e sist a n ce a t t h e colle ct or for a cir cu it w it h e m it t e r a n d ba se r e sist or .

A t est volt age, Vo , is applied at t he collect or wit h t he base resist or and em it t er resist or at signal ground. I n response, a current I o flows from Vo t hrough RE in parallel wit h RB + r π. This induces a volt age VRE = ( I o – I b ) RE across RE t hat is applied t o r π in series wit h RB. Base current I b is a fract ion of I o as given by

Equ a t ion C.4 5

Applied volt age Vo sum s up t o

Equ a t ion C.4 6

The approxim at ion is based on r o > > RE and is consist ent wit h t he fact t hat t he signal volt age drop across t he out put of t he t ransist or is m uch great er t han across t he em it t er resist or. Elim inat ing I b in ( C.46) using ( C.45) result s in t he solut ion for Ro , which is

Equ a t ion C.4 7

The result has t wo lim it ing form s based on t he relat ive value of RB: When RB > > r π + RE,

Equ a t ion C.4 8

The approxim at e form uses I C I nt uit ively, for RB For RB

I E.

, t he feedback current , g m I b r π, goes t o zero.

0,

Equ a t ion C.4 9

The alt ernat ive form s on t he right in ( C.48) and ( C.49) use ( C.15) , βac = g m r π. Again, t he approxim at e form uses I C I E. Not e t hat t he solut ion corresponds t o t he m axim um fract ion of I o t hat can flow t hrough r π( RB = 0) , t o induce a feedback current . When applied specifically t o t he npn – pnp circuit of Fig. C.10, t he lim it ing case is, for RBp zero,

Equ a t ion C.5 0

where Rop is t he signal resist ance looking up int o t he collect or of t he pnp. For exam ple, if REp is select ed t o produce VREp = 1 V and βacp = 50, t he denom inat or is roughly 2, such t hat Rop ( βacp / 2) r op . I n t his case, t he load on t he am plifier is due alm ost ent irely t o t he out put resist ance looking int o t he collect or of t he npn ( Ron = r on ) , wit h t he result t hat t he gain is [ from C.44]

Equ a t ion C.5 1

The ot her ext rem e is for RBp > > r πp + REp , where Rop repeat ed here

r op [ ( C.48) ] . The gain revert s t o ( C.42) ,

The npn – pnp am plifier circuit of Fig. C.10 is used in t he proj ect on t he am plifier t o invest igat e t he signal- derived m agnit ude of t he slope param et ers of npn and pnp t ransist ors. Using a bypass capacit or at t he base of t he npn, as discussed below, t he signal circuit will effect ively have RB = 0, and a gain m easurem ent along wit h ( C.51) yields VAFn . The gain will also be m easured for t he circuit wit hout t he capacit or and wit h RBp > > r πp + REp ( by design) . For t his case, ( C.42) applies and t he gain m easurem ent provides inform at ion on t he com binat ion out put resist ance param et er, VAFnp . Bet ween t he t wo m easurem ent s, values for bot h param et ers are det erm ined. I n t he m easurem ent circuit of t he npn – pnp am plifier, t he gain referred t o t he signal source ( am plifier circuit gain) is

Equ a t ion C.5 2

where Ronp is t he signal resist ance at t he out put node ( Fig. C.10) , t hat is, t he com bined resist ance looking back int o t he collect s of t he npn and pnp t ransist ors. I n general, t his is

Equ a t ion C.5 3

Wit h RBp effect ively m ade zero wit h t he shunt ing capacit or, Ronp capacit or, Rop is obt ainable from ( C.47) for use in ( C.53) .

r on = VAFn / I C. Wit hout t he

I n t he am plifier proj ect , t he circuit - gain equat ion ( C.52) is used t o convert m easured gain int o Ronp and t hen inform at ion on VAFn and VAFp . Wit h t he availabilit y of t hese num bers, we can t hen calculat e t he gain produced by t he t ransist or ( base t o collect or) , using ( C.44) .

C.7.3 DC (Bias) of the NPN – PNP Amplifier The circuit equat ions for t he circuit of Fig. C.10 are ( collect or power supply t hrough pnp base)

Equ a t ion C.5 4

and ( npn base)

Equ a t ion C.5 5

I n t he proj ect on t he am plifier, RBp is det erm ined for a design collect or current . The select ion uses ( C.54) wit h, for exam ple, VCC 9 V, t hat is, less t han t he m axim um available from t he DAQ out put . Then wit h RBn = RBp , VBBn will be less t han VCC by t he am ount of t he drop across REp ( for exam ple, 1 V) . This m akes t he good assum pt ion t hat βDCn βDCp , A LabVI EW program t hen set s up t he circuit for t he design collect or current by adj ust ing t wo supply volt ages ( DAQ out put channels) .

C.8 Frequency Response of NPN – PNP Amplifier Due to the Base Shunt Capacitor I n t he npn – pnp am plifier proj ect , we det erm ine VAFn direct ly t hrough a gain m easurem ent for a circuit configurat ion in which ( C.51) is valid. The requirem ent t hat RBp 0 will be im plem ent ed by shunt ing t he base of t he pnp t ransist or t o ground wit h a capacit or, Cb , as shown in Fig. C.12. The capacit or m ust be sufficient ly large t o hold t he base at ground at t he frequency of t he gain m easurem ent s.

Figu r e C.1 2 . Se gm e n t of t h e n pn – pn p a m plifie r of Fig. C.1 0 sh ow in g t h e a ddit ion of a pn p ba se - bypa ss ca pa cit or , Cb .

The expression t o det erm ine t he required value of Cb can be obt ained as follows: We st art wit h t he expression for Ro wit hout Cb , which is ( C.47) and repeat ed here ( referring t o t he generalized circuit Fig. C.11) :

Wit h t he capacit or in parallel wit h RBp , RB in ( C.47) is replaced wit h t he im pedance of t he parallel com binat ion of RBp and Cb . The result ing Rop is frequency dependent and is given by

Equ a t ion C.5 6

This can be m anipulat ed int o t he form

Equ a t ion C.5 7

where

Equ a t ion C.5 8

and

Equ a t ion C.5 9

The approxim at e form uses RBp > > r πp + REp . At f f 1 , Rop ( f 1 ) r op , such t hat a good approxim at ion is obt ained wit h dropping t he " 1" in t he num erat or. The approxim at e form is t hen

Equ a t ion C.6 0

Furt her rearranging leads t o

Equ a t ion C.6 1

where

Equ a t ion C.6 2

and

Equ a t ion C.6 3

The approxim at e form again uses RBp > > r πp + REp .

Mat hcad- generat ed plot s of t he m agnit ude of Rop ( f) using ( C.57) ( and f 2 and f z exact ) and ( C.61) ( wit h t he approxim at e form s for f 2 and f z) are shown in Fig. C.13. These are for VAFp = 150 V, βacp = 50, RBp = 330 KΩ, REp = 800 Ω, Cb = 2 µF and I C = 1 m A. Charact erist ic frequencies are f z = 1.9 Hz and f 2 = 38.2 Hz. The approxim at e form is very close t o t he exact form except in t he lowest frequency range. For f 0, Rop ( f) r op in bot h cases. For exam ple, in t he exact and approxim at e cases, Rop ( f) = 1.12r op and Rop ( f) = 1.05r op , respect ively, for f = 0.

Figu r e C.1 3 . M a t h ca d- ge n e r a t e d plot s of t h e m a gn it u de of R op ( f) u sin g ( 5 7 ) a n d ( 6 1 ) . Th e ca lcu la t ion m a de w it h t he a ppr ox im a t e for m , ( 6 1 ) , a lso u se s t h e a ppr ox im a t e for m s for f 2 a n d f z .

Subst it ut ing Rop ( f) for Rop in ( C.52) , we obt ain t he frequency- dependent am plifier- circuit gain

Equ a t ion C.6 4

Then using ( C.61) for Rop ( f) in ( C.64) result s in

Equ a t ion C.6 5

where

Equ a t ion C.6 6

The approxim at e form uses Ropm ax > > r on and t he approxim at e f 2 and f z. The design frequency f 3dB is obt ained from form s of f 2 , f z, and f p , f 3dB sim plifies t o

[ ( 6.8) ] . Ut ilizing t he approxim at e

Equ a t ion C.6 7

The result is significant ly lower t han f 2 in ( C.61) because Rop ( f) is in parallel wit h r on , which is m uch sm aller t han t he high- frequency value of Rop ( f) . The param et er βacp appears from t he associat ion βacp = g m r πp [ ( C.15) ] . Mat hcad- generat ed plot s of ( C.65) for t he exact and approxim at e values for f p and f z are shown in Fig. C.14. The param et er and com ponent values are from t he plot s of Fig. C.13 wit h t he addit ion of VAFn = 250 V, βacn = βacp = 50, and RBn = RBp = 330 kΩ. Wit h capacit or Cb = 2 µF, f 3dB = 3.8 H ( exact f p and f z) and f 3dBapprox = 4.5 Hz [ ( C.67) ] .

Figu r e C.1 4 . Plot s of ( C.6 5 ) w it h a ppr ox im a t e a n d e x a ct va lu e s for f z , ( C.6 3 ) , a n d f p , ( C.6 6 ) . Th e a ppr ox im a t e for m is su fficie nt ly close for se le ct in g Cb .

C.9 Common-Emitter Stage with Emitter Resistor and the Emitter-Follower Amplifier Stage I t was shown t hat t he em it t er resist or of t he m easurem ent circuit of Fig. C.10 can have a significant effect on out put resist ance. The em it t er resist or has t he effect of increasing t he input resist ance as well, such t hat it is com pat ible wit h high- resist ance sources and t he resist or adds t o t he bias st abilit y. The com m on- em it t er st age wit h an em it t er resist or is, in fact , a very com m on configurat ion in BJT elect ronics. Here, we analyze t he effect of t he em it t er resist or on t he input resist ance ( at t he base) and on t he gain of t he com m on- em it t er st age. The developm ent leads direct ly t o an assessm ent of t he signal perform ance of t he em it t er- follower ( com m on- collect or) st age. The t wo aspect s of t he circuit wit h t he em it t er resist or are discussed in t he following.

C.9.1 Input Resistance in the Common-Emitter Emitter-Resistor Circuit The discussion is applicable t o t he circuit of Fig. C.10, where t he input resist ance is at t he base of t he pnp. I n t his circuit , RE REp and, for t he analysis, a base signal volt age, Vb , is applied direct ly t o t he base of t he pnp. A general signal circuit for a com m on- em it t er st age ( out put , Voce) wit h em it t er resist or is shown in Fig. C.15. Also indicat ed is t he out put for t he em it t erfollower st age ( Voef ) .

Figu r e C.1 5 . Lin e a r cir cu it for de r ivin g t h e in put r e sist a n ce of t h e com m on - e m it t e r st a ge w it h e m it t e r r e sist or . The a m plifie r ou t pu t n ode s for t h e com m on - e m it t e r st a ge ( V oce ) a n d t h e e m it t e r - follow ( V oe f ) st a ge a r e in dica t e d.

Assum e t hat r o > > RL, such t hat we can neglect t he current t hrough r o . ( This assum pt ion is violat ed in t he circuit of Fig. C.10, as t he load is t he out put resist ance of t he npn, r on .) Wit h t his sim plificat ion, t he loop equat ion at t he input of t he circuit is

Equ a t ion C.6 8

having used Vbe = I b r π. The input resist ance at t he base is t hus ( wit h respect t o signal ground)

Equ a t ion C.6 9

The following form of t he result provides a convenient way of assessing t he effect of t he resist or on t he input resist ance:

Equ a t ion C.7 0

The result shows t hat wit h RE in t he circuit , t he input resist ance is increased over t hat of t he circuit wit hout RE by a fact or of approxim at ely VRE/ VT. For exam ple, wit h VRE = 1 V, VRE/ VT is about 40 at room t em perat ure. For t he npn – pnp circuit of Fig. C.10, Rib at t he base of t he pnp is som ewhat less t han given by ( C.70) because t he effect ive load, t hat is, r on , is so large and t he sim plificat ion m ade above, r o > > RL, is not valid. However, as is usually t he case in design, such approxim at e form s are sufficient . This t akes int o considerat ion t hat exact solut ions are not required or j ust ified, given t he variat ion in t he m odel and circuit param et ers t hat nat urally occur. I f bet t er precision is, however, required, a good approxim at ion for ( C.70) is readily obt ained by replacing, in ( C.70) , 1 + βac wit h . This is specifically applied t o t he circuit of Fig. C.10, where t he input is at t he base of t he pnp and r on RL and t he out put resist ance of t he pnp is r op . The approxim at ion is based on t he expect at ion t hat Voce > > Voef Fig. C.15 such t hat t he volt ages across r on and r op are sim ilar.

Equ a t ion C.7 1

Suppose t hat t he gain expression is applied t o t he circuit of Fig. C.1( b) but wit h an em it t er resist or inst alled. From t he signal source, t he gain is t hen

Equ a t ion C.7 2

where t he resist ance at t he base, Rb , is now

Equ a t ion C.7 3

Wit h ( C.71) for t he base- t o- out put gain,

Equ a t ion C.7 4

The result shows t hat t he m axim um gain is approxim at ely RL/ RE. Therefore, alt hough t he circuit can have good bias st abilit y, t he em it t er resist or seriously reduces t he signal gain. The circuit wit h a bypass capacit or would have a gain given by ( C.19) . The circuit wit h a bypass capacit or would st ill have t he advant age of bias st abilit y. Essent ially all pract ical com m onem it t er circuit s have t he em it t er resist or, wit h or wit hout t he bypass capacit or. A t wo- st agecircuit significant volt age gain wit hout a capacit or is discussed in t he next unit .

C.9.2 Emitter-Follower Amplifier Stage When t he out put is t aken at t he em it t er inst ead of at t he collect or ( Fig. C.15) , t he circuit becom es an em it t er- follower am plifier st age. ( The collect or resist or is unnecessary and t he collect or t erm inal is connect ed t o t he power supply.) The out put volt age in t his case is

Equ a t ion C.7 5

The em it t er- follower st age gain ( t ransfer rat io) is t he rat io of ( C.75) and ( C.68) , t hat is

Equ a t ion C.7 6

A m agnit ude assessm ent can be m ade from

Equ a t ion C.7 7

For exam ple, wit h VRE = 1 V, a vef = 0.97 at room t em perat ure. The input resist ance, from ( C.70) , for t he sam e condit ions in addit ion t o I C = 0.1 m A and βac = 100 is Rib = 1 MΩ. The em it t er- follower st age is seen t o have a gain of approxim at ely unit y and a very high input resist ance. I t s prim ary role is t herefore t hat of a buffer st age. An alt ernat ive form for t he em it t er- follower st age gain is

Equ a t ion C.7 8

This is equivalent t o a unit y- gain am plifier wit h an out put resist ance of 1/ g m . The out put resist ance is, for exam ple, about 26 Ω at I C = 1 m A. Therefore, when an ext ernal load is at t ached t o t he em it t er- follower st age out put , t he gain rem ains near unit y for very sm all load values. An exam ple of an applicat ion t hat t akes advant age of t he charact erist ics of t he em it t erfollower st age is shown in Fig. C.16. This is a cascade of an em it t er- follower st age and a com m on- em it t er st age. The overall gain is t he product of t he input net work funct ion and t he gains of t he t wo st ages. That is,

Equ a t ion C.7 9

where . For exam ple, suppose t hat βac = 100 and t hat t he bias collect or current s are I C1 = 0.1 m A and I C2 = 10I C1 = 1 m A. The em it t er resist or is RE = VBE/ I C1 = 6000Ω ( neglect ing t he base current , I B2 ) wit h VBE = 0.6 V such t hat and t he gain of t he em it t er- follower st age is 0.87. Wit h VCC = 10 V and VCE = 5 V, t he gain of t he com m on- em it t er st age is –192. Bot h gains are at room t em perat ure. Therefore, t he gain from t he base of t he em it t er- follower st age t o t he out put is –168.

Figu r e C.1 6 . Ca sca de of a n e m it t e r - follow e r st a ge a n d a com m on e m it t e r st a ge . Th e ove r a ll ga in is t h e pr odu ct of t he ga in s of t he se pa r a t e st a ge s. Th e loa d on t h e e m it t e r - follow e r st a ge is r π2 of t he com m on - e m it t e r st a ge .

The input resist ance at t he base of t he em it t er follower is Rib 500 kΩ. Assum e, for exam ple, t hat RB 50 kΩ. The overall gain for t his case is –136. By com parison, t he circuit , which om it s t he em it t er- follower st age ( RB connect ed direct ly t o t he base of t he com m on- em it t er st age) , has a gain of –9.5.

C.10 Summary of BJT Model Parameter Relations Transconduct ance.

Em it t er- base j unct ion com m on- em it t er st age input resist ance.

Collect or – em it t er out put resist ance.

Tot al base – em it t er input resist ance.

C.11 Summary of Circuit Equations Base current equat ion for com m onem it t er am plifier.

Collect or current equat ion for com m on- em it t er am plifier. Collect or power- supply volt age solut ion com m on- em it t er am plifier wit h single power supply. Base- t o- collect or gain. Neglect int ernal out put resist ance of driver t ransist or. Overall gain from funct ion generat or ( signal source) . Overall gain wit h very large source resist or, Rs, as in am plifier gain experim ent s. Rs > > rπ, RB > > rπ. Base- t o- collect or gain expression t hat includes t he out put resist ance of t he t ransist or. Base- t o- collect or large- signal " gain" t hat includes nonlinearit y of I C, VBE relat ionship. Linear relat ion applies when I c/ I C rat io is sm all enough for ln( 1 + I c/ I C) I c/ I C. General solut ion for base- t o- collect or gain for npn – pnp am plifier wit h em it t er resist or, REp . Out put resist ance at collect or wit h em it t er resist or ( general) .

Base- t o- collect or gain of npn – pnp am plifier, REp = 0. Approxim at e base- t o- collect or gain of npn – pnp am plifier wit h em it t er resist or REp ( and RBp = 0) . Frequency- dependent out put resist ance at t he collect or of pnp wit h REp

Base current equat ion for com m onem it t er am plifier.

Charact erist ic frequencies of Rop ( f) funct ion.

Frequency- dependent am plifier gain of npn – pnp am plifier wit h em it t er resist or and base- bypass capacit or. Charact erist ic frequency of a v ( f) funct ion.

Maxim um out put resist ance at t he collect or of t he pnp wit h em it t er resist or. Design equat ion for select ing Cb for npn – pnp m easurem ent circuit .

I nput resist ance at base of com m onem it t er st age wit h em it t er resist or. Gain of t he em it t er- follower st age.

Alt ernat ive form of t he gain of t he em it t er- follower st age.

C.12 Exercises and Projects Proj ect Mat hcad Files

ExerciseC1.m cd – Proj ect C1.m cd – ExerciseC2 – Proj ect C2.m cd

La bor a t or y Pr oj e ct C1

NPN Com m on- Em it t er Am plifier

PC.2

DC Circuit Set up and Param et er Det erm inat ion

PC.3

Am plifier Gain at One Bias Current

PC.4

Am plifier Gain versus Bias Current

PC.5

Gain- Measurem ent Frequency Response

La bor a t or y Pr oj e ct C2

NPN – PNP Com m on- Em it t er Am plifier wit h Current - Source Load

PC.7

Measurem ent of t he PNP Param et ers

PC.8

DC Circuit Set up

PC.9

Measurem ent of t he Am plifier Gain

Laboratory Project 1. Basic Circuit Analysis for Electronic Circuits and Programming Exercises P1.1 Resist or Volt age- Divider Measurem ent s P1.2 Resist or Volt age Divider wit h Current Measurem ent P1.3 Resist or Volt age Divider wit h Resist or Measurem ent P1.4 Resist or Volt age Divider wit h a Sine- Wave Source Volt age P1.5 Frequency Response of a Resist or- Capacit or Circuit Exercises and Analysis Exercise01.m cd - Proj ect 01.m cd

P1.1 Resistor Voltage-Divider Measurements

Com pon e n t s

Pr ogr a m m in g Ex e r cise 1 .1 Use Tab t o swit ch bet ween Tools. Use Space Bar t o swit ch bet ween Wiring Tool and Posit ion Tool ( arrow) . Get Tools Palet t e under Windows m enu ( or Shift / Right Click) from t he Diagram .

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Open a new VI t o const ruct your VI _ 0 1 .vi. The VI opens wit h a Front Panel ( t op) and a Diagram ( under) . Swit ch from one t o t he ot her using t he Windows m enu or Ct rl/ E. The VI opens wit h t he Operat e Value Tool

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Place a Digit al Cont rol and Digit al I ndicat or on t he Front Panel ( exam ple below) . ( Right Click on Front Panel t o get t he Cont rols Palet t e.) The Digit al Cont rol and Digit al I ndicat or are in t he Num eric Palet t e ( below) . Save t he file wit h your choice of Nam e.

Go t o t he Diagram ( Ct rl/ E) or Window> > Show Diagram . Place a Sequence St ruct ure in t he Diagram . ( Right Click on Diagram t o get Funct ions> > St ruct ures> > Sequence St ruct ure.) Enlarge t he St ruct ure by cont act ing t he Arrow Tool ( Posit ion Tool) at t he bot t om - right corner of t he St ruct ure ( drag) .

Right Click on t he edge of t he Fram e and Add Fram e Aft er. Click on arrows t o swit ch bet ween Fram e 0 and Fram e 1.

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Place AO Updat e Channel.vi in Fram e 0. ( Funct ions> > Dat a Acquisit ion> > Analog Out put > > AO Upda t e Cha n ne l.vi.) Place AI Sam ple Channel.vi in Fram e 1. ( Funct ions> > Dat a Acquisit ion> > Analog I nput > > AI Sa m ple Cha n ne l.vi.)

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Posit ion t he icons, et c., wit h t he Arrow Tool ( Left Click> > Drag) . Wire t he Digit al Cont rol ( darker) t erm inal t o t he value t erm inal of t he Analog Out put VI , AO Upda t e Cha n ne l.vi. Press t he space bar t o alt ernat e bet ween t he Wiring Tool and Posit ion ( arrow) Tool. To wire, get t he Wiring Tool ( space bar) , Left Click on a t erm inal, release, drag t he Tool t o t he opposit e t erm inal, and Left Click. To clean up wiring m ist akes, use Ct rl/ B. Not e t hat t he t erm inal nam e ( value in t he exam ple) of

an icon is displayed while t he Wiring Tool is over t he t erm inal.

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Wire t he Digit al I ndicat or t erm inal ( light er) t o t he out put t erm inal ( sam ple) of t he Analog I nput VI , AI Sa m ple Ch a n n e l.vi. Place t he Const ant ( 4) and t he St ring ( 0) in t he Diagram as shown in t he exam ple ( Fram e 0) . Use t he Writ ing Tool t o t ype in t he num bers. The locat ion of Const ant s and St rings, under Funct ions, is shown below. Place Const ant s ( 4) , ( 10) and ( 0) and St ring ( 0) in Fram e 1.

Wire t he Const ant s and St rings as shown in t he exam ples. To wire, get t he Wiring Tool ( space bar) , Left Click on a t erm inal, release, drag t he Tool t o t he opposit e t erm inal, and Left Click. To clean up wiring m ist akes, use Ct rl/ B.

Change t he nam es of t he Digit al Cont rol and Digit al I ndicat or. Use t he Writ ing Tool. This can be done from t he Diagram or t he Front Panel. Click on t he exist ing nam e ( e.g., Num eric) and edit .

Pr oce du r e •

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Calculat e t he resist or values. Connect t he circuit . To Run a VI , from t he Front Panel, use Operat e> > Run or ( bet t er) use Ct rl/ R. Ru n t he VI wit h Chan0_out = 10V ( Vout ) and not e t he value of Chan0_in ( VRG2) . This should be consist ent wit h your resist or rat io choice. Try a variet y of Chan0_out values. ( The m axim um is 10 V.)

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( Opt ional) To inst all t he circuit Diagram on t he Front Panel, open VI _ 0 1 .vi from Pr oj e ct 0 1 .llb. Use t he Arrow Tool, Click on t he circuit diagram , use Window's copy ( Ct rl/ C) , and past e it int o you VI Front Panel.

P1.2 Resistor Voltage Divider with Current Measurement

La bVI EW Com put a t ion

Pr ogr a m m in g Ex e r cise 1 .2 •

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Save a copy of VI _ 0 1 .vi ( your nam e) and give it a new nam e ( such as # 2) . On t he Front Panel, place a Digit al I ndicat or for I RG ( Cont rols> > Num eric) . On t he Front Panel, place a Digit al Cont rol for t he resist or value. ( Cont rols> > Num eric.) I n t he Diagram ( below) place a Divide operat ion. ( Funct ions> > Num eric> > Divide.) Wire t he Diagram as in t he exam ple.

Pr oce du r e •

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Set your value of RG2 in t he Digit al Cont rol ( MΩ) . To set in t hree digit s, change t he precision. Right Click on t he Cont rol, go t o Form at and Precision, and change Digit s of Precision.

Ru n VI _ 0 2 .vi wit h Chan0_out set at 5 V and not e t he value of I RG. Default and save t he Front Panel for com parison wit h t he Mat hcad evaluat ion file. For Default , m enu Operat e> > Make Current Values Default .

P1.3 Resistor Voltage Divider with Resistor Measurement

Ba sic sa m ple sh ow n be low .

Pr ogr a m m in g Ex e r cise 1 .3 •

Save a copy of VI _ 0 2 .vi wit h a new nam e and add Digit al I ndicat ors for VRG1 and RG1 as in VI _ 0 3 .vi ( basic sam ple below) . The new VI will find and indicat e t he value of RG1.

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I n t he Diagram , we will add Ge t Y Va lue .vi. This VI is found in t he Funct ions Palet t e wit h t he sequence shown on t he left . Not e t hat t he full Palet t e Set is required. Your Palet t e m ay be an abbreviat ed form called Basic. I f so, open t he Palet t e and use t he St ick Pin t o keep it open. Then Click on Opt ions as shown below. Select t he default Palet t e Set .

Ge t Y Va lu e .vi is used t o ext ract a given Y value in a waveform . AI Sa m ple Ch a n n e l.vi is a special case of a waveform wit h only one com ponent . I n t he VI of part P1.2, we connect ed t he out put direct ly t o a Digit al I ndicat or, in which case, La bVI EW sort ed out t he com ponent value aut om at ically. Place Ge t Y Va lue .vi as shown in t he Diagram ( cursor, Arrow) . Connect t he balance of t he circuit as shown. The new m at h form ulat ions are indicat ed below and in t he Diagram .

La bVI EW Com pu t a t ion s

Pr oce du r e •

Ru n t he VI _ 0 3 .vi for Chan0_out set at 10 V. Not e t he value of RG1 and VRG1. Default and save t he Front Panel for t he Mat hcad evaluat ion file.

P1.4 Resistor Voltage Divider with a Sine-Wave Source Voltage

Pr oce du r e •

The VI sends out , on Chan0_out , a sine- wave superim posed on t he dc value. Add t he connect ion, Chan1_in, direct ly t o t he out put channel. Ru n t he VI for various values of Chan0_out . Not e t hat t he m axim um allowed Chan0_out is about 6 V since t he dc and ac peak m ust be less t han 10 V. Verify t hat t he result s are consist ent . For exam ple, t he peak ac values m ust be 1.5 of t he dc values since Vs = VDD/ 2. Default and save t he Front Panel using Chan0_out = 4V.

P1.5 Frequency Response of a Resistor-Capacitor Circuit

Com pon e n t s C1 = C2 f 3dBhi = 50f 3dBlo Rs

RG/ 50

f 3dBlo = 5 Hz ( approxim at ely)

Typical C1

0.5 µF

Pr oce du r e •

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Configure t he circuit for t he low- end m easurem ent and f 3dBlo . I nst all C1 and do not inst all C2 . Ru n VI _ 0 5 .vi t o obt ain f 3dBlo . Obt ain a Log of t he Front Panel t o save t he result s. To obt ain a Log, go t hrough m enu sequence Operat e> > Dat a Logging> > Log. To ret rieve dat a: Operat e> > Dat a Logging> > Ret rieve. An exam ple of ret rieving a Log using VI _ 0 1 .vi is shown here. Not e t hat at t he first Dat a Logging, you will be asked t o nam e a Dat a Log file. Select any nam e and Click Save, t o inst all Log File in t he Proj ect folder.

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Now m ove t he capacit or C2 = C1 t o t he C2 locat ion and inst all a large capacit or, C1new , in place of C1 , which sat isfies C1new > > C2 ( e.g., C1new = 47 µF) . Not e t hat t he source side of t he capacit or ( connect ed t o Rs) is m ore negat ive t han t he out put side ( Chan0_in) . Ru n VI _ 0 5 .vi t o obt ain f 3dBhi . Default and save t he Front Panel. Not e t hat when reopening t he VI , t he Front Panel will cont ain t he inform at ion last default ed from t his f3dBhi m easurem ent . The first m easurem ent is in t he dat a Log. Repeat ing, t o ret rieve t he inform at ion from t he dat a Log, go t hrough m enu sequence Operat e> > Dat a Logging> > Ret rieve. To t hen go back t o t he default ed Front Panel, click OK and go t hrough Operat e> > Reinit ialize All t o Default Values. Not e t hat if C2 = C1 are act ually bot h in t he circuit at t he sam e t im e, t he out put in t he plat eau region is 1/ 2 as large ( Exercise 1) . This configurat ion is not im plem ent ed here. The use of C2 = C1 is only for convenience and f 3dBlo < < f 3dBhi is sat isfied wit h Rs < < RG.

Laboratory Project 2. Basic NMOS Common-Source Amplifier with Programming Exercises P2.1 NMOS Com m on- Source Circuit wit h Drain Current Measurem ent P2.2 NMOS Com m on- Source Am plifier wit h Resist or Gat e Bias Circuit P2.3 Am plifier wit h Signal and Gain Measurem ent Exercises and Analysis Exercise02.m cd - Proj ect 02.m cd

P2.1 NMOS Common-Source Circuit with Drain Current Measurement

Ch ip D ia gr a m Conn e ct pin 1 4 t o Ch a n0 _ ou t . M a in t a in Ch a n 0 _ ou t > Cha n 1 _ out .

Com pon e n t s

Pr ogr a m m in g Ex e r cise 2 .1 •

On t he Front Panel of a New VI , inst all t wo Digit al Cont rols and t wo Digit al I ndicat ors ( Am pP2 .1 .vi) . Also inst all a Menu Ring ( Cont rols> > Ring and Enum > > Menu Ring) .

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I n t he Diagram ( below) , place, from left t o right , one Case St ruct ure: Funct ions> > St ruct ures> > Case, and t wo While Loops: Funct ions> > St ruct ures> > While Loop.

On t he Front Panel, using t he Text Tool ( Shift / Right Click for Tool Palet t e) in t he Menu Ring, t ype 10 V. Right Click on t he Menu Ring and execut e Add I t em Aft er. I n t he new list ing, t ype 6 V. Go t o t he Diagram and wire t he out put of t he Menu Ring t o t he " ?" on t he edge of t he Case St ruct ure. Not e t hat t he I t em s correspond t o int egers 0 and 1 at t he t erm inal. I n t he Diagram , place t wo copies of AO Upda t e Ch a n n e l.vi in t he first ( left ) While Loop and place AI Sa m ple Cha n n e l.vi in t he right - hand Loop. I n t he lat t er, also place Ge t Y Va lu e .vi ( Funct ions> > Waveform > > Waveform Operat ions> > Ge t Y Va lue .vi) . Connect t he const ant s and Front Panel t erm inals as in t he exam ple. I nst all const ant values 10 and 6 in t he 0 and 1 case st at es, respect ively, and wire t o t he value t erm inal of t he Chan0_out AO Upda t e Ch a n n e l.vi icon. Configure t he current com put at ion funct ion as in t he exam ple ( lower- right side in Diagram ) and wire t o t he current Digit al I ndicat or and resist or Digit al Cont rol. Opt ionally, relabel t he Digit al Cont rols and Digit al I ndicat ors

according t o t heir funct ions ( as in Am pP2 .1 .vi) . Pr oce du r e •

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Connect t he circuit using t he RD select ed. I nst all t he value of RD( MΩ) in t he Digit al Cont rol. To obt ain t hree digit s of precision in t he resist or Digit al Cont rol, Right Click on t he Cont rol and go t o Form at and Precision... Set Digit s of Precision. Ru n Am pP2 .1 .vi wit h VDD ( Chan0_out ) set at 10 V. Adj ust VGS ( Chan1_out ) for a drain volt age, VDS, of roughly 8 t o 9 V. Obt ain a log of t he Front Panel t o preserve t he current ( I D) and VGS inform at ion for t he Mat hcad file. Rem inder: Dat a Logging is under t he Operat e m enu. Now reset VDD t o 6 V and re- r u n . Not e t hat VDS drops by roughly 4 V, indicat ing t hat t he t ransist or drain t erm inal is a current source. Not e t hat t he change in t he I D indicat ed is only slight . Reset VDD = 10 V. I ncrease VGS by an am ount t hat m akes VDS about 2 t o 3 V. Not e t he increase in drain current . Log t he Front Panel t o preserve t he inform at ion for t he Mat hcad file.

P2.2 NMOS Common-Source Amplifier with Resistor Gate Bias Circuit

Com pon e n t s

Pr ogr a m m in g Ex e r cise 2 .2 •

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Save a copy of Am pP2 .1 .vi ( your nam e) and give it a new nam e. As in t he exam ple ( below) , use t hree While Loops t o send Chan0_out and receive on Chan0_in and Chan1_in. Not e t hat t he index " i" of a loop on t he left is connect ed t o t he border of t he following Loop t o est ablish t he proper order of execut ion of t he program . Provide Digit al I ndicat ors for VGS and VDS.

Pr oce du r e •

2RG2 ) . Ru n Am pP2 .2 .vi wit h VDD set at 6 V t o obt ain VGS of about 2 V ( due t o RG1 Rer u n and adj ust VDD t o obt ain VDS equal t o about one- half of VDD. Not e t hat decreasing VDD raises VDS t oward VDD. Default and save t he Front Panel for t he Mat hcad evaluat ion.

P2.3 Amplifier with Signal and Gain Measurement

Pr ogr a m m in g Ex e r cise 2 .3 follows below. ( Advanced- Opt ional) Pr oce du r e •

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Move t he bot t om of RG2 from ground t o Chan1_out . The VI will send out a sine- wave signal via t his channel wit h peak Vs. Set Chan0_out ( VDD) as in VDD/ 2) . t he circuit for P2.2 above ( for VDS Ru n Am pP2 .3 .vi ( Pr oj e ct 0 2 .llb) for various values of Vs. Re- set for a Vo peak of about 1V ( VDS/ 3) . Not e t he gains, which are Vo/ Vs and Vo/ Vg. Verify t hat t he gain from t he source is about t wo- t hirds of t he gain t he gat e, based on t he select ion ( rat io) of t he gat e bias resist ors. Default and save t he Front Panel for t he Mat hcad evaluat ion.

Pr ogr a m m in g Ex e r cise 2 .3 •

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Make a copy of Am pP2 .2 .vi wit h a new nam e. Go t o t he Diagram and delet e all except Cont rol and I ndicat or t erm inals. I nst all a Sequence St ruct ure in t he Diagram ( below) . I n t he first Fram e, inst all AO Upda t e Cha nn e l.vi. ( Funct ions> > Dat a Acquisit ion> > Analog Out put .)

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Press Ct rl and drag ( wit h Arrow Tool) an addit ional copy, also in Fram e 0. Connect a volt age- out ( VDD, Chan0_out ) value as shown in t he exam ple. Connect a num eric 0 ( value) t o set Chan1_out init ially t o 0 V for t he dc m easurem ent s. Connect channel num bers ( St ring) and device num ber ( Num eric, 4 in t he exam ple) .

Add a Fram e Aft er. I n t his Fram e ( 1) , inst all t wo copies of AI Acqu ir e W a ve for m .vi. ( in m enu Funct ions> > Dat a Acquisit ion> > Analog I nput .) These will be used for t he dc m easurem ent s. A given node volt age will be sam pled 100 t im es and t he sam ples will be averaged for t he result . Connect const ant s t o t he icons as shown in t he exam ple. These include device ( Num eric, 4, default ) , channel ( St ring) , num ber of sam ples ( Num eric, 100) , sam ple rat e ( Num eric, 10000) , high lim it ( 10 V) and low lim it ( 0 V) . Place t wo copies of Get Waveform Com ponent s in Fram e 1 ( Palet t e Funct ions> > Waveform > > Get Waveform Com ponent s) . Then Left Click on t he out put ( right side) of t hese and select " Y" . Connect t he input s t o t he waveform out put s of AI Acquire Waveform . Connect t he out put s of Get Waveform Com ponent s t o t he input s of M e a n .vi funct ions. These are locat ed in Funct ions> > Mat hem at ics> > Probabilit y and St at ist ics or in Funct ions> > Analyze> > Mat hem at ics> > Probabilit y and St at ist ics. Connect t he out put s of t he M e a n.vi icons t o t he t erm inals of t he Digit al I ndicat ors of VDS ( Chan0_in) and VGS ( Chan1_in) . Add a Fram e Aft er ( 2) . I n t his Fram e we place a general- purpose funct ion generat or and oscilloscope funct ion. This is FG1 Cha n .vi and is in Funct ions> > User Libraries> > Funct Gen. A Digit al Cont rol and a Digit al I ndicat or are required for t his Fram e. I nst all Digit al Cont rol, Vs, and Digit al I ndicat or, Vo.

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Connect t o FG1 Cha n .vi, t he various t erm inals, const ant s, and st rings. The connect ions include Frequency ( Num eric, 50) , Vacin ( Vo) , Chan_out ( St ring, 1) , Sinewave - SqWave ( False) , Graph Out ( leave disconnect ed for now) , Chan_in ( St ring, 0) , Vs ( Digit al Cont rol) , and VDCout ( Num eric, 0) . Now add anot her Fram e aft er ( 3) . I n t his Fram e, inst all t he sam e funct ion, FG1 Ch a n .vi. This can be copied and past ed from Fram e 2. Add, in t he Front Panel, an addit ional Digit al I ndicat or, Vg. Make t he connect ions t he sam e as in Fram e 2 except Chan_in ( St ring, 1) . I n Fram e 2, configure, using a divide funct ion, Vo/ Vs, as shown in t he exam ple. Add a Digit al I ndicat or in t he Front Panel wit h t he label Vo/ Vs and connect t he out put from t he divide funct ion t o t he t erm inal of t his Digit al I ndicat or. Click on t he edge of Fram e 2 and inst all Add Sequence Local and, t o t his, Connect Vacin ( Vo) . Move t o Fram e 3, inst all a Divide funct ion, and configure Vo/ Vg as in t he exam ple. Not e t hat Vo com es from t he Add Sequence Local from Fram e 2. I n t he Front Panel, add an addit ional Digit al I ndicat or t o read Vo/ Vg. Now add t he graph in t he Front Panel. ( A det ailed descript ion of using a graph is given in Sect ion A.1.5.) The graph for t his case is a Waveform Graph. Get t his in t he Front Panel under Cont rols> > Graph> > Waveform Graph. Use t he Coloring Tool t o adj ust t he color of t he graph background by Right Clicking on t he graph wit h t he Coloring Tool. Right Click on t he sam ple t race in t he Plot Legend t o adj ust t he color of t he t race. Using t he Operat ing Tool, Right Click on t he X Scale or Y Scale> > Form at t ing t o set t he Grid Opt ions. Configure t he Diagram for connect ing t o t he graph. Out side t he Sequence St ruct ure and on t he right , inst all a Build Array funct ion. ( Funct ions> > Array> > Build Array.) Connect t he Plot out put of FG1 Cha n .vi in t he t wo Fram es, 2 and 3, t o t he t wo input s of Build Array. Connect t he out put of Fram e 2 on t he t op input .

Laboratory Project 3. Characterization of the PMOS Transistor for Circuit Simulation P3.1 SPI CE Param et ers and Pin Diagram P3.2 SPI CE Equat ions P3.3 PMOS Transist or P3.4 Low- Volt age Linear Region of t he Out put Charact erist ic P3.5 PMOS Param et ers from t he Transfer Charact erist ic P3.6 PMOS Lam bda from t he Transfer Charact erist ic P3.7 PMOS Out put Charact erist ic P3.8 PMOS Lam bda Exercises and Analysis Exercise03.m cd - Proj ect 03.m cd

P3.1 SPICE Parameters and Pin Diagram SPI CE PARAM ETERS SPI CE N a m e

M a t h Sym bol

D e scr ipt ion

VTO

Vt no , Vt po

Zero VSB t hreshold volt age.

KP

Transconduct ance param et er.

GAMMA

γn , γp

Threshold volt age param et er.

LAMBDA

λn , λp

Act ive- region slope param et er.

CD 4 0 0 7 Pin D ia gr a m

P3.2 SPICE Equations SPI CE Equ a t ion ( PM OS)

N M OS Eq.

D e scr ipt ion

3.2

Out put charact erist ic low- volt age conduct ance.

3.10

Out put charact erist ic for full linear range ( 0< VSD< Veffp ) .

3.8

Act ive region t ransfer charact erist ic and out put charact erist ic ( VSD> Veffp ) .

3.12

Act ive region relat ion solved for VSG.

P3.3 PMOS Transistor Use pins 6 ( gat e) , 14 ( source) , and 13 ( drain) . Connect t he NMOS body ( pin 7) t o t he m ost negat ive node, Chan1_out , for PM OSpa r a m .vi. Leave pin 7 disconnect ed when running PM OSout put .vi. Not e t hat t he source and body for t his t ransist or are int ernally connect ed. Not e t hat Chan0_in is used for posit ive volt ages only. Thus, it is always set aut om at ically for t he unipolar m ode, which slight ly im proves t he resolut ion. Chan1_in m ust m easure posit ive and negat ive volt ages.

P3.4 Low-Voltage Linear Region of the Output Characteristic

Com pon e n t s

La bVI EW Com pu t a t ion s

Pr oce du r e •

Ru n PM OSline a r .vi and adj ust VSGst art ( V) such t hat Veffpst art ( V) > 0.5 V. The m axim um I D is set for 0.1 V. Ru n t he VI t o obt ain param et ers as indicat ed in t he Front Panel. Default and save t he Front Panel t o save inform at ion for t he Mat hcad analysis.

P3.5 PMOS Parameters from the Transfer Characteristic

Com pon e n t s

La bVI EW Com pu t a t ion s

Pr oce du r e •

Ru n PM OSpa r su b.vi wit h VSD = 3 V and VSD = 9 V. VDD ( Chan0_out ) st art s at 2 V such t hat t he m inim um current is I Dm in = ( 2 V – VSGm in) / RS. I D st ops aut om at ically at I D = 500 µA or Chan0_out = 10 V. Verify t hat t he VI funct ions properly. PM OSpa r sub.vi will run as a subVI of t he next VI .

P3.6 PMOS Lambda from the Transfer Characteristic

Com pon e n t s

La bVI EW Com pu t a t ion s

Pr oce du r e •

Ru n PM OSpa r a m .vi t o r un subVI PM OSpa r sub.vi at VSD = 3 V and VSD = 9 V t o resolve Lam bda and final values of kp and Vt po. Default and save t he Front Panel t o save t he param et er values for t he Mat hcad result s analysis file.

P3.7 PMOS Output Characteristic

Com pon e n t s

La bVI EW Com pu t a t ion s Line a r Re gion

Act ive Re gion

Pr oce du r e •

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I nst all PMOS param et ers from P3.6 int o t he Front Panel of PM OSout put .vi. A given VSD sweep will halt at Chan0_out = 10 V. Set VSGst art ( V) as necessary t o obt ain I D 100 µA for VSD in t he act ive region. Verify t hat t he m easured dat a and SPI CE calculat ion agree reasonably well. Writ e in you file pat h and save a dat a file for Mat hcad. The file will cont ain t he dat a point s for t he highest current out put charact erist ic. Default Front Panel and save. These dat a will be used in t he Mat hcad analysis file. Wit h t he dat a default ed and saved in t he graph of t he VI , a dat a file can be obt ained at a lat er t im e. From t he Diagram of PM OSou t pu t .vi, click on XYt oD a t a File .vi, copy t he dat a from PM OSout put .vi, and past e it int o t he Cont rol Graph of XYt oD a t a File .vi. Nam e t he pat h and dat a file and r u n t he VI . XYt oD a t a File .vi is locat ed in t he User.lib in t he LabVI EW folder. Therefore, it can also be opened from t he Diagram of a VI under Funct ions> > User Libraries> > Dat _File.

P3.8 PMOS Lambda La bVI EW Com pu t a t ion s St raight - line curve fit from act ive region dat a: I D = Slope · VSD + I Do

λp = Slope/ I Do k p = I Do / Veffp 2 Pr oce du r e •

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La m bda .vi is configured for Enable Dat a Base Access t o read t he dat a from PM OSou t put .vi. La m bda .vi can read all of t he Front Panel inform at ion in PM OSout put .vi when a log of t he Front Panel has been obt ained. From t he Diagram of La m bda .vi, open PM OSou t pu t .vi. Obt ain a dat a log of t he Front Panel of t he PM OSout put .vi ( under Operat e Menu) . Ru n La m bda .vi t o read t he graph of m easured dat a ( from PM OSout put .vi) and t o plot t he m easured dat a from t he act ive region. The VI obt ains Kp and λp from t hese dat a, for each of t he volt age sweeps. Not e t hat Lam bda varies. Com pare t he average Lam bda value wit h t hat from PM OSpa r a m .vi. Click on Ca ll Plot I D _ VSD .vi Gr e e n t o bring up a plot of t he act ive- region equat ion plot for –1/ λp < VSD < VSDm ax , com pared wit h t he m easured dat a. La m bda .vi will be used in t he Mat hcad analysis file.

Laboratory Project 4. Characterization of the NMOS Transistor for Circuit Simulation P4.1 SPI CE Param et ers and Chip Diagram P4.2 NMOS Transist or P4.3 SPI CE Equat ions P4.4 NMOS Param et ers from t he Transfer Charact erist ic P4.5 NMOS Lam bda from t he Transfer Charact erist ic P4.6 NMOS Gam m a SubVI P4.7 NMOS Gam m a P4.8 NMOS Circuit wit h Body Effect Exercises and Analysis Exercise04.m cd - Proj ect 04.m cd

P4.1 SPICE Parameters and Chip Diagram SPI CE PARAM ETERS SPI CE N a m e

M a t h Sym bol

D e scr ipt ion

VTO

Vt no , Vt po

Zero VSB t hreshold volt age.

KP

Transconduct ance param et er.

GAMMA

γn , γp

Threshold volt age param et er.

LAMBDA

λn , λp

Act ive- region slope param et er.

CD 4 0 0 7 Pin D ia gr a m

P4.2 NMOS Transistor Use CD4007 pins 3 ( gat e) , 4 ( source) and 5 ( drain) . Connect pin 4 ( source) t o pin 7 ( body) . Connect PMOS body ( pin 14) t o t he m ost posit ive node in t he NMOS m easurem ent s, Chan0_out or ground, depending on t he circuit . I n t he γn m easurem ent ( N M OSga m m a .vi) and t he t ransfer charact erist ic m easurem ent ( N M OS_ Cir .vi) , pin 14 is connect ed t o ground. Not e t hat t he NMOS of pins 6, 7, and 8 has int ernally connect ed body and source. This t ransist or is used in a following proj ect .

P4.3 SPICE Equations SPI CE Equ a t ion

D e scr ipt ion

3.8

Act ive region t ransfer charact erist ic and out put charact erist ic ( VDS > Veffn , VSB = 0) .

3.12 Act ive- region equat ion solved for VSG.

3.14 Threshold volt age dependence on VSB. X variable for Vt n versus X plot in γn det erm inat ion.

P4.4 NMOS Parameters from the Transfer Characteristic

La bVI EW Com pu t a t ion s

Com pon e n t s

Pr oce du r e •

Set RS value. Run NMOSparsub.vi and adj ust VSSinit for a m inim um I D

50

µA. Test run NMOSparsub.vi wit h VDS = 3 V and 10 V. Execut ion halt s at I D 500 µA. The VI runs as a subVI in t he next part . Default and save. Saved VSSinit is used in t he Top VI in t he next part .

P4.5 NMOS Lambda from the Transfer Characteristic

Com pon e n t s

La bVI EW Com pu t a t ion s

Pr oce du r e •

Se t RS. Ru n N M OSpa r a m .vi t o obt ain a set of NMOS param et ers. The VI runs N M OSpa r sub.vi aut om at ically wit h VDS = 3 V and VDS = 10 V. The sweep st ops at I D 500µA or | Chan0_out | = 10 V. Default and save t he VI .

P4.6 NMOS Gamma SubVI

Com pon e n t s

Not e: VGS will be larger wit h t he body effect .

Pr oce du r e •

Not e t hat PMOS body pin 14 and t he NMOS drain t erm inal are at ground. Set RS and VSSinit from N M OSpa r su b.vi. Run N M OSga m su b.vi wit h VSB = 0 V and 3 V t o verit y t hat circuit is funct ioning properly. Not e t he change in t he VGS range for t he larger VSB. VSSinit is adj ust ed aut om at ically for larger values of VSB, t o obt ain, approxim at ely, a st art ing I D of about 50 µA. Default and save t he Front Panel t o save VSSinit .

P4.7 NMOS Gamma

Com pon e n t s

La bVI EW Com pu t a t ion s

Pr oce du r e

•

Set RS. Wit h N M OSga m sub.vi open, r u n N M OSga m m a .vi t o obt ain Gam m a. Adj ust 2φF t o t ry t o m at ch Vt no ( int ercept , curve fit ) wit h Vt no ( VSB = 0, t ransfer charact erist ic, graph on right ) . Save t he result s.

P4.8 NMOS Circuit with Body Effect Com pon e n t s Use RS from N M OSga m m a .vi.

Pr oce du r e •

Set RS. I nst all SPI CE param et ers from N M OSpa r a m .vi and N M OSga m m a .vi. Ru n N M OS_ Cir .vi t o obt ain I D versus VGS wit h a sweep of VSS. The it erat ion solut ion obt ained in SPI CEga m m a .vi ( Diagram below) is com pared in t he graph of N M OS_ Cir .vi. Adj ust VSSinit t o obt ain I Dm in of about 50µA. Re- adj ust Gam m a for best fit . Then save a dat a file wit h your dat a file nam e. The dat a file m ust be in t he folder wit h t he Mat hcad file. The file nam e m ust have a * .prn ext ension.

• •

A file can be obt ained from t he graph of t he default ed and saved VI using XY1 t oD a t a File .vi. The VI XY1 t oD a t a File .vi is locat ed in \ \ LabVI EW 6\ User.lib\ Dat _Files\ D a t .llb. Not e t hat XY1 t oD a t a File .vi is different from XYt oD a t aFile 2 .vi, as used t o obt ain a dat a file in t he Diagram of N M OS_ Cir .vi. The Cont rol Graph of XYt oD a t a File 2 .vi accept s single plot s while XY1 t oD a t a File .vi is for graphs wit h t wo Y funct ions ( wit h only one Y funct ion in t he dat a file) . For convenience, a copy of XY1 t oD a t a File .vi, Ge t D a t a File .vi, is included in t he Pr oj e ct 0 4 .llb. For clarificat ion, XY1 Y2 t oD a t a File .vi accept s graph dat a wit h t wo Y funct ions and includes bot h in t he dat a file.

Laboratory Project 5. PMOS CommonSource Amplifier P5.1 SPI CE Equat ions and Pin Diagram P5.2 PMOS Com m on- Source Am plifier DC Set up P5.3 Am plifier Gain at One Bias Current P5.4 Am plifier Gain versus Bias Current Exercises and Analysis Exercise05.m cd - Proj ect 05.m cd

P5.1 SPICE Equations and Pin Diagram CD 4 0 0 7 Pin D ia gr a m

SPI CE Equ a t ion

D e scr ipt ion

3.8 ( NMOS)

DC drain current volt age relat ion ( PMOS) .

5.6

Gain versus I D .

5.7

Gain versus I D , Veffp .

P5.2 PMOS Common-Source Amplifier DC Setup

La bVI EW Com pu t a t ion s

Com pon e n t s

Pr oce du r e •

I nst all RD value. Adj ust VSG in Se t VSD .vi and r u n t he VI t o find t he value for I DMAX = 500 µA ± 50 µA. VSS is ram ped up from 10 V ( default value) t o find t he value for VD = –4 V. Not e t hat if RD is t oo large, VD will be > –4 V init ially ( for VSS = –10 V) at I Dm ax . Default and save t he Front Panel.

P5.3 Amplifier Gain at One Bias Current

La bVI EW Com pu t a t ion s

Com pon e n t s Sam e as Se t VSD .vi Su bVI 's Se t VSD .vi ( Set Bias) FG1 Ch a n .vi ( Funct ion Generat or) SR.vi ( Send- Receive Funct ion) Oscilloscope .vi ( Chan1_in Read Waveform )

Pr oce du r e •

Sub VI FG1 Cha n .vi sends out t he bias VSG and, in series, a sine- wave signal equal t o VSG/ 20. Set VSGinit as det erm ined wit h Set VSD.vi as t he VSG 500 µA. This is t he init ial VSG in t he sweep of t he next required t o obt ain I D part . Ru n t he VI t o obt ain t he gain for t his bias current . Obt ain a dat a log of

t he Front Panel. Default and save. Re- r u n wit h a new VSGnew = VSG – 0.5 V t o obt ain t he gain at a lower bias current . Obt ain a dat a log.

P5.4 Amplifier Gain versus Bias Current

La bVI EW Com pu t a t ion s

Com pon e n t s Sam e as Se t VSD .vi Su b VI 's Ga in Su b.vi Se t VSD .vi ( Set Bias) FGsin e .vi ( Funct ion Generat or) SR.vi ( Send- Receive Funct ion) Oscilloscope .vi ( Chan1_in Read Waveform )

Pr oce du r e •

•

Ru n Ga in .vi t o r u n Ga inSu b.vi over a range of current s. Set VSGinit ( V) t o t he value obt ained above for I D 500 µA ( default ed in Se t VSD .vi) . The VI aut om at ically halt s ( decreasing) at I D 50 µA. Default and save t he Front Panel. Now obt ain a dat a file as follows. Open Gr a ph ToD a t a File .vi ( copy of XYt oD a t a File .vi) in Pr oj e ct 0 5 .llb. Copy t he dat a from t he graph I D versus VSG of Ga in.vi. ( Right Click on t he graph, t hen Dat a Operat ions> > Copy Dat a.) Then past e t he dat a int o t he Cont rol Graph of Gr a ph ToD a t a File .vi. ( Right Click on t he graph and t hen Dat a Operat ions> > Past e Dat a.) Type t he dat a file pat h and nam e t he dat a file. Ru n t he VI t o obt ain a dat a file t o be read by t he Mat hcad evaluat ion file. Repeat for t he gain plot , av versus I D. Recall: The dat a files m ust be in t he folder wit h t he Mat hcad file. The file nam e m ust have a * .prn ext ension.

Laboratory Project 6. PMOS CommonSource Amplifier Stage with CurrentSource Biasing P6.1 PMOS Schem at ic and Pin Diagram P6.2 SPI CE PMOS and Circuit Equat ions P6.3 PMOS Current - Source Am plifier DC Set up P6.4 Am plifier Gain P6.5 Am plifier Frequency Response Exercises and Analysis Exercise06.m cd - Proj ect 06.m cd

P6.1 PMOS Schematic and Pin Diagram CD 4 0 0 7 Pin D ia gr a m

P6.2 SPICE PMOS and Circuit Equations SPI CE Equ a t ion

D e scr ipt ion

( NMOS)

DC drain current – volt age relat ion ( PMOS) .

5.15

Midfrequency gain versus I D .

5.6

Midfrequency gain versus I D wit h bypass capacit or Cs.

6.1

Gat e signal volt age, Vg , frequency- dependent relat ion t o signal source, Vs.

6.4

Gain frequency response wit h Cs only ( Cg infinit e) .

6.9

Approxim at e f 3dB wit h Cg infinit e.

3.8

P6.3 PMOS Current-Source Amplifier DC Setup

Com pon e n t s

VSG versus I D from Lab Proj ect s 4,5. La bVI EW Com pu t a t ion s

Pr oce du r e •

I nst all your value of RS in t he Front Panel. Verify t hat VDD = 10V. Ru n D C.vi t o verify your select ion of RS RD . Goal is I D 300 µA. Verify t hat VG is about VDD/ 2. Default and save t he Front Panel. Not e t hat VSD is about 2VSG.

P6.4 Amplifier Gain

La bVI EW Com pu t a t ion s

Use Pr oj e ct 0 6 .m cd for calculat ions. Su bVI 's FG1 Ch a n .vi Spe cAna ly.vi La bVI EW Com put a t ion

Pr oce du r e •

• •

•

The SubVI of Ga in.vi, FG1 Cha n .vi, sends out a signal wit h sine- wave peak Vs ( Chan1_out ) . The first m easurem ent is wit h only capacit or Cg inst alled. Be sure t o conform t o t he capacit or polarit y requirem ent . Set t he Signal Frequency t o 1000 Hz. Set your value of RS and check VDD = 10 V. Ru n Ga in.vi t o m easure t he gain. The gain should be less t han 1 wit hout t he 0.5 V should t hus suffice for good source bypass capacit or. A signal of Vs linearit y and m easurem ent precision. Now inst all t he capacit or Cs. Not e t hat t he source is at a posit ive volt age. Ru n t he VI while set t ing Vs at various values. Adj ust Vs unt il t he THD% ( t ot al harm onic dist ort ion, % ) is reduced t o below about 5% . Cont inue t o lower Vs and r u n Ga in .vi. Verify t hat t he m easured gain, av, is invariant for sm aller values of Vs except as event ually lim it ed by DAQ resolut ion and noise. Find t he largest Vs ( up t o 5% THD) , which is consist ent wit h a const ant gain m easurem ent wit h increasing Vs. Ru n t he VI again wit h a lower frequency ( e.g., 800 Hz) t o verify t hat t he gain is not frequency dependent in t his frequency range. Now default and save t he Front Panel.

P6.5 Amplifier Frequency Response

Pr oce du r e •

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•

The frequency of t he input source volt age is swept from 1 t o 1000 Hz t o 1000 Hz. Set Vs in Fr e qRe sp.vi as det erm ined above for a valid volt age gain m easurem ent . Open FG1 Cha n .vi t o observe t he waveform at t he out put . Set your value of RS. Run Fr e qRe sp.vi wit hout Cs. Recall t hat t he gain will be less t han 1. The frequency response is dict at ed by Cg only. Verify t hat f 3dB is about equal t o or less t han 1 Hz. Not e t hat f 3dB < 1 H if t he digit al indicat or f3dB indicat es 1 Hz. I nst all Cs and run t he VI . Obt ain a value for f3dB. Default and save t he Front Panel. Then use XYt oDat aFile.vi t o obt ain a dat a file for t he frequency response. A copy of t he VI is in Pr oj e ct 0 6 .llb.

Laboratory Project 7. NMOS CommonSource Amplifier Stage with SourceResistor Bias P7.1 SPI CE Equat ions and Pin Diagram P7.2 NMOS Com m on- Source Am plifier DC Evaluat ion P7.3 Am plifier Gain at Opt im um Bias for Linear Out put P7.4 Opt im um Bias St abilit y Test P7.5 Am plifier Frequency Response Exercises and Analysis Exercise07.m cd - Proj ect 07 1.m cd - Proj ect 07 2.m cd

P7.1 Chip Diagram and SPICE Equation

CD 4 0 0 7 Pin D ia gr a m

SPI CE Equ a t ion

D e scr ipt ion

3.8

Dc current – volt age relat ion.

( NMOS)

5.15

Volt age gain versus I D .

5.6

Volt age gain versus I D wit h bypass capacit or Cs.

6.8

Corner frequency ( f 3dB) wit h capacit or Cs.

6.12

Precision f s.

P7.2 NMOS Common-Source Amplifier DC Evaluation Pr oce du r e ( D e sign) •

• • • • •

St art in t he Mat hcad file Proj ect 07.m cd t o com put e circuit com ponent values as follows: We will design for a select ed I Dm ax at Chan0_out m ax = 10 V wit h VDSm in = 1V. Select your I Dm ax in t he range 100 µA < I Dm ax < 500 µA. Make RG1 = RG2

100 kΩ. Thus, t he gat e volt age is

VG = Chan0_out m ax / 2. Select t he circuit source resist or, RS, t o sat isfy VG = VGS ( I Dm ax ) + I Dm ax Rs. VGS ( I Dm ax ) can be calculat ed using previously m easured param et ers or obt ained graphically from , for exam ple, N M OSpa r a m .vi from Proj ect 4. Aft er acquiring a real RS ( which is close t o t he calculat ed value) , calculat e an act ual, new I Dm ax using t he sam e equat ion in reverse wit h t he real RS. Neglect t he change in VGS. We will select RD t o set t he condit ion of VDSm in = 1 V ( at Chan0_out m ax ) from RD = ( VDD – VDSm in ) / I Dm ax – Rs. ( Use act ual, new I Dm ax .)

Pr oce du r e ( M e a su r e m e n t ) •

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•

I nst all your value of RS in CSAM PBI AS.vi ( for current sensing) . Wit h VDD = 10 V ( VDDm ax ) , run t he VI t o verify t he design. VDSm in can be significant ly different from design 1 V due t o param et er variat ion. For exam ple, 1 < VDSm in < 1.5 V is sat isfact ory, where t he low lim it at ion is based on VDSm in > Veffn . This is t he requirem ent t o be in t he act ive region. I n t he exam ple, t he design drain current is I Dm ax = 300 µA. Verify t hat as VDD is reduced, I D decreases and VDS increases. Check VDD = 4 V, t he m inim um in t he sweep for param et er m easurem ent of t he next part . Verify t hat at t he m inim um VDD, VDS > I D·RD Obt ain a log for Chan0_out = 10V. Reduce VDD from t he m axim um VDD = 10 V and det erm ine, approxim at ely, I D RD . This is t he value bet ween 4V < VDD < 10V t hat corresponds t o VDS t he operat ing point ( bias) condit ion for t he am plifier gain m easurem ent . This will be found aut om at ically in t he gain m easurem ent VI .

P7.3 Amplifier Gain at Optimum Bias for Linear Output

Com pon e n t s*

Not e t hat g m is in µA/ V. *

Ru n t he first part of Procedure wit h Ga inN M OS.vi, below, wit hout t he capacit or, t o obt ain Veffn and bias I D , for com put ing g m .

La bVI EW Com pu t a t ion s Param et ers: Vt no , k n

Pr oce du r e ( Obt a in Pa r a m e t e r s a nd Bia s Va r ia ble s) •

Open Ga inN M OS.vi. I nst all your RS value. Wit hout t he capacit or inst alled, set t he Mode Swit ch t o Param ( red, swit ch in logic st at e 0) . Ru n t he VI for a VDD sweep t o get t he param et ers. ( Not e: The sweep rat e is configured t o be slow in case t he capacit or is in place during t he sweep.) The VDD sweep is from 4 V t o 10 V. Obt ain a log of t he result s.

Pr oce du r e ( Ga in M e a su r e m e n t ) •

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•

•

I n t he Param m ode, t he VI finds and indicat es VDDbias corresponding t o t he opt im um VDS = ( VDD – VRs + Veffn ) / 2. This perm it s m axim um signal swing wit hout dist ort ion. Set t he indicat ed value of VDDbias int o t he Set VDD Digit al Cont rol. Ru n t he VI wit h t he Mode Swit ch set t o Gain ( green, swit ch posit ion logic 1) wit hout t he capacit or. Obt ain a log of t he Front Panel. Default and save t he Front Panel. At t he end of t he param et er sweep, Veffn is indicat ed for VDDbias. The value is ret ained in t he Digit al I ndicat or in t he gain m easurem ent . The value of I D indicat ed in t he gain m easurem ent is t he am plifier gain bias value. Use Veffn along wit h bias I D, t o com put e g m and t hus Cs. Use Proj ect 07.m cd for t he calculat ion. I nst all t he capacit or. Make cert ain t hat t he polarit y of t he capacit or is correct . Check t hat t he Mode Swit ch is set t o Gain ( swit ch posit ion logic 1) . Check t hat t he value of VDDbias m at ches t he value in Set VDD Digit al Cont rol. The VI will m easure t he gain at t his one VDD set t ing ( opt im um for dist ort ion- free out put ) . The signal frequency is init ially 500 Hz. Ru n t he VI and vary t he value of Vs t o det erm ine t hat t he gain result , Vd / Vg , is not affect ed by changes, t hat is, by dist ort ion. Default and save t he Front Panel. Obt ain a log of t he result s. Also, run wit h slight variat ions in Freq ( e.g., 300 Hz) . Not e t hat t he param et er values are preserved when running t he gain m ode. Param et er, bias variable, and gain dat a are required for t he proj ect Mat hcad file.

P7.4 Optimum Bias Stability Test •

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•

•

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As will be explored in a proj ect Mat hcad file, t he basis st abilit y com put at ion is perform ed here wit h La bVI EW . Recall ( Sect ion 5.5) t hat t his t akes int o considerat ion a possible range of Vt no and k n values. Here, an analysis is m ade regarding t he ext ent t o which your design is opt im um in t erm s of bias st abilit y. Not e t hat t his is separat e from t he m axim um signal condit ion t hat has been included in t he design.

Open Ca lVD Sopt im u m .vi. I n t he Digit al Cont rols, set you values for VDD, k n , Vt no , and I D. I D is t he nom inal value of t he design for t he nom inal values of t he param et ers. Your value of I D, along wit h your param et er values, will be assum ed t o be, for t his evaluat ion, t he nom inal values. The com put at ion holds t he bias current const ant at t he design value ( as ent ered int o t he Front Panel) . As VG is increased ( X axis) , t he added increm ent of VG is t he added drop across t he new RS, for a given new VG. Ru n t he VI . Verify t hat t he value of VGS in t he t op Digit al I ndicat or m at ches reasonably well your m easured value ( Front Panel of Ga inN M OS.vi) . This SPI CE com put at ion uses your m easured param et er values and I D . The values should be consist ent . The t op graph is it s VDSlim it s versus VG. The cent er ( dashed) curve is for your param et ers. The downward slope reflect s t he increasing drop across VG. The t op and bot t om plot s are for t he t wo ext rem es of VDS t hat occur for t he worst case of t he com binat ion of t he lim it s of k n and Vt no . The com put at ion is for Vt no± = Vt no ± 100 m V and . The sam e opt im um signal level condit ion as used in your design is m aint ained t hroughout . The lower graph cont ains plot s of t he out put signal lim it ing values. The best com binat ion of bias st abilit y and signal level is at t he peak of t hese curves. St ep t hrough t he RS Array Digit al I ndicat or t o locat e your RS and t he

•

associat ed index. Then det erm ine t he corresponding VG and RD ( sam e index) . The value of RD should m at ch your design value. The value of VG should m at ch t he value from t he Front Panel of Ga inN M OS.vi. Locat e your value of VG on t he X- axis of t he t wo graphs. I f it falls in t he range of values surrounding t he peaks, t he circuit is opt im ized bot h in t erm s of signal lim it s and bias st abilit y. Not e t hat bias st abilit y was not t aken int o considerat ion in t he design. I n t he design, t hough, oft en a given crit erion serves as t he basis and t he design m ay t hen be evaluat ed for ot her crit eria.

P7.5 Amplifier Frequency Response

Pr oce du r e •

• •

I n Fr e qRe spN M OS.vi, t he frequency of t he wit h source volt age ( sine- wave Chan1_out ) is swept from 1 t o 1000 Hz. Chan2_in should be disconnect ed t o reduce t he st ray capacit ance at t he gat e. I n t he Front Panel of t he VI , set VDDbias and Vs at t he values det erm ined in t he gain m easurem ent wit h Ga inN M OS.vi.

Along wit h Fr e qRe spN M OS.vi, open FG1 Cha n .vi t o observe t he out put waveform . Verify t hat Cs is inst alled and r u n t he VI t o obt ain a value for f 3dB. Open, from t he Diagram of Fr e qRe spN M OS.vi, Fram e 2, XYt oDa t a File 2 .vi. Ru n Fr e qRe spN M OS.vi again, wit h t he dat a m ode swit ch set t o Green ( logic st age 1) , t o obt ain a dat a file of t he frequency- response plot in

•

XYt oD a t a File 2 .vi. ( Not e t hat wit h t he dat a VI open, t he dat a are t ransferred t o t he VI and can t hen be saved in t he VI .) The dat a file is used in t he Mat hcad proj ect file. Default and save t he Front Panels of bot h XYt oD a t a File 2 .vi and Fr e qRe spN M OS.vi. Not e t he m axim um index for t he Mat hcad file. The f 3dB result will differ from t he design, as t he design was based on t he sim ple form . This will be explored in t he Mat hcad file. A dat a file can be obt ained lat er from t he saved dat a in t he graph of Fr e qRe spN M OS.vi, wit h XYt oD a t a File 2 .vi. As not ed above, t he dat a file VI can be obt ained from t he Diagram of Fr e qRe spN M OS.vi. The dat a file VI is locat ed in D a t .llb in t he User.lib folder ( Program Files> > Nat ional I nst rum ent s> > LabVI EW 6) . The VI can also be accessed from t he m enu sequence in Fr e qRe spN M OS.vi, Browse> > Show VI Hierarchy, and open t he dat a file VI from t he Hierarchy Window. Ret urn t o Proj ect 07.m cd.

Laboratory Project 8. NMOS SourceFollower Stage P8.1 SPI CE Equat ions and Pin Diagram P8.2 Source- Follower DC Evaluat ion P8.3 Source- Follower Volt age Transfer Relat ion P8.4 Source- Follower Volt age Transfer Relat ion wit h Body Effect Exercises and Analysis Exercise08.m cd - Proj ect 08.m cd

P8.1 SPICE Equations and Pin Diagram SPI CE Equ a t ion

D e scr ipt ion

7.1

Threshold volt age for VB = VSS.

7.7

Source- follower volt age- t ransfer relat ion wit h Vsb = 0.

7.12 Source- follower volt age t ransfer relat ion wit h body effect .

4.11 Body- effect t ransconduct ance. CD 4 0 0 7

D o n ot con ne ct pin 1 4 .

P8.2 Source-Follower DC Evaluation

Pin 14 m ust not be connect ed. Chan0_out will be plus and m inus and t he drain is at ground. Com pon e n t s For Ga in.vi

Not e t hat wit h RS is select ed for t he condit ion of m axim um body- effect ( VGSm ax 5 V) , I Dm ax > 500 µA for t he case wit hout body effect . The current sweep VI 's halt at I D = 500 µA. Pr oce du r e •

I n t he Front Panel of D Cche ck .vi, set t he value of RS in t he Digit al Cont rol. Wit h VSS ( m agnit ude) set at 10 V, r u n t he VI t o verify t he dc design. Not e t hat | VS| is equal t o t he VGS m agnit ude. Verify t hat I D > 500 µA for t his case of no body effect .

P8.3 Source-Follower Voltage Transfer Relation

Pin 14 m ust not be connect ed t o ground. Chan0_out will be great er t han 0 for t he posit ive signal. La bVI EW Com put a t ion

Pr oce du r e •

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• •

Ga inSF.vi m easures t he gain ( t ransfer relat ion) of t he circuit over a range of drain current . Param et ers Vt no and knprim e are obt ained from t he I D sweep. Vt no is used in t he volt age t ransfer- relat ion calculat ion as plot t ed along wit h t he m easured dat a.

Open Ga inSF.vi and inst all your value of RS. Open FG1 Cha n .vi t o observe t he waveform at t he out put . Run t he VI and verify t hat t he curves m at ch reasonably well as in t he exam ple. Adj ust t he m agnit ude of VSS t o obt ain a m inim um I D of about 50 µA Adj ust t he value of Vs while r e r u n n ing t he VI . Use t he largest Vs wit hout dist ort ion. Large- signal dist ort ion is m anifest ed by a poor curve fit , part icularly at t he low end of t he current range. Default and save t he Front Panel. The value obt ained for knprim e m ust be

•

available for t he next VI . I t is used in t he calculat ion of . The alt ernat ive form , g m = 2I D / Veffn , is used in t he calculat ions for t his VI . Obt ain a dat a file of t he plot using XY1 ToD a t a File .vi.

P8.4 Source-Follower Voltage Transfer Relation with Body Effect

Pin 14 m ust not be connect ed t o ground. Chan0_out will be great er t han 0 for t he posit ive signal. La bVI EW Com put a t ion

Pr oce du r e •

• •

Move t he body pin connect ion as in Circuit P8.2. I n Ga inBE.vi, inst all a first guess value for γn ( Proj ect 4) . I nst all t he value of knprim e, obt ained from t he Front Panel of Ga inSF.vi. Run t he VI and readj ust γn for t he best fit . Adj ust | VSS| init for a m inim um I D of about 50 µA. Not e t he reduced value of t he volt age t ransfer relat ion ( gain) .

Open Com pa r e .vi from Pr oj e ct 0 8 .llb. Past e t he result s from t he graphs of t he plot s for wit h and wit hout body effect int o t he cont rol graphs. Ru n t he VI t o com pare t he result s. Use XY1 ToD a t a File .vi t o obt ain a dat a file of t he plot in Ga inBE.vi.

Laboratory Project 9. MOSFET Differential Amplifier Stage P9.1 SPI CE Equat ions and Pin Diagram P9.2 DC Evaluat ion of t he Single- Power- Supply Different ial Am plifier P9.3 Det erm inat ion of t he PMOS Param et ers P9.4 Am plifier Gain Measurem ent P9.5 Transist or Param et ers and DC I m balance P9.6 Com m on- Mode Gain Measurem ent Exercises and Analysis Exercise09.m cd - Proj ect 09.m cd

P9.1 SPICE Equations and Pin Diagram SPI CE Equ a t ion

CD 4 0 0 7

D e scr ipt ion

8.34

I nvert ing gain.

8.40

Noninvert ing gain.

8.38

Signal resist ance at source node.

PM OS 1

PM OS 2

P9.2 DC Evaluation of the Single-Power-Supply Differential Amplifier

Com pon e n t s RD1 = RD2 = RD Rs = RD / 2 VD

VDD/ 2 – VSG

For Chan0_out = 10 V: 100 µA< I D < 400 µA ( Choose One) RG < 100 kΩ

Mat ch t he gat e resist ors on each side t o obt ain VG = VDD/ 2. On a given side, t he resist ors m ust be equal, but can be different on opposit e sides. Pr oce du r e

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Aft er com plet ing t he circuit connect ions, open D C.vi. Set Chan0_out = 10 V and run t he VI . D C.vi scans Chan1_out t o balance t he circuit ( i.e., t o set VD1 = VD2 wit hin 20 m V) . Try Chan0_out in t he range 5 t o 10 V. Verify t hat 100 µA< I D< 400 µA ( your design) wit h m axim um Chan0_out = 10 V. Not e t he value sent out by Chan1_out . This should be only m V if t he gat e resist ors were select ed properly. Verify t hat VSD is roughly 2VSG. Default and save t he Front Panel wit h Chan0_out = 10 V. The VI serves as a subVI in t he next part t o bias and balance t he circuit .

P9.3 Determination of the PMOS Parameters

Pr oce du r e •

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•

Pa r a m e t e r s.vi sweeps out put channel Chan0_out from VDD –1 t o VDD + 1 ( where t he design bias VDD is set in t he Front Panel) . The gain m easurem ent will be m ade at VDD, int erm ediat e t o t he sweep range. Since volt age VSD is approxim at ely equal t o 2VSG, VSD will be relat ively const ant during t he sweep, as is required for a reliable m easurem ent of Kp and Vt po .

Ru n t he VI for VDD set at 6 V and 8V and verify t hat Vt po is close t o t he sam e for bot h VDD values. For t he larger VDD ( and VSD) , kp ( at VSD) should be slight ly larger. Now set VDD = 6, 7, or 8 V and t he File Mode swit ch t o Green ( on) and rer u n t o obt ain a param et er dat a file. The file has RD1 , RD2 , k p ( t echnically, and Vt po. The Param et ers are act ually for M2 . These will be read by t he evaluat ion Mat hcad file.

)

The param et ers can be obt ained wit h Sim Pa r a m .vi from t he dat a saved in Pa r a m e t e r s.vi. Past e t he dat a from t he I ndicat or Graph ( sam ple, VDD = 7 V) of Pa r a m e t e r s.vi int o t he Cont rol Graph of Sim Pa r a m .vi and r u n t he VI wit h t he Dat a Mode swit ch set t o on ( Green) .

P9.4 Amplifier Gain Measurement

Pr oce du r e •

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Ga in.vi runs D C.vi t o set up t he bias and balance t he circuit . I t t hen sends out a signal squarewave and reads t he response at t he t wo out put s. Gain is calculat ed as out put volt age divided by Vs/ 2. The 1/ 2 account s for t he volt age divider of t he t wo gat e resist ors.

Set in Chan0_out ( VDD) , which you select ed above in Pa r a m e t e r s.vi. Run Ga in.vi t o obt ain t he gain at t he t wo out put s. Adj ust Vs for an out put volt age m agnit ude sim ilar t o t hat in t he exam ple. Now r u n AvgGa in .vi wit h your VDD ( Chan0_out ) and Vs from Ga in .vi. as a subVI repeat edly and averages t he gains cont inuously during t he m easurem ent s. Wit h t he Run Mode on ( Green) , allow t he VI t o cont inue t o r u n unt il t he average gain no longer appears t o be changing. Reset Run Mode t o halt execut ion. Repeat wit h t he File Mode but t on set t o on ( Green) . The dat a file cont ains I D1 , I D2 , VSG VSD, a v1 , and a v2 . The Mat hcad evaluat ion file will read t hese dat a. Use Sim AvgGa in .vi t o obt ain t he dat a file from t he dat a saved in AvgGa in .vi. Past e graph dat a and copy and past e t he Digit al Cont rol values.

Gains will be obt ained from t he graph dat a and need not be copied from t he Digit al I ndicat ors.

P9.5 Transistor Parameters and DC Imbalance

Pr oce du r e •

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Sw e e p.vi runs a special version of D C.vi, D Cim ba l.vi, as a subVI of Sw e e p.vi. Sw e e p.vi sends out a range of bias volt age, 5 V< VDD < 10 V ( Chan0_out ) , in 0.5 V st eps. VSG, I D1 , and I D2 are m easured at each st ep. A t hree- colum n dat a file is saved for t he Mat hcad proj ect evaluat ion.

Not e t hat Circuit P9.2 has t he gat es connect ed t o m ake cert ain t hat t he gat e volt ages are equal. There is no balancing in t his circuit , as t he goal is t o st udy circuit im balances. D Cim ba l.vi calls for Chan1_out = 0 V. Open Sw e e p.vi and set in t he resist or values. Also open D Cim ba l.vi. Ru n D Cim ba l.vi t o verify t hat t he circuit is funct ioning properly. Ru n Sw e e p.vi. Set t he File- Mode swit ch t o on ( Green) , writ e in t he file pat h ( or click on t he Browse but t on) and dat a file nam e and r u n t he VI t o obt ain t he dat a file. The dat a dc variables will be used in t he proj ect Mat hcad file t o obt ain k p and Vt po . The values are used in a com put at ion for a graphical com parison of m easured and com put ed current rat ios versus drain current .

•

Ru n Sw e e pSim .vi t o obt ain t he dat a file from t he graph dat a saved. [ Not e t hat t he VSG graph is not shown in t he sam ple Sw e e p.vi ( above) . The act ual Sw e e p.vi has a Front Panel as t he sam ple Sw e e pSim .vi ( below) .] Copy and past e dat a from Sw e e p.vi.

P9.6 Common-Mode Gain Measurement

Pr oce du r e •

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The com m on- m ode gain can be obt ained direct ly wit h Circuit P9.2. This is accom plished wit h t he VI , CBGa in .vi. The squarewave input signal is applied wit h Chan1_out .

Open CM Ga in .vi and set in t he resist or values. Set Vs t o a larger value t han t hat used in Ga in.vi, t o com pensat e for lower gain. Ru n t he VI t o verify t hat t he circuit is funct ioning properly. Expect t he gain t o be about unit y, based on t he design RS = RD / 2. ( I deal com m on- m ode gain is zero.) Open and r u n AvgCM Ga in .vi. Obt ain a dat a file consist ing of drain current s, VSG, gains, and VSD. Use Sim AvgGa in .vi t o obt ain a dat a file from dat a saved in AvgCM Ga in .vi. Copy and past e t he graph dat a and t he drain current s, VSG and VSD. Gains will be averaged from t he graph dat a.

Laboratory Project 10. Current Mirror and Common-Source Amplifier with CurrentSource Load P10.1 SPI CE Equat ions and Pin Diagram P10.2 Evaluat ion of t he Current - Source Circuit P10.3 Evaluat ion of t he Mirror- Current Circuit P10.4 Evaluat ion of t he Bias Set up P10.5 Measurem ent s of t he Am plifier Gain versus Bias Current Exercises and Analysis Exercise10.m cd - Proj ect 10.m cd

P10.1 SPICE Equations and Pin Diagram SPI CE Equ a t ion

D e scr ipt ion

10.3

Am plifier gain, VGS form .

10.4

Am plifier gain, I D form .

PM OS3

PM OS2

N M OS1

P10.2 Evaluation of the Current-Source Circuit

Com pon e n t s

Pr oce du r e •

Set your value of RRef in t he Digit al Cont rol. Ru n Re fCu r r e n t .vi t o det erm ine t he current range. Chan1_out is swept from t he I nit ial value t o –10 V. Readj ust I nit ial Chan1_out t o obt ain a m inim um drain current of about 50 µA. Verify t hat t he m axim um current is about 500 µA.

P10.3 Evaluation of the Mirror-Current Circuit

Pr oce du r e •

I nst all t he addit ional circuit com ponent s, which form t he current source. Set your resist or values in t he Digit al Cont rols. Use I nit ial Chan0_out from Re fCu r r e n t .vi. Run M ir r or Cu r r e n t .vi t o assess t he m irror current ( current –10 V. source current ) . Chan0_out is swept from t he I nit ial value t o Chan1_out is varied downward t o m aint ain VSD2 = VSD3 . Any difference bet ween t he current s indicat es a difference in t ransist or param et ers of M2 and M3 .

Com pon e n t s RD2

RRef

P10.4 Evaluation of the Bias Setup

Pr oce du r e Se t VoI D .vi sends out t he gat e volt age of t he driver t ransist or ( M1 , NMOS) and t hen sweeps Chan1_out t o set t he out put bias volt age ( Chan1_in) at VDD/ 2. This VI is a subVI in t he gain m easurem ent VI ( below, next part ) . To run t his VI as a t op VI , set t he I ndex t o zero. Set Chan0_out I nit ial t o 0V.

•

Ru n Se t VoI D .vi while adj ust ing VGS for t he lowest value of t he I D range of about 50 µA. Verify t hat t he bias- set t ing circuit funct ions properly. Adj ust t he Cont rol- Loop Const ant t o obt ain a final dc value convergence rat e sim ilar t o t hat in t he exam ple. Default and save t he Front Panel.

P10.5 Measurement of the Amplifier Gain versus Drain Current Pr oce du r e •

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I n Ga in.vi, set VGS1 I nit ial t o t he value from t he evaluat ion of Se t VoI D .vi above. The VI will sweep VGS1 over a range t o include a m axim um response of about 500 µA, according t o t he design above. Due t o t he high gain, t he input signal volt age will be sm all in t erm s of t he DAC. A subVI com put es t he act ual out put signal volt age from t he value request ed. The value com put ed is used in t he gain com put at ion.

Open Se t VoI D .vi along wit h Ga in.vi. Set all num bers in t he Digit al Cont rols of Ga in .vi. Ru n t he VI and adj ust Vs such t hat Vo m in and Vo m ax are confined bet ween 1 and 4 V, as in t he exam ple. These are indicat ed for t he init ial bias current ( highest gain) . Also, adj ust ( down) t he Cont rol- Loop Const ant of Se t VoI D .vi if t he bias set t ing funct ion oscillat es out of cont rol. Save t he Front Panel when t he VI is funct ioning properly. Open AvgGa in_ I D .vi. This VI runs Ga in.vi as a subVI repeat edly and averages t he plot s of each execut ion. Set t he Run Mode swit ch t o Cont inuous and t he File Mode swit ch t o on ( Green) and r u n t he VI for dat a sm oot hing. Swit ch t o One Plot t o halt t he execut ion. The dat a file includes gain, VGS1 , and I D . This is used in t he proj ect Mat hcad analysis file. Obt ain a dat a file from saved dat a in AvgGa in_ I D .vi wit h Sim AvgGa in _ I D .vi.

Laboratory Project 11. Operational Amplifier with Resistor Feedback P11.1 SPI CE Equat ions P11.2 Bias Circuit Set up P11.3 Opam p Offset Volt age P11.4 Evaluat ion of t he Bias Balancing Circuit P11.5 Evaluat ion of t he Gain and Signal Lim it s wit h Swept I nput P11.6 Evaluat ion of t he Gain wit h Sine- Wave and Square- Wave Signals P11.7 Det erm inat ion of t he Opam p Frequency Response Exercises and Analysis Exercise11.m cd - Proj ect 11.m cd

P11.1 SPICE Equations SPI CE Equ a t ion

D e scr ipt ion

11.16

Out put volt age of resist ance- feedback opam p wit h offset volt age, Voff .

11.3, 11.4

Midfrequency gain dependence on opam p gain a vo .

11.20

Frequency- response funct ion of resist ancefeedback opam p am plifier.

11.21

Bandwidt h ( corner frequency) of opam p am plifier wit h opam p open- loop corner frequency, f 3dB.

P11.2 Bias Circuit Setup

1 Offset Null 1 2 I nvert . I nput 3 Non- I nvert . I nput 4 V8 I SET 7 V+ 6 Out put 5 Offset Null 2

Com pon e n t s

Pr oce du r e •

Do not init ially t urn on t he power supply. Connect t he circuit aft er having m ade precision m easurem ent s of t he resist ors. Turn on t he power supply only wit h t he circuit com plet ely connect ed, I nst all t he resist or value RSET in t he Digit al Cont rol of D CCh e ck .vi. Ru n t he VI . Check t he dc values. Verify t hat I SET is roughly 25µA VO is norm ally close t o V+ or V–. Default and save t he Front Panel.

P11.3 Opamp Offset Voltage

Com pon e n t s 4x10 3 R2

Rf

( Very Approxim at e) AvNI

4000

Pr oce du r e •

I nst all Rf and re- r u n D CCh e ck .vi. Verify t hat | VO| is less t han t he value wit hout t he feedback resist or. I f not , use a sm aller Rf .Default and save t he inform at ion in t he Front Panel. D a t a she e t Offse t Volt a ge

M in . Typ. Max. Un it Vio

I nput Offset Volt age

mV

Vo = 1.4 V, Vic = 0 TS271C/ I / M

1.1 10

P11.4 Evaluation of the Bias Balancing Circuit Com pon e n t s R1 = R3 R1 / R2 = R3 / R4 = 1000 Rf

4000R2

Pr oce du r e •

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Connect t he addit ional circuit com ponent s, R1 and R3 . ( Gain m easurem ent result s depend on t he precision of t he values ent ered.) The VI will sweep Chan1_out t o drive t he out put t o near 0 V. Set t he value of Rf in t he Digit al Cont rol of I t e r a t e Vo.vi.

Ru n t he VI t o verify t hat t he balancing circuit is funct ioning properly. The VI , I t e r a t e Vo.vi, is a subVI in t he am plifier gain evaluat ions, for balancing t he circuit ( i.e., for set t ing t he dc out put t o near 0 V) . The indicat ed VO( init ) should m at ch t he value from t he result of P11.3. Save t he Front Panel.

P11.5 Evaluation of the Gain and Signal Limits with Swept Input

Pr oce du r e •

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Ent er t he resist or values in t he Digit al Cont rols of Sca nAm p.vi. The gain of int erest is am plifier gain, Av = Chan0_in/ V+ . This is obt ained from t he m easured Slope of n Chan0_in versus Chan0_out and t hen

Opam p gain, a vo , is calculat ed in a Form ula Node using Av and t he ideal gain AvNI = 1 + Rf / R2 | | R1 . Thus, t he gain- m easurem ent result s depend crit ically on t he precise value of t he resist ors. Ru n t he VI and reset Chan0_out Range as necessary t o obt ain an out put range of about plus and m inus 1 V [ graph Y axis and I ndicat ors, Vom ax( V) and Vom in( V) ] . Save t he Front Panel.

Form ula Node Com put at ion of avo

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Reset t he Chan0_out Range, such as in t he exam ple ( left ) , t o drive t he out put t o t he lim it s. Run t he VI and not e t he lim it s Vom ax( V) ( VOH) and Vom in( V) ( VOL) . Com pare t hese wit h t he dat asheet values. Not e t hat t he dat asheet num bers ( below) were obt ained for a single power supply and V+ = 10V and V– = 0V. Thus, Vom ax approxim at ely 1 V below t he power supply and Vom in is approxim at ely 50 m above t he negat ive supply ( ground in t he dat asheet case and –8 V for our opam p am plifier) . D a t a she e t Lim it Volt a ge s ( Pow e r Su pply = 0 t o + 1 0 V)

M in . Typ. Max. Un it VOH High- level out put volt age

V

Vid = 100 m V, RL = 100 kΩ 8.7 8.9

VOL Low- level out put volt age ( Vid = –100 m V)

50 mV

P11.6 Evaluation of the Gain with Sine-Wave and Square-Wave Signals

Pr oce du r e •

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Signa lAm p.vi sends out a sine- or square- wave input signal wit h a frequency as select ed from t he Front Panel. Use a frequency of 1 or 2 Hz. I t m ust be low as t he frequency response of t he am plifier is very low wit h t he high gain of t his configurat ion.

I nst all resist or values in t he Front Panel of Signa lAm p.vi.Ru n t he VI and com pare t he gain for sine- and square- wave signals. Com pare for t wo different frequencies. Adj ust Vs for a m axim um out put signal of about 1 V. Save t he Front Panel. D a t a she e t La r ge - Sign a l Volt a ge Ga in Sym bol Param et er Min. Typ. Max. Unit

Avd Large- signal volt age gain

V/ m V

Vo = 1 t o 6 V, RL = 100 kW, Vic = 5V 30 50

Tm in. < Tam b. < Tm ax. 20

P11.7 Determination of the Opamp Frequency Response

Pr oce du r e •

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The VI sweeps t he input sine- wave signal over a range of frequencies, 1Hz< f< 1kHz. The gain is com put ed and plot t ed and t he bandwidt h of t he am plifier is com put ed and indicat ed. The GBP is t hen com put ed and indicat ed.

I nst all precision resist or values for R3 and R4 in t he Front Panel of Fr e qRe sp.vi. Run t he VI t o obt ain t he frequency response. Verify t hat Vo( m ax) is less t han about 1 V. This m ust less t han t he oscilloscope lim it of 2 V. Save t he Front Panel. D a t a she e t Ga in – Ba n dw idt h Pr odu ct Sym bol Param et er Min. Typ. Max. Unit GBP

Gain – Bandwidt h product ( Av = 40 dB, RL = 100 kΩ, CL = 100 pF, fin = 100 kHz)

0.7

MHz

Laboratory Project 12. Operational Amplifier Integrator and Oscillator P12.1 SPI CE Equat ions P12.2 Opam p I nt egrat or P12.3 Opam p Oscillat or Exercises and Analysis Exercise12.m cd - Proj ect 12.m cd

P12.1 SPICE Equations SPI CE Equ a t ion

T

2.2 Rf Co

D e scr ipt ion

12.4

Opam p- int egrat or peak volt age am plit ude of t he t riangular- wave for applied square- wave wit h peak Vs and period T and wit h Ry = R1 | | R2 and Cf .

12.6

Cosine- wave out put for sinewave input wit h peak Vs, period T, Ry = R1 | | R2 and Cf .

12.26 Period of oscillat or for Rf wit h Co and R1 = R3 . 12.18 General form for Tplus in t erm s of R1 , R3 , Vom , and Vop .

12.22 General form for Tm nus in t erm s of R1 , R3 Vom , and Vop .

P12.2 Opamp Integrator

Com pon e n t s Refer t o Proj ect 11 for resist or values. Use Proj ect 12.m cd t o calculat e t he capacit or value. Obt ain Cf from t he square- wave equat ion

( 11.4 )

Vs+ is t he volt age applied at t he noninvert ing t erm inal ( pin 3) of t he opam p, and Vs is t he volt age from Chan0_out . Use Tm ax = 0.1 S for t he int ial frequency of f= 10 Hz.

Pr oce du r e •

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Connect t he circuit , which includes adding t he capacit or and m oving Chan1_in t o connect t o Chan0_out . I n t he Front Panel of I n t e gr a t or .vi, set Vs ( Chan0_out Peak( V) at 4 V t o 10 V. This is adj ust ed t o set t he init ial peak ( lowest frequency) of t he t riangular wave. Also open subVI , I t e r a t e Vo.vi, t o observe t he process of set t ing t he out put t o near 0 V. Ru n t he VI wit h t he signal set t o t he SqWave m ode. Re- adj ust Vs for a value of Vo( Peak- t o- Peak) ( init ) of bet ween 5 V and 6 V. Verify t hat t he init ial and final peak- t o- peak out put volt age rat io is approxim at ely 10. Not e t hat it will be less t han 10 due t o t he finit e Rf Cf The ideal int egrat or has infinit e Rf . Not e t hat only t he last half of t he out put array is used in t he out put volt age peak det erm inat ion, t o avoid init ial t ransient s. Also, t he average value of t he out put volt age channel is subt ract ed from t he waveform in t he oscilloscope. Obt ain a log of t he Front Panel. Default and save. Now set t he input waveform swit ch t o Sine- wave and re- r u n . Not e t he lower peak value. Obt ain a log of t he Front Panel.

P12.3 Opamp Oscillator Com pon e n t s Use R1 = R3 from t he int egrat or. Make Rfosc = R1 = R3 and use Cf from t he int egrat or. Tosc

2.2RfoscCf ( 12.26)

Not e t hat Tosc is about ½ of t he design Tm ax from t he int egrat or or about 50 m s.

Pr oce du r e •

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Turn off t he power supply t o reconnect t he circuit int o t he oscillat or configurat ion. Not e t he connect ion of Chan1_in, which m easures t he capacit or volt age. The m ain VI , Oscilla t or .vi( below) , cont ains subVI 's Cou nt Cycle s.vi and T.vi.Cou n t Cycle s.vi det erm ines t he num ber of cycles in t he oscillat or out put dat a array ( Chan0_in) by checking for sign changes. I t t hen increases or decreases t he sam ple rat e ( for a fixed num ber of sam ples) unt il t he num ber of sign changes in t he array is 4. T.vi t hen checks t he num ber of sam ples in t he posit ive and negat ive pulses and m ult iplies t he t ot al by t he sam ple rat e t o obt ain t he oscillat or frequency. This frequency is used t o set t he t im e base of t he oscilloscope, OscOscill.vi, t o display five cycles of t he oscillat or waveform in t he Front Panel of t he m ain VI .

Connect t he circuit wit h t he power supply off t o avoid dam age t o t he chip. Then t urn on t he power supply. Open t he oscillat or oscilloscope VI , OscOscill.vi. Set t he oscilloscope frequency, fscope, t o t he expect ed frequency of t he oscillat or ( e.g., about 50 Hz) . This set s up t he scope for a full sweep of 2/ fscope = 40 m sec ( Not e t hat t he scope is set for 2048 sam ples per sweep. Thus t he resolut ion is 2/ ( 2048fscope) = 19 µs for t his exam ple.)

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Ru n OscOscill.vi t o verify t hat t he circuit is oscillat ing. Reset fscope for a t im e base t hat includes about t wo cycles of oscillat ion and r e r u n . Not e t hat t his fscope set t ing is approxim at ely t he frequency of t he oscillat or. Open subVI Cou n t Cycle s.vi. Set Tim e Ba se ( in it ) ( m se c) ( full sweep t im e of scope) t o include about t wo cycles of t he oscillat or waveform . ( Use Tim e Ba se = 2 / fscope .) Run t he subVI t o verify t hat t he VI can find t he final t im e base, which includes about t wo cycles.

Open Oscilla t or .vi. Set Tim e Ba se ( init ) ( m se c) t o t he value obt ained in Coun t Cycle s.vi. Set in t he value of Rfosc. Ru n t he VI t o obt ain a final plot of t he oscillat or waveform and t he frequency and period of t he oscillat or. Not e t he value found for t he capacit or. Com pare t his wit h t he value expect ed. The precision of t he value depends on t he precision of t he Rfosc. Not e t hat if t he Tim e Ba se ( in it ) is not set close t o t he final value, t he VI will find t he correct value, aft er som e searching. Set t he value of R3 for t he record. I t plays no role in t he VI . Save t he inform at ion in t he Front Panel by obt aining a log. 10 Rfosc( very approxim at ely) . Set in t he new value in Replace Rfosc wit h Rfosc Oscilla t or .vi. Use Oscilla t or .vi t o m easure t he new oscillat or frequency. Com pare t he capacit or m easurem ent . Obt ain a log for t his case. Now replace R3 wit h R3 R3 / 10 ( very approxim at ely) . Set in t he new value of R3 for t he log record. Run t he VI . Not e t hat t he capacit or m easurem ent is not valid for t his case. The capacit or now charges t o about 10% of t he m axim um out put volt ages before swit ching. This increases t he frequency of oscillat ion, due t o t he short er t ransient t im e. Obt ain a log and save.

Laboratory Project A. Communicating with the Circuit Board Using the DAQ PA.1 Sending and Receiving Volt ages wit h t he Sending and Receiving VI s PA.2 Sending and Receiving Volt ages from t he Front Panel PA.3 Plot t ing Measured Sam ples PA.4 Using t he Aut oranging Volt m et er PA.5 Observing t he Oscilloscope Out put Graph PA.6 Discret e Out put Volt age from t he DAQ PA.7 Discret e I nput Volt age from t he Circuit Board PA.8 Using t he Sim ult aneous Sending/ Receiving Funct ion TABLE PA.1 Diagram

Front Panel

Tools Palet t e

Shift / Right Click

Funct ions Palet t e

Right Click–St ickpin t o hold

Menu Sequence:

Window> > Show Funct ions Palet t e

Tools Palet t e

Shift / Right Click

Cont rols Palet t e

Right Click–St ickpin t o hold

Menu Sequence:

Windows> > Show Cont rols Palet t e

PA.1 Sending and Receiving Voltages with the Sending and Receiving VIs •

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Connect Chan0_in direct ly t o Chan0_out on t he circuit board or connect or block. Double Click on bot h of t he icons in t he Diagram of M e a su r e .vi ( init ial version) t o bring up t he VI Front Panels. These are AO Upda t e Cha n ne l.vi and AI Acqu ir e W a ve for m .vi. Set bot h VI s t o your device num ber for your DAQ card and t o channel 0 ( using t he Operat ing Tool or finger) . Set t he num ber of sam ples t o 10, for exam ple. Set t he high lim it and low lim it in AI Acqu ir e W a ve for m .vi t o default 0.0 V. Obt ain a default st at us of t he set t ings in bot h VI s. For t his, go t o m enu Operat e> > Make Current Values Default .

I n t he Front Panel of AO Upda t e Cha nn e l.vi, set in a volt age of 1 V or sim ilar ( using t he Operat ing Tool) . Ru n t he VI , AO Upda t e Ch a n n e l.vi. To r u n t he VI , use m enu sequence Operat e> > Ru n ( or, preferred, Ct rl/ R) . Then r u n AI Acquir e W a ve for m .vi and not e t he volt age read ( waveform array Digit al I ndicat or) . Click on t he up and down arrows by t he Y t o scroll t hrough m ore dat a point s. Verify t hat t hat send and receive are consist ent . Try som e ot her volt ages. Not e t he m axim um allowed is t he highlim it , 10 V. Close t he send and receive VI s. Leave M e a su r e .vi open.

PA.2 Sending and Receiving Voltages from the Front Panel •

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I n t he Front Panel of M e a su r e .vi ( version 2) , r u n t he VI ( Ct rl/ R) wit h a variet y of volt ages sent out and verify t hat t he send ( out put ) and read ( input ) agree. From t he Diagram of M e a sur e .vi, Double Click on M e a n .vi t o open t he Front Panel of t his VI . Not e t he X Array Digit al Cont rol and t he m ean Digit al I ndicat or. Now r un M e a su r e .vi wit h Send Volt s = 0.1 V. Not e t hat t he m easurem ent dat a appear in t he Array Digit al Cont rol. These are t he dat a point s t hat are averaged.

Now go t o M e a n .vi, Right Click on t he indicat ors, select Form at and Precision, and t ype 4 for Digit s of Precision. Then scroll t hrough t he array dat a ( by clicking on t he up and down arrows of t he Array Digit al Cont rol as shown in t he sam ple) and com pare t he num bers wit h t he m ean. There will probably be som e scat t er in t he least significant digit , due t o noise. Not e t hat t he num ber received and averaged is not exact ly t he sam e as t hat request ed t o be sent out . This is due t o t he discret e nat ure of ADC ( analog- t o- digit al conversion) and DAC ( digit al- t o- analog conversion) as discussed and dem onst rat ed in a following sect ion.

PA.3 Plotting Measured Samples •

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Open Plot Sa m ple s.vi. Prepare t he Diagram for displaying t he sam ples. For high resolut ion ( discussed lat er) , set t he high lim it and low lim it as shown in t he exam ple t o 1 V and 0 V, respect ively. The num ber of sam ples can be 10 t o 100 and is not crit ical at t his point . We only want t o gain som e experience wit h graphs and display t he point scat t er expect ed under t he condit ions set up here. The num ber of sam ples is 40 in t he exam ple.

Go t o t he Front Panel t o r u n t he VI wit h t he volt age sent out sim ilar t o t hat shown in t he exam ple, 0.1 V. This m ust be lower t han t he high lim it set t ing for t he DAQ input , which is 1 V. At t his volt age level, t here will cert ainly be som e dat a scat t er. Click on t he Y- axis num bers, go t o Form at t ing..., and set t he Digit s of Precision t o 3.

Now r u n t he VI repeat edly. Not e t hat even t hough t here is dat a scat t er, t he average value is relat ively const ant ( in t he Received Volt s I ndicat or) . Not e also t hat t he X- axis is in m sec. The t ot al t im e in t he graph is 40 t im es 1 m s ( including 0) and AI Acquir e W a ve for m .vi is set for 1000 sam ples/ sec. To set ( or verify) t he sam e sam ple rat e as in t he exam ple, open t he Front Panel of AI Acqu ir e W a ve for m .vi. Type in t he num ber 1000 for t he sam ple rat e and default t he value. To default , Right Click on t he indicat or and go t o Dat a Operat ions> > Make Current Value Default . Save t he VI and close. Re- r u n t he VI wit h Se n d Volt s = 0 .0 1 5 . Subt ract t he difference bet ween t he m easured value of 0.1 V and 0.14 V sent out . Com pare t he difference wit h t he resolut ion expect ed, as obt ained from Table PA.2. Not e t hat t he high lim it is 1V and t he m ode is Unipolar. TABLE PA.2

Unipolar

Range

Resolut ion

0 t o + 10V

2.44 m V

TABLE PA.2

Bipolar

0 t o + 5V

1.22 m V

0 t o + 2V

488 µ V

0 t o + 1V

244 µ V

0 t o + 500m V

122 µ V

0 t o + 200m V

48.8 µ V

0 t o + 100m V

24.4 µ V

- 10 t o + 10V

4.88m V

- 5 t o + 5V

2.44m V

- 2 t o + 2V

1.22m V

- 1 t o + 1V

488 µ V

- 500 t o + 500m V

244 µ V

- 200 t o + 200m V

122 µ V

- 100 t o + 100m V

48.8 µ V

- 50 t o + 50m V

24.4 µ V

PA.4 Using the Autoranging Voltmeter •

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Open a new VI in LabVI EW. Then Right Click on t he Diagram , and go t hrough Funct ions> > Select A VI .... and locat e Pr oj e ct A.llb.

Click on Volt m e t e r .vi and Click OK. Place t he icon on t he Diagram . Double Click on t he icon t o get t he Front Panel.

Now place AO Upda t e Cha n ne l.vi in t he Diagram of your new VI . This is in Funct ions> > Dat a Acquisit ion> > Analog Out put .

Double Click on t he icon t o open t he VI . Set t he device num bers t o m at ch t hat of your DAQ. Verify t hat out put channel 0 ( Chan0_out ) is connect ed direct ly t o input channel 0 ( Chan0_in) on t he connect or block or circuit board. Now r u n AO Upda t e Cha n n e l.vi repeat edly t o send out a series of volt ages, such as 0.09 V, 0.9 V and 9 V and for each, r u n Volt m e t e r .vi. Observe t he aut om at ic changing of t he lim it s set t ing for t he various volt ages sent out . Not e t hat t he volt age is always m easured wit h good precision. Try a negat ive volt age out .

PA.5 Observing the Oscilloscope Output Graph •

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To run t he oscilloscope of Fig. A.14, in t he proj ect library, Pr oj e ct A.llb, open VI FG_ A.vi. ( This VI can also convenient ly be opened from t he Diagram of a new LabVI EW VI .) Then under t he Browse m enu ( from t he Front Panel of FG_ A.vi) go t o Show VI Hierarchy. Locat e t he icon for Oscilloscope A.vi and Double Click t o open t he VI .

Ru n FG_ A.vi at various values of Vs ( Vac peak signal out ) and VDCout and observe t he com binat ion waveform out put in Oscilloscope A.vi. The lim it set t ing is 10 V. The funct ion generat or VI , FG_ A.vi, is discussed in a following sect ion.

PA.6 Discrete Output Voltage from the DAQ •

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The VI s for t his exercise are in Pr oj e ct A.llb. The first exam ple is for DAC ( digit al- t o- analog conversion) , where t he receiving resolut ion is m uch sm aller ( bet t er) t han t he sending resolut ion. This t herefore reveals t he discret e nat ure of t he out put volt age. The VI for assessing t he discret e nat ure of DAQ operat ion is D iscr e t e .vi. This VI first sweeps t he request ed volt age t o be sent out in a quasi- cont inuous m anner. The program m ed sweep increm ent size is Max Volt s/ 100. For exam ple, for a sweep range of Max Volt s = 10 m V, t he sweep increm ent s are 100 µV. However, t he out put volt age has a resolut ion of 4880 µV ( bipolar) .

> The receiving funct ion is set wit h high lim it and low lim it of m agnit ude 0.1 V. The resolut ion for receiving is t hus 48.8 µV, t hat is, m uch less t han t he t he out put volt age st eps of m agnit ude 4880 µV. We will exam ine, for exam ple, t he bipolar m ode of t he out put channels. For t his, we need t o verify t he DAQ configurat ion for bipolar out put . Go t o t he St art Menu> > Program s> > Nat ional I nst rum ent s> > Measurem ent s and Aut om at ion. ( There m ay be a short cut for t his on t he deskt op.) Open Devices and I nt erfaces and t hen Right Click on t he DAQ designat or and get Propert ies.Click on t he AO t ab and set bipolar. Open D iscr e t e .vi. Verify t hat Chan0_out is connect ed direct ly t o Chan0_in on t he connect or block or circuit board. Verify t hat in t he Front Panel of D iscr e t e .vi, Max Vout is set t o 10 m V ( for a sweep st ep size of 100 µV) and t hat t he high lim it is set for 0.1 V. Ru n t he VI . The exam ple of t his sect ion illust rat es what t o expect for t he case of t he DAQ configured for t he bipolar m ode. Not e t hat t he dc offset of t he DAQ has been subst ract ed from t he plot , such t hat t he m easured volt age appears t o be zero volt s for zero volt s sent out . A num ber for t he size of t he m easured st eps is indicat ed [ Vout St ep Avg ( m V) ] . I t is obt ained by t he VI as an average of all t he st eps. The num ber shown is expect ed, as it is t wice t he DAC reference volt age of Vref = 10V divided by 2 12 or 2Vref / 2 12 = 4.88m V where t he exponent is t he num ber of bit s

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of t he DAC. The st eps are 2.44 m V for a unipolar out put configurat ion. The graph on t he right is a plot of input - channel sam ples versus sam ple index. The dat a illust rat e t he point scat t er due t o noise. The noise- free num ber in t he plot at t he end of t he excut ion should be 2x4.88 m V = 9.76 m V. Not e t hat t he scat t ered sam ple point s are separat ed by a discret e value of 48.8 µV. An Array Digit al I ndicat or displays t he sam ples and a Digit al I ndicat or shows t he average. Try ot her full- range sweep values such as Max Out = 20 m V and 5 m V. Wit h Max Out = 10 m V, go t o t he Diagram and reset t he num ber of sam ples from 50 t o 500. Re- r u n and not e t he increased precision, for exam ple, in Chan0_in Array Avg.

PA.7 Discrete Input Voltage from the Circuit Board •

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For t his m easurm ent , we need a high- resolut ion out put volt age source. I f we are willing t o give up volt age range, t his can be accom plished wit h a sim ple resist or volt age divider. I n t he exam ple here, t he circuit form s an apporxim at e 100: 1 divider ( 270- and 2.7- kΩ resist ors) . This provides a source wit h a resolut ion of 49 µV ( bipolar) .

D iscr e t e .vi will be used t o invest igat e t he discret e nat ure of t he input channels. Open t he VI and set high lim it = 0.1 ( wit h low lim it = –0.1) , for a receiving resolut ion t hat is also about 49 µV. Use Max Vout = 1 V ( 1000 m V) . The out put volt age sweep range is t hen Max Vout / 100 = 10 m V wit h t he volt age divider. The program m ed out put volt age st ep size is Max Vout / 100 = 10 m V. Thus, aft er t he volt age divider, t his is 100 µV. The resolut ion of t he out put and input funct ions is sim ilar. Ru n D iscr e t e .vi. The plot is essent ially a st raight line wit h sim ilar out put and input resolut ion. Not e t hat t he volt age sent out ( X- axis) is t he act ual channel volt age and t hat t he volt age received ( Y- axis) is aft er t he volt age divider. Not e also t hat t he scat t er of t he input channel sam ples ( right graph) reflect s t he discret e nat ure of t he receiving funct ion and t he point s are separat ed by about 49 µV. Set high lim it = 10 V. Run t he VI wit h t he sam e sweep range ( exam ple below) . The out put volt age ( aft er t he volt age divider) has a m uch higher resolut ion ( bet t er) t han t he receiving funct ion. The st eps in t he sweep plot have a m agnit ude equal t o t he receiving resolut ion. Also, t he sam ple point s are scat t ered by t he am ount of t he resolut ion of about 4.9 m V. An exam ple of t his case is shown in Fig. A.18 ( Unit A) . To check t he value of t he differences bet ween scat t ered point s, r un t he VI on SLOW and halt t he execut ion in a t ransit ion region. Then st ep t hrough t he Chan0_in Array( m V) I ndicat or.

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The exam ple here illust rat es t he t ransit ion range of volt age bet ween st eps; t hat is, t he t ransit ion is not abrupt . This is due t o noise and t he bit uncert aint y t hat exist s in t he t ransit ion regions. Again, t he bit - uncert aint y effect m ay be observed during t he sweep wit h Plot Speed set on SLOW. For com paring t he t wo cases wit h t he t wo lim it values and wit h sm oot hing of t he dat a wit h averaging, use AvgD iscr e t e .vi. This VI r u n s t he subVI D iscr e t e .vi sequent ially wit h t he high lim it set t o 01 and 10 ( wit h t he low lim it of –0.1 and –10. The t wo plot s appear t oget her in a single graph in t he Front Panel of AvgD iscr e t e .vi. Open AvgD iscr e t e .vi and D iscr e t e .vi. I n AvgDiscr e t e .vi, verify t hat Max Out = 1000 m V and t hat Num ber Avgs is set at 5 t o 10. Ru n AvgD iscr e t e .vi t o com pare t he t wo plot s wit h dat a sm oot hing.

PA.8 Using the Simultaneous Sending/Receiving Function •

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Wit h Chan0_out and Chan0_in connect ed on t he circuit board, open FG_ A_ 2 .vi. Also open SR_ A.vi and Oscilloscope A_ 2 .vi. Open t hese from Browse> > Show VI Hierarchy. Run t he t op VI for various Vs and VDCout values. Run t he VI at various frequencies and not e t he change in Cycles and Sam ple Rat e. The num ber of cycles is increased wit h frequency aut om at ically t o offset delay bet ween sending and receiving. Not e t he Num ber of Sam ples in t he array as indicat ed in t he Front Panel of SR_ A.vi, for t he various changes. Ru n t he VI wit h SquareWave select ed. I n t he exam ple, VDCout = 5 V and Vs = 0.1 V. There is a slight offset in t his exam ple. The oscilloscope's high lim it and low lim it are set for 10 V and –10 V. Therefore, t he resolut ion is about 5% of t he Vs value. There m ay also be som e DAQ offset .

Laboratory Project B. Characterization of the Bipolar Junction Transistor for Circuit Simulation PB.1 SPI CE Param et ers and Transist or Diagram PB.2 SPI CE Equat ions PB.3 Diode- Connect ed Transist or Measurem ent s

PB.4 Measurem ent of βDC versus t he Collect or Current PB.5 BJT Out put Charact erist ic Measurem ent PB.6 Sim ulat ion of t he Out put Charact erist ic Measurem ent Exercises and Analysis ExerciseB.m cd- Proj ect B1.m cd- Proj ect B2.m cd- Proj ect B3.m cd.

PB.1 SPICE Parameters and Transistor Diagram SPI CE PARAM ETERS SPI CE N a m e

M a t h Sym bol

D e scr ipt ion

IS

IS

Sat urat ion current .

NF

nF

Forward- current em ission coefficient .

I SE

I SE

Base - em it t er leakage sat urat ion current .

BF

βF

I deal m axim um forward current gain.

NE

nE

Base - em it t er leakage em ission coefficient .

VAF

VA

Forward Early volt age.

BR

βR

Reverse current gain.

PB.2 SPICE Equations SPI CE Equ a t ion

D e scr ipt ion

B.6

Dc rat io of collect or current and t ot al base current .

From

Collect or current t o base - em it t er volt age relat ion for VBC = 0 V.

B.7

B.25 Form of ( B.7 ) t o calculat e I S.

B.7

Act ive- m ode collect or current t o base - em it t er volt age relat ion.

B.10 I deal base current .

B.12 Tot al base current in t he act ive m ode.

B.23 General equat ion for collect or current versus t erm inal volt ages of t he com m on em it t er.

B.26 General equat ion for collect or current wit h base leakage current and an art ificial βR.

B.38 Dc bet a versus collect or current .

PB.3 Diode-Connected Transistor Measurements

Com pon e n t s

Exercise care when forcing t he t ransist or int o t he circuit board. La bVI EW Com pu t a t ion s

Slope is from curve fit of ln( I C) vs. VBE Pr oce du r e •

D iode _ I V.vi is used t o obt ain t he current - volt age charact erist ic for Circuit s, B1 and B2. The result s will be inst alled int o t wo Cont rol Graphs of Be t a .vi ( below) . Running Be t a .vi t hen produces values for I C, βDC versus I C, and

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param et ers n F and I S. Connect Circuit B1. I n t he Front Panel of D iode _ I V.vi, set t he value of RE. Ru n D iode _ I V.vi and re- r un while reset t ing I nit ial Chan 0_out for Min I E of about 0.01 m A. The VI will halt for I E= 1 m A or Chan0_out = 10 V. Obt ain a log of t he result s. Default t he Front Panel t o save I nit ial Chan0_out . I t is used in t he next circuit . Connect Circuit B2. Set t he value of RB. Ru n t he VI . I t will halt for Chan0_out at about 10 V. Obt ain a log of t he result s.

Open Be t a .vi. Copy t he I E and I B dat a from t he graph ( log scale) of D iode _ I V.vi and past e t he dat a int o t he Cont rol Graphs I E ( log scale) versus VBE and I B versus VBE, respect ively. These dat a are saved in t he log of t he Front Panel of D iode _ I V.vi. ( Rem inder: For dat a copy and past e, Right Click on graph face and Dat a Operat ions/ Copy or Past e.) Default and save Be t a .vi.

Ru n t he com put at ion VI , Be t a .vi. Be t a .vi will com put e and plot βDC versus I C and indicat e param et ers n F and I S. Not e t hat t he plot uses t he values of VBE from t he dat a of I E. An int erpolat ion of t he VBE values of I B t hen is m ade t o find t he corresponding I B values.

Be t a .vi finds t he highest VBE on t he low end ( for I E or I B) and t he sm allest

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VBE on t he high end, such t hat t he t wo plot s coincide over t he full range of VBE in t he com bined- plot graph. Not e t he VBE scale in t he right graph of Be t a .vi. The com put at ion of NF uses t herm al volt age, VT, com put ed for T = 27°C. At t he low current s of t he m e asurem ent s, t he device heat ing is probably negligible and t he t ransist or t em perat ure is probably about 27°C. Obt ain a dat a file of m easured I B and I C for use in a Proj ect B Mat hcad file, Proj ect B1.m cd. Open I C_ I Bt oFile .vi ( below) from t he Pr oj e ct B.llb. Copy and past e t he plot s in t he graph on t he right side of Be t a .vi int o t he Cont rol Graph of I C_ I Bt oFile .vi. Writ e your file pat h and file nam e. The file m ust appear in t he folder wit h t he Proj ect B1.m cd.

For sim ulat ion only, copy and past e t he dat a st ored in t he log of t he Front Panel of D iode _ I V.vi. Follow t he procedure for Be t a .vi above.

PB.4 DC versus the Collector Current Measurements bDC versus t he Collect or Current " href= " ?x= 1&m ode= sect ion&sort Key= t it le&sort Order= asc&v iew= &xm lid= 0- 13- 0470651/ ch31lev 1sec4&open= t rue&g= &cat id= &s= 1&b= 1&f= 1&t = 1&c= 1&u= 1&r= &o= 1&srchText = " class= " v2" > Measurem ent

PB.5 BJT Output Characteristic Measurement

Com pon e n t s Sa m e cir cuit a s in PB.4 La bVI EW Com pu t a t ion s SPI CE I C versus VCE. This is perform ed wit h subVI SPI CE.vi. St raight - line curve fit from act ive- region dat a:

I Co

I C( VCE = 0) ( act ive- region ext rapolat ion)

VAF = Slope/ I Co Pr oce du r e •

Open subVI , I C_ VCEsu b.vi. This VI will send out a value of VBB and sweeps VCC t o sweep VCE. The m axim um VCE is set for 4 V. Set t he value of t he resist ors. Ru n and re- r u n while set t ing VBB for an act ive- region collect or current of about 0.5 m A. Not e t hat at t his collect or current , a m axim um VCE of 4 V should be at t ainable as t he circuit was designed ( PB.3, PB.4) for I Cm ax 1 m A for VRc 9V. Default and save.

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Now open VI , I C_ VCE.vi. Set t he value of t he resist ors. Set VBB from t he subVI , I C_ VCEsu b.vi. Set VCEm ax at 1 V. Ru n t he VI and adj ust BR for a best fit . Then re- r un t he VI wit h VCEm ax set at 4 V t o obt ain a good value for VAF. VAF is com put ed from dat a point s in t he range 1 < VCE < VCEm ax. Default and save t he Front Panel. Double check t o be sure t hat t he subVI is default ed and saved. The dat a are used in t he out put charact erist ic m easurem ent sim ulat ion.

PB.6 Simulation of the Output Characteristic Measurement Pr oce du r e •

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Sim I C_ VCE.vi sim ulat es t he out put charact erist ic m easurem ent and associat ed curve fit t ing. Dat a are supplied from an act ual m easurem ent from any sam ple I C_ VCEsu b.vi. The dat a include I C versus VCE and VBE versus VCE. Copy and past e t he t wo dat a set s from t he sam ple ( saved Front Panel or log dat a) I C_ VCEsu b.vi. Set up all values in t he Digit al Cont rols. The inform at ion will be used t o com put e and display t he out put charact erist ic, m easured and SPI CE, and various param et ers and dc variables in t he Digit al I ndicat ors. Param et ers βDC and I S are com put ed for VCE = VBE, according t o t he definit ions. VAF is com put ed from a select ed range of βDC from t he act ive region. ( Cont inued below.)

Ru n t he VI and re- r un while adj ust ing BR for t he best fit . Use a sm all VCEm ax for t his. Verify t hat VCEm in < VCEm ax for t his sim ulat ion. Not e t hat for t he best fit , t he SPI CE curve goes from slight ly great er t o slight ly less t han t he m easured dat a wit h increasing VCE in t he sat urat ion region. Re- r u n for com put ing VAF in various ranges ( e.g., 1 V t o 3 V, 2 V t o 4 V, et c) . Not e t hat VAF varies, and depends on t he volt age range, unlike t he ideal SPI CE basic m odel. Of prim ary int erest is t he evaluat ion range of 1 V t o 3 V, as t his bracket s t he bias volt age of 2 V of t he am plifier proj ect , Proj ect C1. Default t his case. Not e also t hat t he curves will fit in t he act ive region for any com binat ion of VBB and RB. However, t he βDC value will only be correct for t he act ual circuit values. For clarit y on t his point and ot hers, t he com put at ions will be repeat ed in t he Mat hcad proj ect file. Save t he result s.

Laboratory Project C1. NPN CommonEmitter Amplifier PC.1 SPI CE Equat ions and Pin Diagram PC.2 DC Circuit Set up and Param et er Det erm inat ion PC.3 Am plifier Gain at One Bias Current PC.4 Am plifier Gain versus Bias Current PC.5 Gain- Measurem ent Frequency Response Exercises and Analysis ExerciseC1.m cd - Proj ect C1.m cd

PC.1 SPICE Equations and Pin Diagram SPI CE Equ a t ion

D e scr ipt ion

Com m on Em it t er Am plifier wit h Rc ( bias) Load a vb = –g m RC g m = I c/ VT

C.17

Base- t o- collect or gain.

C.22

Circuit gain wit h large source resist or.

C.28

Precision base- t o- collect or gain.

C.15

Transist or input resist ance.

C.40

Transist or out put resist ance.

PC.2 DC Circuit Setup and Parameter Determination

Com pon e n t s

Use Proj ect C1.m cd for calculat ions. Verify bias of Circuit C3 ( i.e.VCC < 10 V) .

Pr oce du r e •

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Type in RC. Run Se t VCE.vi while re- adj ust ing VBB t o verify t hat 0.1 m A< I C< 1 m A can be obt ained wit hout VCC> 10V. VCC is ram ped up t o obt ain VCE= 2 V. This will be t he operat ing point ( bias) volt age in t he gain m easurem ent . Det erm ine VBB for I C= 0.1 m A, as in t he exam ple. Default and save t his in t he Front Panel, for use in t he next t wo part s. Now re- r u n and det erm ine t he value of VBB corresponding t o I C= 0.5 m A. This is used in t he next st ep. Circuit C1 is used t o obt ain dc param et ers as in Proj ect B. To obt ain a fresh set of param et er values, open subVI I C_ VCEsubC.vi. Set in RC and RB and VBB as det erm ined above for I C= 0.5 m A. Ru n t he VI . When it has been verified t hat t he VI operat es properly, open

I C_ VCE_ C.vi and set in RC and RB and VBB for I C= 0.5 m A in t he Front Panel of t his VI . Ru n t he VI t o obt ain values for VAF and I S. Get VAF for 1 V< VCE< 3 V. Default and save t he Front Panel t o preserve t hese num bers. These param et ers are also available for Proj ect C2 on t he npn – pnp am plifier.

PC.3 Amplifier Gain at One Bias Current

Com pon e n t s Com put e Cb for Circuit C3. ( Use Proj ect C1.m cd.) I t will be m ore t han adequat e for Circuit C2.

Su bVI s Se t VSD .vi ( Set Bias) FG_ 1 0 .vi ( Funct ion Generat or) FG_ 1 2 .vi ( Funct ion Generat or) SR_ 1 0 .vi ( Send – Receive Funct ion) SR_ 1 2 .vi ( Send – Receive Funct ion) Oscilloscope _ 1 0 .vi ( Chan0_in) Oscilloscope _ 1 2 .vi ( Chan2_in) La bVI EW Com pu t a t ion s

Pr oce du r e •

Connect t he addit ional com ponent s in Circuit C2, Rs, and Cb . Connect

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Chan2_in for reading for reading t he base signal volt age. Ga in Su b.vi sends out bias and signal volt age ( Chan1_out ) . ( The signal is superim posed on t he bias; t he bias is m odulat ed wit h signal.) Chan0_in reads t he response ( out put of am plifier) . The VI t hen resends t he input signal ( Chan1_out ) and reads t he response at t he base ( Chan2_in) . These result s are displayed in t he t wo graphs. The ac peak values are used t o calculat e t he gain. The VI also com put es and displays rπ, βDC, and βac.

Open Ga inSub.vi. Set t he Digit al Cont rols for collect or resist or, RC, base resist or, RB, and Rs. Rs is used t o com put e t he signal current t hrough Rs. Set Frequency at bet ween 10 and 1000 Hz. Set VBB for 0.1 m A as det erm ined wit h Se t VCE.vi. VCC( init ) m ust be less t han or equal t o 2 V. Default t he Front Panel t o hold t hese values for when Ga inSub.vi is used as a subVI . Rat io VBB/ Vs is set at 5. The VI uses t his t o set Vs = VBB/ 5, producing, roughly, I B/ I b = 5. This result s from I B = ( VBB – VBE) / RB and I b = Vs/ RB. This current rat io provides for operat ion in t he linear m ode. Ru n Ga inSu b.vi and verify I C 0.1m A. Verify t hat signals for Vbe = Vin and Vce = Vo appear t o be undist ort ed ( m aint ain sine- wave int egrit y) . Assess all num bers in t he Digit al I ndicat ors. At t he low current of t he m easurem ent , Gain should be very close t o g m ·RC. Default and save t he Front Panel t o save set t ings for t he next VI .

PC.4 Amplifier Gain versus Bias Current Pr oce du r e •

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Ga in.vi is t he m ain VI t hat obt ains t he volt age gain as a funct ion of collect or bias current . Open Ga in .vi and verify t hat VBB( init ) is set t o your value for I C= 0.1 m A and VBB/ Vs= 5. VCC( init ) will be forced t o 1 V in t he execut ion of Ga in.vi. Keep subVI Ga inSub.vi open t o help observe t he m easurem ent in progress and t o obt ain Front Panel inform at ion for t he m axim um current . Verify t hat t he correct dat a are default ed in t he Front Panel of Ga inSub.vi. The resist ors values are not reset in t he t op VI . Open 5 COLD ATA.vi. Open VI s using Browse> > Show VI Hierarchy from t he m ain VI .

Ru n Ga in .vi t o obt ain t he gain for a range of collect or current wit h m axim um IC 1m A. Not e t hat t here is a 5 0 0 m s delay bet ween bias st eps t o allow t he capacit or t o charge t o st eady st at e. Verify t hat Chan1_out ( Max) ( bias plus signal) does not exceed 10 V. Set t he file m ode swit ch t o Get File. Ru n t he VI t o obt ain a dat a file.

The dat a file includes result s for I C, a vb , βDC, and βac and r π. The dat a provide for m aking a com parison bet ween m easured dat a and SPI CE com put at ions in t he Mat hcad proj ect file. Default and save t he Front Panel of 5 COLDATA.vi for a dat a file backup. Default t he Front Panel of Ga in.vi t o save t he value of VBB for t he m axim um current . Default and save t he Front Panel of Ga in Su b.vi t o save t he value of VBE at t he m axim um current .

For obt aining a file from t he saved dat a in Ga in.vi, use Ga in D a t a .vi. Transfer t he dat a from t he t hree I ndicat or Graphs of Ga in.vi t o t he t hree equivalent Cont rol Graphs in Ga in D a t a .vi. Ru n Ga inD a t a .vi t o obt ain t he dat a file.

PC.5 Gain-Measurement Frequency Response

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Circuit C3 has t he input signal applied t hrough t he coupling capacit or. Chan0_out V( CCV) provides t he input and out put circuit bias. The base signal wit h dc rem oved is m easured again wit h Chan2_in. Reconnect t he circuit according t o Circuit C3. Connect t he t op of RB t o Chan2_out and t he bot t om of Rs t o Ch a n2 _ out . Open Se t VCEC3 .vi and r un t o det erm ine circuit bias I C and VCC. Not e t hat if VCC > 10 wit h VCE < 2 V, a sm aller value of RC or larger value of RB is required; t hat is, t here is not a valid solut ion. ( I f VCE 2 V for VCC = 10 V, t his is sat isfact ory.) This sit uat ion could occur if t he value of βDC used in t he resist or design calculat ion was not represent at ive of t he value for your t ransist or. When t he circuit operat es properly, default t he Front Panel t o save t he values. This saves a set of variable values for t he Mat hcad proj ect file. The VI for t he frequency- response m easurem ent is Fr e qRe sp.vi ( below) . The VI sends out a signal t hrough out Chan1_out over t he frequency range of) Freq( init ) t o 1 kHz. The response at t he base input node on t he source side of t he capacit or is m easured wit h in Chan2_in as in Circuit C2. Open Fr e qRe sp.vi and inst all your value of RC in t he Front Panel. Select Vs 5m based on Vbe ( r π/ Rs) Vs. Recall t hat r π versus such as t o obt ain Vbe current is cont ained in t he dat a file obt ained from Ga in.vi and in t he Front Panel of Ga in .vi. The inform at ion should also be saved in t he Front Panel of 5 ColD a t a .vi. Open subVI FG1 Cha n .vi t o m onit or t he waveform of t he signal from in Ch a n 2 _ in . Keep Se t VCEC3 .vi open t o verify t hat t he dc set up funct ions properly. Not e t hat t he dc set up process is configured t o be slow t o allow t he capacit or t ransient t o be com plet ed.

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Ru n Fr e qRe sp.vi. Verify t hat in Chan2_in ( ac peak) is about 5 t o 10 m V at t he highest frequency. Adj ust Vs accordingly. Verify t hat a flat response is obt ained at t he higher frequencies. I f not , a larger capacit or is needed. Default and save t he Front Panel t o preserve t he f3dB inform at ion. From t he Pr oj e ct C1 .llb, open XYToD a t a File .vi. Copy and past e t he graph dat a t o obt ain a frequency- response dat a set .

Laboratory Project C2. NPN – PNP Common-Emitter Amplifier with CurrentSource Load PC.6 SPI CE Equat ions and Pin Diagram PC.7 Measurem ent of t he PNP Param et ers PC.8 DC Circuit Set up PC.9 Measurem ent of t he Am plifier Gain Exercises and Analysis ExerciseC2.m cd - Proj ect C2.m cd

PC.6 SPICE Equations and Pin Diagram SPI CE Equ a t ion

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D e scr ipt ion

C.52

Am plifier gain.

C.44

Base- collect or gain.

C.53

Am plifier load.

C.40 , C.41

NPN and PNP out put resist ance.

C.47

Transist or out put resist ance.

C.67

Design frequency of t he am plifier.

PC.7 Measurement of the PNP Parameters

Com pone nt s, PN P Calculat e REp

Calculat e RBp

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Circuit C4 is for obt aining t he relevant SPI CE param et ers for t he pnp. Of int erest are VAFp , βDCp , and I Sp . To obt ain t he param et ers, connect Circuit C4 using t he resist ors calculat ed for t his part ( pnp) . These will also be used in t he com plet e am plifier. The VI for obt aining t he param et ers is I C_ VEC.vi. Open I C_ VEC.vi. I nst all, in t heir Digit al I ndicat ors, RBp and REp. Ru n t he VI I C_ VEC.vi wit h subVI I C_ VECsu b.vi open t o observe t he plot in progress. Reset VBB as necessary t o obt ain an act ive- region I C of about 1 m A. Verify t hat I C = 1 m A wit h | VBB| < 10 V can be obt ained. | VBB| should be roughly 10 V at I C = 1 m A for m axim um m easurem ent precision. Adj ust param et er βR for a curve fit using VCEm ax = 1 V. Not e t hat VCEm in is aut om at ically set t o 0.5 V for sm all VCEm ax.

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Det erm ine t he value of VAF specifically for t he range t hat includes t he bias 5 V. Set VCEm in = 4 V and value of VCE for t he am plifier, which is VCE VCEm ax = 6 V. Run t he VI t o obt ain VAF. Com pare t he result wit h VCEm in = 3 V and VCEm ax = 7 V. Not e t hat in bot h cases t he range bracket s t he operat ing point VCE = 5 V. Default and save t he Front Panel t o preserve t he param et er values. The com put at ional subVI , SPI CE_ I V_ Re p.vi, com put es t he SPI CE plot , which is plot t ed along wit h t he m easured dat a. The Form ula Node from t he Diagram of SPI CE_ I V_ REp.vi is shown below. A solut ion for I C as a funct ion of VEC using t he circuit and device equat ions is obt ained. This is also explored in t he proj ect Mat hcad file.

PC.8 DC Circuit Setup

Com pone nt s N PN RBp

RBn .

I f slight ly different , use RBp > RBn . Design I C = 1m A.

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Se t VCE2 .vi ram ps VBB downward from t he m axim um ,VBB( init ) = VCC( init ) . Thus, init ially, t he npn will be in sat urat ion and VCE will be very approxim at ely 100 m V. The first check is for one point , m axim um VBB = VCC = 10 V. The init ial goal is verify t hat t he npn is in sat urat ion and t hat t he current is great er t han 1 m A for VCC = 10 V. Connect Circuit C5. Not e t hat t he bot t om of RBp is now ground and Chan1_out m oves t o t he bot t om of RBn. Also, t he collect ors are connect ed t oget her and Chan1_in m oves t o t he base of t he npn. Move t he plus side of Chan2_in and t he t op of REp t o Chan0_out . Set in resist or values in Se t VCE2 .vi. Verify t hat VBB( init ) = 10 V and VCC( init ) = 10 V. Set t he Run Mode swit ch t o One VCC ( logic 1) . Ru n t he VI . Verify t hat I C> 1 m A and and t hat VCE is 50 t o 300 m V ( in sat urat ion) . Set VCE2.vi calculat es t he VCE operat ing point ( bias volt age) as ( VCC – VREp ) / 2 for any VCC ( opt im um signal swing m agnit ude) . When t he Run Mode is set t o Set VCE, t he execut ion of t he VI halt s when t his level of VCE is reached.

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Set t he Run Mode swit ch t o Set VCE. Run t he VI . Verify t hat t he execut ion halt s when VCE is about equal t o VCE( V) Op.Pt . Not e t hat in t he exam ple, I C = 1.14 m A for VCC = 10 V and VBB = 9.02 V. Verify t hat t he final VCE is close t o VCE( V) Op.Pt . Default t he Front Panel t o save t he values of RBn and REp. Se t I C.vi runs Se t VCE2 .vi as a subVI . I t ram ps VCC downward t o find t he VCC corresponding t o t he design I C = 1 m A. Open Se t I C.vi and have Se t VCE2 .vi open as well. Se t I C.vi will be a subVI in t he gain m easurem ent VI . Run t he VI t o verify t hat t he VI can det erm ine t he VCC corresponding t o I C = 1 m A. I n t he exam ple, VCC has been ram ped down t o 9.0 V and VBB is now down t o 8.1 V. The rout ine will occur aut om at ically in t he execut ion of t he gain m easurem ent VI .

PC.9 Measurement of the Amplifier Gain

Com pon e n t Com pu t a t ion

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Am pGa in .vi sweeps t he signal frequency over t he range f init < f s< 1000 Hz. Not e t hat on t he low end of t he sweep, t his is a fairly slow process. The funct iongenerat or VI sends several cycles at each frequency, which is, e.g., 1 sec/ cycle at f s = 1 Hz. The am plifier volt age gain is calculat ed at each frequency st ep. This is t he signal out put volt age, Vo , divided by t he signal input volt age, Vs. Vs is correct ed for digit al- t o- analog error. The correct ion is perform ed by subVI , D AC.vi. The first m easurem ent is m ade wit hout Cb . Ent er t he value of RBn in t he Front Panel of Am pGa in .vi. Alt hough it is default ed in Se t VCE2 .vi, it is needed in t he Top VI in t he calculat ion of a vb . Also open subVI 's Se t I C.vi and FG1 Ch a n .vi t o observe t he program in progress. At least t em porarily open Se t VCE2 .vi t o verit y t hat t he com ponent values in t he Front Panel are correct and have been m ade t he default values. Set Freq( init ) t o 10 Hz in t he Front Panel of Am pGa in .vi. Verify t hat VCC( init ) and VBB( init ) are set t o 10 V. Run t he VI . Upon com plet ion of t he execut ion t here should be a low- frequency plat eau in t he response curve. The VI uses t he m axim um in t he plot for t he am plifier ( circuit ) gain. The roll- off at high frequencies is due t o circuit board and t ransist or capacit ance. Not e t hat t he exam ple is wit h t he capacit or in place. There will be no low- frequency roll- off wit hout t he capacit or.

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Now reset VCC( init ) and VBB( init ) t o m at ch t he values in t he Digit al I ndicat ors ( in lieu of 10 V as in t he exam ple) . The dc set up will be considerably fast er. Re- r u n Am pGa in .vi t o verify t hat it funct ions properly.

I f t he gain curve appears already t o be in t he high- frequency roll- off at t he lowest frequencies, re- r un t he VI wit h Freq( init ) set t o 1 Hz. Re- r u n t he VI and adj ust X ( downward for increasing Vs) t o obt ain a Vo ( signal sine- wave peak) of about 1 V or about one- t hird of VCE ( operat ing point ) . Not e t hat t he DAQ lim it m ust be set at 10 V t o accom m odat e t he dc + signal m easured wit h Chan0_out . Therefore, t he out put signal volt age m ust be relat ively large t o have sufficient m easurem ent resolut ion. Log t he Front Panel. Add t he capacit or, Cb , t o Circuit C6. Set Freq( init ) t o 1 Hz. Ru n Am pGa in .vi. I f a proper select ion of Cb was m ade, t he response curve should have a flat port ion as in t he exam ple. The flat segm ent cont ains t he gain value. Not e t hat if f3dBlo indicat es 1 Hz, t hen it is less t han 1 Hz. I n t his case, lower Freq( init ) t o obt ain a curve t hat includes t he f 3dB frequency. I t m ay be necessary t o increase X ( decrease Vs) for a sat isfact ory value of Vo, as t he gain is higher wit h t he capacit or. Log t he Front Panel when a sat isfact ory result has been obt ained.