An Engineering Approach to Digital Design [Facsimile ed.] 0132776995, 9780132776998

Citation preview

William

I .

Fletcher

mmmm APPROACH

TO DIGITAL DESIGN (2>CV)(UCC0) = cvx cv = 0 + (2>CV)(CV = 0)(UCCO)

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RDY PD JAM •

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CYCLE PATH

i

YES

cont

SC +

U

7

u

4

SI

7

3

2

>1

'o

82S123 32 X 8

o Q o 7 o 6 o3

I X I O co
*—

except

after c," etc.

(3)

Semantics— assigning words definitions Definitions: assigning

(3)

Semantics— input/output specifications (commonly referred to as truth-table specifications) for the gates.

words

For example:

meanings or conceptualizations

For example:

APPLE

LION

A

B

C

LV LV

LV

HV

HV HV

LV

LV LV LV

HV

HV

AND

defines an

(4)

Gramma/— proper word

grouping structure and

(4)

Grammar— interconnection

function

rules.

punctuation. (a)

(b)

(c)

Outputs go to inputs, except under certain defined conditions. Inputs can be tied together if both are to be driven by the same source No output should be required to drive beyond its

(d)

variation in word grouping order for the purpose of proper information transfer during communication.

Syntax— the

For example:

Mary" conveys one message; however, the same words arranged differently, "Mary hit John" conveys "John

hit

drive limit.

Etc.

Syntax— circuit/network/system synthesis (clearly the same "words" can be so used to convey two quite unique "messages"). For example, the same "gates" interchanged

in

sequence yield

far different

results.

quite a different message.

A-

A+B+C

B-

C vs

A

B C

Digital

and

its

•

Symbology

B + C

9

example of the use of a higher order symbology to represent a much more involved process stemming from a basic science. Fig. 1-5.

DIGITAL

An

AND THE REAL WORLD

As mentioned

earlier, the

use of digital practices can be a viable method for solving

problems are emphasized stems from the fact that the major areas of involvement for electrical and digital engineers are the (1) measurement, (2) control, and (3) transmission of information and energy. Thus if we look at the "what we do," we find that we are continually trying to find solutions to problems related to the measurement, control, and transmission of information or energy in the domain of the real world. However, the real world tends to have a continuous nature. Because of this, the discrete domain needs to be buffered in some way. As a result of this buffering requirement, we should view the digital domain in the perspective shown in Figure

design problems in the real world.

The reason

that design

1-6.

However, Figure 1-6 does not completely describe the relation between the two domains because there are several important processes in the real world that are at least modeled as discrete processes. A few of these are: light, nuclear radiation, and the electric signals governing the human nervous system which are, interestingly enough, most definitely discrete phenomena. But for the most part, Figure 1-6 does depict the typical relation between the outside world and the digital domain. 10

Introductory Digital Design Concepts

Fig. 1-6.

The conceptualization

of the digital system

and

its

relation to the real world.

The interdomain converter depicted

in Figure 1-6

converts or translates information of one

domain

is

a specialized system that

into information of another

domain. For example, you will serve as a special interdomain converter shortly when you are asked to convert a decimal number to its binary equivalent This operation we define as an ANALOG-TO-DIGITAL CONVERSION. You will remember that one of the reasons for "why digital" is that digital systems are theoretically more reliable and

and temperature. This stems directly from the fact that digital systems are made up of arrays of simple and reliable single-pole / single-throw switches that are either open or closed. (These switches can exist as either mechanical, electromechanical or electronic devices, as is discussed later.) Thus we see a simple analog-to-digital conversion can be performed with a switch as shown in Figure 1-7.

Fig. 1-7.

A

less

subject to drift with time

rudimentary analog-to-digital conversion

Digital

and

the Real World

1

Since pure digital systems are

made up

of arrays of simple

and

reliable

switches with only two positions, a numerical system that already existed was

adapted to serve as the "tool" needed for utilizing the basic concept. This numerical math system, called the binary system, is based on the two symbols "0" and "1" in contrast to the decimal system which has ten symbols: 0,1, 2,..., 9. Remember that we are talking about a numerical system, not to be confused with Boolean algebra, which is a deductive mathematics related to a logic process and not necessarily a numerical value process. This is mentioned to avoid the confusion created by inter-relations between Boolean algebra, computers, and binary arithmetic. We should see now that in order to use a digital system, such as a digital computer for mathematical computations, we must first convert our mathematical symbolisms (decimal in this case) into binary symbolisms to allow the computer to perform this mathematical operation. Once this is done, the inverse process must be performed to convert the binary results into a readable decimal representation. The obvious question: "Is digital worth all of the conversion?" The answer cannot be simply stated in yes / no terms, but must be particular situation.

In certain instances,

Such would not be the case

if

we were

it

may

left to

the individual

and the

not in fact be worth the bother.

able to create

and use multiple-valued

systems to create a "totally decimal machine." Obviously, descriptors usable for our "decimal computer," there

if

logic

there were ten unique

would be no need

to convert

any information into the now required two-valued binary system. However, practically speaking, binary systems presently dominate and will continue to be the dominant system for some years to come. Since such is the case, and man ultimately must learn how to communicate with his machine, it is necessary that we study the processes involved in number conversion and the different codes used to represent and convey information. In the next section

converters verters,

called

we cover some

voltage /current

which are used

of the basics of the special interdomain

analog-to-digital

in large quantities in

and

digital-to-analog

con-

wide areas of application.

DIGITAL-TO-ANALOG/ANALOG-TO-DIGITAL CONVERTERS Our

discussion up to this point has brought us to the understanding that the real

world inputs are mainly continuous and nonlinear, and digital systems operate on sequences of discrete information. Further, we have indicated that digital systems,

many

have distinct advantages over the more traditional analog systems. Thus it is important that the digital engineer be informed of the basics of inter-domain conversions and methods of transforming continuous signals into sequences of discrete information, which then can be processed, transformed, and reconverted back to a continuous signal if need be. The two conversion processes in

are

cases,

commonly (1)

referred to as:

analog- to-digital (A/D),

(2) digital-to-analog

12

(D/A).

Introductory Digital Design Concepts

Consider the system shown in Figure 1-8, which illustrates the general model for a digital system used as a control system in the real world. We see from the figure that the single analog input fans-out into a multi-line definition for the digital system, which is quite simple to understand once the conversion technique is understood. For example, a voltage from the transducer as indicated in Figure 1-8 is sequentially sampled and held by the SAMPLE and HOLD network, then this sampled voltage is converted to digital words and displayed as a sequence of information in a parallel format acceptable to the digital system. Thus

A/D

we

see the

process as one of generating a time-spaced sequence of multi-digit informa-

tion that

is

linearly related to the assigned value of the analog input. Likewise in a

broad sense, the

D/A

process

is

one of

converting or transforming

linearly

multi-line digital information to a single analog signal. Inter-domain converters Digital

Output of a process monitor (transducer)

recording device

(the analog input)

a

a

"O

o

1

1 /

A/D

«

le/H

1 o.

E 03

CO

Digital

control

system Control

Analog

I

control

1

Filter

D/A Processed digital output

J

Fig. 1-8.

A

general model for a system that controls an analog process using digital

methods.

It

has just been mentioned that analog- to-digital converters require sampling

the input signal

if

this signal is

time varying. This immediately raises two questions

related to the sampling process:

(1)

"How

(2)

"Given a sequence of samples, how

often must the input signal be sampled?" is

the original signal reconstructed?"

Without a lengthy mathematical development, the answered by the Uniform Sampling Theorem:

first

question can be reasonably

Digital-to-Analog/Analog-to-Digital Converters

13

A is

band- limited signal that has no frequency components above

X Hz

uniquely determined by samples that are taken at the uniform rate of

In short, this theorem, which

proven in

many

{cycles

2X Hz

per second)

or greater.

sampled data systems, states that any band-limited signal can be reconstructed by appropriate filtering if it is sampled at a frequency which is at least twice that of the highest frequency component contained in that signal. For example, the complex signals generated in a hi-fi stereo system are considered to be band limited between 20 Hz and 20,000 Hz. Theoretically this signal could be sampled at a rate of 40,000 samples per second (2 X 20,000 Hz) and the discrete output of this sampling circuit could be filtered to completely recover the original signal. However, practically speaking, five times the highest frequency component is considered to be fairly is

texts dealing with

standard.

The reconstruction of a sampled analog wave form which has been digitized is generally done with a combination of a digital-to-analog converter and a frequency-selective network called a low-pass filter, as shown in Figure 1-8. A low pass filter is a special network that stops the passage of frequency components which exceed some specified cutoff frequency fc and passes all frequency components below fc It can be shown that if the data whose highest component is X Hz .

is

sampled

at the

frequency /0 then fc can be specified as ,

be pointed out that the larly true

when

SAMPLE/HOLD

when

out

D/A

is

A/D.

c

not always required. This

the period of the highest frequency

lower than the conversion time of the left

is

X 2 )(2) +

xl + ( a _ 2 )(2- ') +

•••

'

>

v

>0 :.(a_

x

)2

=\

By

successive multiplications

by the base

the

number can be evaluated

as

(2 in this case), the fractional portion of

shown:

0.75

2

L50

(i±O50) =

n

2 0.50 >

a

1.00

0.00 )

a -3

a —m

Thus we

0.00

0.00

see

(19.75) 10

=

(10011.110) 2

Number Conversion by

Substitution

27

Now

going back to the original problem where 19.75 volts were present on the input of our analog-to-digital converter, we would expect to see the voltage equivalent to the representation in Figure 1-16. IMSB] High 1

Low

Low eight-bit

o

o

High

A/D

Assuming

1

binary

1

relates to a high voltage

High

19.75 volts

a

1

in this

case

High 1

High 1

Low

0

lsb:

The output

Fig. 1-16.

To

this

point

we have

voltage representation of 19.75 for an eight-bit

illustrated

(1) Direct Substitution:

A

A/D.

two methods of number conversion:

technique whereby a

number (N) r can be con-

verted to base s by directly substituting into the following:

(JV),= "2

(aj) -(rJ) s

j=-m (2)

s

and carrying out the indicated mathematics in base = 5. Divide/ Multiply by Radix: A technique whereby a number (N) r can be converted to base = 5 by dividing (multiplying) (N) r by s using base = r arithmetic.

These techniques have been generalized to any system-to-system conversion. However, when base systems other than 10 are encountered, there can be difficulty carrying out the mathematics in a different base system. To avoid this, both techniques can be used to convert a given number in any base to any other base and use only decimal arithmetic. For example:

(N) r = (X) s n

where

r^lO StMO

First

(N) r = (y)io by (Y) l0

We

see that

(N) r

is

= (X) first

s

substitution

by divide/ multiply radix

converted to (Y) w a base 10 number, by direct ,

Next (Y) l0 is converted to (X) s a base s number, by divide/multiply by radix s, which is another decimal arithmetic exercise. This procedure is best understood by examples. substitution using only decimal arithmetic.

28

Introductory Digital Design Concepts

,

Example

Convert the decimal number (105) 10 into its: (a) binary, (b) trinary (base 3), (c) quinary (base 5) and (d) octal (base 8) equivalents by the divide method. 1-2:

Solution:

Remainders

Successive divisions

2 105

(a) binary:

+(1101001);

1

2j52

1

2J26

0

2J13

0 1

2J06

0

2J03 2|01_

1

00

1

3

(b) trinary:

1

105

(10220),

0

3J35

2

3J03

2

3]01_

0

00 (c)

(d)

quinary:

5

octal:

1

1

105

K410).

5J2T

0

5J04 00

1

4

8 105 1

1

8J13 8

5

J0J_

00

Example

Make

1-3:

1

the indicated conversions

for

the

following numbers

(substitution method), a.

(743) 8

= (?) 10

Solution:

7x8 2 + 4x The

solution to this

8

1

+3 X8° = ?xl02 + ?xl0 + ?xl0° 1

problem involves finding the equivalent decimal value of

each of the terms on the left-hand

Powers

Coefficients (7)s

(4) 8

(3) 8

= = -

side.

2

(7), 0

(8

(4) 10

(8*)8

= =

(3) 10

(8°) 8

)8

Total

(64) I0

(7)io

(8) 10

(4), 0

-0)io

(3)io

X X X

(64) 10 = (448) 10 (8) 10

(l),o

= =

(32) 10 (3)io

(483) 10 b.

(432) 5

=

(?>

Number Conversion by

Substitution

Solution:

4x5 2 + 3x We

can find the solution

conversion to base

5

+2X5° = ?X7 2 + ?X7' + ?X7°

1

10.

Powers

Coefficients 2

= = =

(4) 5 (3) 5 (2) 5

problem by performing an intermediate step of

to this

(4)io

(5

(3),o

(5') 5

(2),o

(5°) 5

= = =

)5

Total

X(25)

(25) l0

(4), 0

(5),o

(3),oX(5) 10

(0,0

(2),oX(l) 10

1

= (100) 10 = (15) 10 = (2) I0

o

(H7).o This number can

now be

converted to base 7 by the division process.

Remainders

Successive Division

71117

K225) 7

,

7|_16

5

7 [02

2

00

2

Check: (225) 7

Remember, symbol

=

(2) 10

x(7 2 )

+

(5) 10

X

1

o

o\

(7°) 10

+ _ =

(2) 10

98

+

X(7

,

+

14

7 in base 7 does not exist, but

) 10

=

5

is

(1 17) 10

conveyed by (10) 7

Likewise, the symbol 8 in base 8 does not exist, but the decimal value

represented as (10) 8

Example a.

;

and so

.

is

forth.

Convert the following numbers,

1-4:

(101101)2 =(?) 10

Solution (substitution method): 1

x

2

5

+

0

x

2

4

+

x

1

2

3

+

1

x

2

2

+

0

X

2

1

+

1

X

2°

=

(45) 10

Solution (division method) : *

Remainders

Successive Division

10101101101

b.

r*(45) 10

ioio |ioq

(ioi) 2

000

(100) 2

= =

5

4

(1101101) 2 = (?) 10

Solution (substitution method):

x

1

2

6

Some

+

1

x

2

5

+

0

x

2

4

+

1

x

2

3

+

1

x

2

+0x

2

1

+

1

x

2°

=

(109) 10

other examples can be used to show the process involved with converting

fractional values into equivalent bases.

*

2

Remember

:

( 1

0) 0 = ,

(

1

0 1 0) 2

Introductory Digital Design Concepts

Example (c)

Convert the number (0.875) 10 into

1-5:

(a) binary, (b) trinary,

its:

quinary, and (d) octal equivalents using the multiplication method. (a)

binary:

(0.875) 10

1.750 1.500

X2 X2 X2

(O.Hl):

X

tfnoo) 8

1.000

(b)

trinary:

(c)

quinary:

(d)

octal:

(0.875), 0

8

7.000

There

exists

a simple

method

conversion of binary numbers into any base that

and so

forth.

The number system

is itself

a power of 2; that

that uses 16 as

its

hexadecimal, and uses the symbols 0 through 9 and the alphabet, A, B, C, D, E, and F, to represent the 16 values as

TABLE

1-3

Decimal

into their

In fact, this process can be extended to the

equivalent octal representations.

16, 32,

numbers

for converting binary

base

first

is

is,

4, 8,

referred to as

six letters of the

shown

in

Table

1-3.

Decimal-binary-octal-hexadecimal equivalence number representations

Binary

Octal

Hexadecimal

Decimal

Binary

Octal

Hexadecimal

8

1000

10

8

1

0

0000

0

0

1

0001

1

1

I

9

1001

11

9

2

0010

2

2

I

10

1010

12

A

3

0011

3

3

I

11

1011

13

B

4

0100

4

4

12

1100

14

C

5

0101

5

5

13

1101

15

D

6 7

0110

6

14

1110

16

0111

7

6 7

15

1111

17

l

l

I

l

l

Number Conversion by

E F

Substitution

31

number

a binary

If

being converted to an octal representation, instead of

is

you need only to make groups of three bits each the radix point, and then find their equivalent total value to number. For instance, from our previous examples:

the previously described processes,

on

either side of

produce the octal

Example

1-6:

101001.1 11) 2 = (151.7) 8

(1

001

T

1

m

001

10]

'

1

The binary to hexadecimal See Example 1-7.

Example

1-7:

ono

lorn 9

6

More

7

1

1) 2

is

done by grouping four

bits at

a time.

= (69.£) 16

inp

j

E

'

and

similar

is

be said about octal and hexadecimal number representations in a future

will

on codes.

section

1-11

101001.1

(1

t

COMPLEMENTS OF NUMBERS mathematical relationship between numbers that allows numerical subtractions by performing addition operations. In the decimal system, using a number's complement and a pencil and paper to perform subtractions yields no savings whatsoever, as will be shown. However, in the binary system complements are easily obtained and using the same hardware to add and subtract represents a

There

exists a

considerable savings.

r's

complements. The definition of the

r's

complement of a number

TV

is

as

follows:

(N) rc where n

and

r

(d) (e) (f)

n

—N

if/V^0,

0forW =

(

3

-

illustrate the process of finding the r's

c

f

.

see that determining

subtraction process

numbers 32

complement:

147

c

Thus we

0

in the integer portion of TV

= 853.00 (0.53) 1Or = 1-0.53 = 0.47 3 147.53) IO = 10 - 147.53 = 852.47 4 (1010) 2f = 2 - 1010= 10000- 1010 = 00110 (0.101)2 = 2°-0.101 = 1.0-0.101 =0.011 4 (1010.101) 2 = 2 - 1010.101 = 10000- 1010.101 =

(a) (147) 10f .= 10

(c)

r

= number of digits = radix number

The following examples

(b)

=

if

an

r's

the definition

complement is

of a

101.01

number

followed explicitly.

TV requires

some

However, with binary

there are shortcut techniques that bypass the subtraction requirement.

Introductory Digital Design Concepts

The

first

of these techniques

(1) Invert

each

is

done quite simply

number

digit of the

in a two-step process:

(referred to as the "logical complement"),

then (2)

add

1

to the least significant digit of step (1).

For example, given: ...00010110.0110 step(l)...

11101001.1001

step (2)+ ...

This technique

is

1

11101001.1010

widely used in digital computers and can be quickly

accomplished with any modest instruction set. The other of these techniques can be done by examination as follows. Given: ...00010110.0110000... Procedure: leaving

digits

all

unchanged and has no effect.

Thus

the 2's

from the right end of the number scan to the left, unchanged until the first 1 is encountered. Leave this 1 Start

invert the rest of the digits to the

complement of ...00010110.011000...

Subtraction with

r's

=

...

11101001.101000...

complements. The subtraction of two positive base

(1)

M and S, (M— S) goes as follows: Add M to the complement of S.

(2)

Check

numbers

Crossing the radix point

left.

r

r's

(a) If

the results for overflow carry:

an overflow carry

sents (b) If

discard

results,

it.

The

rest of the result repre-

(M-S).

an overflow carry does not occur, the

negative. Therefore, take the

r's

result of the first step

complement of

the results

is

and add a

negative sign to the results.

Consider the following examples: (a)

(A/-S) = (1010-0111) 1010

overflow carry

2's

0011 -+

+ 0011

discarded

(b)

complement of 01

1001

1

answer

(M-5') = (0111-1010) 1

0111

0110 I

no overflow carry +

1000

complement

of 00 1

1 1

.0 100

11.0110

discarded

answer

Thus

complement technique employing the same hardware used the 2's

two binary numbers perform additions is simple and

for subtracting to

straightforward.

(r-l)'s complement

number

N

is

The

definition of the "r

minus one" complement of a

as follows:

(N) r _ hc

=

r

n

-r- m -N

= number of digits in the integer portion of N m = number of digits in the fractional portion of N r = radix number

where

n

The following examples

illustrate the process of finding the

(r—

l)'s

complement:

=\tf- 1- 147 = 852.00 2 (0.53) 9c = l-10~ - 0.53 = 0.46 3 2 (147.53) 9 c = 10 - 10~ - 147.53 = 852.46 4 (1010), c = 2 - - 1010 = 0101. = — 2~ 3 — 0.101 =0.0101 11... (0.101)i ^ 4 -2~ 3 1010.101 =0101.010111... (1010.101), c = 2 {\41\

(a)

(b) (c)

(d)

c

1

(e)

1

(f)

Again arriving processes

if

at

an

(r

—

l)'s

the definition

is

complement

of a

number

some subtraction

TV requires

followed explicitly. However, there

is

also a shortcut

complements that requires no subtraction. This is done quite simply by complementing each digit (0 or 1) of the number up to the most

method

for finding l's

significant digit specified. (...

0001010.101000.

..)i,c

Subtraction with (r— l)'s complements.

...1110101.010111...

The subtraction

(1)

M and S, (M—S), goes as follows. Add M to the (r— complement of S.

(2)

Check

numbers

of two positive base r

l)'s

results for

overflow carry:

an overflow carry exists, add it to the least significant digit. If an overflow carry does not exist, the result is negative. Therefore, complement the results and add a minus sign in front.

(a) If

(b)

Consider the following examples:

34

=

Introductory Digital Design Concepts

(a)

(M-S) = (1010-0111) 1010 lOOO ^Ts complement of 01

overflow carry

A

add around

1

0010

—

1

0011

answer

(b)

(M-5') = (011 1-1010) 0111 0101 -^rs complement of 1010

no overflow carry 0

1

100-^-0011 answer

(c)

(M-S') = (1010.101000-

111.01000)

0001010.101000 1111000.101111

C

0000011.010111

0000011.011000

answer

From

we

complement of a binary number is easily accomplished, the subtraction of this number from another is at most a three-step process, two of which use the same computer hardware required to perform a straight addition. The other (bit INVERSION) is a standard feature of most digital computers. Further, there are other special number notations related to digital computing. Those interested are referred to other references.

1-12

this exercise

see that

if

the

CODES Coding and encoding monly referred to as

is

the process of assigning a group of binary digits,

"bits,"

to represent,

tag,

identify,

com-

or otherwise relate to

multivalued items of information. By assigning each item of information a unique

combination of bits (l's and 0's), we transform some given information into another form. In short, a CODE is a symbolic representation of an information transform. The bit combinations are referred to as "WORDS" or "CODE

Codes

35

WORDS."

There are some other general definitions assigned to with which you should become familiar. These are:

bit

combinations,

or — a binary Bytes — usually a group of eight Nibbles — usually a group of four Words — a group of bytes; usually a word has two bytes or Bit

digit (1

0)

bits

bits

four nibbles

The encoding of information can be an intricate and involved process, particularly when data security is of importance. However, encoding is not nearly as difficult as decoding that same information without knowledge of the encoding scheme. There are many different coding schemes, each having some particular advantages and characteristics. One of the main efforts in coding other than security is to standardize a set of universal codes that can be used by all. Some typical

examples of codes are given as follows:

(1)

binary codes

(2)

binary coded decimal codes

(3) reflected

codes

(4) unit distance (5)

codes

alphameric codes

(6) error detecting

1-13

codes

BINARY CODES As

illustrated in the analog-to-digital conversion

among

example, there

discrete signals, binary circuit elements (switches),

is

a direct analogy

and binary

digits;

and a

combination of n binary digits can represent the conditions of n switching elements in a digital system. These conditions (voltage in electronic systems) can represent discrete elements of information other than simple numeric values. The assignment of "bit patterns" to discrete elements of information

Two

is

generally referred to as

examples of binary coding schemes are illustrated in Figure 1-17. Note that Code X is a code for the decimal numbers 0 through 15 that assigns the binary codes which are equivalent to their numeric value. Code Y is encoded in yet another way. If n elements of information in some form are to be coded with two-valued bits, the question arises as to how many bits are required to assign each element of the original information a unique code word (bit combination). It should be noted that unique is important, otherwise the code would be ambiguous. Probably the best way to approach the number of bits required to assign a unique code to any number of information elements is to evaluate how many unique code words can be derived from a combination of n bits. binary coding.

36

Introductory Digital Design Concepts

Four-bit

Four-bit

Decimal

Binary

Binary

Code

Code X

Code Y

0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0

0 1

2 3

4 5

6 7

8 9 10 12 13 1

A

15

A

Fig. 1-17.

0 0

1

0

1

0

1

1

0

1

0 0 0 1 1 0

1

1

1 1

1

1

0 0 0 0 0 1

1

0

1

0

1

0

1

1

1

0 0

1

1

1

1

1

1

0 0 0 1 1 0

1

1

1

1

1

0 0 0

1

1

1

1

1

0

1

1

0

1

1

1

1

0 0 1 0 0 0 1 0 0 0 1

1

1

1 1 1

1

simple example of binary

codes assigned to the decimal numbers

0 through

15.

For example: Let n = number of

bits in the

code word and x

= number

of

unique words. If

«=1, then x = 2 n = 2, then x = 4 a? = 3, then x = 8

n

From

this

= j,

then x

we can conclude

that

(0,1)

(00,01,10,11) (000,001,... Ill)

—

2J

if

we

are given

x elements

of information to

code into binary coded format, the following expression must hold:

x

\og2 x

or

j > 3.32 log 10 x

where j — number of bits in code word. From this we can evaluate how many

bits

would be required

to

code the 26

alphabetic characters plus the 10 decimal digits as follows:

26 alphabetic symbols

+

10 digits .'.

=

36 discrete elements of information

j > 3.321og 10

or j

>

5.16 bits

Since bits are not defined in fractional parts, six-bit

(36)

we know j>6.

In other words, a

code would be required that leaves 28 unassigned code words out of the 64

which are

possible.

Binary Codes

37

1-14

BINARY CODED DECIMAL CODES There are many Binary Coded Decimal codes (BCD), all of which are used to represent decimal digits. Therefore, all BCD codes have at least four bits and at least six unassigned code words. Some examples of BCD codes are shown in Table 1-4. These are:

BCD

code, sometimes referred to as the Natural Binary

(1)

8421

(2)

Decimal code (NBCD); Excess-3 code (XS3);

(3)

5421 code;

(4)

84-2-1

(5)

biquinary code.

TABLE

1-4

code

+ 8, +4, -2, -

(

Coded

1);

BCD codes

Decimal

8421

Excess-3

5421

84-2-1*

7421

5311

Value

Code

Code (XS3)

Code

Code

Code

Code

Biquinary

8421

8421

5421

84-2-1

7421

5311

ABCDEFG

0

0000

0011

0000

0000

0000

0000

0100001

l

0001

0100

0001

0111

0001

0001

2

0010

0101

0010

0110

0010

0011

3

0011

0110

0011

0101

0011

0100

4

0100

0111

0100

0100

0100

0101

0100010 0100100 0101000 0110000

5

0101

1000

0101

1011

0101

1000

1000001

6

0110

1001

0110

1010

0110

1001

1000010

7

0111

1010

0111

1001

1000

1011

1000100

8

1000

1011

1011

1000

1001

1100

1001000

9

1001

1100

1100

1111

1010

1101

1010000

*Note: Dashes

(

—)

are minus signs.

There are many

BCD

codes that one can contrive by assigning each column or bit position in the code some weighting factor in such a way that all of the decimal digits can be coded by simply adding the assigned weights of the 1 bits in the code word.

8421

For example:

9

is

coded 1001 1

The

NBCD code

in

NBCD,

which

is

interpreted as

X8 + 0X4 + 0X2+ 1x1=9

handy and widely used code for the representation quantities in a binary coded format. For example: (19.75) 10 would be represented in NBCD as is

a

(i9.75) 10

38

- (goo? TooT onT

Introductory Digital Design Concepts

OlOl) nbcd

of decimal

should be noted that on the per digit basis the equivalent of the decimal digit it represents. It

As mentioned above,

BCD

there are

many

NBCD code is the binary numeral

possible weights that can be assigned in

and because of this there are some desirable properties that one code has over another which makes it more applicable. At least two of these properties give some figure of merit to a given code. These are: order to derive a

(1)

code;

The self-complementing property and

(2) the reflective property.

1-15

BCD CODE PROPERTIES When

be performed, often an arithmetic "complement" of the numbers will be used in the computations. Certain codes have a distinct advantage in that their logical complement is the same as the arithmetic complement. For example, the 9's complement of an Excess-3 code word is the same as its logical complement. This has a particular advantage in machines that use decimal arithmetic. Some examples of this self-complementing feature in some BCD codes are shown in Table 1-5. arithmetic

is

to

TABLE

1-5

Self-complementing

BCD codes

Decimal

631-1

2421

Excess-3

Value

Code

Code

Code

631-1

2421

8421

0

0011

0000

0011

1

0010

0001

0100

2

0101

0010

0101

3

0111

0011

0110

4

0110

0100

0111

5

1001

1011

1000

6

1000

1100

1001

7

1010

1101

1010

8

1101

1110

1011

9

1100

1111

1100

The second property mentioned above was the "reflection" or "reflective" property. The 9's complement of a reflected BCD code word is formed simply by changing only one of its bits. A reflected code is characterized by the fact that it is imaged about the center entries with one codes are shown in Table 1-6.

bit

changed.

Some examples

BCD Code

of reflective

Properties

39

TABLE

1

-6

Reflective

1

Code 2

Value

ABCD

WXYZ

0

0100*1010«-

3

0000^0001^0010)

(a)

An

example two-variable

four-variable

\

TRUTH-TABLE

(b)

The

three-variable

TRUTH-TABLE,

TRUTH-TABLE.

A TRUTH-TABLE

as suggested

is

a tabular or graphic technique for

listing

combinations of input variables, arguments, or whatever they may be called, in a vertical order, listing each input combination one row at a time (see Figure 2-3). When every possible combination is recorded, each combination can be studied to determine whether the "output" or "combined interaction" of that combination should be ASSERTED or NOT- ASSERTED. Of course the informaall possible

tion used to determine

the

combined interaction or output must come from

studying arguments of the logic problem.

two- variable

normally 2-3(c)

TRUTH-TABLE

listed to the right of

show

the standard

Figure 2-3(a) illustrates the use of a

and how the output or combined

interaction

is

each possible input combination. Figures 2-3(b) and

form for three and four variable

TRUTH-TABLES.

In

what is suggested here is that after all of the input variables have been identified, and all the possible combinations of these variables have been listed in the TRUTH-TABLE on the left, then each row should be studied to determine what output or combined interaction is desired for that input combination. Furreview,

ther,

note that the input combinations are listed in ascending order, starting with

the binary equivalent of zero.

The

TRUTH-TABLE

also allows us to establish or

prove Boolean identities without detailed mathematical proofs, as

will

be shown

later.

The TRUTH-TABLE came into existence during the study when logicians used them to validate their thinking. fortunate that

its

TRUE/FALSE

early years of logic It is

somewhat un-

connotation has been carried over into

digital

hardware design. In digital design, the TRUTH-TABLE is used primarily to specify an INPUT/OUTPUT relation for a digital network, not to determine the truth value of an argument. You will find it closely related to the "functional tables" used in algebra to tabulate data from which we plot curves on an (x,y)

The TRUTH-TABLE

63

TRUTH-TABLE

coordinate system (see Figure 2-4(a)). Realistically speaking, the

can be considered analogous to the "transfer function" specification for an electronic amplifier system, where one is given a nonlinear amplifier specification in an INPUT/OUTPUT TABLE and then is asked to tailor the response of the amplifier system to meet the "best-fit" for the values specified in the table (see Figure 2-4(b)). fix)

-8 X

6

y = f(x) I

-2

6 I

-1

2

0

0

1

1

l

1

2

Jl

I

8

2

1

8

1

i

\

-4

\

/

\

-

\

1

2

f

-

\

1

V

1

~2 -1

1

-1 -1

0

0

1

2

2

8

2

(a)

.

(a)

An

(b)

illustration of the use of a functional table to describe a

illustration of the use of

the

-2 -1

\

1

ing,

Vout

in

Q

1

Fig. 2-4.

V

\ \

an

INPUT/OUTPUT

mathematical function, (b)

table to describe the transfer function of

an

The analog designer then goes about selecting components, designing, analyzbreadboarding, and "tweeking" until he meets the design criteria set forth in INPUT/OUTPUT SPECIFICATION TABLE. In the same manner, the

digital designer uses a

be met by a continue to

TRUTH-TABLE

circuit design.

refer

to

the

However,

as a set of discrete conditions that have to

in the interest of preserving tradition

To

illustrate

we

INPUT/OUTPUT SPECIFICATION TABLES

TRUTH-TABLES. On the other hand, we will change entry from FALSE to NOT-ASSERTED and the ASSERTED. the use of a

TRUTH-TABLE

in

1

entry

this

from

TRUE

interaction of these 2-5.

The

two

is

specification for

defined as

FLEN,

it

from some known specification. is specified in a TRUTH-TABLE, you must learn how to interpret the discrete nature of this INPUT/OUTPUT definition. This is done almost instinctively by considering each input combination (row) and inserting

will

be assumed at

this time,

Once

the output

Digital

Design Fundamentals

has been

filled-in

as

to

manner, consider the

Example 2-1: Let E = ENABLE, F = FLIP, where ENABLE and FLIP are logic mnemonics describing some definite action in a digital system. The

TRUTH-TABLE describing the combined the output FLEN and is shown in Figure

will

the interpretation of the 0

following example.

64

An

amplifier.

the conjunction

AND between each input variable OR

then in turn inserting the conjunction This technique is demonstrated in Figure 2-5. tion,

Fig. 2-5.

and

its

An

example

TRUTH-TABLE

interpretation.

Row Row Row Row

condition for that combina-

between each row statement.

E F

FLEN

2:

0 0 0 1 1 0

0 0 0

3:

1

1

0: 1

1

becomes obvious by examining the TRUTH-TABLE in Figure 2-5 that combined interaction of ENABLE and FLIP (FLEN) can be defined in two It

the

ways:

(1)

FLEN

is

ASSERTED

if

and only

if

ENABLE and FLIP are ASSERTED

or (2)

FLEN

NOT-ASSERTED if ENABLE and FLIP are NOTASSERTED, or ENABLE is NOT- ASSERTED and FLIP is ASSERTED, or ENABLE is ASSERTED and FLIP is NOT-ASSERTED

Now,

is

you study these two statements abstracted from TABLE, you should become aware of two points: (1)

The same or is

(2)

as

covered

The

the

TRUTH-

identical information resides in both statements, a point that

later in this chapter.

both statements relies heavily on the two conjunctions and OR. This is a very important point, and one on which a great deal of emphasis will be placed. clarity of

AND

AND

and OR serves as a bridge be shown that the grammatical usage of between a problem stated in words and a hardware realization of that same problem. Also, it will be found that and OR are associated with "gates" and "functions," which are discussed in the next section. It will

AND

A WORD ABOUT GATES AND FUNCTIONS be shown shortly that the foundation of logic design is seated in a well-founded axiomatic system called Boolean algebra, which will be shown to be what is known as a "Huntington system." In this axiomatic system the definition of the and OR operators is set forth, and these are found to be well-defined operators having certain properties that allow us to extend their definition to hardware applications. However, for the time being, note again the grammatical usage of the conjunctions and OR in Example 2-1. These conjunctions, sometimes referred to as connectives, actually suggest a function that can be emulated by some hardware logic device. This connection between grammar and hardware is mentioned again because of its importance in formulating a word statement that can be related directly to a hardware logic network. It

will

AND

AND

A Word about Gates and Functions

65

The

hardware devices just mentioned are commonly referred to as "gates." There are four basic "gates" used in varying degrees in logic hardware design.

logic

They

known

are

(1) the

AND

(2) the

OR

as:

gate,

gate,

NAND gate, the NOR gate.

(3) the

(4)

Keep

in

mind

"function" or "operation" refers to a logic

"AND

function,"

when we called

refer to

an

an actual piece of hardware, where operator. Thus, when we refer to an

that the usage of "gate" refers to

we

an

AND gate.

are referring to the logic operator

"AND

we

gate,"

This

This distinction

is

presented at

this

AND

point because each of the

and

OR

logic operators or

demonstrated shortly and used throughout the

is

In the author's opinion,

is

it

the other hand,

are referring directly to a piece of hardware

four gates mentioned can be used for both functions *

AND. On

text.

unfortunate that the names given to the logic

gates are so closely associated with the basic logic operators

(AND, OR).

This

leads one to believe they are single function devices, which they most emphatically are not\ For example, because an it

provides only an

provide only

an

OR

OR

AND

AND gate

function.

is

called such,

Likewise,

it

is

it is

OR

gate

when an recommended for an

is

OR

easy to believe that

functions, leading to bewilderment

operator and an

easy to believe that gates

AND gate used for AND operator. For is

example, mathematical statements, sometimes referred to as Boolean expressions, are synthesized from a

word statement using

AND

and

OR

connectives,

and then

implemented with hardware gates, and this process should be straightforward. However, it has been found that confusion sets in when it is suggested that the AND functions be implemented with OR gates and the OR function is implemented with AND gates. To illustrate at least in part how a word statement can be formulated into a mathematical statement (Boolean expression), consider Example 2-2. in turn this expression

Example

is

is an example of how a conditional statement can be symbolized into a mathematical statement.

The following

2-2:

Bob

will

go to school

//

Carol and Ted go to school, or Carol and Alice go

to school.

This statement can be symbolized as a Boolean expression as follows:

B/FC AND or

i

B = (C

I •

T OR C AND A l

T) + (C

l •

A)

*The words "operator" and "function" are used interchangeably throughout our

66

Digital

Design Fundamentals

discussions.

Thus

word statement is transformed into a mathematical AND and OR connectives the following symbols.

the information in the

expression by assigning the

-AND

•

-OR

+

The next step is to transform this Boolean expression into a hardware network, and this is where the rub comes. Since AND and OR connectives are used, the AND and OR gates should always be used right? WRONG! Maybe AND and OR gates should be used, but, on the other hand, it might be better to

—

use

OR

gates for the

The this

AND functions and NAND gates for the OR functions.

actual hardware implementation for this example

is

not demonstrated at

we have not introduced the symbology for gates as yet. The main remember is don't confuse gates with logic operators and remember that the

time because

point to

four gates mentioned can be used for both

AND

and

OR functions.

THE LOGIC OPERATORS In the last section you were assured that a well-founded system exists that

is

based

on some well-defined AND and OR operators. Further, it was illustrated how a word statement can be symbolized and transformed into a mathematical-looking expression (Boolean) using these same operators. Then it was postulated that gates could be used as a hardware operator to transcend the "paper domain." With this importance placed on the operator coupled with our faith that all four basic gates exhibit both AND and OR operator capabilities, it is best that we define the AND and OR operators in terms of the ASSERTED response of a gate. It should be remembered that in order for a logic variable to be completely defined, a "lever' position associated with the ASSERTED conditions must be made. This level position can be associated with properties such as light, pressure levels of air and fluids, sound intensity levels, voltage levels, or any other measurdevices that are voltage level

information related from Definition:

A

"gate"

output.

is

this

made because we

be dealing mainly with responsive in this text, and because of this the level point on will be treated in terms of voltage levels.

able physical evidence. This point

is

defined as a multi-input

The output

level

(

>

2)

(HIGH/LOW)

will

hardware device that has a two-level of this gate

function of the two-level combinations applied to

its

is

a

strict

and repeatable

inputs. See Figure 2-6 for a

general model of a gate.

In reference to "level"

ASSERTED

OR

and ASSERTED, we

see that the "levels" assigned to

AND

and

The Logic Operators

67

determine the variability referred to as "exhibiting both

operator capabilities."

Two-level output that is a strict function of two-level input combinations

r

t

n inputs, each of which can take on one of two levels

Gate (hardware)

(HIGH/LOW)

The general model

Fig. 2-6.

Definition:

of a gate.

two possible output levels when ALL of its input are brought to a common level (Lx)*, and maintains this output level ONLY under this input condition, is said to exhibit the Boolean AND function.

A gate whose output transfers

Any

to

one of

AND

gate which exhibits the Boolean

distinctive-shaped symbol, as

Fig. 2-7.

shown

The

its

function

is

assigned a schematic

in Figure 2-7.

distinctive-shaped

symbol for any gate that exhibits the Boolean AND function.

Other schematic symbols are added to

on the number

A

Definition:

of inputs

gate

ANY

of

and assigned

whose output its

held under

ASSERTED

transfers to

levels.

common

levels

when

and this output level is input conditions where any one input or any combination of

inputs remain at the input level (Lx),

Any

symbol based

one of the two possible output

inputs are brought to a all

this distinctive-shaped

is

gate which exhibits the Boolean

distinctive-shaped symbol, as

The

Fig. 2-8.

symbol

shown

level (Lx),

said to exhibit the Boolean

OR

function

is

OR function.

assigned a schematic

in Figure 2-8.

distinctive-shaped

any gate that exhibits the Boolean OR function.

Like the

AND

distinctive-shaped

ASSERTED To

for

operator symbol, other schematic symbols are added to this

symbol

based

on

the

number

of

inputs

and

assigned

levels.

two definitions, consider the following. If a gate has three inputs (A, B, and C) and this gate's output transfers to either one of the two possible levels only when A and B and C are all at the same level (Lx), it is said to exhibit the Boolean AND function. Note that it is assumed that the other output level is the output under the other seven input conditions. Further, if a gate has three inputs (A, B, and C) and this gate's output transfers to either one of the two clarify these

•Note: The

68

Digital

level

Lx can be assigned

Design Fundamentals

either high or low.

possible levels

when A

or

same

three are at this

B

C

or

at a particular level (Lx), or

is

level (Lx),

when any two

this gate is said to exhibit

or

Boolean

the

all

OR

function.

From

AND

seems that if a gate is not exhibiting an function, it must be exhibiting an OR function. But this is not the case, for there are 256 different output specifications that can be made for a gate with three inputs, of which only four exhibit and OR characteristics. However, it is true that if an AND characteristic is identified for a gate, this same gate has an OR these definitions

it

AND

To

characteristic also.

we consider

illustrate this,

a two-input device whose output

can take on one of two voltage levels (a high voltage level and a low voltage level) based on all possible input voltage level combinations. We show this representation in an INPUT/OUTPUT SPECIFICATION TABLE; see Figure 2-9.

A

A C

Two-input gate

B

LV LV LV HV HV LV

LV LV LV

HV HV

HV

(a)

LV

HV

= low voltage = high voltage

(b)

(a)

Fig. 2-9.

C

B

Some

two-input gate, (b) The

INPUT/OUTPUT

specification for

that two-input gate.

By studying we

the

INPUT/OUTPUT SPECIFICATION TABLE

see that the output transfers to a high voltage

(HV) under

for this gate,

the unique input

combination of A AND B being at the same or common input level. In this case, both inputs must be at the high voltage level. Thus we can say the output of this gate

is

ASSERTED HIGH when A

HIGH. From

this

AND

we make

is

ASSERTED HIGH AND B This gate

the following definition.

is

is

ASSERTED

defined as the

and has been assigned the modified distinctive-shaped schematic symbol shown in Figure 2-10 when it is used for an AND operator or function. two-input

Fig. 2-10

The

gate

symbol for the two-input gate

when

AND

it

is

The

distinctive-shaped

AND

AND

distinctive-shaped

symbol

used for an

A

operation.

C(H)

B{H)

The mathematical function

descriptor (symbol) for the

The

first

B =

In fact,

LV LV LV

HV HV

HV

are:

•

the earlier statement that the

OR operation or function.

LV LV LV HV HV LV

A B = AB = A AB

and second symbols {A B and AB) are used

Remember

C

AND operator has not

been standardized. Some of the symbols which are commonly used

A AND

B

AND

we were assured

in this text.

gate can also be used for

that

if

an

an

AND existed, the OR

The Logic Operators

69

To illustrate this, consider the first PUT/OUTPUT SPECIFICATION TABLE. We see

was automatic.

three entries in

the IN-

the output of this gate

low voltage (LV) under the conditions of A OR B OR BOTH being a low voltage. From this we can say that this gate exhibits a Boolean OR

transfers to a at

ASSERTED LOW when A is ASSERTED LOW OR B is ASSERTED LOW OR BOTH are ASSERTED LOW. Thus the OR distinctivefunction with the output

AND

shaped symbol can be assigned to the gate when it is used for an OR operator or function. However, some added symbology must be given to help one identify the number of inputs and at what voltage levels the OR function is invoked (see Figure 2-11). Here we see a low ASSERTION level indicator, O, sometimes referred to as simply a state indicator or "ninny" or bubble (slang), has been added to the inputs

and outputs of

the basic symbol.

The

OR

distinctive-shaped

symbol

The low ASSE RTION-level indicator symbology used to indicate that at

To

Fig. 2-11.

The

when

used for an

it

is

it is

OR

the low level operator is invoked.

distinctive-shaped symbol for the two-input

interpret schematic

Look

which the

OR

AND

gate

operation.

symbols such as the one shown

in Figure 2-11:

symbol to identify the logic operator. In this case we see it as an OR function. Second: Look at the output. If a low ASSERTION level indicator O is present, the operator indicated by the symbol is ASSERTED LOW. If no low-level ASSERTION indicator is present, the operator indicated by the symbol is First:

for the distinctive-shaped

ASSERTED HIGH. ASSERTED LOW. Third:

Look

at the inputs.

If

In

this

low-level

case

output

the

ASSERTION

indicators

are present at the inputs, the operator indicated

symbol

LOW.

is

invoked when the inputs are

ASSERTION

indicator

the operator indicated

by the symbol

is

inputs are

inputs are

no

ASSERTED HIGH. ASSERTED LOW.

Taking another example that

illustrates

distinctive-shaped symbols, consider that

70

Digital

Design Fundamentals

by the

ASSERTED

low-level

If

is

is

present,

invoked when the

In this case

we

see the

the ease of the interpretation of

you were given the following symbol.

You You

First:

Second:

an

see

OR

see that the

no bubble

You

OR operator is ASSERTED HIGH

(i.e.,

at the output).

one or both of the inputs must be LOW before the output is to go HIGH, that is, the output is ASSERTED HIGH when one or the other or both

Third:

see that either

LOW level.

inputs are at a

Thus we

operator suggested by the basic symbol.

see that

we have

these schematic symbols. Also,

Take

a simple analysis process for quickly interpreting

it is

obvious that one should be able to adapt these

on faith that becoming familiar with the concepts of distinctive-shaped symbols will pay dividends in the future, for it allows you to do much of your work by simple inspection processes. For now, let us get back to the problem at hand, which is learning about the OR and AND operators of gates. Like the AND connective, the OR is also a conjunction and its position in a to a design process.

verbal statement case where as the the

all

is

it

important. Since the statement regarding the

inputs are

ASSERTED,

it is

common

"INCLUSIVE-OR." The commonly used

OR

OR

includes the

practice to define this function

functional descriptor symbols for

operator are

A ORB = A + B = AVB The A + B symbology

is

used in

this text.

Let us consider another two-input gate with an

CATION TABLE illustrated in

INPUT/OUTPUT

Figure 2-12.

A

A

B

LV LV LV HV HV LV

C

Two-input gate

B

HV HV Fig. 2-12.

SPECIFI-

Another two-input gate and

C LV

HV HV HV

INPUT/OUTPUT

SPECIFICATION TABLE.

We function

see

from the

last three entries in the table that this

ASSERTED HIGH when A OR B OR BOTH

This gate

is

defined as

distinctive-shaped symbol

the

in

OR

ASSERTED HIGH.

and has been assigned the Figure 2-13 when it is used for an OR operator

two-input

shown

OR

are

gate exhibits an

gate

or function.

Note the Here we

see this

first

INPUT-OUTPUT SPECIFICATION TABLE. exhibiting an AND function ASSERTED LOW when A

entry in the

same gate

The Logic Operators

71

A(H)

A C(H)

B

C

LV LV LV HV HV LV

B(H)

LV

HV HV

AND B is

distinctive-shaped symbol

for the two-input

used for an

OR

OR

gate

when

it

is

operation.

ASSERTED LOW. Thus the AND distinctive-shaped symbol is addition of the LOW-LEVEL ASSERTION indicators when an OR

are both

used with the gate

The

Fig. 2-13.

HV HV HV

used for an

AND operation or function (see Figure 2-14). The

AND

distinctive-shaped

symbol C(L)

LOW-LEVEL ASSERTION INDICATORS used to indicate the ASSERTED level

related

to the function defined by the

distinctive-shaped symbol

Fig. 2-14.

A

The symbol used

O

signal

OR gate

when used

for

special note regarding the general usage of low-level

Refer to Figure 2-2. Here This

an

for

indicates the

is

we

see a

affixed to the

LOAD operation of this

applied to this input. This

more complex devices

for the

O

is

device

is

an

AND operation.

ASSERTION indicators:

LOAD

input of the register.

performed when a low-level

considered to be a general schematic notation

that have each input function defined directly

on

symbol.

their

summary, we have demonstrated that both the AND gate and the OR gate can be used as AND and OR operators if you are free to choose the ASSERTED In

levels

for

your

signals.

Many

applications are used throughout this text that

reminded once more of the distinction between gate and operator or function. // should be noted that a strict avoidance of using a TRUTH-TABLE with Ts and O's to describe the INPUT/ OUTPUT specification of a gate was maintained. This was done to preserve the previous assignment of 1 = ASSERTED and 0 = NOT-ASSERTED. Using l's and O's to describe a gate operation masks out its dual application. Thus, TRUTH-TABLES with Ts and O's are used only to specify problem statements throughout this text. From this it is assumed that "problems" are something more illustrate this

very important point.

Also,

you

are

than a single gate situation. Also,

it

is

come in more than two inputs, but some operator, check a manufacturer's

important to note that gates

before arbitrarily using an n input gate for

data book to determine what gates are available. In the next section

more

is

covered regarding voltage levels and the practical

application of gates used to transform

72

Digital

Design Fundamentals

word statements

into

hardware

realizations.

HARDWARE ASPECTS RELATED TO ASSERTED AND NOT-ASSERTED CONDITIONS It is

now

time

about some more of the real-life hardware concepts related to Again let us restrict our discussion to the semiconductor type of

logic gates.

to talk

devices.

a fact that once an electronic logic hardware family has been selected

It is

such as Transistor-Transistor-Logic (TTL), or Complementary-Metallic-Oxide-

Semiconductor (CMOS), there

is

a definite set of voltage ranges that determine the

INPUT/OUTPUT relationship for each gate. For example: The SN7408, which is a TTL quad- AND gate package, requires both inputs of each selected gate to be at a voltage

> 2.0

volts. Also,

it

voltage to be

volt before the output

requires at least one of at,

is

its

guaranteed to transfer from ~0.0 to 3.6

inputs to be

high region

Region of uncertainty Asserted low voltage region Low-level noise margin

Fig. 2-15.

regions

An

illustration of a logic voltage

waveform showing

ASSERTED

voltage

and noise margin.

Hardware Aspects Related

to

ASSERTED and NOT-ASSERTED

Conditions

73

As

mentioned, you

just

what voltage times the

level

you would

ASSERTED

some other system.

will

find

at

times you have the choice as to

like to assign to the

ASSERTED

condition.

on you by the inputs given

levels are forced

Historically, phrases such as

POSITIVE LOGIC

Other

you from and NEGAto

TIVE LOGIC have been relegated to the concepts of TRUE = HIGH for POSITIVE LOGIC systems and TRUE = LOW for NEGATIVE LOGIC systems. Further,

you

POSITIVE

or

will

find that once a designer has chosen a logic system, be

NEGATIVE,

he

will stick

it

with the system throughout his design and

POSITIVE and NEGATIVE LOGIC. This fact, coupled with an apparent aversion to NEGATIVE LOGIC, has contributed largely to the fact that most basic material is treated from a POSITIVE LOGIC point of seldom,

if

ever, will

he mix

an appropriately chosen juncture, the NEGATIVE LOGIC is introduced quite modestly and then quickly forgotten, as far as actual applications are concerned. In this text it is found that "MIXED LOGIC SYSTEMS" are used freely, and that many times by using MIXED LOGIC, hardware savings can be achieved. It is therefore important to formally define POSITIVE and NEGATIVE LOGIC in terms of ASSERTED. These are the simple defini-

Then somewhere,

view.

at

tions:

POSITIVE LOGIC is defined by ASSERTED HIGH.

NEGATIVE LOGIC is ASSERTED LOW.

logic variables or

mnemonics

that are

defined by logic variables or mnemonics that are

Within any given system it is entirely valid to use both ASSERTED levels, and in most cases it is impossible to have strictly a POSITIVE or NEGATIVE LOGIC system if you are considering the system at the gate level rather than system level. Therefore, logic systems in general are truly MIXED, but few refer to them as such. As mentioned above, the ASSERTED voltage range assignment to be chosen or given must be remembered; therefore, we add the extra element to the mnemonic of each logic argument to aid the designer in remembering the ASSERTED voltage range. Keep in mind that this "extra element" is really only an aid when the logic family has been selected and the logic operator identified, and schematic diagrams are being drawn. The aid mentioned we defined as the POLARIZING ELEMENT and placed it at the end of the mnemonic as previously outlined.

The use of polarized mnemonics is a great aid to you as a designer using mixed logic, allowing you to use mixed logic assertion levels throughout your design without having to worry system.

This

is

why

it

is

felt

if

the system

is strictly

a positive or negative logic

that these concepts should be introduced at the

inception of logic studies so that they can be used freely and without the painful relearning that seems to

more

traditional positive

To

accompany the process after becoming and negative logic studies.

further strengthen the case for polarized

illustration of their value in clarifying

74

Digital

Design Fundamentals

familiar with the

mnemonics, consider another

an interface design problem.

Example

2-3:

which

a

Consider that you are to design a system (your system) to operate in some prescribed manner, which at this time is not important. What is important is that your system is to receive inputs from two other systems, one of is

POSITIVE LOGIC system

LOGIC system (B)

(A) and the other

is

a

NEGATIVE

(see Figure 2-16).

At the outset of your design, it will pay great dividends to translate system A's and system B's outputs into polarized mnemonic form in such a way that you can continue with your design without regard to whether any particular mnemonic has its origin in a positive logic or negative logic system. This is done, as shown in Figure 2-16, by drawing a boundary around your system and making your translation to the right of the boundary as shown. Make certain that you avoid redefining the mnemonic portion in your translation because this usually creates confusion or at best retranslation later.

System

An

how

Your system

Fig. 2-16.

boundary

mnemonics can be derived from

API

/

API (H)

BPI

y

bpi (L)

illustration of

polarized

traditional

logic variables.

A

positive logic

CPI

j

system

CPI (H)

Your system

(mixed DPI

System B negative logic

system)

EPI

\

EPII L)

FPI

/

FPU

system

We

logic

DPI [H)

\

L)

and CPI are all mnemonics having origins in the positive logic system.* Therefore, API and CPI are to be interpreted as API(H) and CPI(H), and BPI is to be interpreted as BPI(L). In other words, API and CPI are logic signals that are to be interpreted as being ASSERTED HIGH. On the other hand, BPI is to be interpreted as ASSERTED LOW. Now the mnemonics, DPI, EPI, and FPI have their origin in a negative logic system. Therefore, EPI and FPI are translated to EPI(L) and FPI(L), respectively. DPI is, on the other hand, translated to DPI(H). It should now be apparent that once this translation is completed, you then work only with the boundary mnemonics of your system, thereby reducing your "mental baggage" by never having to worry about whether or not any given variable stems from a negative logic system or a positive logic system. Further, it will be shown that a knowledge of the input assertion levels is necessary to make an optimal choice of gates to implement a design. see that API, BPI,

*Traditionally the bar over a variable

"BPI "BPI

NOT"

or

"NOT

BPI."

is

In this text,

"NOT,"

BPI is read as variables such as BPI are read as:

read as

that

is,

NOT-ASSERTED."

Hardware Aspects Related

to

ASSERTED and NOT-ASSERTED

Conditions

75

2-7

USING MECHANICAL SWITCHES FOR SIGNAL

SOURCES Most

digital

systems incorporate mechanical switches for generating signals as well

on a control panel are: RESET (SANITY), which initializes the system, RUN/START, which initiates the operation, SINGLE-STEP, which allows the slow single-step operation of an otherwise high-speed system as well as other special function switches. The use of a switch as a signal source requires special consideration regarding switch properties and schematic documentation. For example, you first should understand that one of the physical switch positions must be declared as the ASSERTED position. This position is typically the "IN" or "UP" position. Then once the physical position has been established the proper connections must be made to the switch to assure the proper signal ASSERTION level is derived. Another important property to remember is that most switches suffer from "contact-bounce" upon closure. This contact-bounce is the result of the springlike operation of the switch mechanism and the microscopic irregularity of the switch contacts. The results of contactbounce can be simulated by the repeated random operation of an ideal SPST switch and can take several milliseconds to die out. There are several methods of "debouncing" a switch, which are discussed in Chapter 5. However, at this time assume that the switches are ideal and dwell more on the schematic application of the switch. This application is demonstrated in Example 2-4.

as inputting data. Typical switches found

Example The first

2-4:

It is

required that a control panel have two control switches.

"RESET"

which is a SPST switch, and is to generate the signal SANITY(L). The second switch is the RUN/STOP switch, which is a SPDT switch and is to generate the START(H) signal. Figure 2-17 illustrates the schematic drawing for these two switches. Note the use of the "Pull-up" resistor, which is used to guarantee the high voltage level and avoids leaving any device input to "float." From Figure 2-17 we see that working out switch

is

the

switch,

the physical location of the contact-pole positions first

and then making

the

appropriate electrical connection to the switch makes the use of a switch for an input signal to a digital system a simple process.

R (pull-up)

The contact associated

RESET (ASSERTED)

with the

-

SANITY(L)

(a)

position of

the switch Digital

R (pull-up)

The contact associated with the

system

RUN START(H)

position of the

(b)

switch

SPDT The contact with the

associated

STOP

position

1

Digital

Design Fundamentals

The schematic documen-

tation of the switch requirements specified in

of the switch

76

Fig. 2-17.

Example

2-4.

-8

THE CONCEPT OF THE INVERTER Once you understand that ASSERTED conditions and voltage levels are interrelated, and further understand that the conjunctions AND and OR in a word statement relate directly to some hardware operator, you are well on your way to design. However, once under way you will find that the set of conjunctions AND and OR is not sufficient, for there will be times when the word NOT is necessary to describe a condition for a problem. NOT means NOT-ASSERTED. Further, you will find when you are selecting operators (by selecting gates) that the hardware set of AND/OR gates also comes up short, for there will be times when a voltage level inversion

is

necessary.

To

illustrate this

necessary function, consider the following

problem statement. Example

control panel. in

There are three people who

2-5:

Each

of the three

some prescribed pattern

men

man

a

critical

rocket launch

has a two-position switch he must operate

(note pattern, not sequence) in order that the rocket

can be launched (Figure 2-18). Because of special psychological studies made on these men, those in control found that each responded differently to the same stress. Based on this study, those in control prescribed the following conditions for rocket launch:

and Jim has the

the

his switch in the

ASSERTED

and Jim has

If

position, or

his switch in the

NOT-ASSERTED

Kay

has his switch in the

ASSERTED

if

Kay

position

and A.T. has

has his switch in the

ASSERTED

position

ASSERTED

his switch in

ASSERTED

and A. T. has

position

position

his switch in

position.

mm Af In »*"

1

o

Fig. 2-18.

Rocket launch

control panel.

The Concept of the INVERTER

77

Now, by

assigning

mnemonics

as described previously

have not selected hardware yet and therefore we elements at

Launch rocket

KSWCH

ASSERTED position Jim's switch in the ASSERTED position A.T.'s switch in the ASSERTED position Kay's switch in the

JM SWCH AT SWCH

we have

Put into a Boolean expression,

LNCH RKT =

(K

SWCHJM SWCH AT SWCH) + (K SWCHJM SWCH(?))

can see thus

NOT-ASSERTED

we

far that

haven't described the case for the situation

NOT-ASSERTED position or where the output of ASSERTED if one of the system inputs is in a

where A.T.'s switch is in the an AND function must be

In other words,

condition.

ASSERTED and A.T.'s

switch

is

if

because

same voltage is

output

we introduce

ENABLE

the

condition.

the

AND

is

to

function.

ASSERTED. logic INVERTER.

The function of the IN-

is

INVERT

simply to complement or

ASSERTED

be launched

operator must be at the

incoming signal. Keep in mind that with the

to

AND

inputs to a gate used for an

level before its

Therefore,

VERTER

all

is

ASSERTED

is

condition the signal of A.T.'s switch in order to is

the rocket

and Jim's switch NOT- ASSERTED, something must be done

under the conditions where Kay's switch

This

not assign the polarizing

this time), let:

LNCH RKT

We

will

(remember we

the logic voltage level of

changes only the voltage

it

For example:

If

its

level associated

the voltage level associated

NOT-ASSERTED position is ^0 volts, then passing this signal through an INVERTER simply changes the same logic condition (A.T.'s switch NOT-ASSERTED) from ~0 volts to 3.6 volts. It will with A.T.'s switch being in the

be assumed here that an before the output of the

AND operator, all of

its

AND gate used for the AND operator. Therefore, AND gate can yield an ASSERTED condition for is

its

inputs must be

ASSERTED at

a relatively high voltage.

Hence, we see an INVERTER could transform the NOT-ASSERTED low voltage at the output of A.T.'s switch (~0 volts) to a high voltage at the input of the gate, thus enabling the gate to ASSERT its output on the

AND

AND

condition:

K SWCH JM SWCH AT SWCH •

The

INVERTER

an

definition given here for

the traditional definition of the

differs considerably

INVERTER. However,

it

from

more accurately

an INVERTER is a it performs no logic interaction function between two variables; say that merely changing a voltage level constitutes a logic operation would

describes the physical function that

really performs. Since

it

single input device,

and

to

be misleading. Therefore, logic-operator like the

symbol

for the

we

define

AND

INVERTER

is

it

as

an

operator or

shown

in

Fig. 2-19.

OR

Digital

Design Fundamentals

operator.

function rather than a

The

Figure 2-19.

The

symbol for the

78

INVERTER

distinctive-shaped

INVERTER.

distinctive-shaped

To

"The

further discuss the statement

INVERTER

merely changes the

assertion voltage level," consider Figure 2-20, which illustrates this statement

using "polarized mnemonics."

Using the

Fig. 2-20.

INVERTER

to

change

AT SWCH(H!

the assertion voltage level of a given logic

AT SWCH(L)

mnemonic.

The point

ASSERTED

can become confusing when reading other texts because most of these make the assumption that the ASSERTED levels are always within the same voltage range. As will be shown later, this can be a relatively expensive assumption. Therefore, don't become confused by a schematic symbol as shown in Figure 2-2 1(a), and remember the schematic symbol in Figure 2-2 1(b) is equivalent. of having "mixed"

AT SWCH(L)

AT swch(h:

AT SWCH

AT SWCH

levels

Equivalent to

Fig. 2-21.

(a)

The

traditional positive logic inverter symbology. (b)

Using polarized

mnemonic symbology. It

certainly

real value

is

true that

when reading

AT SWCH(H) = AT SWCH(L),

but

it is

of

no

or interpreting drawings. So don't spend time worrying

about the overbar that traditionally reads NOT. One simply has to look at the polarizing element to determine the voltage level the signal line will be at when the logic operation defined level

is

is

is

from the polarizing element, then

different

the operation

by the mnemonic

NOT- ASSERTED. As

ASSERTED. it is

simple as that!

If

the voltage

immediately known that

The

reverse argument

is

made when one is designing a circuit, which is very handy. Now, if we are dealing with NOT-ASSERTED conditions

at the expres-

NOT-ASSERTED

logic require-

sion level,

is

it

possible to synthesize these

ments, such as the one in Example 2-5, in the following manner:

LNCH RKT = By adding

K SWCH JM SWCH AT SWCH + K SWCH JM SWCH AT SWCH

the polarizing elements

we

•

•

•

•

get:

LNCH RKT(H) =[K SWCH JM SWCH AT SWCH + K SWCH JM SWCH AT SWCH ](H) •

•

The implementation of this logic expression is shown in Figure 2-22. Here we see the inverter was added in such a way that when A.T.'s switch is

in the

range, which allows the to transfer to

The

AT SWCH(L) will be in the high voltage AND function (K SWCH JM SWCH AT SWCH)

NOT-ASSERTED its

ASSERTED

specific point

concept, which

is

position,

made

•

level, in this

•

case the high voltage level.

here leads the

way

to a general

implementation

covered in the next section. The Concept of the INVERTER

79

+5

K SWCH(H)

Asserted

[KSWCH

•

JMSWCH

•

ATSWCH]

(H)

Position

LNCHRKT(H) JM SWCH(H)

Asserted Position

+5

1

1

k

[KSWCH

Asserted Position

AT SWCH(H)

1

•

ATSWCH(L)

JMSWCH

•

ATSWCH]

(H)

NC = No Connection Fig. 2-22.

The unsimplified implementation

of the rocket launch problem.

GENERAL IMPLEMENTATION PROCEDURES Consider the mixed input assertion level notation illustrated in Figure 2-23. The validity of the output expression indicated in Figure 2-23 can be established quite easily from your knowledge of two things: (1)

The

functional

HIGH (2)

only

AND

when

all

operation of the

AND

gate, that

is»

the output,

is

inputs are high.

The given assertion level for the A variable is low. Keep in mind that in general you may or may not have control over the assertion levels of your inputs.

Fig. 2-23.

A

notational illustration of mixed

input assertion levels.

C can only be high when the B NOT-ASSERTED. Thus we derive

Therefore, from an empirical standpoint the output variable

is

ASSERTED

and the A variable

is

the expression

C(H) = (AB)(H) which

is

interpreted as:

ASSERTED Note

and B

is

C

(the output)

is

ASSERTED

High when A

is

NOT-

ASSERTED.

that the assertion levels of the individual inputs

were deleted from

interpretation leaving only the logic message of the expression

and

its

this

assertion

always done, for several reasons. One important reason is that it reduces the sheer bulk of the output expression. Another, and probably the most important, reason is that carrying these assertion levels to the output expression is a

level.

80

This

Digital

is

Design Fundamentals

This can be seen by realizing that each logic symbol

superfluous operation.

definition automatically establishes the input conditions under which the logic function

specified by the

symbol

function of an

AND

carried out. Therefore, to specify the output of the

is

AND

gate as

C(H)=[J(H)«(H)](H) is

an unnecessary operation

if

we have

the definition of the

symbol

in

mind.

We

simply say

C(H)=[J-2J](H) Attaching the polarizing element to the overall expression is done for diagnostic purposes as well as for information pertaining to the possible later use of this

some other symbol.

expression as an input to

Another key point related to the output notation specified in Figure 2-23 is logic expressions with complemented variables can be implemented in hardware simply by assigning the complemented variables with low polarizing elements to symbol inputs without low-level indicators or those complemented variables with high polarizing elements to symbol inputs with low-level indicators. See Figure 2-22. Here we see that the operation just prescribed results in output expressions with complemented variables. This very important concept is re-demonstrated by the following example. Suppose you were given the following expression and asked to implement this expression in hardware:

F= The method

of attack

(1) First its

(2)

is

AB+AC

as follows:

recognize that the circuit represented by this expression

inputs {A, B,

this circuit

Therefore, you must be sensitive to the given

(3)

ASSERTED

Based on the

ASSERTION indicated

levels,

this is that

INVERTERS

levels,

use power,

and take up room.

way

that

levels for the inputs

and

INVERTER functions are minimized.

exhibit no logic operator,

The reason they merely change voltage

Therefore, their use should be minimized.

process of implementing the given function

F=

AB+AC

based on the following input and output

A, B, and

ASSERTED

some other system.

functions.

we do

choice in such a

be

to drive

imposed on you by the input and output make a selection of gates that will perform the

this

F must

is

restrictions

AND/OR

illustrate the

(F)

level for the output.

Make

To

to receive

and C) from some other system.

Recognize that the output of

the required

is

restrictions,

ASSERTED LOW C are all ASSERTED HIGH General Implementation Procedures

81

consider the following steps to an implementation: (1) Select

a gate that exhibits an

operator.

has the

(2) Select

The only one we have studied

(3)

is

thus far

is

the

AND

for the

OR

gate which

OR function symbol shown:

a gate for the

inputs to the selected far

OR function ASSERTED LOW

the

AND OR

functions that complements (matches) the

operator.

The only one we have studied

thus

OR gate which has the AND function symbol shown:

two operators together and match the input variables ASSERTED LEVELS to the AND operator using an INVERTER only when needed. This is done in Figure 2-24. Bring

Fig. 2-24.

these

An

illustration of the circuit

generates F(L) = (AB

Had you

which receives /1(H), B(H), and C(H) and

+AC)(L).

not used the mixed logic concepts you have studied thus

far,

your

would more than likely have looked like the one in Figure 2-25. In this figure you see that an extra INVERTER is required tsk, tsk. Thus it is hoped that you recognize some merit in the mixed logic concepts, since it has been positively reinforced by an example that illustrates a circuit savings. Granted, these concepts are somewhat subtle, but their use does make circuit design a little more exciting as well as making circuit saving more obvious. circuit

—

82

Digital

Design Fundamentals

Fig. 2-25.

2-10

A

traditional implementation of the function F.

AXIOMATIC SYSTEMS AND BOOLEAN ALGEBRA Thus

far

we have

discussed the

AND, OR, and INVERTER

functions

and

stated

can be proven that these functions make up a sufficient set to define a two-valued Boolean algebra. However, we have attacked the introduction to Boolean algebra in a slightly reversed manner purposely, to develop some physical insight into what this axiomatic system might be about. It is time to introduce some formal treatment of this two-valued Boolean algebra. When contemplating the origin of new knowledge, you soon come to the realization that this new knowledge must originate from some sound basis if it is to be meaningful. To be meaningful it need not include total or even partial usefulness, for there is much knowledge that may not be of immediate use. However, if the foundation of this knowledge is couched in sound reasoning and it has certain basic properties, its usefulness may only be hidden from view by the shortsightedness of its interpreters, and may well be brought into view by related studies at any that

it

time.

An

illustration of

how

later studies bring to light the usefulness of

new

knowledge unearthed by the pure research of yesteryear is shown almost daily. Hardly a day goes by in which applied research does not uncover ways and means whereby pure research can be brought into application. For example, the theoretical work of Boole done in the mid-1800's was not applied to hardware until Shannon extended this knowledge in the late 1930's. Had Boole not done his work properly and had those who followed him not nurtured his work, it might well be that it would have gone unnoticed; and its applications as we know them today, and as those in the future will know them, would be unknown or at best channeled into some other area. Thus we see that the responsibility rests heavily on those doing pure research to make certain that the knowledge unearthed is properly founded and documented. To support this, great thinkers have given us principles on which to base the formulation of new thoughts related to axiomatic systems.

Axiomatic Systems and Boolean Algebra

83

Axiomatic systems are founded on some fundamental statements referred to as axioms or postulates. As you delve deeper into the origin of axioms and postulates, you find these to be predicated on a set of undefined objects that are accepted on faith. Faith is defined in many ways, one of which is taken from the Bible, Hebrews 11:1. "Faith

is

the substance of things

hoped

for, the

Though

generally applicable, this definition of faith

For one

to accept

something on

evidence of things not seen." is

not quite the one required.

he has to accept the fact that not every object Thus it is is definable, yet statements must be made regarding these objects. assumed that those of us involved have a conceptualization of what those objects are without further definitions; this we will call faith. An example of faith as it is defined here and how it is arrived at can be cited as follows: When you were a baby it is most likely that your mother pointed at a table and repeated the word "table" to you, and on various other occasions she pointed out other objects and said again, "table." Thus you accepted a conceptualization of an object you associated with the word "table", and now you have the faith that those same-looking objects are still tables, which is another indication that nobody can really define "things" to babies who have no set of objects (other definitions) on which to faith

base their understanding. They merely accept things on

faith.

on to exercise faith when we define objects in terms of more primitive objects and in turn define these more primitive objects in terms of still more primitive objects; continuing until we find that, practically, we must have some place from whence we can start. From this place there exist no further primitive objects on which we can base definitions. Therefore, from this place the logician selects objects on faith and builds from there. For example, in geometry one starts from the basis of statements regarding the undefined objects, the point and the line, which are accepted on faith and, from these, elegant axiomatic

Thus we are

called

systems are developed.

Axioms and postulates are statements about undefined objects that are believed by faith. They are the statements that make up the framework from which new systems can be developed. They are the basis from which theorems and the proofs of these theorems are derived. For example, proofs are justified on the basis of a more primitive proof. Thus we use the statement: From this we justify this. Again, we find a process that is based on some point for which there exists no further primitive proofs. Hence we need a starting point and that starting point is a set of axioms or postulates.

Axioms are formulated by combining should have some basic properties in order

intelligence for

them

to

and empirical evidence and be useful. These properties

are:

(1) (2)

(3) (4)

They are statements about a set of undefined objects. They must be consistent, that is, they must not be self-contradictory. They should be simple but useful, that is, not lengthy or complex. They should be independent, that is, these statements should not be interdependent.

84

Digital

Design Fundamentals

In regards to the

way

strict

adherence to

(3)

and

(4),

these should be modified in such a

that they facilitate ease of use.

The study

of axiomatic systems related to logic motivated the creation of the

known

set of postulates

you are

as the Huntington Postulates.* (At this point

it is

assumed

fundamental level that you are willing to accept a conceptualization of an object rather than any further definition.) These postulates as set forth can be used to evaluate proposed systems and those systems that meet the criteria set forth by these postulates become known as Huntington Systems. Further, once a proposed system meets the criteria set forth by the Huntington that

Postulates,

at a sufficiently

automatically all theorems

and

properties related to other Huntington

Systems become immediately applicable to the new system. Thus, if we define some set of black and white "chicken feed" and define some operators over this set of chicken feed which meet the criteria of the Huntington Postulates, we have

immediately established that those things true about other Huntington Systems are also true about the chicken feed system. Thus we propose a Boolean algebra and test it with the Huntington Postulates to determine its structure. We do this so that we can utilize the theorems and properties of other Huntington Systems for a

new system

that

is

defined over a set

and hardware operators. Boolean algebra, like other axiomatic systems, is based on several operators defined over a set of undefined elements. A SET is any collection of elements having some common property and these elements need not be defined. The set of elements we will be dealing with is {0,1}. The 0 and 1, as far as we are concerned, are some special symbols and have no numerical connotation whatsoever. They are simply some objects we are going to make some of voltage levels

;

statements about.

An OPERA TOR

(-,

+)

is

defined as a rule defining the results of

Because these operators operate on two elements, they are commonly referred to as "binary operators." However, this has nothing to do with the fact that we are presently dealing with "binary systems."

an operation on two elements of the

set.

Huntington's Postulates

(1)

A set of elements of elements in

S

S

is

closed with respect to an operator

if

for every pair

the operator specifies a unique result (element) which

is

also in the set S.

In other words: For the operator

S

if

A and B

There (2b) There

exists exists

if

the results of

and for the operator the A and B are elements in S.

are in 5;

be found in S

(2a)

+

an element 0 an element 1

•

in

in

S such S such

A + B must be found in results of A B must also

that for every that for every

A A

in 5,

A+0 = A.

in S,

A

•

1

=A

*E.V. Huntington (1904) formulated this set of postulates that have the basic properties described desirable, consistent, simple,

and independent.

Axiomatic Systems and Boolean Algebra

85

A + B= B+A commutative laws A B=BA A+(B C) = (A + B) (A + C) distributive laws A-(B+C) = {A-B) + {A-C) For every element A in S, there exists an element A

(3a)

(3b) (4a)

(4b) (5)

such that

A A =0 and -

y4+Z=l. There

(6)

A

two elements

exist at least

B

and

in

S such

that

^

is

not

equivalent to B. Therefore, if

we

if

define

we propose the following two-valued Boolean algebra system, that the set S = {0, 1} and prescribe the rules for + and INVERTER

is,

as

follows:

Rules for

Rules for

0 0 1

1

A

B

AB

+

0

1

0 0

0

0

0

1

1

1

1

0

0 0

or 1

1

0

0 0 0

1

1

1

1

INVERT

and

test

(1)

Closure

(2)

From

11 =

(b)

— no

A

B

A+B

0 0

0

0

1

1

1

0

1

1

1

1

A

0

1

1

0

we

find:

results other

than the 0 and

1

are defined.

the tables:

0+0=0

(a)

(3)

obvious

is

J

Function

A

our system with the postulates,

"+

1

0+1 = 1+0=1 1.0 = 01=0

The commutative laws

are obvious

by

the

symmetry of the operator

tables.

(4a)

The

distributive laws

can be proven by a

B

C

B+C

A-(B+C)

AB

AC

0

o~

0

0

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

0

0 0 0 0 0

0 0 0 0 0

0 0 0 0

1

0

1

1

1

0 0 0 0 0 0

1

1

1

1

0

1

1

1

0

1

1

1

1

1

1

1

1

L

86

TRUTH-TABLE

Digital

Design Fundamentals

(A-B)

+ (A-C) 0

1

J

(4b) (5)

Can be shown by a similar table. From the INVERTER function table: 1-1

= 1.0 =

0-1=0 0 + 0 = 0+1 =

0-0 =

0,

1+1=1+0=1, (6)

It is

obvious that the

having at

From

this

set

S = {0,

1} fulfills the

two elements where 0^=

least

minimum

2-1

(4a)

A = 0 I A = A A A = A =0 A

(5a)

X=

(lb)

(2a)

(lb) 0

1

+A =

1

+A = A A +A = A A+A = \

(lb) (lb)

-

Duality

listed:

Identities

(la) O

(3a)

requirements of

1.

study the following identities in Table 2-1 can be

TABLE

1

(Note the duality*)

A is

defined for Huntington Systems, just as

it is

for

other axiomatic systems, and the dual of a given expression

can be derived by simply replacing the with

From

's

and

0's

with

l's

and

l's

•

's

with

+ 's and + 's

with 0's in that expression.

the identities in Table 2-1 the theorems in Table 2-2 can be developed

and

proven.

TABLE (1) (2)

(3) (4) (5) (6)

Each of the postulates

Theorems

A + AB = A (absorption) A + AB = A + B AB + AB = A (logic adjacency) AC + ABC = AC+ BC AB + AC + BC = AB + BC

ABC

these theorems

and

2-2

identities,

and

A+B + C + --

)

and many others can be proven mathematically using or by a TRUTH-TABLE, as will be shown. However,

have been previously established for other Huntington Systems, we need not put forth the effort; but in the interest of developing some valuable experience in manipulating Boolean expressions, some of these theorems will be proven as follows. It should be noted that each theorem does have a dual that is not listed but is left for an exercise. since these theorems

relations

Axiomatic Systems and Boolean Algebra

87

Theorem

1

(Absorption):

A + AB = A(\ + B)

'.A

Theorem

+AB

-4(1) =A = A

A

B

AB

A+AB

0

0

0

0

0

1

0

1

0

0 0

1

1

1

1

1

2:

A+ AB

= A\+ AB = A(B + B) + AB = AB+AB+AB = AB + AB + AB+AB = A(B + B) + B(A+A) = A +B

AB = A + B AB A+AB B A

A+B

1

0

0

0

0

1

1

1

1

1

1

0

0

0

1

1

1

1

0

0

1

1

t

t

.A

A 0

+

0

Theorem 3 (Logic -adjacency):

AB + AB = A(B + B) = A(\) = A .AB + AB = A

Now

A

B

AB

AB

AB + AB

A

0

0

0

0

0

1

0

0 0

0

0 0

1

0

0

1

1

1

1

1

1

0

1

1

t

t

Boolean algebra to be a Huntington System, the properties related to other Huntington Systems become applicable to the Boolean system. It is interesting to note that the 0 and 1 elements in the Boolean set can be redefined by using the = and those properties which are true for

88

1

that

we have shown

and 0 then become Digital

the proposed

true for

Design Fundamentals

ASSERTED

and

NOT-ASSERTED. Thus we

can show the ASSERTED and NOT-ASSERTED concepts are consistent. These results can be further extended to voltage levels and voltage operators, which we call gates. In other words, we can define two voltage levels that are elements of a set and design hardware which have one-to-one correspondence with the operators defined in the Boolean system. We then have a hardware system about which we can say that those things true for the other Huntington Systems are true for our hardware system. Now we see that we have a postulative basis for the digital hardware system based around the AND/OR gates and INVERTERS. It is important to note that we have developed our hardware system around AND/OR operators and INVERTER functions, which will require some further adaptation for the other hardware gates (NAND and NOR) in order for these to be used consistently. This will be illustrated shortly. With reference to the ASSERTED and polarized mnemonic format, it can be

shown by inspection (la) ir(H)

that the following are identities:

= F(L)

(lb)

nL) = F(H)

(2a)

F(H) = F(H)

(most important)

(2b)F(L) = F(L)

From

these

it

can be proven

that:

F(H) = F(L)

= F(H)

F(L) Proof

F(H) from (la)

^Hj =

F(L)

=

F(L)

from (lb) :.

Therefore

we introduce

=

F(L)

F(H)=F(L)

the following table of relations (Table 2-3).

TABLE (la) (2a)

(3a)

2-3

Useful relations

= F(L) F(H) = F(L) F(H) = F(H)

F(H)

= F(H) F(L) = F(H) F(L) = F(L)

(lb) F(L)

(2b) (3b)

and (lb) that a given function F ASSERTED at either level has an exact equivalent which is arrived at by complementing both the function and the polarizing element.

We

see

from

(la)

Axiomatic Systems and Boolean Algebra

89

and (2b) we see that the complement of a function can be derived by simply complementing the polarizing element. These are the ones most often used

From

(2a)

in design.

and (3b) we see an alternate way of arriving at the complement of a function using DeMorgan's theorem on the function F and leaving the polarizing element as it was. This identity is used generally when some functional transformation is desired and plays no real part in the design process.

From

(3a)

TABLE

FiU) =

/'(H)

A

Useful relations

HL)

F(L)

/•(H)

F(H)

2-4

C^^>

hardware

F(\\)

RL)

FiL)

= F(H)

F(L)

F(H)

T(L)

^Q

illustration of these useful relations

= F(H)

f(L) = F(L )

is

shown

Table 2-4. Pay introduced in Table in

symbol for the INVERTER 2-4. This new symbol is supported by the same rules set forth regarding the low-level ASSERTION indicator for the AND and OR basic distinctive-shaped symbols. In short, the symbols in Table 2-4 support the rule set down earlier stating that a function stemming from an output without a low-level indicator yields an output mnemonic that is ASSERTED HIGH. Conversely, a function stemming from an output with a low-level indicator yields an output mnemonic which is ASSERTED LOW. Likewise, when the input mnemonic polarizing element does not match the assignment of the state indicator at the input, then that variable appears at the output as a complemented variable. We find later that this is a very useful concept for schematically generating complemented functions. The theorems listed in Table 2-2 serve an important function in that they are used to reduce the number of variables in a given Boolean expression. In particular, Theorem 3, the logic adjacency theorem, is a key theorem used in the development of a graphical simplification method called "MAPPING," which is treated in Chapter 3. To illustrate how you can use these theorems for simplification, consider the following two examples: special attention to the alternate

Given:

F=

X+ YXZ |Thm

F=

X+ZX tThm

.F= 90

Digital

it

2t

X+ Z

Design Fundamentals

+ ZX

(to

be simplified)

Given:

S = Y + Z + YX +

=

is

be simplified)

(to

Y+Z+X + X

= (7+Z)+ .'.5=1 More

X

f

said concerning the use of theorems for reduction in Chapter

DeMorgan's theorem are

also very important; in particular, they yield

important insight into the use of functions,

which

theorems are

is

3.

AND-INVERTER

and

OR-INVERTER

some logic

presented in the next section. In general, the results of these

summed up

in Figures 2-26(a)

and

2-26(b).

/4(h:

D(A

B\

•

(A

B) (H)

•

[?°

FIH)

B) (L) =

A B

(A

vl-Ls

[y°

f(h)

A +B

F(L) = F(H)

A(H

B

=

+

B) (L) =

A

-r

B

=

A

•

B

F(L) = F(H)

(a)

A

•

is

B(L)\

equal


L >0

>

—

LNCH rkkh;

CJj

^

STANDARD PRODUCT-OF-SUMS

expres-

sion for the rocket launch problem.

The shorthand symbology

or

for canonical

LNCH RKT = LNCH RKT =

II

POS

expressions

M ,M ,M ,M 0

1

2

is

as follows:

5

IlO, 1,2,5

Consider the table shown in Figure 2-45 to help you establish the relationship between the and MINTERM numbers.

MAXTERM

From

Figure 2-45

we

see that:

mj

= Mj

Mj = mj 104

Digital

Design Fundamentals

which indicates that

MAXTERM j can be

derived by complementing

MINTERM

J-

Fig. 2-45.

The

MAXTERM

MINTERM

and

~ABC

mQ

->

^

jg C ^ ABC ^ m 2 ABC -> m 3 ABC -* m 4 ABC ->m 5

designations.

>4fiC

An lists

and

interesting point

MINTERM

lists.

m

-*

MQ

A+ B

_

^

+ £

M + B + C -> M 2 + B + C -> M 4 + B + C - M5 ^ + 5 + C->M 6K

A A A A

6

ABC-*

A +B + C + B + C

A +B +

7

->

?

C^M

7

MAXTERM The subscript numbers of the terms in the MAXTERM

can be made in the relationship between

correspond to the same subscript numbers for MINTERMS that are not included in the MINTERM list. From this we can say the following. list

Given: II (set of

We know

MAXTERM numbers)

that the function derived

from

this list will yield precisely the

same

results as the following:

2

(set

MINTERM

of

numbers

that are not included

MAXTERM

in the

list

For example, Given:

^,5,0 we know immediately

=

11(0,1,4,6)

that

F(^,5,C) = 2(2,3,5,7) It

is

shown

implementing

in

Chapter 4 that it

a worthwhile bit of information

should be pointed out that at times a

result in a simpler form, it

is

when

circuits with fixed building blocks.

In summary, Also,

this

and

POS

implementation

will

both cases should always be examined. and POS Boolean implementations fall into

therefore,

should be obvious that

SOP

one of two basic two-level models, as shown in Figure 2-46. A very important point and one well worth remembering is that canonical forms reduced by standard techniques result in two-level standard forms, which are sometimes referred to as "disjunctive (SOP)" and "conjunctive (POS)" forms. This is not to say that these simplified forms cannot be factored into other forms such as

or

F = AB+AC + D = A(B+ C) + D F(H) =[A(B + C) + D](H)

This expression can be implemented in a three-level implementation as shown in Figure 2-47. Maxterm Representation

105

Generally speaking, the extra delay in some of the signal paths

and

desirable

this

trying to limit the

type of implementation

number

is

is

not always

not often encountered except when

of gate inputs. However, note that reading the expres-

^(H) from the circuit distinctive-shaped symbol set. sion for

in Figure 2-47

is

made

quite obvious

by using

the

r

Inputs


0

1

7

3

1

0 0

1

u 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 0 1

8

F

IP

5 i

2

ps

1

0 u 0 0 1 1

0

1

Wo A B c

D

F

0

1

I

0 1

0 0 0 0 0 0

I

-

h 0 0 0 0

2 3

4 5

0 0

1 I

1

I

0 0

1 1

1

1

o

0

1

1

0

0

1

1

0

I

6 7

0 0

1

o

1

1

0 0

0

1

1

0

!

1

1

6

2

D

D

1

^

4

D

0

\

2

0

\ '

6

\

pe

4


4

6 1

1

1

1

2

D

1

14

6

00

10

11 0

1

0

1

\

9

15

7

\AB C

13

5

1

8

0

1

2

10

12

1

3

11

01

4

i

01

'

'

'

but leave IP numbers alone

D

In Figure 4-22 the

MUX implementation of F(L) requires one IC package

and a single INVERTER. Generally speaking, that will be all that is ever needed (worst case) for any four-variable problem. Thus the mixed logic concepts can be utilized with multiplexers and still minimize INVERTER requirements. There are other variations of this method which will be left for exercises.

4-5.3

At

OTHER IDEAS RELATED TO MUX USAGE present, 16-to-l

MUX's

are the largest readily available devices. However, the

manufacturers have provided

ENABLE/STROBE inputs

to allow for expansion to

meet multiplexer input needs. Using these inputs, a "MUX STACK" or a "MUX TREE," as they are sometimes called, can be designed. Two methods are illustrated in Figure 4-23.

x X X X Q

SELECT INPUTS^

r x X X X CJ Q

D Note:

OUTPUT

F=

(A, B, C, D, E)

Select inputs are

to be connected

in

parallel.

a(h:

(MSB

ENABLE/STROBE inputs can be used to expand two 16-to-l MUX's to a 32-to-l MUX. (b) The MUX STACK or MUX TREE for expanding 16-to-l MUX's to a 32-to-l MUX. Fig. 4-23.

(a)

An

illustration of

how

the

Multiplexers

223

X X X X Q D

C

B

A

r 0 1

74150 2


v

8

1

1

(

)

1

Kitty-corner;

/~\

01 Offset

1

/~\ 13

5

In

9

J U

Kitty-corner

1

3

7

15

2

6

14

1

11 10

10

(a)

Fig. 4-42.

Example maps

illustrating

EXOR GATES

and

applications.

EXOR and AND-OR-INVERT

Gates

245

AB CD

AB 00

01 0

10

11 12

4

CD

00

8

00

01

10

11

0

4

1

5

12

8

00 1

\

N

01

01 3

15

7

3

11

7

15

11

14

10

11

11

y

6

10

10

'

2

3

(c)

(b)

Fig. 4-42.

(Cont.)

Here you should recognize a kitty-comer and/or offset grouping in the K-map. Once you recognize these, you know that there is either an EXOR or NEXOR function involved. You then hunt it out by factoring your expression as shown for the example maps in Figure 4-42.

or

ABC D + A BCD + A BCD + ABCD

F,

=

F,

= CD{A®B) + CD(AOB)

F = C[(D)(A@B) + (D)(A(BB)] ]

.\F,(H)

= C[(D)®(A®B)](H)

which when implemented with EXOR gates turns out much simpler than a conventional logic. The EXOR implementation for F is shown in Figure 4-43. x

F = ABC + ABC + ACD + ACD 1

or

F2 (H)= (A(B@C) + A(CD))(H)

and F, or

Thus using

=

ABCD + ABCD + ABCD + ABCD

F3 (H)= (£0Z))(,4 0C)(H) an EXOR gate, at times, can reduce

review the concept related to (1) If

standard

K-map

EXOR

(2)

246

let

us

recognition.

groupings occur in a ki tty-corn er or offset pattern, you

should recognize that either

K-map

package count. Again,

EXOR

or

EXOR

functions exist in the

simplified expression. Therefore:

Rather than learning a whole new mapping concept just for should examine the simplified expression and factor out the EXOR function and implement directly.

MSI and LSI Circuits and Their Applications

EXOR, you

EXOR

and

X QQ

Fig. 4-43.

An

example of

EXOR

implementation

for Fi in Figure 4-4.

x

T

V 0 x

HINTS FOR READING EXOR AND NEXOR EXPRESSIONS DIRECTLY FROM THE MAP In the last section you were given information related to recognizing offset and kitty-corner groupings as indicators of

EXOR

and

NEXOR

sub-expressions.

You

were given a foolproof but laborious method for finding these expressions, which

you should not forget. In this section you are given some simple mapping rules that will allow you to extract these expressions automatically, but you are likely to forget them. Thus, these rules are treated as an interesting approach and introduced in example form.

Example

how

the

4-8:

EXOR

Given the two maps in Figure 4-44, it and NEXOR rules apply (see Figure

will

be demonstrated

4-45).

Mapping

steps

referring to Figure 4-45:

Fig. 4-44.

Hints for Reading

Offset adjacencies examples.

EXOR and NEXOR

Expressions Directly from the

Map

247

(1) (2)

Make Draw by

fashion as illustrated.

a line connecting the two groups, keeping track of the boundaries cut

this line, as

shown.

A

and B boundary

Cuts

K-map

loops that group entries in standard

(AB)

->

(A

O B)

(CD)

.AB

CD\

00

01

-C

©D

/10

11

0

4

12

1

5

-•13 1

8

I

00

01

9

l)

0 3

7

15

2

6

Ll4

11

11

10

Cuts C.and

4

y

D

boundary

Fig. 4-45.

(3)

The

Offset adjacency read examples.

variables associated with the boundaries cut

variables connected with either an

by these

lines are the

EXOR or a NEXOR connective,

but you

must determine which it will be. This is done by picking one of the groups, either one, and determining if these variables go with an EXOR or NEXOR. For example, if A and B boundaries are cut, do you have AB or AB in one of the groupings? If so, it is an EXOR connective. If it is an AB or AB, then it is a NEXOR {A © E) connective. Thus we see: F\

=

F2 = (4)

Now

fill

in the (?) with the

map

(?)(

A®B)

(?)(C©Z))

variable associated with the area in the

map

which both groups are common. This is easily done by looking at the map. Looking at the F map observe that both groups are common to C, or both are within the C boundaries. For F2 both groups are within the A in

]

,

boundaries.

..F = x

These same

C(A®B) = C(AQB)

rules apply to the kitty-corner

grouping

Figures 4-46 and 4-47.

248

and

MSI and LSI Circuits and Their Applications

also.

F2 = A{C®D) For example, see maps

in

Example

4-9:

v

Given:

AB

Cu\

00

01 0

10

11 4

12

8

5

13

9

15

11

14

10

00

B and C

Cuts

F3

= (?)(B

A

3

11

common

boundaries

.\

F3

=A(B@C)

or

F3

=A(BQC)

10

Example of a

Fig. 4-46.

Example

S

©C)

Both groups are to the

01

NEXOR

and groups go with

a

\

boundaries

kitty-corner adjacency.

4-10:

\AB

Given:

CD

00

01

11

A (B®D)

C(B®D)

F4 Fig. 4-47.

= (A

Example of a

+

C)

(BOD)

kitty-corner adjacency.

Summary. (1) (2)

(3)

We

first

group the

map

in

standard

K-map

fashion.

Scan the map for offset and kitty-corner groupings. Connect these groups appropriately with a line, keeping track of the boundaries cut by this line and knowing that these cut boundaries give information related to what variables are connected with the EXOR or

NEXOR

connective.

(4)

Examine one

(5)

boundary-cut variables goes with an EXOR or a NEXOR. Determine the variable ANDed with the EXOR or NEXOR by finding what variable is common to the area in which the groups are found.

of the groups to determine

Hints for Reading

EXOR and NEXOR

if

the term associated with the

Expressions Directly from the

Map

249

As has been mentioned

and steps are designed to be forgotten, rules add an interesting dimension to his

before, rules

but for the interested student these

map-reading expertise and

4-9

AND-OR-INVERT GATE The semiconductor

at least

make

interesting conversation.

(A-O-l)

industry has provided the designer with an array of different

devices that are relatively simple in construction but widely applicable.

EXOR

and

AND-OR-INVERT

gate

example, the

NEXOR gates shown

in Figure 4-48

available in integrated circuit form,

devices

do have some

are not complex but generally useful.

and

is

it

another of

is

The

type of circuit

this

used quite widely.

These A-O-I

you are

interesting aspects related to their use. If

For

interested

A-O-I gates, you should consult the manufacturer's data books to determine exactly what A-O-I configurations exist, along with the A-O-I expanders

in the use of

that

add a degree of

flexibility to these devices.

AND LEVEL

r

A(H)

OR

INPUTS

Fig. 4-48.

The

D D

.

indicate at least one im-

Fig. 4-49.

F(H)=

.

and Their Applications

SOP

expression) (L)

/\(h:

B(L)

.

gate.

mediate application for the type of device. This expressions which are to be ASSERTED LOW:

=

B

a/(h;

Figure 4-48 and the A-O-I

F(L)

F(L) = (A +

D)} (H)

A-O-I device used

an

function.

to

ASSERTED

On

the other hand, there are other interesting applications for these devices.

that in Figure 4-49

demonstrates that

A-O-I

an A-O-I gate it is

is

drawn

in a

POS

Note

symbolic notation. This figure

ASSERTED HIGH with for an ASSERTED HIGH

possible to implement a function

However, the actual A-O-I device used application need not be exactly the same as the device that would be used for an ASSERTED LOW application, though it could be. An example will be given illustrating the use of an A-O-I implementation. gates.

Example

4-11:

Given the map

an A-O-I

device.

See Figure 4-51 for the implementation.

Fig. 4-50.

An

example

illustrating the

A-O-I

in Figure 4-50,

map

AB

use of the

00

gate.

01

\

F=

b(h:

A-O-I implementation of F(H) specified

33

C(L)

A-O-I

+ AB)(L)

:.

A(L)

B(H)

B(L)

C(H)

4-10

is

+

BC

|

3>

A-O-I

F(H)

AjH)

what

AB

F(H) = (A + B)(B + C)(H)

F(L)

we cover

=

in Figure 4-50.

BID

In the next section

4

F

(BC + AB)

F(L) = (BC

10

11

Cy 3y

0

0

Fig. 4-51.

implement F(L) and F(H) with

yet another

3> method

of implementing logic using

called "wired logic."

WIRED LOGIC The phrase "wired

logic"

is

frequently used in contemporary digital design.

It is

a

phrase describing the condition where two or more outputs of special "busable" gates or devices are tied together on a common line. This line is commonly called a

"bus line" or more simply a "bus." Those gates that drive this bus line are referred to as "bus drivers," naturally; and those gates that receive levels from this bus line are referred to as bus receivers. Wired Logic

251

Two

widely used devices for implementing wired logic are:

(1)

"open collector" output devices;

(2)

"TRI-STATE"

output devices.*

Before launching into the subtleties of using the open collector and

examine how one might conceptually use these device

is

shown

devices.

A

tri-state devices,

typical

open

collector

in Figure 4-52.

Indicates

O

open collector

+v

Open

collector

(sometimes referred to as an uncommitted collector)

Fig. 4-52.

To

An

example 2-input open-collector output

NAND gate.

open

illustrate the application of the

collector devices, consider Figure

4-53.

An

Bus "pull-up"

Fig. 4-53.

resistor

arrangement for "wired

illustration of

a bus

logic."

Bus drivers

A(H)

F3

(L)

Inputs to bus receivers

Bus wire

C(H 0(H)

F 2 (L)

From open

this figure

we

see that a bus "pull-up" resistor

collector devices have

bus. Therefore, the resistor drivers "pull the bus low."

no current drive capability

R

is

From

F

3

this

because of *TRI-STATE

252

we

is

for raising the voltage of the

see that the output signal

+ F2(L) ASSERTED OR F2

F3

:

F,(L)

ASSERTED LOW if F, is the OR relationship that wired is

necessary because

used to "pull the bus up" and the outputs of the

F3(L) = In short,

is

is

ASSERTED.

logic networks like the

a registered trademark of the National Semiconductor Corporation.

MSI and LSI Circuits and Their Applications

one

It is

in Figure

4-53

are called

"wired-OR" (OR-TIE) systems.

However, closer examination

reveals that the following symbol* describes the expression

shown

in Figure 4-54, indicating the

OR

function of an

network in Figure 4-53 is most commonly referred symbolized as shown in Figure 4-55.

Fig. 4-55.

The schematic symbol wired-OR network.

Fig. 4-54.

F^(L)

for a

_

.,

F3 (L) = Fj(L) +

AND gate.

to as a

.

CX

2 (L),

Therefore, the

wired-AND and

F3

(

as

L)

= (F i

+ F2

* (

is

L)

The wired-AND

symbology.

The wired

F 2 (L)

FAL)

AND

"D ID

How you refer to these networks is your choice, be it wired-OR or wiredAND, but those familiar with mixed logic symbology will logically refer to it as an OR function ASSERTED LOW or wired-OR. See Figure 4-56 for an alternate OR symbology. +V Fig. 4-56.

Alternate symbols for a

wired-AND

circuit.

Wired

many

logic

is

of particular interest in large bus-oriented digital systems

when

separate systems are to input and receive data and information from a single

source system.

computer can have many peripheral I/O each of which must send and receive data to and from the

For example, a

devices dedicated to

it,

digital

Wired Logic

253

host computer.

plain to see that

It is

it is

impractical for each

I

/O

device to have

and data lines, particularly if the number of these devices becomes large. Therefore, most computers communicate with the I/O units on a set or several sets of lines called bus structures or bus systems, and each I/O device hangs its inputs and outputs on these bus systems in parallel with the other I/O devices, similar to clothes hanging on a line. This illustrates that only one device at its

own

set of control

a time can utilize the bus system in a multiplexed type of operation. It is usually the host computer software that directs the traffic on the bus system in order to

prevent overlapping interaction.

4-11

PRACTICAL ASPECTS OF WIRED LOGIC AND BUS-ORIENTED STRUCTURES To

preface this discussion,

7out (l) = the

max max

the bus

7out (0)

= the max

us define

some

terms. Let:

leakage current required from the bus system by the output

of a driver

7in (l)= the

let

when

the bus

is

pulled high.

current required from the bus by an input to a receiver is

when

pulled high.

current a driver output can sink

when

this

output

is

pulling

when

the bus

the bus low.

7in (0)

=

the is

V0 (\)= Vo (0) = The

max

current delivered to the bus by a receiver input

pulled low.

the the

minimum acceptable high voltage level for the bus. maximum value for the low voltage level of the bus.

and voltages defined above are parameters that set constraints on the size of the pull-up resistor R shown in Figure 4-53. Should a very large R arbitrarily be chosen, the combination of the leakage current of the drivers and the inputs of the receiver would cause a voltage drop across R resulting in the inability to raise the bus wire to an acceptable level. Further, if the choice of resistor is currents

arbitrarily small, the

the

number

bus drivers

will

be unable to pull the bus wire low. Therefore,

of drivers wired together,

on the

combined with

the

number

of receivers, sets

be used for the pull-up. Consider Figure 4-57 and the associated development to learn about how to size the pull-up resistor. constraints

We

size of the resistor to

see:

^bus=

Kff -[«Ul) + m/, n (l)]fi

Thus:

nIOM (l) +

254

MSI and LSI Circuits and Their Applications

mI V0 (\)

V

X

1

^

'

(D

Bus

*

/

..(1)

out

^-0

/7

A JO)

D

-«

^(0)

/^0

/

out

/JO)

(0)'

'

1

in

(0)

/^o A7

(b)

An

Fig. 4-57(a).

illustration of the current flow for

a wired-logic circuit (b).

when

the bus wire

is

HIGH,

Figure used to calculate the rninimum value of

R.

Similarly,

when

the bus

is

pulled low by one of the drivers, Figure 4-57(b) shows

that the sink current for driver 3

ou t

is:

(o)>-K< o M-^-jj

Thus:

R > / out (0)

+ mlJO)

Practical Aspects of Wired Logic

and Bus-Oriented Structures

255

TTL

For the

family:

/out (l)^250/ia

/in (l)^40 M a /out (0)^15ma

/JO)

From

^

K0 (l) >

3.0 volt

K0 (0)


Is?

of standard

I

OUTPUT,

INPUT,

INPUT DRIVING 1

SOURCE 72

INPUT,

INPUT 2 DRIVING

SOURCE

_L

7n

NPUT n THE GENERAL

INPUT„

LOGIC DEVICE

DRIVING

(made up of

SOURCE

building blocks)

X Fig. 4-61.

X

The "black box" model

of the general logic device.

Generally speaking, a logic family (TTL,

CMOS,

etc.) is

based on a basic

switching circuit configuration that has a particular input stage. This input stage

is

the stage which interfaces the rest of the device to the outside world (see Figure

joined with other devices as shown in called a building block. This building block then

Also, quite often this input stage

4-62).

Figure 4-62 to

make what

is

is

becomes a fundamental module from which higher order integrated circuits are derived. In any case, it is the load of the interface stage input that is used to define the loading factor.

In terms of this input stage loading concept, of an input for a

more complex

shown to

it

in the black

(that

is,

box model

We

then define the "loading" of this complex

FOUR STANDARD LOADS.

can only supply or sink a the "loading" attached to

A word of warning:

is

in Figure 4-61 has four input stage inputs attached

internal to the device).

device input as

possible to define the loading

done by summing the number of input. For example, assume INPUT 2

device. This

equivalent input stages connected to this

it is

finite

amount

Since any given device output stage

of current,

you must be concerned about

it.

It is

easy to be trapped at times by assuming that each input

of a more complex device represents one STANDARD LOAD. This is not always the case, so check the specifications for all of your device inputs and outputs to

260

MSI and LSI Circuits and Their Applications

determine ple, the

STANDARD LOAD equivalence and FAN-OUT capability.

"clock" input (single line) for a

the fan-out of a typical

74LSXX gate
w

|

I 1

1

1

J

1

\

>^

1

FLIP(L) \ !

|

tP d L

Propagation delay

i

/

\A

1

! !

^12nsec*

-8nsec* *Note difference

An

Fig. 4-63.

delays

in

example of propagation delay.

illustrated

switching characteristics at

Vcc

= 5 V,

Ta

= 25°C

tp L H (ns)

TEST

TYPE

CONDITIONS-

low to high Ml N

00. '10

level

TYP

P HL

'"si

Propagation delay time, high-to-low-level output

output

MAX

MIN

TYP

MAX

22

7

15

12

22

8

15

13

22

8

15

H00

5.9

10

6.2

10

H04

6

10

6.5

10

59

10

6.3

10

6

10

7

10

6 8

10

8 9

12

35

60

31

60

35

60

70

100

9

20

10

20

25

35

3

5

04.

1

CL

20

15 pF.

RL

-

400

S2

'30

H10

CL

25 pF.

R

280

|_

H

H20

H30 LOO. L10,

L20

LSOO,

CL

=

50 pF. R

4 kSi

L

LS04 15 pF. R L

CL

=

S00. S04

CL

=

15 pF.

R

S10. S20

CL

=

50 pF.

R

15 pF,

RL RL

LS10. LS20

=

2 k2

i



Final state

Q(H) high

" Q(L) low (a)

Propagation delay = 2 t.u.

Propagation delay = 1 t.u.

SIG(L)

Q(Hl b ?(L)

SIG(L]

r

0

I

|

Q(H)

1

i

t.u.

p

>

i

I

Q(L)

i

Final state 1

Q(H) low Q(L) high

(b)

Fig. 5-10.

An

illustration of the indeterminability of the

after receiving a simultaneous

286

Sequential Machine Fundamentals

SET and RESET.

output of a

cell

for a

Because of simultaneous

this,

all

SET and RESET

never be exercised, that

Note

is

it

is,

a

Qf

generally understood that the condition of a

operation

is

be treated as a condition that should

to

condition.

TRUTH-TABLE

shown

been specially labeled with "Leave alone," "RESET operation," "SET operation," and "don't do." This is done to instill a fundamental design technique that is used throughout that the

this text, as far as sequential circuits are

in Figure 5-9 has

concerned, with phrases like

"SET

that cell

on this condition," or "RESET this cell on that condition" used quite often. This is done in order that a more conceptual understanding of sequential circuit behavior can be realized. Therefore, don't be surprised when you read first-person statements such as: "I want to SET cell A and RESET cell B if the xyz input is ASSERTED." This technique will be demonstrated in Section 5-17 when the design of a "Flip-Flop"

is

treated.

As mentioned, the cell makes up the important portion of memory elements shown in Figure 5-4. It is therefore important that a good understanding of its operation be achieved before moving on to the next several sections. Further, it is important to visualize that propagation delay can and does serve a memory and classifies the cell as an asynchronous sequential circuit. In the next section some elementary but practical applications of a cell are illustrated.

function in the

cell

THE CELL AND THE BOUNCING SWITCH was pointed out that mechanical switches exhibit a contact bounce when closed. The bounce is the result of the spring-loaded impact of the switch throw contact and the pole contacts. Almost every mechanical switch suffers from this problem unless its contacts are specifically designed and "wetted" with mercury. In most general switch applications contact bounce is no real problem. However, it can be very much a problem in digital circuits. This is particularly true when sequential circuits are involved, and each switch closure-bounce sequence is interpreted as an independent input sequence. You can imagine that a bouncing START/ STOP switch for a computer could create all sorts of short start-stop sequences before the switch contact came to rest. The circuit shown in Figure 5-11 In Chapter 2

illustrates

it

how

a cross-coupled

NAND

cell

can be used

to

de-bounce a

SPDT

mechanical switch.

Up

SWCH

UP(H)

SWCH

UP(L)

position

6

Wiper contact

X

O O

Down position

Fig. 5-11.

The

coupled-NAND

switch debouncer centered around a crosscell.

The CELL and the Bouncing Switch

287

A

quick analysis of the circuit shown in Figure 5-11 reveals that the

contact of the wiper with the up-position contact sets the

Then

when

cell

initial

within nanoseconds.

mechanical bounce occurs the cell is firmly locked into the SET condition and subsequent bounces have no further effect. This is true providing the switch design is not so sloppy that it will allow a bounce to milliseconds later

the

first

carry the wiper contact from up-position contact clear back to the contact.

down

position

Figure 5-12 illustrates two other alternative switch de-bounce circuits

centered around a set of cross-coupled sheet for the

INVERTERS.

Figure 5-13 shows the data

DM8544 TRI-STATE QUAD-SWITCH DEBOUNCER

centered

around NOR gate cells. It should be noticed that this device has a strobe input that can be used to disable the complete circuit. This is an important disabling feature when accidental or unauthorized switch flipping can lead to catastrophic results.

(a)

Up

Down

(b)

Fig. 5-12.

Alternative switch debouncing circuits utilizing

INVERTERS.

Fig.

5-13.

The data

(facing

sheet for

page)

DM8544

switch debouncer. (Courtesy

of National Semiconductor).

288

Sequential Machine Fundamentals

^

DM75/DM8544

Proprietary

TRI-STATE Quad Switch Debouncers

General Description

Features

These circuits are for use

in

front panels, and similar

Replaces

SN54279/74279

applications where contact bounce must be eliminated.

Eliminates push-button noise

Within the single package, these circuits do the job of four R-S latches plus pull-up resistors. A strobe is also

Allows clocked devices to be operated from switches

Maximum power

which permits sampling of the switch informaa predetermined time. TRI STATE outputs are

available

tion at

provided

also

connections

direct

for

to

the

250

dissipation

mW

Bus-line connectable

TRI-STATE outputs

switch

Typical propagation delay

line bus.

Connection Diagram

18 ns

Truth Table

TRI STATE

14

16

2

1

STROBE

A2

C2

12

13

4

3

A1

ENABLE

QD

01

02

QA

TRI STATE

STROBE

Q Altl

A1

A2

X

X

H

X

Hi

X

X

L

L

Qaii

L

L

L

'!_

L

H

L

H

H

L

L

H

H

H

H

L

H

Qaih

ENABLE

Z 1)

Indeterminate L

I

82

7544/8544U),

G

B1

NO

(N), (W)

Logic Diagram

TRI STATE

STROBE

ENABLE |

Qb

(?)

|

Qc

(9)

|

QD

(13)

I

I

TO OTHER

LATCHES

The CELL and the Bouncing Switch

289

FUNDAMENTAL DIFFERENCES BETWEEN SEQUENTIAL MACHINES In the past few sections

we have dedicated a good

deal of effort to developing an

understanding of the functional behavior of the blocks of the sequential machine model shown in Figure 5-4. We have introduced the concepts of using a cell for memory, even using propagation delay for memory, and we have discussed some of the timing and operational aspects of combinational circuits that are important to the understanding of sequential machines.

Now let us establish a major distinction between sequential circuits.

Introduc-

ing the concepts of sequential machines presents an interesting dichotomy; on one

hand

and on the other hand there are synchronous and purposes asynchronous circuit concepts

there are asynchronous sequential

sequential circuits.

For

all

intents

because asynchronous concepts are fundamental to all sequential machines. However, the actual uses of asynchronous circuits are somewhat more limited than synchronous; further, asynchronous design tends to be more tedious and difficult for most people, leading to the probable reason why synchronous design techniques seem to have gained considerable domination over asynchronous during the relatively short history of digital design. This results in the trend to teach few or no asynchronous concepts and to deal strictly with synchronous circuits. This author feels that both should be treated, and the order in which they should be treated is: first, a little asynchronous, enough to understand the operation of the "Basic Cell" and traditional Flip-Flops, then a good dose of synchronous circuits, followed by a good dose of asynchronous circuits, and finally at the system level a good mixture of the applications of both. To make certain that we all have a common understanding, asynchronous should be discussed

first,

sequential circuits are basically combinational logic with direct feedback

"paced" or cycled by transitions of

NEXT

EA CH

input

and strictly use

and are

the propagation delay

DECODER

STA TE of the for memory. Synchronous circuits, on the other hand, use hardware devices called Flip-Flops for memory and are paced or cycled by a waveform commonly called the SYSTEM CLOCK. This CLOCK is the "command signal" mentioned earlier that causes the memory element (Flip-Flop) to READ and STORE the code at its inputs. Though this distinction is drawn between the two types of sequential circuits, we find that the Flip-Flop, by itself, is an asynchronous circuit specifically designed to provide the memory requirements of a synchronous circuit. Therefore, other than some subtle distinctions, the operation of both types is basically the same, and the model shown in Figure 5-14 is equally applicable to both. Hence, the following discussions related to the functional operation of a sequential machine is applicable to both. Note further that Chapter 10 is devoted to the study of asynchronous circuits.

special single sychronizing input

FUNDAMENTALS OF SEQUENTIAL MACHINE OPERATION Figure 5-14 finite-state

290

is

a block diagram of a fully labeled general model of a sequential or

machine.

The

labeling

Sequential Machine Fundamentals

is

important because

it

defines or identifies

pertinent signal lines

and

variables that are used to define the operation of the

nothing more than an expanded version of Figure 5-4, expanded to help develop a conceptual picture of the machine's operation as well as to spatially position the basic blocks and signal lines.

machine. This figure

is

Outside world input code or

Outside world input variables f(/P)

r

Combinational Logic or

Next State Decoder f(IP)

Next

-

state

f(PS)

code

or

Next

F

state variables

= f(/P, PS)

Memory Unit

Present state code or

State variables f(PS)

J

Combinational Logic Outputs to World Code Converter

Brought out to the world to identify

the state of the machine

Output code to the outside world Fig. 5-14.

The general model

of the sequential or finite-state machine.

Fundamentals of Sequential Machine Operation

291

by Huffman and Moore when they introduced the concept of the "STATE" of a machine as a means of characterizing the memory of these circuits. They did this by defining the output Sequential machines were

first classified

as such

code (bit pattern) of the memory at appropriately chosen times as the STATE of the machine. The appropriately chosen time is any time the circuit is NOT in a transient condition, that is, changing STATES. To say it again, we define the STATE of a sequential circuit according to the code presented to us directly from the output of the memory element. It should be noted that other names have been given to the STATE of the machine. They are the PRESENT STATE or the STATE VARIABLES. These will be used interchangeably throughout this text. The following definition of a STATE is rather formal; however, it supports the Huffman-Moore concept as well as the control concept of the sequential machine related earlier. The STA TE of a machine is the property of that machine which relates the inputs to the output in such a way that knowledge of the input time function (f) for t>t0 and the state at

By is

t

=

t

Q

completely determines the output for all

t>t0

.

defining the state of the machine in this manner, sequential circuit design

found to be nothing more than combinational design with

illustrated

through the rest of

this text.

Further,

is

it

certain constraints, as

possible to describe the

operation in a discrete step-by-step process by using a graphical aid called a

STATE DIAGRAM. The STATE DIAGRAM and in

Chapter

Now

its

uses are treated thoroughly

6.

turn your attention to Figure 5-14

and consider the function

of the

NEXT STATE DECODER, sometimes called the INPUT or NEXT STATE FORMING LOGIC. The function of this logic network is to decode the inputs from the outside world and the PRESENT STATE of the combinational block labeled the

machine (stored by the memory) and

to generate as

its

output a code called the

NEXT STATE CODE. This NEXT STATE CODE will become the PRESENT STATE CODE when the memory loads and stores it.* This process is defined as a STATE CHANGE or a CHANGE OF STATE. State changing is a continual new state and the PRESENT INPUT CONDITIONS being form the new NEXT STATE CODES (bit patterns). After being

process with each

decoded

to

convinced that the PRESENT STA TE of the machine really reflects its past history you realize that each new succeeding state is a function of the present inputs and the past history of these inputs. This is relatively easy to see when examining the process of getting to any given state. It can be determined that this process is one of repeatedly determining which input conditions were required to cause the machine to transfer to its present state from the state or states just previous. This then provides a simple process of tracing back through each successive state and input conditions to

some beginning. By doing

this the history of all the

input

conditions required to place the circuit into any arbitrary state can be determined.

The combinational

logic block in Figure 5-14 labeled the

OUTPUTS TO

THE OUTSIDE WORLD CODE CONVERTER has the basic function of decoding *This

is

further

292

true only

decoded

when special memory elements memory element to generate

in the

Sequential Machine Fundamentals

are used, otherwise the the true

NEXT STATE CODE

PRESENT STATE CODE.

is

the

PRESENT STATE of the machine and the PRESENT INPUT CONDITION for

the purpose of generating the desired control outputs to the outside world.

many

In

NEXT STATE

decoder block; however, it is felt that a more conceptual picture of the machine's operation can be had if these blocks are shown separately, particularly when one starts to break the model down into classes of machines, as will be done in the next section. In review, a sequential machine is one that steps through STATES (memory output codes) in a sequential manner. The STATE CODES of the machine are generated by the NEXT STATE DECODER that converts the OUTSIDE INPUTS combined with the PRESENT STATE CODE into bit patterns texts this logic

block

is

included with the

WORLD

called the

NEXT STATE CODES

of the machine.

USING VARIATIONS OF THE GENERAL MODEL TO CLASSIFY SEQUENTIAL MACHINES The following models can be derived from the basic model shown by a process of degeneration, as shown in Figures 5-15 through 5-19.

in Figure 5-14

Output Decoder

—

r Outside world

-

outside world

Fig. 5-16.

Class

B machine, sometimes

referred to as the

Moore machine.

r Outside

Next

inputs

State

Memory

Decoder

Element

-•

— Outputs to the

outside

world

Fig. 5-17.

294

Class

C

machine: Moore machine without an output decoder.

Sequential Machine Fundamentals

The

and C circuits with a single input are interesting machines. general model for a counter circuit in which the events to be

class A, B,

These form the counted are entered

STATE DECODER in

memory element or through the NEXT These special circuits and many others will be covered

directly into the logic.

depth in the following chapters.

r Next inputs

Outputs

State

Memory

Decoder

Element

Outside j

v

to the

outside

world

J Class

Fig. 5-18.

D

machine: look-up memory.

r Memory Element

Outside j

Outputs \.

inputs

to the

outside

world

J Fig. 5-19.

Class

E

machine.

important to note again that the class A, B, and C machines are equally applicable for both asynchronous as well as synchronous circuits, and In review,

the

it is

minimum number

nous machines, that

5-10

of

INPUTS

ONE

any of these machines input must be the System Clock. to

is

ONE. For

synchro-

THE FLIP-FLOP To

this point, the

memory element

in the sequential

machine model has been

a propagation delay or (2) some special hardware device that includes a binary cell capable of storing the PRESENT

considered to be one of two things:

STATE

of the machine.

At

this

(1)

time

we

introduce the Flip-Flop as the special

hardware device that is widely used in synchronous finite-state machines. We do this as an introduction to the detailed study of the analysis and design of synchronous sequential circuits covered in Chapter 6. Though the Flip-Flop is used widely as the

memory element

in sequential

circuits,

there are other

memory

applications for this fundamental device, as demonstrated throughout the rest of this text.

The Flip-Flop

295

from the days when basic cells were implemented with cross-coupled relays. The SET and RESET operations of this electromechanical cell gave rise to distinctive audible Flip and Flop sounds.

The name

for the Flip-Flop stems

Falling-edge

Rising-edge

^cHIGH

= HIGH need n0t

f

cLOW

SET

r

Q

Set/ Reset

Basic Cell

Decoder

(one level of feedback

Flip-flop

control

internal)

inputs

RESET

Clock

rLTLTI

Q

Clock

waveform

(b)

SET(L) Q(H)

•

r

Set/ Reset

Decoder

Flip-flop

control

\

inputs

Q(L)

ru~Ln w

Clock

waveform

(c)

5-20.

Fig.

rising-edge

and

t

c

L

ow

(a)

and

0

5)

The

general

falling

Th e

relative

HIGH

and

NAND

cell.

Sequential Machine Fundamentals

waveform

LOW

general model of the Flip-Flop. (c)

model using cross-coupled

296

description of a clock

edge and

A

illustrating

timing periods

more

t

c

the

high

specific Flip-Flop

CLOCKED FLIP-FLOP

The

is

a sequential circuit designed basically to

perform the fundamental process of conditionally storing the binary bits 0 and 1. This operation is accomplished by using a binary cell coupled with some combinational SET/ RESET decoding logic to allow some input control over the SET and

RESET

operations of the

5-20(a)).

Because of

cell.

One

this structure, the

of these inputs

is

the

CLOCK

general model of the Flip-Flop

machine configuration. Thus the general model

(see Figure fits

a class

for the clocked Flip-Flop

is

C

shown

in Figure 5-20(b).

We

observe in Figure 5-20(b) that the general Flip-Flop can have at least two

levels of feedback.

Further,

should be interesting to note, in passing, that in

it

every synchronous machine design using clocked Flip-Flops there are multiple

feedback controlling the circuits. For example, the clocked Flip-Flop itself is a sequential machine with two levels of feedback. When this Flip-Flop is utilized in a class A, B, or C machine, there is yet another overall feedback, and if the class A, B, or C machines are used to control yet another system, then there is still one more level of feedback. Therefore, when using a class A, B, or C machine to control another system, there are no less than four levels of feedback. This points to a real need for sound design practices, or some erratic-behaving systems will levels of

result.

The combinational

SET/ RESET

logic block in Figure 5-20, labeled as the

DECODER,

has a basic and important function. This function is the decoding of the Flip-Flop control inputs, including the CLOCK and the PRESENT STATE of the basic

cell,

and from

RESET. Here we

ASSERTING

one of the two output see a fundamental design procedure emerging: this

lines,

SET

When we

or are

given a specification for a Flip-Flop's operation based on some control inputs and the design

is left

up

PRESENT STATE

we must

to us,

of the cell

consider each input condition along with the

and answer one of

the three basic questions for each

and every possible condition. (1) (2) (3)

Do Do Do

to

SET

I

want want

to

RESET

I

leave

it

as

I

the cell with the next clock pulse

it is

on

the cell with the next clock pulse

this

on

condition?

this

condition?

with the next clock pulse on this condition?

This design procedure is interesting and straightforward and is demonstrated many times throughout the remainder of this text. The next section introduces some special circuits that can be used to generate the all-important

5-1 1

CLOCK.

CLOCK AND OSCILLATORS we touch upon some circuits that can be used to generate the (CLK) or SYSTEM CLOCK (SYSCLK) for synchronous sequential

In this section

CLOCK

and systems. oscillator circuits and circuits

It is

not intended that

all

the theory be developed relative to

merely intended that enough material be presented so that you can put a clock circuit together and have it work. their applications. It

is

Clock and Oscillators

297

However, generally speaking, transient device electronics

is all

As mentioned,

that

is

and some knowledge of

circuit analysis

required to derive the expressions given for fQ

.

clock circuits are rectangular waveform generators and their

output need not be square waves, as illustrated in Figure 5-20(a). Clock oscillators are mainly specified by the following criteria:

(2)

Frequency (/G ) in Hz (cycles per second) Frequency stability equals the percent of fQ changes and device aging

(3)

Duty

(1)

cycle =/cH igh/[(^c HIGH/ + (t low)]

A

For example:

drift

due

to temperature

X 100%

square wave duty cycle equals 50%.

Thus we

see that the

particular oscillator circuit chosen should allow the designer to carry out

mathematical calculations to develop an oscillator which

The

oscillator circuits

which can developed around

circuits

shown

fulfill

good temperature

(3)

high input impedance.

stability,

circuits are

Special Note: Since there

±

1

of these circuits are

and

somewhat

5%. This

limited at high frequencies.

quite a wide variation in device characteristics

is

and parameters, the expressions given ball park), typically

Many

symmetry,

(2)

CMOS

specifications.

devices for the following reasons:

(1) inherent threshold

However, these

meet

in Figure 5-21 are offered as a reasonable selection of

a wide variety of clock needs.

CMOS

will

some

is

for fQ are only approximately true

(i.e.,

in the

true in all cases except the crystal controlled

circuits.

RC oscillators

(simple)

R

=

390

n

-AAA* Buffer

Output

c

Inverters = 7404,

(f

Q

)

74L04, 74LS04 Advantages

1

f o

~3(

Irough estimate)

(1)

(2)

Simple High frequency

Disadvantages (1) (2)

(3) (4)

Fig. 5-21.

298

A

Crude frequency determination Subject to temperature drift No duty cycle control Some power supply dependency

collection of oscillator circuits suitable for digital system clocks.

Sequential Machine Fundamentals

AA/V

Buffer

—

Ft.

R

—VV\/—

i

Output *

(f

0

)

Inverter =

^

f o

0.46 if

R^C

"2

»

—-

(2)

74C04

(3)

1

"1 and

/? 1

>

10 K and

Simple Reasonably close frequency determination Reasonably square output Relatively temperature stable with good R and C Power supply independent

(1)

(CMOS)

(4)

1Q

_ 12) (5)

Disadvantages (1)

Frequency

(2)

No duty May not

(3)

limit


0

•

V\A/

CMOS

Output

Inverters

0.46 f 0

if

R2

»

1

/?,,/?,> 10 k and

2tt/?J30 X 10- 12

0

(1)

Simple

(2)

Close to square wave output

(3)

Reasonable temperature stability Reasonably insensitive to power supply variation Will always start

)

(4)

(5)

Disadvantages (1) (2)

High frequency limits No duty cycle control

(c)

C

Output

(triangle

wave)

(f

Q

)

it

C04^

/?>K)k

rsC04

KC14

Output (square wave) Advantages

(3)

Simple (1 capacitor, 1 resistor) Schmitt output (clean edges) Good temperature stability

(4)

Good

(5)

Reasonable (50%) duty cycle Symmetrical triangle-wave output also

(1)

< Q

f

100 kHz

(2)

Combined 74C04 and 74C14

/?= 51 k 0.58 o

/?(C

(6)

+ 40pF;

predictability

Disadvantages




10 k

—WV/

74C14 (Schmitt with

TQ

=*

Vcc

= 5

(2)

Simple Temperature stable (reasonably) with good R and C

(3)

Self-starting

(1)

oscillator)

V

Disadvantages 1.89 /?C 0.53

(1

)

(2)

Frequency limited

No duty

cycle control

(f)

100

Output (fj

Advantages

7404, 74LS04, 74S04

(1)

High frequency capability

Disadvantages 1

f °

2WLC T

r

^1 ^2

(1)

'

(2)

(g)

Fig. 5-21.

300

Sequential Machine Fundamentals

(Cont.)

Reasonably complex No duty cycle control

ft 510

510

WAr

i

vw

o

Buffer

c

4>

Output

{f Q

,

Advantages (1)

(2) (3)

(4)

Quartz crystal frequency =

Inverter 7404,

f Q

Frequency stability Simple crystal oscillator High frequency Will always start

74LS04, 74S04 Disadvantages

X -> 0 at f0 Xc2 — 510 £2 at fQ

(1)

Cost

(2)

No symmetry

1

(overtone suppression]

adj.

(h)

Crystal controlled oscillator

Advantages

510 V\A/ Buffer

Output

(1)

Frequency

(2)

More simple than

(3)

High frequency

stability

circuit

(/?)

(f

Q

Disadvantages

(2)

No overtone suppression No symmetry adj.

(3)

Might require starting

(1)

74LS04, 74S04

Inverter 7404,

(i)

Vcc

R

'x1

R

f

x2

—ww-)|

i

— vw—sym I ,

n

vs/v*

)|

adj.

Q.

Q.

Q

+5 0-

Q

+5 0-

3D Output

C CLR

Q

74123 one shot

CLR

Q

(1)

T,

=0.25(/? '

f

c

HIGH

x2

+

C„ 2

Q

oscillator

»700n )if/? »700n x2

= fcH lG H 0 -25(«„Cx ,)if/?x1

'cow

(f

(2) (3)

Duty cycle

adj.

Reasonably temperature stable IC package

One

Disadvantages f

c

LOW'

SeC (1)

(2)

Complex (two capacitors/ two resistors) Power supply sensitive

(j)

Fig. 5-21.

(Cont.)

Clock and Oscillators

301

5-12

TYPES OF TRADITIONAL CLOCKED FLIP-FLOPS The design procedure just outlined in Section 5-10 allows you of Flip-Flops if you so choose. However, there are several

to design all varieties

basic types that are

These are the "DELAY" or "D" Flip-Flop and the "JK" Flip-Flop, both of which can be converted to a TOGGLE or "T" Flip-Flop or any of several other types. Other types of Flip-Flops do exist, but they seem to have very limited use. These are the "SR" (SET/ RESET), which has been replaced by the JK, the JK-T Flip-Flop, and other similar exotic devices. For the most part, let us concern ourselves with the five basic types: readily available in integrated circuit forms.

(1) (2) (3)

(4) (5)

5-1 3

Clocked SET/RESET Clocked D-Latch Clocked T Clocked JK Clocked JK MASTER/ SLAVE

THE SET/RESET FLIP-FLOP To

initiate the

SR and

its

study of Flip-Flop operation and design,

characteristics, as

shown

first

consider the clocked

in Figure 5-22.

Figure 5-22(a) shows the accepted schematic symbol for the

SR

Flip-Flop to

be used when drawing schematics for a design using the SR Flip-Flop. Note that the S input is just above the Q output on the same line. The R input is on the same line with the Q output, with the clock input centered between S and R.

we begin

approach to the design of the clocked Flip-Flop. In this logic diagram it can be seen that if S(H) is ASSERTED at the rising-edge of the clock, the SET(L) is ASSERTED and the basic cell is SET, thus g(H)—>HIGH. Further, it can be seen that if R(H) is ASSERTED, the cell is RESET on the rising-edge of the clock, thus g(H)-»LOW. At this point it should be noted that when the clock is high, the cell is vulnerable to changes on the S(H) and R(H) inputs. In other words, the inputs S(H) and R(H) have a straight shot at the basic cell when the clock is high, allowing changes in these inputs to alter the information that was gated into the cell on the rising-edge of the clock. This may or may not be a problem in some cases. More will be discussed later about this feature and the effects it can have on sequential machine In Figure 5-22(b)

to see the building block

design.

CHARACTERISTIC TABLE shown in Figure TRUTH-TABLE for specifying the operational characteristic The

The Qn and Qn + device.

Qn

is

to

1

tic

302

is

added

of the

a special

SR

Flip-Flop.

PRESENT STATE OF g(H) and Qn is to NEXT STATE OF 0(H) or the STATE after the rising-edge

Note further

table suggests the

is

to illustrate the sequential nature of the

be interpreted as the

be interpreted as the of the clock.

notation

5-22(c)

-I- 1

that the bracketed notation to the side of the characteris-

ACTION

taken on the basic

Sequential Machine Fundamentals

cell

on the

rising-edge of the

clock. This

is

important information to those

other type of Flip-Flop using the model

information

is

who

shown

are interested in designing

in Figure 5-20(b).

How

some

to use this

illustrated in a later section.

R

c

S

Q

Q

T (a)

SIH)

SET(L)

I

Falling-edge

Rising-edge

/

Clock

RESET(L)

I

R(H)

J (b)

S R Qn 0

0 0 0 0 0 1 0 1 1 0 1 0

operation

RESET

operation

1

0

SET

operation

1

1

0

1

1

1

No

0

1

Qn +

1

1

1

Qn

Qn +

Don't do

- before rising-edge of CLOCK = after rising-edge of CLOCK (c)

Qn

->

Qn +

0 0

0 1

1

0

1

1

1

s R 0 0 1 0 0 1 0 0

RESET but no SET SET and no RESET Definite RESET and no SET Don't care SET but no RESET

Don't care Definite

(d)

Fig. 5-22.

The documentation

related to the

RS

Flip-Flop. (a) Schematic

symbol, (b) Logic diagram showing the two major blocks

DECODER

and

BASIC CELL, (c) The the clocked SR Flip-Flop.

the

excitation table for

SET/RESET

characteristic table, (d)

The

The SET/RESET

Flip-Flop

303

The EXCITATION TABLE shown in Figure 5-22(d) is also an important design aid, and the information plotted in this table is derived from the CHARACTERISTIC TABLE in Figure 5-22(c). The EXCITATION TABLE graphically answers the question: What input conditions must prevail to cause the indicated transitions? For example, what input conditions must exist prior to the rising-edge of the clock in order to produce Qn = 0-+Qn + 1 =0? By looking in the CHARACTERISTIC TABLE for the entries where Qn = 0 and g« + l=0, we find that

S = 0, R = 0 and S — 0, R = 1 are the only conditions where Qn = Qn + 1 = 0. Thus S = 0 is a completely specified condition and R=& is the other condition. From this we can state that for an SR Flip-Flop to make a Qn = 0—>g« + 1= 0 transition, S must not be ASSERTED and R is a don't care (0). The rest of the entries in the

EXCITATION TABLE

are

filled

important information related to the

out in a similar manner.

SR

Flip-Flop,

and

will serve as the guide to

developing similar documentation for the following Flip-Flop

5-14

This covers the

circuits.

THE "D"-LATCH FLIP-FLOP The D-Latch storage.

It

is

edge-triggered

LATCH

is

an interesting device used quite extensively for temporary data important to draw a distinction between the D-LATCH and the

is

D

Flip-Flop.

designed in such a

follow the data or

DL

Though they way that when

are similar in the clock

input, while the edge-triggered

D

their

operation,

the

2(H) output will Flip-Flop loads on the edge

is

high, the

of the clock waveform, usually the rising-edge, further changes at the

D

input until

and locks out the effects of any the next rising-edge. These edge-triggered

devices and their operation are discussed in the edge-triggered Flip-Flop section.

Figure 5-23 illustrates the schematic symbol, logic diagram,

and

EXCITATION TABLES

for the

D-Latch Flip-Flop.

(a)

Fig. 5-23.

(b)

The

CLOCKED D-LATCH

diagram.

304

CHARACTERISTIC,

Sequential Machine Fundamentals

Flip-Flop. (a)

The schematic symbol,

(b)

The

logic

D Qn Qn + n

n

1

n

1

0

1

1

1

1

n o

Qn

1

0

o n

RESET cell* DCCCT rp SET cell SET cell** ||

0

Qn +

->

D

1

0

o 1

1

1

0

0

1

1

1

(d)

(c)

*0 RESET is read as: Don't care if a RESET operation is performed. **0 SET is read as: Don't care if a SET operation is performed. (c)

The

The

characteristic table, (d)

excitation table.

(Cont.)

Fig. 5-23.

Considering the schematic shown in Figure 5-23(b), observe that when the

ASSERTED

HIGH

ENABLED

and the output will follow the input (DL ) if it changes during this time. As mentioned earlier, this feature may or may not be a desirable one, depending on the application for the clock

is

or

the input logic

is

device.

515

THE "CLOCKED T" FLIP-FLOP The "T" Flip-Flop

derives

its

name from

toggle implies a change of state

even though

by

it

does not

the

T

operation, which

input

is

is

"toggle."

ASSERTED. The T

exist in integrated circuit form,

The word Flip-Flop,

can be quickly generated

D

and JK Flip-Flop. Figure 5-24 illustrates information regarding the use and function of the T Flip-Flop.

slight modifications

characteristic

when

its

on the

the

should be noticed in Figure 5-24 that the T Flip-Flop is a multiple-feedback system and is one in which the outputs are fed directly back into the It

SET/RESET

D

RS and

decoder, unlike the

modes

multiple feedback leads to several undesirable conditions. If

One

the

of these undesirable

propagation

delays

of

modes gates

is

Flip-Flops just discussed.

This

of operation under certain

oscillation.

a

and

c

are

slightly

longer

than

and d, the Flip-Flop will break into oscillation with the rising-edge of the clock and will remain in oscillation for the period of time the clock is at its high level. This oscillation mode is intuitively obvious from the control definition of the T input, that is, if T and CLK are both ASSERTED the Flip-Flop is to change states. Once the state is changed, conditions are such that another change is called for. Thus if T and CLOCK are held high and the propagation delays of a and c>b and d, oscillations will prevail. The other undesirable mode of operation develops when the combined propagation delay of a and c is less then b and d. Under these conditions the Flip-Flop will revert into a simultaneous SET and RESET mode with both outputs held HIGH and will

the propagation delays of b

remain there

until the falling

edge of the clock.

The 'CLOCKED T" Flip-Flop

305

(a)

SET(L)

|

r(H]

CLK(H) RESET(L)

i I

(b)

T Qn

Qn +

0

0

1

1

1

0

1

1

1

0

0 0

Qn

1

0 0

RESET cell SET cell SET cell RESET cell

-*

Flip-Flop.

The

(d)

The CLOCKED "T" (b) The logic diagram

1

T

0

0

1

1

1

0

1

1

1

0

0 0

(d)

(c)

Fig. 5-24.

Qn +

The schematic symbol of the T Flip-Flop. (c) The characteristic table,

Flip-Flop. (a) for the

T

excitation table.

Neither of these modes of operation

is

desirable; however,

if

extremely short

perform the normal operations. This clock high duration should be slightly longer than A/c + A/6 or Atd -\-Atb This clock timing constraint was commonly used in the early days of digital design. clock pulses are used to trigger the circuit,

it

will

.

5-16

THE "CLOCKED JK" FLIP-FLOP The "JK" Flip-Flop

probably the most functional and interesting of all Flip-Flop types. Its origin undoubtedly stems from an extension of the RS Flip-Flop. It will be shown that the JK is functionally identical to the RS except for the case where / and are both ASSERTED together. It should be remembered that when using an RS Flip-Flop the case where R and S are both ASSERTED is one that must be avoided because of the indeterminability problem. A JK Flip-Flop is designed in is

K

306

Sequential Machine Fundamentals

such a way as to cause the basic

cell to

simply toggle or change states with the

waveform should both / and K be ASSERTED.* This is the only difference between the JK and the RS Flip-Flops, and as a result of this the J input can be thought of as the SET input and the K as the RESET input. Thinking this way can reduce a good deal of the mental baggage associated with Flip-Flop nomenclature. Figure 5-25 illustrates the necessary descriptive and functional features concerned with JK Flip-Flops. Note that the logic diagram in Figure 5-25(b) has been modified somewhat. Two extra inputs have been added to the cell. These are the asynchronous SET and RESET inputs that completely override the CLOCKED inputs to the cell. These inputs are standard for most integrated Flip-Flops and are normally added in order to make the device more flexible. They are not to be included in the clocked operational description for the Flip-Flop; they are to be thought of as a separate and independent function. However, the use of these asynchronous SET and RESET is restricted to the low period of the clock in order to avoid simultaneous SET and RESET conditions. rising-edge of the clock

R K

C

S

J

Q

Q

T (a)

(b)

J

K Qn Qn +

0 0 0 0 0 1 0 1 1 0 1 0

0

0

1

1

0 1

0 0

0

1

1

1

1

1

0

1

1

1

1

0

1

0 0 0

0

RESET SET RESET RESET SET SET SET RESET

Qn

->

table, (d)

1

0

0 0

1

1

0

1

1

J

K

0 0 1 0 0 1 0 0

(d)

(0 Fig. 5-25.

Qn +

The JK Flip-Flop. (a) The schematic symbol, The excitation table.

(b)

The

logic diagram, (c)

The

characteristic

There is yet another type of Flip-Flop called the JK MASTER/SLAVE, which is discussed after the next section along with some of the devices that are presently found in integrated circuits. These devices are designed in such a way

*Watch out again when the CLOCK J and same two anomalous modes the T has.

K inputs are ASSERTED;

The

because

this

CLOCKED

JK

Flip-Flop has the

JK'' Flip-Flop

307

that the undesirable

procedure which

modes

are avoided.

will hopefully yield

In the next section

some

we

discuss a design

insight into the actual design of a

Flip-Flop. Further, this design technique will allow

you

to design special purpose

Flip-Flops should the need ever arise.

5-17

THE DESIGN OF A CLOCKED FLIP-FLOP It is

important to note that the design philosophy illustrated in

an

this section is

introduction to a general design approach used throughout the following chapters

on sequential

models are defined and the function of each block of the model are designed based on the interaction required between the blocks of the model by calling out such sequential circuit actions as: "SET the cell on this condition" or "RESET the cell on that condition." design. Specifically, general

The past from a given

section defined or specified the operation of the different Flip-Flops

circuit

without regard to where the circuit came from or

designed. In this section

given a

will

be

illustrated

CHARACTERISTIC TABLE

Figure 5 -20(b).

It is

circuit packages;

you

it

true that

may come

it

was

go about designing a Flip-Flop

to

and using

most of the

however, there

how

how

the Flip-Flop

model shown

in

circuits described exist in integrated

a time when

it

becomes necessary

for

and design a different type of Flip-Flop. Besides, it is comforting to the Flip-Flops shown in the past section didn't just come from thin air,

to define

know

that

that there really

is

a definite design technique used to develop them.

should be pointed out that the following technique techniques. This particular process

areas of design,

where

its

is

just

was chosen because

it

Again,

it

one of several possible carries over into other

use provides a decisive advantage over the more

traditional approaches.

STEPS TO FLIP-FLOP DESIGN Step 1: Given a

CHARACTERISTIC TABLE

prescribing

operation, examine each entry of this table (both inputs

and answer (1)

(2)

(3)

the following questions for each

row

and

some

desired

the output desired),

of the table:

Does the cell need to be SET for this condition, or would a SET cause the wrong transition (SET or # SET)? Does the cell need to be RESET for this condition, or would a RESET cause the wrong transition (RESET or # RESET)? Does the cell need to be left alone?

REMEMBER,

a simultaneous SET and RESET is NEVER TO OCCUR. After each row in the CHARACTERISTIC TABLE has been examined and the questions above have been answered, a TRUTH-TABLE can be plotted with

SET and RESET

308

as output variables.

Sequential Machine Fundamentals

Step

2:

Based on the answer

TRUTH-TABLE,

and

the questions above

the resultant

MAP and RESET MAP and derive the SET/ RESET DECODER block in Figure 5 -20(b). SET

plot a

tional logic for the

Example

to

combina-

Using the technique just described, design a clocked SR Flip-Flop given the CHARACTERISTIC TABLE and the maps shown in 5-2:

Figure 5-26.

0

CLK S R Qn Qn+\ SET RESET 0 0 0 0 0 0 {No SET, PRESET 0

1

0

0 0

2

0

0

3

5

0 0 0

6 7

4

1

1

0

0

0

0

1

1

1

9f

0

1

0

0

0

0

0

1

0

1

1

0

1

1

0

0

0

0

1

1

1

1

9f

0

No RESET

{& SET,

0

1

•

0 Input can happen with

8

0 0

0

0

0

0

9

0 0

1

1

9f

0

10

0

1

0

0

0

11

0

1

1

0

0

1

12

1

0

0

1

1

0

13

1

0

1

1

14

1

1

0

15

1

1

1

0 %

&

CLK

optional

. .

'

{No SET, Yes RESET

No RESET {#SET, No RESET

{Yes SET,

0

% 9

9f

CHARACTERISTIC TABLE

no

Input conditions must

not happen

TRUTH-TABLE for

SET/RESET

DECODER Step No.

2: Plot

maps:

\CLKS flQ„\

\CLKS

00

01 0

00

0

01

0

7

0

Thus we

5

0

01

10

0

7

0 15

11

14

10

/0 6

2

0

0

RESET(L) - (CLK

S)(L)

9

0

0

10

14

•

0

0 13

5

3

8

0

0

11

11

12

0

0

10

11 4

1

0

0

SET(L) = (CLK Fig. 5-26.

00

0 1

6

2

10

0

01

0

9

13

5

0

0

00 0

0

0

\

8

0

3

11

10

11 4

1

/?Q n

•

R)(L)

Steps to Flip-Flop design.

see that the circuit resulting

from

this

design

is

the

same

as that

shown

in Figure 5 -22(b).

The Design of a Clocked Flip-Flop

309

The design

D-LATCH

of a

and a

T

Flip-Flop

is

equally easy, as demon-

strated in the following examples.

Design the D-LATCH as prescribed by the CHARACTERISExample 5-3: TIC TABLE and SET and RESET map shown in Figure 5-27.

SET

RESET

0

0

0

{No SET, PRESET

1

1

Qf

0

{#SET,

1

0

0

0

1

1

1

0

0

0

1

0 0

1

0 0

0 0

1

1

1

0

1

1

1

1

1

1

9f

CLK

D

Qn

0 0 0 0

0 0

0

1

Qn +

\

No RESET •

•

{No SET, Yes RESET

0 0

J

•

•

J

T

Y

SET/RESET

HARACTERISTIC TABLE

DECODER TRUTH-TABLE

.CLK D 00

.CLK

Q/f

01 0

0

1

6

0

0

0

SET(L) = (CLK

•

0

5 1

6

0

0

0

3

0

7

table

and the SET and

\

0

RESET(L) = (CLK

D)(L)

10

11 2

1

0

The Flip-Flop design

Fig. 5-27.

0

0 3

01 0

4

0 1

00

10

1

2

D

RESET map

•

D)(L)

for the

D

Flip-Flop.

Thus we see again that when the logic for SET(L) and RESET(L) is designed and coupled with the basic cell, we have the D-LATCH Flip-Flop shown in Figure 5-23(b). should be noted that both the RS and D-LATCH Flip-Flops required no feedback from the cell itself to SET/RESET DECODER. However, the T FlipIt

Flop does, as

310

illustrated

Example

5-4:

istic table

and

by the following.

Design a the

T

Flip-Flop as prescribed by the following character-

map shown

in Figure 5-28.

Sequential Machine Fundamentals

CLK

T

Qn

0 0

0

0

0

1

1

9f

0{#SET,

1

0

0

0

&

3

0 0 0 0

1

1

1

%

0-

4

1

0

0

0

5

1

0 0

1

1

0

0 1

2

Qn +

6

1

1

0

1

1

7

1

1

1

0

0

T CHARACTERISTIC TABLE

\

00

01 0

0

©

3

0

RESET RESET

DECODER TRUTH-TABLE

4

•

0

0

1

0

5

The Flip-Flop design

table

6

0 3

0

and the SET and

4

0

0

0

RESET(L) = (CLK

Qn)(L)

10

11 2

i

0

T

01 0

0 7

•

00

6

0

0

SET(L) = (CLK Fig. 5-28.

0 0{Yes SET, No l{No SET, Yes

10

11 2

1

1

No RESET

\ CLK T

0

0

#{No SET, PRESET

SET/RESET

\CLK T ?A7

RESET

SET

\

•

RESET map

7

5

0

T

Qn)(L)

•

for the

T

Flip-Flop.

Thus again we

see that the circuit resulting

Flip-Flop that functions as prescribed by a the Flip-Flop

model shown

from

this

design gives rise to a

CHARACTERISTIC TABLE

in Figure 5-24(b). Exactly the

same

and

fits

steps are followed

to design the other Flip-Flops described in this text.

5-18

FLIP-FLOP CONVERSION

FROM ONE

TYPE TO ANOTHER There are times when one type of Flip-Flop must be converted to another in order to fulfill some design obligation. However, more importantly, the process of conversion provides an insight into the process of recognizing which Flip-Flop is the

optimum

or the best choice for a particular task.

SET/ RESET described. To Example

attack

illustrate

5-5:

D-LATCH

is

to a

that the

same

used in keeping with the design philosophy previously the conversion process, consider the following example.

Convert the

T

Note again

RS

Flip-Flop to a (a)

D-LATCH,

(b) T,

and

(c)

a

Flip-Flop.

Flip-Flop Conversion from

One Type

to

Another

31

The general attack on a problem like this is to use the model Figure 5-29. Here we see that the process of converting one type of

Solution:

shown

in

Flip-Flop to another

very similar to that of converting a basic cell into one of the general types. In other words, some combinational logic decoder must be is

new

designed for converting

input definitions into input codes which will cause

the given Flip-Flop to perform as desired.

Different flip-flop

Fig. 5-29.

1

convert

The model used one

Flip-Flop

to to

another.

Flip-Flop

Given

Conversion Logic

Flip-Flop

Q

Q >

Qn -+Qn + 0 0

1

Qn

S R 0 0 1 0

0

o

0

1

2

1

0 0

1

0

1

0

1

1

1

3

1

1

D Q

Note: The order of the

0 1 0 0

0

1

D L Qn ,

inputs are not

standard

Conversion Table (a)

S

=

D

Q

VC

=

D

(b)

D.

R

R

\/

S

C

Q

Q

D,

L

Q

(c)

Fig. 5-30.

(a)

The conversion table for converting an RS Flip-Flop (c) The circuit conversion of an RS to a D.

conversion map.

312

Sequential Machine Fundamentals

to a

D. (b) The

SET and RESET

Therefore, to convert an

RS

Flip-Flop to a

D-LATCH, you

need only

combine the EXCITATION TABLES for both Flip-Flops as shown in Figure 5-30(a) and make a TRUTH-TABLE (CONVERSION TABLE) for each of the inputs for the Flip-Flop to be converted. To construct this TRUTH-TABLE, arrange the tabulation in the same order as the EXCITATION TABLE and show the inputs to be controlled as a function of the Qn present state of the machine and the inputs of the new Flip-Flop desired. This conversion process is shown in Figure 5-30. From the model (Figure 5-30(a)) we know in general that S and R must be a function of D and Qn. Therefore we have the map shown in Figure 5-30(b). Hence the circuit follows, as shown in Figure 5-30(c). To convert an RS Flip-Flop to a T, we do the same thing. However, this time R and S are functions of both T and Qn (the present state). This is shown in Figure 5-31.

Fig. 5-31.

The conversion

of

an

RS

Flip-Flop to a

T

Flip-Flop.

Another example could be the conversion of a D-LATCH to a T FlipFlop. Using a method similar to the last two examples generates the circuit

shown

in Figure 5-32.

The conversion

of a

D-LATCH

to a

T

is

shown

in Figure

5-32(c).

Flip-Flop Conversion from

One Type

to

Another

313

Q"\

o

1

0

un

->

+

U/7

1

l

Lin

U

0 0

0

0

o

0

1

2

1

1

0

3

1

1

0

1

1

1

0

1

1

0 0

0

n

XJ

0'

TQn + TQn

=

1

D

Conversion Table

=

3

0

1

T(+)Qn

(b)

(a)

V DL

V*

T o

Fig. 5-32.

The conversion

of a

D

Flip-Flop to a

T

Flip-Flop.

These examples show that there is a simple and straightforward technique for converting one Flip-Flop type to any of the other types.

5-19

PRACTICAL CLOCKING ASPECTS

CONCERNING FLIP-FLOPS In a previous section

we

discussed some of the interesting concepts related to

operational characteristics of four different types of Flip-Flops. Actually, with one exception, the devices

we have

exception mentioned

the

is

studied are rather limited in their use.

D- LATCH, which

is

often used to latch

The one

and hold

data.

The common problem that all these devices have is the vulnerability of the cell when the clock is ASSERTED (high). This feature makes these devices undesirable for finite-state machine design for the following reason: The lack of a lock-out or edge-triggering feature can cause erratic state transitions in finite-state machines!

The same problem was

also

alluded to previously.

To

further illustrate this

problem, consider the following example.

Example

consider at

314

machine model as shown in Figure 5-33, the indicated time frame (before rising-edge of clock) that the

5-6:

Given the

finite-state

Sequential Machine Fundamentals

NEXT STATE CODE is STABLE. Now, when the rising-edge of the clock does occur, the NEXT STATE CODE is transferred into the Flip-Flops and a "NEW" PRESENT STATE CODE is generated. At this instant this NEW PRESENT STATE CODE presents itself to the NEXT STATE DECODING LOGIC where a whole NEW NEXT STATE CODE is generated. This occurs, of course, after an appropriate propagation delay has elapsed.

NEXT STATE CODE

or even a change in an

while the clock

ASSERTED,

is

still

INPUT

variable

If this is

NEW

generated

the basic cell in the Flip-Flop can be

changed from the condition loaded into it on the rising-edge, presenting an anomaly. If this anomaly does take place, erratic machine behavior will result. What this means is that a multiple-state change can be effected with one clock pulse, contrary to the basic concept of the machine being paced or stepped from STATE to STATE by one clock pulse at a time. To better illustrate this anomaly, consider the next example.

CLK(H)

f

—

Memory D

Next State

NEXT

Decoder

STATE

CODE

Flip-Flop

w/o Lock-Out

Present state

code

Fig. 5-33.

A

finite-state

clock waveform

Example

is

5-7:

machine implemented with Flip-Flops

that are vulnerable

when

the

ASSERTED.

An

by analyzing one

example of the anomaly described above can be state

variable

X

illustrated

(one Flip-Flop output) in the machine

proposed in Figure 5-34. We can see by studying the proposed sequence that the variable X is supposed to step with the clock from a 0 condition to a 1 condition with the first clock pulse, then from a 1 to a 0 on the next clock pulse. What really happened is: Assuming an initial stable 0 condition for X, on the rising-edge of the clock a 1 (NEXT STATE) is loaded into the Flip-Flop. After t seconds, this 1 appears at the output of the Flip-Flop. This 1 is then coupled back around into the NEXT STATE DECODER designed to form the NEXT STATE of 0 as the sequence indicated. Now after t 2 seconds this new 0 NEXT STATE condition is generated and this condition RESETS the basic cell to 0 again after t seconds. x

x

Practical Clocking Aspects Concerning Flip-Flops

31

We

is initiated by the rising-edge of the clock. example is the STATE of variable X at the Of falling-edge of the clock. We see from the figure that the falling-edge catches the NEXT STATE variable at a 0 condition and hence the new present state is 0 rather than I. The net effect of all this is that the next state, which should be a 1, is a 0 and a good deal of oscillating is taking place while the clock pulse is

see that a chain reaction of sorts

particular interest in

this

high.

PRESENT STATE VARIABLE

NEXT Next

STATE VARIABLE

State

Decoder

(a)

r—

0

0

1

1

-i

(b)

Change

state

—

CLK ->

f ,

-
-


CK

CD

DATA TIMES SETUP HOLD (ns)

to

30

80

0t

01

20

50

01

01

SN54H73 SN5473

20

50

0t

01

SN54107

3

38

30 20

125 C J. J.

Q

R

CLEAR

PAGE REFERENCES

DEVICE TYPE

AND PACKAGE -55 C

o

s

PIN

ELECTRICAL

ASSIGNMENTS

0 C to 70 C

W W

SN74H73

J.

N

5-22

6 50

SN7473

J.

N

5-22

6-46

J

SN74107

J,

6 46

SN74L73 SN74H76

N N

5-32

T

5-22

6-54

J.

N

5-23

6 50

J.

N

5 23

6-46

N N

5-24

6-50

J,

5-24

6-54

J.

N

5-21

6 50

J.

N

5-22

6-50

J.

522

6-46

5-22

6-54

5-21

6-54

1

01

Oi

80

01

Oi

SN54L73 SN54H76

50

0'

Oi

SN5476

30

80

0'

Oi

SN54H78

3

3 8

0'

0.

30

80

01

01

30

80

0!

0.

SN54L78 SN54H71 SN54H72

20

50

0t

Oi

SN5472

3

3 8

Of

Oi

3

3 8

0:

0.

SN54L72 SN54L71

J

K L

M N

J,

W W SN7476 SN74H78 J. W J, J,

J,

T

SN74L78 SN74H71

W SN74H72 J. W J, W SN7472 J,

J,

J,

J,

T

SN74L72

J.

N N

J,

T

SN74L71

J.

N

—o

Q O—

CLEAR

J

4

(3

O

O

?3 76

CLOCK DUAL J-K WITH CLEAR

-DUAL J-K WITH CLEAR AND PRESET -DUAL J-K WITHCLEAR

107

Fig. 5-36.

Data sheets

for pulse-triggered

JK

Flip-Flops. (Courtesy of Texas Instruments, Inc.)

Practical Clocking Aspects Concerning Flip-Flops

319

A

waveform for a (RET) device expanded rising-edge-triggered to illustrate the set-up time and the hold time Fig. 5-37.

Active transition point Volts

typical clock

definitions.

Time

t

Inputs can change

up to

this point

1»

t setup

Inputs can change from this point,

hold

i.e.,

data

locked out

Data sheets and

5-38.

Fig.

diagrams for the SN74110 and SN74111.

J-K FLIP-FLOPS

DUAL

logic

(Courtesy

of

Texas

O

WITH DATA LOCKOUT SINGLE

1

1

Instru-

ments, Inc.) «

>CK

CLEAR

J

DWG

TYPICAL CHARACTERISTICS

REF

QO-

CK Q

K

O

K

CLEAR

CLEAR

SINGLE

EDGE TRIGGERED FLIP FLOPS

J-K

H PRESET

O

J

>CK

4 >CK 1=1

DWG REF.

TYPICAL CHARACTERISTICS 'max (MHz)

Pwr/F-F

(mW)

DATA TIMES SETUP HOLD Ins)

Ins)

-55 C

to

50

100

131

Oi

10

20.

0.

45

10

20

Oi

SN54LS107A

33

10

20

51

SN54LS109A

33

45

101

61

SN54109

75

31

Oi

100

131

01

45

10

20.

Oi

45

10

20

Oi

125

75

31

Oi

50

100

13i

Ot

B

45

10

20.

Oi

45

10

20i

Oi

125

75

31

Oi

C

45

10

20i

Oi

SN54S1 12

J,

SN54H106

J,

1

1

1

E

r

t 1

The arrow

125 C

45

A

25 50

F

50

100

131

Oi

SN54H101

G

50

100

13i

Oi

H

35

65

20'

51

SN54H102 SN5470

indicates the edge of the clock pulse used for reference:

Fig. 5-39.

Data sheet

for

RET

PAGE R EFERENCES

DEVICE TYPE

AND PACKAGE

W W J, w SN54LS76 SN54LS1 2A J. w SN54S1 14 J. w SN54H108 J, w SN54LS78A J. w SN54LS1 4A J, w SN54S1 13 J, w SN54LS1 3A J. w SN54H103 J, w SN54LS73A J. w

1

D

>

t

PIN

ASSIGNMENTS

0 C to 70 C

ELECTRICAL

SN74S112 SN74H106

J,

N

5-34

6 58

J,

N

5-32

6 52

SN74LS76A

J.

N

5-23

6 58

N

5-34

6 56

SN74LS1 12A

J.

SN74S1 14

J.

N

5-34

6 58

SN74H108

J,

N

5-32

6 52

J,

(SI

5-24

6 56

N

5-34

6-56

J. J,

N

5-34

6 58

5-34

6-56

SN74LS78A SN74LS114A SN74S1 13

SN74LS113A

J,

N

SN74H103

J.

N

5 31

6 52

SN74LS73A SN74LS107A

J,

N

5-22

6-56

J,

N

5-32

6 56

J.

SN74LS109A

J,

N

5-33

6 56

J,

SN74109

J,

N

5-33

6 46

SN74H101 SN74H102

J,

N

5-31

6-52

J.

N

5-31

6 52

J.

N

5-21

6-46

J

w w J, w J. w w J,

SN7470

for the rising edge,

I

for the falling edge

and FET. JK Flip-Flops. (Courtesy of Texas Instruments, Inc.)

Practical Clocking Aspects Concerning Flip-Flops

321

D-TYPE FLIP-FLOPS

DUAL PRESET

Q

D

>CK Q

CLEAR

T DWG. REF.

DATA TIMES HOLD

TYPICAL CHARACTERISTICS 'max (MHz)

Pwr/F-F

SETUP

(mW)

(ns)

-55° C to 125°C 0°Cto 70° C

(ns)

3t

2t

SN54S74

SN74S74

75

15t

5t

10

25t

5t

25

43

20

5t

3

4

50

Ot

SN54H74 SN54LS74 SN5474 SN54L74

SN74H74 SN74LS74 SN7474 SN74L74

110

75

43 33

Q

TEMPERATURE RANGE

PRESET

»

CLEAR

CLOCK

Fig. 5-40.

Data and specification sheets

for

RET D

Flip-Flops. (Courtesy of

Texas Instruments, Inc.)

Flip-Flop

Propagation delay of

propagation delay = f PP

NEXT STATE DECODER = t

FF d P

r

setup

"VInputs must

Inputs must

remain stable

remain stable

Fig. 5-41.

Worst case timing

determination.

322

Sequential Machine Fundamentals

related to

maximum

clock frequency

The

diagrams for the devices shown in Figures 5-36, 5-37, 5-38, and 5-39 are vastly different from those developed earlier. The reason for this is twofold:

(1) (2)

logic

These devices incorporate the edge-trigger or lock-out features. The actual integrated circuit manufacturing processes many times dictate a particular logic form.

However, the EXCITATION TABLES for these IC devices are identical to those we have developed. Also, note that the rising-edge of the clock for the SN74111 locks the data into the master cell and the falling-edge transfers this data to the outputs, providing advantages or disadvantages depending on the circumstances. We see in Chapter 10 how Flip-Flops with edge- triggering and data lock-out features can be designed in a straightforward manner. However, we use these devices and other similar devices to our advantage in the next several chapters to implement a variety of finite-state machines.

5-20

TIMING AND TRIGGERING CONSIDERATIONS should be noted that two important timing constraints are listed in the typical data sheet listing shown in Figures 5-38, 5-39, and 5-40. These are SET-UP and It

HOLD

times.

The

definition of

SET-UP

time

is

the time required for the input data

edge of the clock. If you choose to ignore this specification, you should expect unpredictable behavior. This unpredictable beto settle in before the triggering

havior manifests

(1)

itself in

several ways:

missed data or ignored actions;

(2) possible partial transient outputs.

These

partial

RESET"

transient outputs are referred to as "partial

outputs. In other words,

it is

possible to start a

SET" and

RESET or SET

"partial

operation,

back to its original state. Worse yet, a metastable condition can be precipitated in which the Flip-Flop is neither SET nor RESET for some undeterminable time. These concepts are fundamental in nature and are discussed at length in Chapter 7. causing the output to start to change, but to

The

definition of

HOLD

time

after the triggering edge of the clock. tion,

unpredictable behavior will In keeping with this

is

the time required for the data to remain stable

Again,

if

you choose

to ignore this specifica-

result.

odd behavior

tions also help determine the

fall

maximum

constraint, these critical timing specifica-

allowable clock frequency for a finite-state

how

the worst case

machine. With

all

^set-up' 'hold*

Flip-Flop propagation delay and propagation delay of the NEXT add together to determine the maximum clock frequency.

constraints^ included, Figure 5-41 illustrates

STATE DECODER

Timing and Triggering Considerations

323

From

this figure

we

see that

if

TCwc ^

'su

+

*FFpd

+

'ns

.-./A_L< Jc T — •

•

^su

^FFpd

+ 'ns

=

worst case

*FFpd

=

worst case Flip-Flop propagation delay from clock edge

'ns

=

worst case propagation delay through the

where

/ su

SET-UP

time

NEXT STATE DE-

CODER 5-21

CLOCK SKEW Clock skew

edge of the system clock to various devices caused by delay introduced by buffer devices and the propagation delay of conducting paths (wires). Skew is of particular importance when shift register operation is involved. For example, there are many times when one

memory

is

effectively a time shift in a triggering

device (destination device)

is

intended to load the output of another

rising-edge

is

in turn

when

this

same

changing the output of the source device (see Figure

5-42).

driving device (source device) on the rising-edge of the clock,

SYSCLK

Af and At 2

are clock

1

At,

SYSCLK +

Af,

Data

DATA

changing

-At,

SYSCLK + Fig. 5-42.

324

An

At,

Destination device loaded with wrong data

example of the missed data caused by clock skewing.

Sequential Machine Fundamentals

skews

Now,

there

if

clock skew which tends to delay the loading of the destination

is

device for a period of time greater than

it

takes to change the present output of the

source device, reliable operation no longer prevails. In short, violates the

Thus

if

HOLD

if

the clock

skew

time requirements of the destination device, you have trouble.

clock drivers (buffers) are used in systems which incorporate this source/

destination relationship, added delay (inverters)

may have

to

be added to assure

reliable operation.

One more

warning:

When

using any device, integrated or not, be certain to

spend some time dwelling on the specification sheets for that device. Many times there are hidden messages in these sheets that will make or break your design. Hence, know your devices and their limitations and use good sense when bringing them together.

Table 5-1 presents a listing of symbols, terms, and definitions for digital integrated circuits. You should study these closely in order to facilitate your interpretation of manufacturers' data sheets.

GLOSSARY TTL

TERMS AND DEFINITIONS

INTRODUCTION These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC Council of the Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical Commission (IEC) for international use.

PART

- OPERATING CONDITIONS AND CHARACTERISTICS (INCLUDING LETTER SYMBOLS)

I

Clock Frequency

Maximum

clock frequency, fmax

The highest rate

at

which the clock input of

maintaining stable transitions of logic of

output logic

level in

level at

a bistable circuit can

be driven through

its

required sequence while

the output with input conditions established that should cause changes

accordance with the specification.

Current High-level input current, l|H

The current into* an input when

a high-level voltage

is

applied to that input.

High-level output current, Ioh The current into* an output with input conditions applied

that according to the product specification will establish a

high level at the output.

input current,

Low-level

l||_

The current into* an input when

a low-level voltage

is

applied to that input.

Low-level output current, Iol The current into* an output with input conditions applied that according

low

level at

Table

to the product specification will establish a

the output.

5-1.

(Courtesy of Texas Instruments, Inc.)

Clock Skew

325

output current, IO(off The current flowing into an output with input conditions applied that according to the product specification the output switching element to be in the off state.

Off-state

Note: This parameter

cause

will

usually specified for open-collector outputs intended to drive devices other than logic circuits.

is

output current (of a three-state output), loz The current into* an output having three-state capability with input conditions applied that according to the product specification will establish the high-impedance state at the output. Off-state (high-impedance-state)

output current, los The current into* an output when that output is short-circuited to ground (or other specified potential) with input conditions applied to establish the output logic level farthest from ground potential (or other specified potential). Short-circuit

Supply current, ICC

The current into* the

Vqc

supply terminal of an integrated

circuit.

Hold Time Hold time, th

The

interval during

which

a signal

is

retained at a specified input terminal after an active transition occurs at another

specified input terminal.

NOTES:

The hold time

1

result.

the actual time between

A minimum

element 2.

is

is

value

is

specified that

two events and may be is

insufficient to accomplish the intended

the shortest interval for which correct operation of the logic

guaranteed.

The hold time may have

a

negative value in which case the

minimum

limit defines the longest interval

(between the release of data and the active transition) for which correct operation of the logic element

is

guaranteed.

Output Enable and Disable Time Output enable time

(of a three-state

output) to high

level,

tp£H

(or

low

level, tp£|_)t

The propagation delay time between the specified reference points on the input and output voltage waveforms with three-state output changing from a high-impedance (off) state to the defined high (or low) level.

the

Output enable time

(of a three-state output) to high or low level, tpzx* The propagation delay time between the specified reference points on the input and output voltage waveforms with three-state output changing from a high impedance (off) state to either of the defined active levels (high or low).

the

Output disable time (of a three-state output) from high level, tpnz (° r ow level, tp|_z)t The propagation delay time between the specified reference points on the input and output voltage waveforms with three-state output changing from the defined high (or low) level to a high-impedance (off) state.

the

'

Output disable time

(of a three-state

The propagation delay time between

output) from high or low

level,

tpxZ*

the specified reference points on the input and output voltage

waveforms with

the

three state output changing from either of the defined active levels (high or low) to a high-impedance (off) state.

Propagation Time Propagation delay time, tpQ

The time between the from one defined

specified reference points on the input and output voltage

level (high or

low) to the other defined

waveforms with the output changing

level.

Propagation delay time, low-to-high-level output, tp(_H

The time between the specified reference points on the input and output voltage waveforms with the output changing from the defined low level to the defined high level.

Table

326

5-1.

(Cont.) (Courtesy of Texas Instruments, Inc.)

Sequential Machine Fundamentals

Propagation delay time, high-to-low-level output, tpHL The time between the specified reference points on the input and output voltage waveforms with the output changing

from the defined high Pulse

level to the

defined low

level.

Width Pulse width,

The time

w

t

between specified reference points on the leading and

interval

trailing edges of the pulse

waveform.

Recovery Time Sense recovery time, tSR

The time

interval

needed to switch

a

memory from

mode

a write

to a read

mode and

to obtain valid data signals at the

OJtpUt.

Time

Release

Release time,

The time

t re | ease

interval

between the release from

a specified

input terminal of data intended to be recognized and the

occurrence of an active transition at another specified input terminal. Note:

When

specified, the interval designated "release time" falls within the setup interval

and constitutes,

in effect, a

negative hold time.

Setup Time Setup time, t su The time interval between the application of

a signal that

is

maintained

input terminal and

at a specified

a

consecutive

active transition at another specified input terminal.

NOTES:

1.

be insufficient to accomplish the setup.

A

the shortest interval for which correct operation of the logic element

is

The setup time

is

the actual time between two events and

minimum

is

specified that

value

is

may

guaranteed.

The setup time may have

2.

a negative value in

which case the minimum

(between the active transition and the application of the other logic

Transition

element

is

limit defines the longest interval

signal) for

which correct operation of the

guaranteed.

Time

Transition time, low-to-high-level,

The time between The defined

low

a

level to

a

waveform

that

is

changing from

waveform

that

is

changing from

the defined high level.

Transition time, high-to-low-level,

The time between

tjLH

specified low-level voltage and a specified high-level voltage on a

tjHL

specified high-level voltage and a specified low-level voltage on a

the defined high levei to the defined low level.

Voltage High-level input voltage,

An

V|H

input voltage within the

more

positive (less negative) of the

two ranges

of values used to represent the binary

variables.

NOTE: A minimum logic

is

specified that

the least positive value of high-level input voltage for which operation of the

element within specification limits

High-level output voltage,

The voltage

is

at

is

guaranteed.

VrjH

an output terminal with input conditions applied that according to the product specification

will

establish a high level at the output.

Table 5-1. (Cont.) (Courtesy of Texas Instruments, Inc.)

Clock Skew

327

Input clamp voltage,

V|«

An

region of relatively low differential resistance that serves to limit the input voltage swing.

input voltage

in a

Low-level input voltage, V||_

An

input voltage level within the less positive (more negative) of the

two ranges

of values used to represent the binary

variables.

NOTE: A maximum logic

is

specified that

Low-level output voltage.

The voltage establish a

level at a

Off-state output voltage, at

Vj_

a level

above the positive-going threshold voltage, Vj+.

Vo(off

an output terminal with input conditions applied that according to the product specification will cause

the output switching element to be

Note: This characteristic

On-state output voltage,

The voltage

at

is

in

the off state.

usually specified only for outputs not having internal pull-up elements.

Vo(on)

an output terminal with input conditions applied that according to the product specification

the output switching element to be

Note: This characteristic

is

level at a

the input voltage rises

in

will cause

the on state.

usually specified only for outputs not having internal pull-up elements.

Positive-going threshold voltage,

The voltage

input conditions applied that according to the product specification will

transition-operated input that causes operation of the logic element according to specification as

from

falls

guaranteed.

the output.

level at

the input voltage

is

Vol

Negative-going threshold voltage,

The voltage

the most positive value of low-level input voltage for which operation of the

an output terminal with

at

low

The voltage

is

element within specification limits

Vj+

transition-operated input that causes operation of the logic element according to specification as

from

a level

below the negative-going threshold voltage, V-r_.

Table 5-1. (Cont.) (Courtesy of Texas Instruments, Inc.)

22

SUMMARY Fundamental and practical information concerning sequential and finite-state machines has been discussed in this chapter. It is imperative that you understand these concepts, for the rest of this text is strongly dependent on your understanding of:

(1) (2) (3) (4) (5)

(6)

combination timing aspects of sequential machines; the concept of memory; the concept of control; the general model of the sequential machine; the distinction between combinational and sequential machines; propagation delay;

(7) the

binary

cell;

(8) classes of sequential (9)

machines;

Flip-Flop design;

(10) the practical aspects of

328

modern

Sequential Machine Fundamentals

Flip-Flops.

BIBLIOGRAPHY 1.

Hartmanis, J. and R. E. Stearns. Algebraic Structure Theory of Sequential Machines. Englewood Cliffs, N. J.: Prentice- Hall, 1966.

2.

Hill, Fredrick

and Petersen, Gerald R. Introduction

J.

New

Logical Design. 3.

McCluskey,

E.

Theory and

York: Wiley, 1974.

Introduction

J.

to Switching

to

the

Theory of Switching Circuits.

New

York:

McGraw-Hill, 1965. 4.

Mano, M. Morris. Computer

Logic Design. Englewood

Cliffs,

N.

J.:

Prentice-Hall,

1972. 5.

A

Mealy, G. H.

Method

for Synthesizing Sequential Circuits. Bell System Tech.

34:5 (1955), 1045-1080. 6.

Moore,

E. F. Sequential Machines: Selected Papers. Reading, Mass.:

Addison- Wesley,

1964. 7.

The

TTL Data Book for

Design Engineers, 2nd ed. Dallas

:

Texas Instruments,

Inc.,

1976. 8.

Torng, H. C.

Introduction to the Logical Design of Switching Systems. Reading, Mass.:

Addison- Wesley, 1964. 9.

10.

Wickes, William E. Logic Design with Integrated

Circuits.

New

York: Wiley, 1968.

Williams, Gerald E. Digital Technology. Chicago: Science Research Associates,

Inc.,

1977.

PROBLEMS AND EXERCISES 5-1.

In your

5-2.

The

own

XYZ

words, define a controlled system.

Elevator

Company

has need for a system that will position an elevator

Use a block diagram approach and define a closed-loop (feedback) control system that you

threshold level with the hall floor each time

and any sensors you

like,

it

stops.

believe will solve this positioning problem. 5-3.

Figure P5-1

is

a schematic of a digital circuit that employs feedback.

devices called out as (a)

Redraw

(b) Identify

together form the

memory

the

element.

the circuit. the portion of this circuit which can be considered to be the IN-

PUT/OUTPUT (c)

FLIP-FLOPS combined

Assume

transforming

logic.

Identify the portion of this circuit which can be considered to be the output

conditioning logic. 5-4.

Discuss in your strictly

combinational

input sequences 5-5.

own words how is

circuit.

provided by

a digital system utilizing feedback differs from a

Include in your discussion this

how

the past history of the

feedback.

your own words define the basic operational characteristics of a sequential machine.

(a) In

(b) (c)

What Draw

single

word

is

basic to the description of a sequential circuit?

a distinction between a sequential machine and a finite-state machine.

Problems and Exercises

329

330

Sequential Machine Fundamentals

5-6.

(a) List the

two

classed as a

essential properties that a digital system

If

you have

MENT in In your

5-8.

(a) Discuss,

shown

be

in Figure P5-2.

classified this circuit as sequential, identify the

MEMORY

ELE-

this circuit.

own words

5-7.

in order to

SEQUENTIAL CIRCUIT.

(b) Classify the circuit (c)

must have

discuss the concept of

memory

as

applies to digital circuits.

it

using timing diagrams, the operation of a binary

cell

developed around

NOR gates. (b)

Draw

(c)

Why

a distinction between a is it

unadvisable to

NAND and NOR cell.

ASSERT

both the

SET and RESET

input of any binary

cell?

(d)

5-9.

What should be ATION)?

the direct consequence of a

SET OPERATION (RESET OPER-

Using timing diagrams, analyze the switch debouncer shown in Figure 5-11.

NOR gate.

5-10.

Design and document a switch debouncer centered around a two-input

5-11.

Using timing diagrams, analyze the switch debouncers shown in Figure 5-12. Discuss any potential problems that might be caused by using these "debouncers."

5-12.

Discuss the basic difference between sequential circuits.

ASYNCHRONOUS

Classify the binary

cell.

What

SYNCHRONOUS does the CLOCK per-

and

function

form? 5-13.

Discuss the concept of the so, relate the

the 5-14.

STATE

machine introduced

of a

in Section 5-8.

In doing

concept of the past history discussed in Section 5-2 to the definition of

STATE.

Without looking back into the

text,

draw and

label the general

fully

model of a

sequential finite-state machine. 5-15.

What

5-16.

Taken

5-17.

Without looking back into the

5-18.

(a)

is

the basic difference between a

as a stand alone device,

is

MEALY

machine and a

MOORE

machine?

a Flip-Flop a synchronous or asynchronous device?

text,

draw

the general

model of a simple Flip-Flop.

Analyze the following CLOCK OSCILLATOR (Figure P5-3) using timing diagrams and determine the frequency of oscillation if the propagation delay through each INVERTER = 30 nsec.

Fig. P5-3.

(b)

5-19.

What

three basic circuit properties

Design a clock oscillator that (a)

(b) (c)

(d)

make

will oscillate at

this circuit oscillate?

50 KHz.

Use the circuit in Figure 5 -2 1(b). Use the circuit in Figure 5 -2 1(d). Use the circuit in Figure 5 -2 1(e). Use a 74C14 as the output buffer and an adjustable obtain ±20% symmetry adjustment.

resistor sufficiently large to

Problems and Exercises

5-20.

Using timing diagrams analyze the operation (a)

(b)

5-21.

The clocked RS Flip-Flop shown in Figure 5-22. The clocked D- Latch shown in Figure 5-23.

why

Discuss

the avoidance of the indeterminability of a binary cell

ingly important where clocked

5-22.

of:

By making a simple

RS

increas-

Flip-Flops are being used.

transformation, convert the

to support the following schematic

becomes

RS

Flip-Flop shown in Figure 5-22

symbol (Figure P5-4).




r

or log r

Thus

the state assignment

Chapter

problem

is

/t

.

definitely a coding problem, as outlined in

1.

The choice

of state assignment has a significant effect

on the amount of

hardware required to implement the combinational circuits associated with a sequential machine, which are the NEXT STATE and OUTPUT DECODER sections. This statement suggests that there must be at least one optimal choice for a state assignment for any given machine, but examining the processes involved indicates that an optimal or even a good assignment must be based on some predetermined criteria. The following is a list of some of the criteria commonly used.

Minimize the number of gates/packages required to implement the

(1)

NEXT STATE DECODER. Minimize the number of gates / packages required

(2)

to

implement the

OUT-

PUT DECODER. Minimize the number of gates/packages overall required to implement both the NEXT STATE and OUTPUT DECODER. Minimize the overall cost of circuit implementation by reducing engineering time, power supply requirements, and printed circuit allocation, and

(3)

(4)

so forth.

Once one assignment

is

of the

first

three criteria

is

selected, the search for

generally a very tedious process.

an optimal

state

Before taking a closer look at the

assignment problem, take a moment to develop some insight into what effects various state assignments have on the NEXT STATE DECODER and how state

hardware that the

is

by the

from a

NEXT STATE DECODER

circuit that

ABLES

actually derived

in

state assignment.

of a sequential

It

should be remembered

machine

is

a combinational

INPUT VARIABLES and the PRESENT STATE VARIgenerate the NEXT STATE CODE, which is further decoded

decodes the order to

TRUE NEXT NEXT STATE DECODER is a

logic internal to the Flip-Flops, in order to develop the

STATE. Thus

the combinational design of the

function of three factors, which are: (1) outside

world inputs;

(2) the state

assignment;

(3) the type of

Flip-Flop to be used in the machine.

can be done about the outside world inputs; they come with the problem. Therefore, a Flip-Flop must be selected and then some state assignment Little

366

Traditional

Approaches

to Sequential Analysis

and Design

prescribed to knit these three factors together in such a

manner

that a

minimal

NEXT STATE DECODER. Similarly, the OUTPUT DECODER must decode the STATE OF THE MACHINE and the INPUT VARIABLES in order to generate the OUTPUTS TO THE OUTSIDE WORLD. However, the choice of the Flip-Flop does not directly

amount

of hardware

influence

design.

its

assignment

is

required to synthesize the

As

just pointed out,

at best a two-variable

is

a multi-variable function in

the derivation of

an optimal

problem, and each of these variables

itself,

further complicating the problem.

is

state

usually

So com-

assignment problem that at present there is no general technique guaranteed to yield an optimal state assignment without some sort of TRY! However, there are some exhaustive search, implying that you CUT plicated

is

the

state

AND

—

redeeming factors such as: (1) Any arbitrary unique assignment will work it may not be optimal but it will at least work, insuring that the system's sequential performance is not strictly dependent on an optimal state assignment*; (2) There is a relatively easy technique available that gives reasonably good results,

optimal

along

results,

better than

random assignments.

Also,

computer programs

available, or at least

some

but typically results

this line, there are several

much

maybe not

algorithms, which can be used to develop state assignment computer programs.f

However, the techniques developed in articles such as these fall short of a comprehensive address of the problem of the multi-input machines that makes up a large segment of contemporary design efforts or that are at least presently far more wide-reaching in application than a machine with only one or two inputs.

To

illustrate the

complexity of the state assignment problem, consider a state

diagram with 16 states (four state variables) and four input variables from the outside world. For any given present state condition code, say (PS,), the NEXT STATE code (NS,) must be a function of PS, combined with the 16 possible input codes derived from the four input variables. In other words, for each of the 16 present states there are 16 possible NEXT STATES, implying that there are 256 possible NEXT STATES. Further, there is an almost infinite number of possible state assignments for these 256 NEXT STATES. For example, the number of possible state assignments can be derived from the following expression:

where

N = N =

number number

sv

ns

Thus

for the

of state variables (Flip-Flops) of

NEXT STATES

example with 16 7V pA

It is

We

will find in

fOne

J.

=

this

it

16!

state variables:

~ 2.09 X

10

13

were possible to try a new state assignment would take approximately 66 years to try all the if it

statement

is

not generally true, but for the time being assume

"Optimal State Assignments for Synchronous Sequential Circuits" by Harrison, and E. A. Reinhard; IEEE Trans. Computers, C-21 (1972), 1365-1373.

of these

Story, H.

Chapter 7 that

and four

=

interesting to note that

once every 100 microseconds,

*

states

is

titled:

State Reduction

it is.

J.

R.

367

and try one uses a

possible state assignments for a simple 16 state machine. Therefore, the cut

method

an optimal assignment is out of the picture even if computer. However, not all the possible state assignments specified by Eq. (2) are unique; for example, there is no real difference in two state assignment sequences if one is generated from the other by simply exchanging two columns. Therefore, the number of unique assignments is given as follows: for finding

UA = For our

16-state four-input

-1 * N™-N )\(N (2 sv)\ ns

-

problem:

UA = 4ttv 0!4! This

not a

is

realistic

5.45

X

10

10

big savings over the 16! derived from Eq.

some process must be developed

(2).

Therefore,

that will aid the designer in recognizing

what

conditions should exist to constitute a good state assignment.

MINIMIZING THE NEXT STATE Keep

in

mind

DECODER

that the design of the

NEXT STATE DECODER is a combinational

design problem to be reduced by using maps, and that minimal nontrivial combina-

MINIMIZING THE NUMBER OF REQUIRED GROUPINGS IN THE MAP AND MAXIMIZING THE SIZE OF THOSE GROUPINGS WHICH ARE REQUIRED. Though simple in concept, tional designs are in concept acheived

the general rule above

two basic

rules for

is

often particularly difficult to apply. However, there are

making

state assignments that at least in part serve the

criteria

concept stated above.

Rule

States having the

1:

by

NEXT STATES

same

for a given input condition should have

assignments which can be grouped into logically adjacent

An example

of Rule

1

is

phrase "given input condition."

shown If

in Figure 6-26.

cells in

Note

a map.

the significance of the

had not all been adjacent assignments would have been

the input branching conditions

advantage gained by logical somewhat impaired. In any case, strive to unit distance those states that identical, the

the

same next

state.

Fig. 6-26.

368

Traditional

Example of using Rule

Approaches

minimal

1.

to Sequential Analysis

and Design

all

have

Fig. 6-27.

Rule

Example of

the corollary to Rule 2.

NEXT STA TES

are the

2: States that

of a single state should have assignments which

can be grouped into logically adjacent Corollary to Rule state

should

2:

be assigned

cells in

a map. See Figure 6-27.

The assignments made logically

adjacent

to the

NEXT STATES

assignments

that

of a single

correspond

to

the

branching variable or variables. That is, select one bit or group of bits if a multi-way branch is called for, and make these bits match the code called for by the input condition on referred to

d,

For example, see Figure 6-27. as a "reduced input dependency" assignment.

This

each branch.

is

commonly

Note that the two least significant bits of the state assignments for states b, c, and e match branch input codes. As mentioned above, many have proposed state assignment techniques and

algorithms for selecting optimal or near optimal state assignments. In particular,

some have developed procedures lar

type of Flip-Flop (D, JK, T,

state

assignment

is

etc.),

selected for a

Flip-Flop? In general,

it

that give near optimal assignments for a particu-

D

bringing up an interesting point.

Flip-Flop implementation,

is it

If

good

a good

for a

JK

has been proven that assignments that are optimal for one

type are not necessarily optimal for another. Therefore, a state assignment should

be influenced by the choice of Flip-Flop. In fact, this author has found that in some cases optimum results can be achieved by mixing the type of the Flip-Flops used. However, generally speaking, the JK Flip-Flop, because of flexible operational characteristics brought about by the extra decoding logic internal to the device, has the edge over the other Flip-Flops; but this is not a hard fact. At times, a D implementation for a particular assignment results in the simplest network.

DESIGN STEPS LEADING TO NEXT STATE DECODERS The following for the

steps are given to establish a procedure for developing the

hardware

NEXT STATE DECODER.

(1)

Determine the number of Flip-Flops required for the memory element section.

(2)

Using whatever

certain that each state

on the

state

you choose, make a

criteria is

assigned a unique code. This

diagram and documented

in a

Design Steps Leading

making generally done

state assignment, is

STATE MAP. to

NEXT STATE DECODERS

369

(3)

PRESENT/NEXT STATE TABLE from the state diagram. This table will form a multi-output TRUTH-TABLE for the NEXT STATE DECODER having the PRESENT STATE and the OUTSIDE WORLD VARIABLES as its inputs and the NEXT STATE specification as its Make

a

outputs. (4)

Keeping

in

mind

that the outputs of the

direct the control inputs of the Flip-Flops,

for each Flip-Flop. This plotting

is

done

NEXT STATE DECODER plot the NEXT STATE maps

only with the

knowledge

of the

operational characteristics of the Flip-Flops used. (5)

Reduce

the

maps and formulate

the

NEXT STATE DECODER

one

output at a time.

An how

example of

this

procedure

will

be shown shortly, but before that examine

the Flip-Flop operational characteristics influence the design of the

STATE DECODER

NEXT

as outlined in Step 4.

The combination of the NEXT STATE DECODER logic and special logic added to a basic cell determines what the NEXT STATE is to be for each Flip-Flop. Therefore, you must go through the mental exercise of examining the inputs of the NEXT STATE DECODER and the EXCITATION TABLE for Flip-Flops, and from this, cause the Flip-Flops to SET or RESET on the clock pulse.

For example, to cause a state variable to change from 0 to 1 at the output of a D Flip-Flop, a 1 must be present on the D input previous to the clock pulse edge. Thus the output code for the NEXT STATE DECODER for a D Flip-Flop implementation is identical to the NEXT STATE CODE. For a JK, two outputs from the NEXT STATE DECODER are required for each Flip-Flop. Here you might tend, quite justifiably, to assume that JK implementations could lead to a more complex NEXT STATE DECODER. This is not necessarily the case. Further, once the NEXT STATE maps for a D Flip-Flop implementation are plotted, a simple procedure can be used to automatically convert them to the other NEXT STATE maps for a JK and T implementation. This makes it easy to examine very quickly the logic required for each type of Flip-Flop implementation and to make a minimal selection.

DATA SAMPLE DESIGN EXAMPLE CONTINUED:

A

random

throughout

state this

assignment

is

made

for the

example data sampling problem used

chapter (see Figure 6-28).

PRESENT/NEXT STATE TABLE shown in Figure 6-29, which multi-output TRUTH-TABLE form, the NEXT STATE maps are plotted for

Using the has a

each output just as they would normally be done for any combinational design. In doing

370

this the

NEXT STATE DECODER

Traditional

Approaches

logic for

to Sequential Analysis

a

D

Flip-Flop implementation

and Design

is

derived as an added bonus. This

D

is

a result of the operational characteristics of the

TRUE NEXT CODE must be present at the output after the Thus the NEXT STATE maps are as shown in Figure 6-30.

Flip-Flop: that the

clock edge.

STATE MAP 00

01 0

o

c

A

random

state

7

0

e

assignment for the odd number of

1

4

0

f 3

1

Fig. 6-28.

6

b

a

10

11 2

5

0

sequence detector

example.

PRESENT STATE

ABC n

n

n

NEXT

Fig.

OUTPL

STATE

INPUT

X

cn+1

OSS 0 0

000 000

0

0 0

1

0

1

0

1

001 001

0

0

1

1

1

1

1

0

4

b 010

0

1

1

0

5

010

1

0

1

1

0 0

0 0

0 0

0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

0

0 0

0 0

0 0

0 0

0

a

1

2

c

3

011 011

0

8

0 100

0

9

100

10

0 101

11

101

6

e

7

1

1

0 1

110 110

0

14

0 111

0

15

111

12 13

f

1

1

6-29.

The

STATE TABLE

PRESENT/NEXT

with state assignments

taken from Figure 6-28.

0 0 0 0 1

1

Design Steps Leading

to

NEXT STATE DECODERS

371

A n

>J

c

n

oo

01

oo

12

W

0

u

u 7

n U

J)

1

6

0

0

(A VJ

A /?++ =DA -A n B n 1

15

1

14

10

CX+BCX n

n

n

v)

2

10

9

13

5

u

8 fh V)

U

1

01

io

11

0

\A n B n

0

0

x\

cn

"oo

01

1

00

B n+\

=

=

0

+BX + BC

A n B n Cn

n

n

w

0

0

1

00

01

0

€y

14

y

Fig. 6-30.

The

0

0 =

A n Cn X +

BCX n

n

10

14

0

,=DC C n+^

1

0

0 6

0

9

15

0

0

1

0

0 13

i

3

10

0

0

1

8

12

4

0

1

0 6

10

9

0 15

7

3

(is 13

5

n

A n Bn

2

0 1

01

10

11 4

0

NEXT STATE

maps

for the

example problem.

important to keep in mind as you are plotting these maps that the NEXT VARIABLES (A n+l Bn + and C„ +1 ) are functions of the input (X) and

It is

STATE the PRESENT STATE VARIABLES ,

states are filled in with

J9*s

l

,

(A n

,

Bn and ,

C„). Also,

note that the unused

because these states never occur

if

the

machine

is

functioning properly.

From

the current example, this particular state assignment

NEXT STATE DECODER,

2 1

three-input

4

Traditional

Approaches

requires:

AND function three-input AND function two-input AND function

1

372

which

four-input

2

OR function two-input OR function

10

gates with 27 inputs

to Sequential Analysis

and Design

/

would need a

Now

applying the rules set forth

earlier,

make a

state

assignment and compare the

results.

By studying Rules

and 2 and relating them to the example problem state diagram, the state assignment shown in Figure 6-3 1 is made. This state assignment Use is derived by applying the rules and developing the following arguments. Table 6-2 to aid you in your decision. 1

STATE ASSIGNMENT MAP

\AB \

00

01 0

0

a

0

b

6

0 3

1

1

10

11 2

C

4

0 5

7

e

f

(a)

PRESENT STATE

ABC n

n

n

NEXT INPUT

STATE

OUTPUT

X

A n+1 co+1 A1 B n+^ A1

OSS

0

1

1

1

0 0

000 000

0 1

0 0

b 001 001

0

1

0

1

3

1

1

1

1

0 0

4

0 010

0

5

010

1

0 0

0 0

0 0

0 0

6

c 011

0

1

1

1

7

011

1

1

0

1

0 0

0 100 100

0

0 0

0 0

0 0

0 0

101 101

0

0 0

0 0

0 0

0

0 110 110

0

13

0 0

0 0

0 0

0 0

14

e

0

0 0

0 0

0 0

0

0

a

1

2

8

9 10

f

11

12

15

111 111

1

1

1

1

1

1

1

(b)

Fig. 6-31(a).

A

state

assignment arrived at by applying Rules

1

and

2. (b)

The

PRESENT/NEXT

STATE TABLE.

Design Steps Leading

to

NEXT STATE DECODERS

373

Rule

1:

States b

and

c both

have e and f for next states

and States e

and f both have a for a next

state.

Further: Rule

2: States

b and c both are the next states of a

and and f both are the next states of both b and c states. Special note: These rules will not always be nonconflicting, so Rule 1 should take precedence over Rule 2 if a conflict arises. However, a special requirement introduced in Chapter 7 regarding asynchronous inputs alters this precedence. States e

TABLE

Rule

6-2

Previous

State in

Next

State(s)

Question

State(s)

ej

a b

c,b

c

e,f

b,c

e

b,c

f

a a

a a

1

e,f

applies

Observe from Figure 6-32 that the new savings, that

state

Rule 2 applies

assignment results in a considerable

is:

2 1 1

4

AND functions two-input AND function three-input

two-input

OR function

gates with 10 inputs

Thus by simply applying Rules 1 and 2 good results have been achieved. Whether or not it is optimum for a D Flip-Flop implementation is hard to say for certain, because there are 138 other assignments left to try. At this point criterion 4 comes into the picture. In short, is it really necessary to carry out an exhaustive search trying to save one or two more gates? This is a judgment you will have to make for yourself. If you are building only a small number of systems, then it is recommended that you not spend expensive engineering time worrying about how to save a gate or two.

However, there are a couple of other quick checks that you can make when reducing the

might help

374

NEXT STATE DECODER

in the reduction process.

Traditional

Approaches

This

logic, to see is

if

a

JK

or a

T

Flip-Flop

the subject of the next section.

to Sequential Analysis

and Design

\A n B n

cn x\

"oo

01 4

n u

13

5

n u

9 (7)

HI

n+

15

7

2

/?

n 14

6

V

n

/4

1

1

n u

1I

10

8 Hi

3 1I

12

ft Hi

1

n1

10

11

0

10

0

0

n

cn

x\

n

00

01

1

10

1

12

0

8

i

00

0

0 13

5

0

01 n+^

B

n

n

n

n

11

w

Cn X\

10

00

01

3 1

1

10

1

2

Fig. 6-32.

610

The

0 15

=

£>

C

=4 n

0 14

6

10

0

1

Ci+1 +1

1

0

1

0

9

0 7

0

10

0 13

0

1

14

6

8

0 5

1

01

0

0

0

1

1

12

"3s

00

15

0

10

11 4

0.

9

0

0 7

3

2

\A n B n

0

0

NEXT STATE map

derived from Figure 6-31.

TRYING A JK OR T FLIP-FLOP //

was just mentioned

that once the

NEXT STATE MAPS

Flip- Flop

implementation,

it

equivalent

map for a JK

T Flip-Flop

or

is

to

convert

these

maps

to

D the

implementation. This becomes obvious once

T Flip-Flop to a D Flip-Flop and in the NEXT STATE map represent. In beginning quickly review the EXCITATION TABLE for each Flip-

you remember the conversion remember just what the entries the conversion process,

a simple process

are plotted for a

of a

JK

or

Flop and the hardware conversion of each to a D Flip-Flop as shown in Figures 6-33 and 6-34, and consider how this information leads the way to a direct JK or T Flip-Flop implementation.

Trying a

JK

or

T

Flip-Flop

375

Given

a

D

PRESENT STATE

Flip-Flop:

NEXT STATE Qn +

— +1/

Q

c 5

0 0

>c Qn +

1

D

*

0

Q D

Ft

1

0

D 0

1

1

1

0

0

1

1

1

EXCITATION TABLE (a)

Note: The D, Flip-Flop

Given

a

JK

NEXT STATE is

(Qn +

1

)

of a

identical to D.

Flip-Flop

Q PRESENT STATE

J

Qn

->

NEXT STATE Qn +

Q >

J

0

0

1

1

0 0

1

0

1

1

0 0

0

0 0

K

1

1

EXCITATION TABLE (b)

Given

a

T

Flip Flop:

x

T = Qn

Qn +

1

PRESENT STATE

D :.T=Qn X D But

Qa7

+

1

=

NEXT STATE Qa?

0 0

+

1

T

0

0

1

1

1

0

1

1

1

0

EXCITATION TABLE (c)

A

Fig. 6-33.

It

(Qn)

quick review of the excitation tables for the D,

Flip-Flops.

should be noted in Figure 6-33(b) that any time the

is 0,

time the

the

you make

K

input

is

is,

0.

You

is

a

1,

the

/ input

is

Approaches

one-half of each

map

to Sequential Analysis

for a

is,

0.

Also, any

specified as a don't care

are probably saying, "so what?" Well,

this observation,

Traditional

PRESENT STATE

specified as a don't care condition, that

PRESENT STATE

condition, that

376

JK and T

JK

and Design

it

turns out that

if

implementation can be

plotted automatically with Jds

NEXT STATE MAP illustrated shortly.

and the

plotted for a

The

table of

rest

D

can be

filled in

automatically from the

How

implementation.

works

this

hardware Flip-Flop conversions

is

shown

be

will

in Figure

6-34. Given type:

Converted to

a

D

D

Q

5

Q

S

>c

>c

D

D

R

Q

R

Q

Q

s

Q

JK

J

J

>c

>c

4>

K R

K R

Q

Q

K=D

J = D,

T= Dif Q Fig. 6-34.

Q=

1,

Hardware conversion from

T=D

and

if

Q = 0, T=D

T

and JK Flip-Flops

because the exclusive

OR

to a

= 0,

D

T=D\f Q=

Flip-Flop.

1

Remember,

if

gate can be used as a controlled

inverter.

In Figures 6-33 and 6-34 observe that the conversion from a

D

implementation to a JK implementation is one of first entering #'s in the J map wherever the state variable is 1, then making a direct transfer for the rest of the cells because JA — DA as can be seen in the conversion table.

Trying a

JK

or

T

Flip-Flop

377

To

plot the

K map from the D map, placet's in all the cells where the present

state of that state variable

equal to 0 and then

is

complement of the corresponding See Figure 6-35.

cell

of the

the rest of the cells with the

fill

D map.

This

is

done because

KA =DA

.

\AB

CX\

00

01

11 4

-0.

00

.12

8

r'6 13

1

01

—10

o

I

0

0

I

|9

*Note

0

|

15

7

3 1

1

°

I

o

B and C

map

cells for

B and

is

for

A

are similar

but the 0's are inserted

1

I

1

this translation here

variable only.

|

in

different

C.

i

1

^

2

10

1

i

14 1

10

0

0

)

Compliment

Direct transfer

because J — A .

PRESENT STATE of A = 0

PRESENT STATE of A =

DA .

1

because

KA

transfer

=

.

DA .

AB

CX\

00

^ 00

CXV_00

1

o.

^

4

1

00

0

0

(0

01 0

8

2

0

0

12

8

f0

i

1

1

T

10

01

10

11 4

5

1

0

0

0

9

13

5

01

0

0

13

1

1

I

|

—

9

0

0

|

1

1

3

|

15

7

1

3

1

15

7

1

1

1

1

0

1

1

0

11

'

0

0

1

1

|

*y

10

[

1

1

2

10

0

0

J

10

14

16

i

0

Transferring a

When

0

14

I

I

1

10 1

;'

K.

J,

Fig. 6-35.

6

D map

to J

and

D map

K

maps.

T

map, cells 0-7 in both maps are identical. This is because when the state variable, which in this case is QA =A = 0, TA —DA Further, the cells 8-15 in the T map are the complements of the entries _f or the corresponding cells in the D map. This is because when QA =A = \, TA = DA See Figure 6-36. Again, this can be verified by examining the hardware conversions transferring a

to a

.

.

shown in Figure 6-34. Thus plotting a D NEXT STATE map is very simple and that map to the JK maps or T is equally simple.

378

Traditional

Approaches

to Sequential Analysis

and Design

the conversion of

done in order to examine and compare the hardware required for each Flip-Flop type and make an optimal choice of Flip-Flops. The T Flip-Flop is This

is

discussed here because

a simple process to convert a

is

it

JK

that

is

readily

by connecting the J and K inputs together. Another interesting point about the JK Flip-Flop that arises from the J and K maps being half filled withB's is that the Boolean expressions for any given /, or K are completely independent of Q Because this is the case, both the J and K maps can be plotted from the NEXT STATE map into a single map with J entries plotted in the Q = 1 sector and the K entries in the Q = 0 sector. When reading the map for Jit assume all entries in the


T

Qd

LOAD

(11)

Fig. 6-47.

-i>

o

t>

(Courtesy of Texas Instruments, Inc.)

Multi-Mode Counters

393

SYNCHRONOUS COUNTERS-POSITIVE EDGE TRIGGERED r*oi

DAD Al

IMT

DESCRIPTION 1

1

F|

TYP TOTAL

DEVICE TYPE

POWER

AND PACKAGE

CLEAR

nAn

-55 C to 125 C SN54S162 J, W SN54LS162A J, W SN54LS160A J, W SN54162 J, W SN54160 J, W SN54S168 J, W

DISSIPATION

Set-to-9

Awnr-H

270

Sync

Sync-L

Sync

Sync-L

Sync

Async-L

Sync

Async-L

Sync

None

3

25

MHz

25

475

SN54LS168A SN54LS192 SN54192

SN54LS190 SN54190

W W J, W J, W J, W J, J,

SN54L192

mW

O

I

>J

J4 D I

/

J

J

i

,

\fj vv

MHz 25 MHz 25 MHz 25 MHz 25 MHz 40 MHz 25 MHz 25 MHz 25 MHz 20 MHz 20 MHz 3 MHz

BINARY

BINARY

DOWN

BINARY RATE MULTIPLIER,"^ ]

25

Fig. 6-48.

A

Sync

None

Sync

None

Async

Async-H

Async

Async-H

Async

None

Async

None

Async

Async-H

mW mW 93 mW 305 mW 305 mW 500 mW 100 mW 85 mW 325 mW 90 mW 325 mW 42 mW

SN74S162

SN74LS162A SN74LS160A SN74162 SN74160 SN74S168 SN74LS168A SN74LS192 SN74192

J,

N

J,

N

J,

N

J,

N

J,

N

J,

N

7-226

J,

N

7-226

J,

N

7-306

J,

N

7-306

7-190

SN74LS190

J,

N

7-296

SN74190

J,

N

7

SN74L192

J,

N

7-306

M

7

CM 7/ HA 1ID/ C7 DIM

Async-H

345

93

Sync

Sync-L

Sync

Async-L

MHz

listing of available

W SN74S163 W SN74LS163A SN54LS161A J, w SN74LS161 A SN54163 J, w SN74163 SN54161 J, w SN74161 SN54S169 J, w SN74S169 SN54LS169A w SN74LS169A SN54LS193 J, w SN74LS193 SN54193 J, w SN74193 SN54LS191 J, w SN74LS191 SN54191 w SN74191

475

1

SN54S163

J,

J,

N

SN54LS163A

J,

J,

N

J,

N

296

999

mW

SN5497

synchronous integrated

J

J,

w

N

J,

N

J,

N

7-226

J,

N

7-226

N

7-306

J,

N

7-306

J,

N

7

296

J,

N

7

296

SN74L193

J,

N

7-306

SN7497

J,

N

7-102

J,

SN54L193

J,

7-190

J,

J,

circuit counters (standard

TTL, LSTTL, Schotky TTL, and CMOS). (Courtesy of Texas Instruments,

6-15

NO.

0 C to 70 C

0

40

6-BIT

Async-H

Sync-L

20

UP

Async

Sync

20

4-BIT

None

Async-L

25

4-BIT

Async

Sync

25

!

None

Sync-L

40

N-|

Asy nc-H

Async

Sync

25

DECADE RATE MULTIPLIER,

Async

MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz

25

UP/DOWN

None Async-H

Sy nc-L

25

n pp a n p

Sync

Async

Sync

25

DECADE

mW 93 mW 93 mW 305 mW 305 mW 500 mW 100 mW 85 mW 325 mW 100 mW 325 mW 42 mW

40 MHz

PAGE

Inc.)

DESIGN OF SPECIALIZED MULTI-MODE COUNTERS The design techniques for multi-mode counters are illustrated nicely by the odd number of l's design example. However, to reinforce the concepts learned in the previous example, another design

Example

is

demonstrated.

Design a three-bit, modulo 6, unit-distance code, up-down counter with a synchronous CLEAR, one which has the same sequential code as

Example

6-10:

6-9.

This design process

It is interesting to

is

illustrated in Figure 6-49.

a case where the D Flip-Flop implementaimplement from a total gate count point of view,

note that this

tion is decisively the simplest to

is

thus refuting such sweeping statements as:

optimal than

394

Traditional

D

"JK

implementations are always more

implementations."

Approaches

to Sequential Analysis

and Design

CLEAR LSB

CLK o

up

Q. t

NEXT STATE

PRESENT STATE

INPUT

A n B n Cn

UP

000 000

0

1

1

0

b 001 001

0 1

0 0

d 010 010

0

0

1

1

5

1

1

1

0

6

c

011 011

0

0 0

0

1

1

0

100 100

0

1

1

1

0

0

0 0

0 101 101

0

11

1

0 0

0 0

0 0

12

e

110 110

0

0

1

1

1

0

0 0

0 111 111

0

0 0

0 0

0 0

0

a

1

2 3

4

7

8

f

9 10

13 14 15

1

1

0 0

0

0

0

1

1

1

(c)

Fig. 6-49.

The design

State diagram, (c)

maps,

(f)

steps leading to a three-bit,

PRESENT/NEXT STATE

modulo 6

assignment

unit-distance counter, (a) Block diagram, (b) table, (d)

The

NEXT STATE

maps,

(e)

JK

Schematic diagram.

Design of Specialized Multi-Mode Counters

395

\AB CUP\ 00

00

y 1

01

0

01

1

0

cy —

—

9

0

—

15

7

1

0

0

0

DA

10

14

6

0

0

2

0

2

10

1

0

—

3

10

11 4

0

dFiTTE\ / 3 BC(UP) + BC(UP)

=

0 =

\AB CUP\

00

01

C(B

2 gates

O

UP)

\AB CUP\

10

11

gates

{ 8 inputs 4 inputs

00

01

00

12

00

0

0

0

0

0

0 15

0

0

+ C(UP)( i9 I

0

10

ates

D c =AB(UP) +AB(\JP)

10 inputs

=

©

A(B

a

JK implementation:

\AB

CUP\ 00

00

01

y

0

3"

0

0

0

10

6 gates 14 inputs

J

3 gates 6 inputs

J

Fig.

Traditional

Approaches

0

0

649

0 1

0

0 14

6

2

9

15

7

3

11

12

0

1

01

10

11 4

0

10

0

1

/a

1

£C(UP) + £C(UP)

C(5

O

UP)

(e).

to Sequential Analysis

and Design

0

3 gates 8 inputs 2 gates

UP)

Fig. 6-49 (d).

Trying

10

14

10

0

0

1

0

11

D=A(UP)+ABC

396

0 15

1

-14

fl

0

01

11

10

0 13

13

01

10

11

12

4 inputs

\AB CUP\

00

01

11

0

1Q

4

0

8

?

1

0

1 1

13

5

0\

9

0

0

/

\

L 3

15

7

0

•J

0

= £(UP) + B(UP)

10

4

1

4

1

V?

2

0

1

0

0^|

!

=

B

®

UP

\AB CUP\

00

01 0

00

0

0

0

01

1

0

01 -15

0

1

1

0 3

0

0

5

13

7 -I

15

0

0

1

0

6 gates 1

00

00

01

1

w

00

0

0

14

0

^

10

0

0

0

1

1

V

0

14

6

0

10

0 5

^1 2

9

3

0^ 7

3

1

£; 1

^0

0

01

0

2

0

0

9

15

7

12

1

0

0

10

01 4

0 13

5

00

8

2

0

0

i

CUP\

10

11

W

0

01

10

C(UP)

4-

fi

.AB 0

11

1

1)

0

=^(UP)

/C

1

14

1

J#Q = A(UP) + C(UP)

2 inputs j J

\4£ CUP\

10

0

9

V? 6

10

8

2

0

1

0

0

1

0

13

10

11 4

0

(

0

>

I

6 gates 1 14 inputs J

3 gates

1

6 inputs

J

=

,

L

4£( UP

=

Gate

tally:

©

(UP)

)

/C

c

UP)

=

£(UP) + £(UP)

=

B

O

UP

For the unit distance code up-down counter

D implementation — 10 JK implementation — 18

Fig. 6-49 (e).

gates and 26 inputs gates and

40 inputs

(Cont.)

Design of Specialized Multi-Mode Counters

397

_)

_l

1

QQ

X

X

_l

X

X

Q_

QQ

Z>

X

_i

_i

QQ

UPI

UP(

X

_1

QQ

Z>

!

y CLK(H) +v

r

a. R D

R D \/ S C

c

Q XT

Q

Q

Q

x

Q

Q

X

x QQ

CO

QQ

Fig. 6-49 (0.

ally

Another interesting point is that using an edge-triggered Flip-Flop virtueliminates the mode change fault caused by using Flip-Flops without the

edge- triggering or data-lockout-type features. All

in

all,

a good design engineer should be able to design special

multi-mode counters

the need arises.

if

However, your

first

attempt in any

whether you could possibly use an integrated for your application (see Figure 6-48). If not, you should attempt to

given situation circuit

is

to determine

7416X or 7419X series of help you develop knowledge

design counters that are expandable, similar to the counters.

Several design exercises will be given to

in this area.

The next two found

6-16

RIPPLE

sections cover

some other types

of special counters:

some

in integrated circuit form, others requiring design effort.

COUNTERS

Ripple counters such as the one in Figure 6-50 are asynchronous counters that differ distinctly

tion stems

from the

from the

full

synchronous counters studied thus

far.

This distinc-

fact that the clock inputs of the Flip-Flops in the counting

chain of a ripple counter are not tied together.

In

fact,

the clock inputs are

cascaded from output to input. Further, note that each Flip-Flop is fed back on itself, making it a modulo 2 counter. Therefore, a ripple counter is a cascade of modulo 2 counters, each triggered by the output of the preceding stage. Hence, its

398

Traditional

Approaches

to Sequential Analysis

and Design

one closely related to the ripple sent up a piece of taut rope by applying a quick jerk to one end. Ripple counters such as the one shown in Figure 6-50 have the advantage of simplicity over synchronous counters, but are at a disadvantage in two aspects:

counting up-date process

is

(1) speed; (2)

a forced straight binary-code sequence.

OUTPUTS

A

Fig. 6-50.

Though

four-bit binary ripple counter.

the code sequence restriction

of the output update

is.

is

not a serious handicap, the rippling nature

This rippling operation reduces the

maximum

counting

frequency and aggravates the "glitching" problem related to using direct combinational decoding techniques for decoding the output code. This nasty problem is discussed further in Chapter

7.

The maximum frequency

sum

of the

constraint

maximum is

6-11: If

maximum

count to the

an eight-stage ripple

counter

Flip-Flops with worst case transition times

=

is

1

established by the

zero "roll over" point.

be

to

or 0 to completely ripple from the

designed is

the

using

maximum

Let:

the worst case ripple through period. This

a

rPd =

all

25 nsec, what

input frequency at which this counter will operate

—

is

transition time of the Flip-Flops in the counting chain. This

established at the

Example

constraint of the ripple counter

LSB

is

max time the MSB.

the

to

the worst case propagation delay for the individual

it

takes

Flip-Flops

used. n

i=

or

1

— n,T

if all t 's T

are

assumed

equal.

Ripple Counters

399

For

this

problem:

rrp =

=

(8)(25) nsec 1

•-/max

=

5

200 nsec

MHz

So in fact the same counter could be designed using the same Flip-Flops and synchronous techniques and made to operate at frequencies in excess of 25 MHz. However, this counter could be used at a significantly higher count rate if a count decoder circuit is not needed. Thus ripple counters, particularly the large modulo number counters, have a significant frequency handicap if their outputs are to be decoded.

The

modulo number of a ripple counter, in theory, is as max count number designed and asynchronously re-setting

alteration of the

simple as decoding the

or setting the Flip-Flop back to an

where the same

circuit

shown

initial state.

in Figure 6-50

is

This

is

illustrated in Figure 6-51,

altered to develop a decade

(modulo

10) ripple counter.

Fig. 6-51.

A

modulo

10 ripple counter.

The timing diagram shown

both the guaranteed transient conditions that prevail with any (synchronous or asynchronous) binary sequence counters as well as the transient reset states created by the asynchronous reset. These transient reset states further illustrate the finite possibility of only one of the Flip-Flops (A or situation can lead to

400

Traditional

some

in Figure 6-52 illustrates

C) being

reset without the other being reset,

serious problems.

Approaches

to Sequential Analysis

and Design

and

this

Reset pulse

Fig. 6-52.

The timing diagram

for the

modulo

10 ripple counter that illustrates the transient states

guaranteed by a ripple counter.

ASYNCHRONOUS COUNTERS

Description

Count

Parallel

Freq.

Load

(RIPPLE CLOCK)— N EG AT IV E- EDGE

Clear

Typ. Total

Device Type

Power

And Package

Dissipation

-55"C

Decade

4

bit

binary

Divide-by- 12

Dual decade

Dual 4-bit binary

Fig. 6-53.

3

MHz MHz MHz MHz MHz MHz MHz MHz

50 35 32 32 32 32 30

MHz MHz MHz MHz MHz MHz MHz

Yes

Low

3

MHZ

None

High

32 32

MHz MHz

None None

High High

25 25

MHz MHz

None

High High

25

MHz

50 35 32 32 32 32 30

Yes Yes

Low Low

Set-to-9

Set-to-9

High High High High

Yes

Low

Set-to-9

High

Yes Yes

Low Low

None None None None

High High High High

Set-to-9 Set-to-9

Set-to 9

None

High

TRIGGERED

mW mW mW mW mW mW mW mW 240 mW 150 mW 39 mW 39 mW 160 mW 160 mW 60 mW 20 mW 39 mW 160 mW 210 mW 225 mW 190 mW 240 150 40 40 160 160 60 20

to

125"C

W W J, W J, W J, W J, W J, W

J,

J,

J,

SN74196 SN74176 SN74LS90 SN74LS290 SN7490A SN74290 SN74LS196 N,T SN74L90

Sn54196

J,

SN54176 SN54LS90 SN54LS290 SN5490A SN54290 SN54LS196 SN54L90

J,

SN54197 SN54177 SN54LS93 SN54LS293 SN5493A SN54293 SN54LS197 SN54L93

W W J, W J, W J, W J, W J, W

SN54LS92 SN5492A SN54390 SN54490 SN54393

A list of available integrated circuit ripple counters.

OX to 70X

J, J,

J,

SN74197 SN74177 SN74LS93 SN74LS293 SN7493A SN 74293 SN74LS197 N,T SN74L93

W W J, W J, w J, w J, J,

J,

J, J, J,

J, J,

J, J,

J, J, J,

J,

J, J,

N N N N N N N N,T N N N N N N N N,T

SN74LS92 SN7492A

J,

SN 74390 SN 74490

J, J,

N N

SN 74393

J,

N

J,

N N

(Courtesy of Texas Instruments, Inc.)

Ripple Counters

401

Because of the disadvantages of ripple counters they should be used with a certain degree of caution and with a knowledge of their limitations. See Figure 6-53 for a list of available asynchronous ripple-type counters. The next section introduces a synchronous counter that exhibits several advantages over the ripple and synchronous binary sequence counters.

6-17

RING COUNTERS Ring counters (see Figure 6-57) are special purpose synchronous counters that are sometimes referred to as Johnson or Moebius counters. These sequential counters have special applications in cases where code sequences with symmetry are desired. There are basically two types of ring counters: (1)

Standard-ring

(2)

Twisted-ring

The standard-ring counter requires n Flip- Flops to derive a modulo (n + I) counter. The twisted-ring counter requires n/ 2 Flip-Flops for a modulo n counter. In most applications the ring counter is not really used for a counting function, but rather as a special sequence generator as mentioned above. First consider the four-bit standard-ring counter sequences shown in Figure 6-54. Here a sort of diagonal symmetry is generated when a 1 is shifted or rotated through the four output bits.

A B C D

or

A B C D

0 0 0 0 1 0 0 0 0 10 0 0 0 10 0 0 0 1

o 0 0 0 0 0 0 1 0 0 10 0 10 0 1 0 0 0

0000

0000

Fig. 6-54.

Two

possible sequences for

a four-bit standard-ring counter.

Consider the three-bit twisted-ring counter sequences shown in Figure 6-55. This figure shows that twisted-ring sequences are apparently generated by inverting one of the end bits (MSB or LSB) and shifting it into the other end bit on each clock pulse.

ABC

Traditional

ABC

000 0 0 110

~ ~ ~ 000

1

402

or

111

111

110 10

0 0 0

0 0 0

to Sequential Analysis

6-55.

Two

possible

three-bit

twisted-ring 6 counter sequences. M

0 0 1 0 11

0 11 0 0 1

Approaches

Fig.

0

and Design

As previously discussed

can "hang" if they are not properly designed. Noise or power-up conditions can cause the counter to be jammed to one of the unused states from which it will not return to the main counting sequence. Therefore, it is necessary to design ring counters that in the analysis section, ring counters

are self -correcting (will not hang).

method

We

do

will

this

using the traditional design

illustrating a general design technique that will

Example

avoid the anomaly.

Design a self -correcting 3-bit twisted-ring counter with the indicated counting sequence. This design is illustrated in Figure 6-56. 6-12:

ABC n = 3 and number of states =

0 0 0 (AM 0 0 (c) 1 1 0 (a)

id) (e)

1

1

2/7

= 6

AB

?

00

1

01 0

0

1

1

The designed

(0001

twisted-ring

6

4

b

C

a

0

10

11 2

sequence

0 0 0

0*

-»

unused

states

3

1

f

5

1

0*

d

e

STATE MAP (a)

\AB

\

C

00

01 0

0

1

1

0

0

DA

=

\

01 0

0

0

1

0

5

7

0*

6 1

3

0

AC + BC

10

1

2

1

0*

0

00

4 1

3

1

1

6

2

0*

L

10

1

4 1

5

7 1

0*

D B =A

(special 0*'s avoided)

AB 00

01 0

6

0*

0

0

4

0

1

3

i

10

11 2

5

7

1

1

0*

D C =B (b)

Fig. 6-56. (a)

The design

The sequence

table

steps leading to a 3-bit self -correcting twisted-ring counter,

and

state

map.

(b)

The maps.

Ring Counters

403

AB 00

01

6

2

0*

1

0 3

1

00

5

0*

6

0

0

4

0

0 3

1

0*

10

11 2

0

0

0

01 0

4

7

0

0

10

11

0

5

7

0*

1

C (special 0*'s avoided)

AB

AB

?

00

01 0

6

2

0*

0

0

JB=

10

11 6

2

0*

0

5

0

0

7

5

0*

0

1

4

0

3

1

0*

0

0

0

1

7

01 0

4

0 3

1

00

10

11

KB =A

A

AB

AB 00

01 0

0*

0

0

6

0

0 J c=

0

0 7

0*

6

7

5

0*

0

0

1

4

0

0 3

1

1

10

11 2

0

5

0*

KC =B

B Fig. 6-56 (b).

The key

01 0

4

1

3

1

00

10

11 2

(Cont.)

to designing self -correcting ring counters

is

in the

way

the 0*

grouped in one of the NEXT STATE MAPS. Generally, the MSB or A map is grouped so that the 0* entries are completely avoided; therefore, their value is forced to 0. As a result of this, if by chance one of the 0* states is induced by noise, the next state for the counter will

(unused

state) entries are

For the D implementation, observe that the mapping described above forces the 0* in the next state of cell 2 to be 001 or state /; and the next state of the 0* in cell 5 to be 010 cell 2. Thus if either 0* state is induced, the counter will always recover. It always be

may

A =0, B=0, and

C=0

take two clock cycles, but

of the six results in

it

(see the

DA map in

will recover.

For the

Figure 6-56).

JK

implementation, one

maps (J or K) must be grouped avoiding all the 0* entries. Doing so the same self-correcting operation. This is generally done by grouping

one of the maps, which will result in simpler implementation. For example, grouping KA results in a simpler implementation than grouping JA Both the D and JK implementations of the three-bit self-correcting twisted-ring counter are .

shown

404

in Figure 6-57.

Traditional

Approaches

to Sequential Analysis

and Design

Q+5v

0

5"

0 + 5i/ Q

O +5i/ Q

fCK CLEAR

7 (6)

3D

D

Q

(7)

3Q

>CK CLEAR

(11)

4D

D

Q

(10)

4Q

-d>CK CLEAR

zr (13)

5D

D

Q

(12)

5Q

CK CLEAR

6D

(14)

D

Q

(15)

6Q

-q>CK (9)

CLOCK

CLEAR (1)

CLEAR

-C^>

.

.

.

dynamic input activated by

transition

from

a high level to a

low

level.

I

Shift Registers

409

SERIAL IN-SERIAL

6-19.2

OUT REGISTERS The SISO

register

another single-mode-type

is

register,

sometimes referred to as the

"bit bucket brigade" circuit. In short, the function of a

A

move

the bits right or

typical four-bit

SISO

left

register

virtue of the design, this register

is

to present

internal Flip-Flops

across these storage elements.

shown

is

register

and then clock the

the input data to the single data input line, to sequentially

SISO

in Figure 6-61.

Note

further that

by

can function also as a serial-in-parallel-out (SIPO)

register.

CLR

CLR

SERIAL

IN Sj

CLK

SHIFT REGISTER

CLKQ^

QB

Qc

QD SERIAL OUT

—


and Pj) are used rather than standard l's and O's. However, by using map-entered variables as discussed in

Chapter

maps

3,

for

the

problem works out

both the

nicely.

See Figure 6-65 for the

NEXT STATE

D and JK implementation.

Shift Registers

411

TTL

TYPES SN54198. SN54199, SN74198, SN74199 8 BIT SHIFT REGISTERS

MSI description These 8-bit

shift registers are

other TTL,

DTL, and MSI

SN54198 SN74198

compatible with most

SMIf

one

M

minimize

typically typically Series

the

full

INPUT

°C

is

is

are characterized for operation over

temperature range of

military

74

Series

INPUT G

°M

simplify

to

transients

input clock frequency

35 megahertz and power dissipation 360 mW.

54 devices

125°C;

switching

Maximum

system design.

T

If »f*l»l INPUT M INPUT

normalized Series 54/74 load, and input clamping diodes

OR W PACKAGE OR N PACKAGE

(TOP VIEW)

logic families. All inputs

are buffered to lower the drive requirements to

... J ... J

devices

are

— 55°C

characterized

to for

operation from 0°C to 70°C. SO

These bidirectional

SMI F

T

RIGHT SCRIAl INPUT

SN54198 and SN74198

0A

INPUT

*

INPUT

Qg

want

in

a

of the features a system designer

all

shift

INPUT

Qq CLOCK GNO

registers are designed to incorpopositive logic:

rate virtually

INPUT

see function table

may

These circuits contain 87

register.

equivalent gates and feature parallel inputs, parallel outputs, right-shift and left-shift control inputs, and a direct overriding clear

line.

The

register has four distinct

modes

serial

inputs, operating-mode-

of operation, namely:

Load

Parallel (Broadside)

Qa toward Q|-|) Qh toward Qa)

Shift Right (In the direction Shift Left (In the direction

(Do nothing)

Inhibit Clock

Synchronous

SO and

parallel loading

SI, high.

The data

is

is

accomplished by applying the eight

of the clock input. During loading, serial data flow

Shift right

is

data for this

and new data

is

accomplished synchronously with the

mode is

is

Clocking of the flip-flop

inhibited

is is

and taking both mode control

inputs,

inhibited. rising

entered at the shift-right data input.

entered at the shift-left

only while the clock input

bits of data

loaded into the associated flip-flop and appears at the outputs after the positive transition

edge of the clock pulse when SO

When SO

is

low and S1

is

is

high and S1

is

low. Serial

high, data shifts left synchronously

serial input.

when both mode cont

inputs are low.

The mode controls should be changed

high. '198

FUNCTION TABLE

OUTPUTS

INPUTS

CLEAR

MODE X

L

SERIAL

CLOCK Si

so X

X

LEFT RIGHT X X X X X X H X

A

.

.

.

H

X

Qa Qb L

L

Q A0 Q B0

X

X H

X

L

H

H

t

H

L

H

t

H

L

H

t

X

H

H

L

t

H

H

H

L

t

L

X

X

QBn QCn QBn QCn

H

L

L

X

X

X

X

Qao q B0

H

H » high level (steady state). L - low level (steady X - irrelevant (any input, including transitions) t - transition

PARALLEL

from low to high

a

b

X

H

L

X

L

QA n QA n

X

X

a

.

.

.

h

Qg Qh L

L

Qgo q H0 g

n

QFn QGn QFn QGn QHn H QHn L Qgo q ho

state)

level

A thru H, respectively. Q AO' Q BO- Q GO- Q H0 " The of Q A- Q B- °-G- or Q H. respectively, before the Q^ n Qg n etc. - the level of Q^, Qg, etc., respectively, before the most-recent t

a ... h - the level of steady-state input at inputs

,

Fig. 6-62.

412

,

A

partial data sheet for the

Traditional

Approaches

74198

shift register,

indicated steady-state input conditions were established transition of the clock.

(Courtesy of Texas Instruments, Inc.)

to Sequential Analysis

and Design

D C

Mode

Q.

control inputs

la Q.

a

a

a

NEXT STATE DECODER FOR 7 F/F Theo/th

cell

1 \7 C

C J +

7 F/F

Q

1

0 7+1

F/F

Q

77

a The Jth

Fig. 6-63.

PRESENT STATE

cell

of a multi-mode shift register.

NEXT INPUTS

STATE

So

3

0 0 0 0

4

1

0 1

2

0 0 1

0 1

1

pj

0

1

5

1

6

1

1

0

7

1

1

1

6-64.

The

0 0

OPERATION

HOLD

0

SR SL

1

1

0

1

1

LOAD

0

1

0 0

Fig.

0

So

1

PRESENT/NEXT STATE TABLE

for

Qj

with

state

assignment based on the operation table shown.

Shift Registers

413

00

01 0

10

11 2

0 7

0'

(a)

Q X oo

01

0

1

00

10

11

0

0

0 1

0

1

^ =5

i

10

01

0

3

I

V

5 o Q,-i

0

/

w

5

V

0

1

/

0

1

Kj'S^Q^

^iV^Vo^-m

+S,S Q Pj +S,S Q Q J+

,

(b)

Fig. 6-65.

The NEXT STATE maps for the Jth cell of the multi-mode The J and K map for a JK implementation of a multi-mode

(a)

register, (b)

shift shift

register.

I a

a

S,(H) 3

Control

2 4-to-1

inputs

0

1

MUX

So

0 Control inputs

5 2 (H)

4-to-1

MUX

By direct

conversion

Fig. 6-66.

414

Using multiplexors to implement the Jth

Traditional

Approaches

to Sequential Analysis

cell

of a multi-mode shift register.

and Design

Because of the input-select feature of the operation of the general multi-mode shift register, a multiplexer is a natural for implementing the NEXT STATE DECODER for the Jth Flip-Flop. Thus the complete cell design for both D and

JK

6-20

Flip-Flops

is

shown

in Figure 6-66.

SHIFT REGISTER SEQUENCES The

which can be controlled to shift a 1 or 0 both left and right and has the parallel outputs available can become a very powerful, controlled sequence generator. As a result of this, shift register sequences are used extensively in the shift register

following fields:

(1)

Secure and limited-access code generations

(2)

Privacy encoding

(3)

Multiple address coding

(4)

Error correcting generators

(5)

Prescribed period and sequence generators

(6)

Random

bit generators

To understand how

a shift register can be used for

all

these varied functions,

consider the system shown in Figure 6-67.

SHIFT LEFT/RIGHT CONTROL

CLK

CLK

R SERIAL DATA

t

y

t

V

t '

v

OUTPUT CODE

Fig. 6-67.

The model

The functions (1)

Control

(2) Set

up a

FOUR-BIT SHIFT LEFT/SHIFT RIGHT REGISTER R

L

NEXT STATE DECODER

for a sequence generator using a simple four-bit register.

of the next state decoder are listed as follows:

SHIFT LEFT and SHIFT RIGHT 1

SERIAL DATA

or 0 to the appropriate

LEFT

or

control inputs.

RIGHT

input.

Shift Register

Sequences

41

OL + OR

IR

= shift

"1"

Fig. 6-68.

IL + IR

right

The "kaleidoscope"

which can be derived from a

The

state

diagram describing the different sequences

4-bit shift register.

diagram shown in Figure 6-68 is an illustration of the 256 possible sequences that can be derived from the simple model shown in Figure 6-67. From this "kaleidoscope" state diagram it is easy to spot both the twisted-ring counter sequences and the standard-ring counter sequences, as well as a whole host of other sequences, all of which are generated simply by controlling the shifting of a 1 or 0 left or right. For those interested in a further study of shift register sequences, you are referred to Shift Register Sequences by Solomon W. Golomb. Now consider how a shift register can be used to derive the twisted- and state

standard-ring counters.

6-21

RING COUNTERS USING SHIFT REGISTER Examine

the

following example to develop an understanding of shift register

counters.

416

Traditional

Approaches

to Sequential Analysis

and Design

Example

6-13:

Design a self-correcting four-bit standard-ring counter using a

74194. Given: (a)

0

0

0

0

(b)

1

0

0

(c)

0

1

0 0

0

0

1

0

0

0

0

1

0

0

0

0

w Now

Examples 6-11 and

referring to

should be locked into the

SERIAL RIGHT

6-12, note that the shift register

SHIFT RIGHT mode and

input or the control equation for

Thus

insures self -correcting operation.

\AB CD\

00

00

0

10

0

2

1

0

plotted.

1

0 14

6

is

0 15

10

0

0

in Figure E6-1

9

0

0

in the shift register

0 13

7

DA

8

0

0 3

0

12

5

that controlling only the

10

11

0 1

1

map shown

4

1

01

the

01 0

Fig. E6-1.

0

0

DA

=

A BCD

Avoiding all of the # states guarantees self-correcting operation. The implementation of the four-bit self-correcting standard-ring counter is shown in Figure 6-69.

O +5

—— T

T

CLK(H

A

B

C

v

Q+5

v

D

+ 5 i/O

Fig. 6-69.

The implementation

of a self-correcting four-bit standard-

ring counter using a 74194.

Ring Counters Using

Shift Registers

417

Of

course, the

of arbitrary length.

same technique can be used This is left as an exercise.

to derive twisted ring counters

Notice that the reason for selecting the MSB or LSB for the special map grouping is that these are the only accessible Flip-Flops. Note also that the ring counter in Figure 6-69

The next

fits

the general

model

set forth in

Figure 6-67.

section introduces similar concepts related to the control of

arrays of registers that

makes up

RAN DOM- ACCESS MEMORIES

or simply

RAM's.

SHIFT REGISTERS

6-22

As mentioned

AND MEMORY

previously, shift registers are only one of the primary building blocks

of digital computers. In fact, a digital

computer can be thought of as an ordered

array of registers, with a control unit that directs the flow of data through this

The ordered array of registers mentioned is generally considered to be classified as MEMORY. Memory, as mentioned in Chapter 5, comes in various types such as RAM's SAM's and CAM's. This section touches upon some of these devices, their relation to shift registers, and their operation. array of registers.

REGISTERS AND SAM'S

6-22.1

A

collection of

multi-mode

shift left-shift right

SISO

registers

can be tipped up on

shown in Figure 6-70 to form what is called a memory "stack." By shifting right we "push" the stack down; by shifting left we "pop" the stack. Stacks are very handy sequential addressed memories (SAM's) and are used extensively in modern computing machines. Stacks such as the one shown in Figure 6-70 are commonly called a LIFO memory, which stands for LAST IN/FIRST OUT memory. There are also FIFO's (FIRST IN/FIRST OUT), which can be fabricated from shift registers. However, FIFO's can be implemented more easily with end, as

tristate

output random-access memories (RAM's).

one shown

in Figure 6-71, are

widely used

Four-bit data

FIFO

memories, such as the

STACK MEMORIES.

in

A

r NO OP(H) SHI FT RIGHT(H

CLK(H)

Q

c

CO

Q

C

Eight-bit

Eight-bit

SL-SR SISO

SL-SR SISO

Reg

Reg

Fig.

418

Traditional

Approaches

v

SISO

Four-bit data out

for a

to Sequential Analysis

and Design

6-70.

An

registers

example of how can be configured

LIFO memory

stack.

Am2841

Distinctive Characteristics

has

Am2841A • Plug-In replacement for Fairchild 3341 • Asynchronous buffer for up to 64 four-bit words • Easily expandable to larger buffers

1

has

MHz

guaranteed data rate

1.2MHz guaranteed data

100% reliability MIL-STD-883

assurance testing

Special input circuit provides true

rate

compliance with

in

TTL

compatibility

FUNCTIONAL DESCRIPTION The Am3341/Am2841/Am2841 A

is an asynchronous first-in firstorganized as 64 four-bit words. The device accepts a four-bit parallel word Dq— D3 under control of the shift in (SI) input. Data entered into the FIFO immediately ripples through the device to the outputs Qg— Q3. Up to 64 words may be entered before any words are read from the memory. The stored words line up at the output end in the order in which they were written. A read command on the shift out input (SO) causes the next to the last word of data to move to the output and all data shifts one place down the stack. Input ready (IR) and output ready

memory

out

(OR)

stack,

signals act as

memory

full

and memory empty

flags

FIFOs

provide the necessary pulses for interconnecting

and also

to obtain

deeper stacks.

Parallel expansion to wider words only requires that rows of FIFOs be placed side by side.

Reading and writing operations are completely independent, so the device can be used as a buffer between two digital machines operating asynchronously and at widely differing clock rates. Special input circuits are provided on

MOS

inputs to pull the input signals up

all

TTL Vqh

s reached, providing true TTL compatibility without the inconvenience and extra power drain of external pull-up resistors. A detailed description of the operation is

to an

V|(-|

when

a

'

this data sheet. The Am2841 and Am2841 A ar° functionally identical to the Am3341, but are higher performance

on £ages 4 and 5 of devices.

LOGIC BLOCK DIAGRAM D0>

Qo

Dl>

0.1 4 BIT

4 BIT

4 BIT

4 BIT

REGISTER

REGISTER

REGISTER

REGISTER

62

63

0

D2 D3

> >

•0-2

ft

ft

Q

s

MR

Q

S

Q

Q

R

—

Q

S

SO

CONTROL

C63

CC2

C1 R

03

STROBE MR

STROBE

MR

s

LOGIC 0 o-l

MR

~6~

-< MR

CONNECTION DIAGRAM

ORDERING INFORMATION

Top View

C mC

V GG

Am3341 Package

Type Molded DIP Hermetic DIP Hermetic DIP

0°Cto +70°C -55°Cto +125°C

Am2841A

16

^ss

2

15

so

3

14

] OR

Order

Order

Order

Number

Number

Number

AM3341PC AM3341DC

AM2841PC AM2841DC

AM2841APC

4

13

Qo

AM2841 ADC

5

12

0,

Temperature Range 0 C to +70 C

Am2841

s,C

AM2841DM

6

8

Note: Pin

Fig. 6-71.

The data

sheet for a

64x4 FIFO memory.

1

is

°2

1

marked

in

°3

9

^] MR

for orientation.

(Courtesy of Advanced Micro Devices)

Shift Registers

and Memory

419

DESCRIPTION OF THE Am3341 FIFO OPERATION

The data

through the

falling

At the output the

The Am3341 FIFO

consists internally of

and one 64-bit control

A "1"

diagram.

four-bit data

register,

is

in

registers

the logic block

of the control register indicates that a

in a bit

word

64 four-bit data

shown

as

stored

in

the corresponding data register.

A

"0"

in a bit of the control register indicates that the corresponding data register does not contain valid data. The control

movement

register directs the

Whenever the

of data through the data registers.

bit of the control register contains a

n th

the (n+1)th bit contains

"0", then

a

a

strobe

is

"1" and

generated causing

(n+1)th data register to read the contents of the n th data simultaneously setting the (n+1)th control register register, the n th control register bit, so that the control clearing bit and the

moves with the data. In this fashion data in the data register moves down the stack of data registers toward the output as long as there are "empty" locations ahead of it. The fail through oper"1" in the ation stops when the data reaches a register n with a flag

(n+1)th control register

Data

or the

end of the

register.

loaded from the four data inputs D0-D3 by LOW-to-H IGH transition on the shift in (SI) input.

applying

a

placed

is

first

in

the

first

control register bit

control register hit simultaneously. is

returned, buffered, to the input

ready (IR) output, and this pin goes

LOW

indicating that data has

been entered into the first data register and the input is now "busy", unable to accept more data. When SI next goes LOW, the fall-through process begins (assuming that at least the second The data in the first register is copied into location is empty). the second, and the causes

IR

to go

first

HIGH,

control register bit

is

cleared.

This

indicating the inputs are available for

the

in

INITIAL CONDITION FIFO empty, SI LOW IR HIGH, word "A" on

first

(SO),

is

on SO

transition

LOW, valid.

move

to

into the

The "0"

to

memory

last

LOW

word

The the

is

the next to the

emptied by reading out

SO

all

last

to the

first

LOW, and

OR

OR

HIGH,

remains

when

Similarly,

when

the data, then

goes

when SO next goes LOW,

there

LOW

the

is

go no data will

more

until

memory

is

full

location will not shift into the second

LOW

IR will remain

instead of returning

state.

pairs of input

and output control

input of one

another, and the

OR

FIFO can

signals are designed so that

be driven by the IR output of

output of the

FIFO can

first

drive the SI

input of the second, allowing simple expansion of the

any depth. Wider buffers are formed by allowing to operate together, as

last

page.

An

over-riding

register bits

shown

(MR)

master reset

is

FIFO

parallel

used to reset (i.

e.

all

control

reset the

LOW).

all

*0

A0

A0

A0

A0

A0

Ao

A0

*1

A,

At

A|

A.1

Ai

Al

Al

A2

A2

A2

A?

A2

A?

A2

A2

A3

A3

A3

A3

A3

A3

A3

A3

80

AO

AO

AO

A0

A0

A0

AO

B|

A

*l

A

A|

Al

Al

Al

82

A2

A2

A2

A2

Aj

A2

A2

83

A3

A3

A3

A3

A3

A3

A3

1

1

LOW

SI goes

LOW

written into

80

80

BO

80

80

Bo

Bo

A0

Bl

Bl

Bl

Bl

Bi

B|

Bi

Al

82'

B?

B2

82

82

82

82

A2

83

B3

B3

83

B3

83

B3

43

(Courtesy of Advanced Micro Devices.)

to Sequential Analysis

FIFO

allowing word "B" to

and Design

to

rows of

the application on the

in

and remove the data from the output

Word "B"

Approaches

on

Data spontaneously ripple through registers to end of FIFO, causing to go HIGH. The time required for data to fall completely through the FIFO is the "Ripple-through Time".

inputs.

stage by raising SI. (A = delay) IR goes

Traditional

in

toward the output.

being read out and

is

goes

SI

SO

shifts

into the last location, so

HIGH

FIFOs

to go

the control register then "bubbles" back

in

as before, but

move

to a

OR

position and

register

last

data arrives at the output.

when

A LOW-to-HIGH

clears the last register bit, causing

toward the input as the data the

a

input signal, shift out

OR

Release data into FIFO by lowering SI. After delay, data moves to second location, and IR goes HIGH indicating input available for new data word.

420

Qq— Q3. An

is

valid

is

on the outputs may no longer be When SO goes LOW, the "0" which is now present at the

outputs.

If

indicates there

indicating that the data

register

the

output end.

at the

OR

on

control register bit allows the data

last

up

buffered and brought

used to shift the data out of the FIFO.

indicating data has been entered

Fig. 6-72.

A HIGH

is

control register bit and therefore there

last

data on the four data outputs

outputs to

another data word.

Write input into

"1"

register stacks

control register bit

out as Output Ready (OR).

data written into the

initially

is

A "1" The

bit,

last

fall

through.

Word "C" all

Co

Co

Co

CO

Co

Co

Ci

Ci

Ci

Cl

Cl

Cl

Co

C2

c2

c2

c2

c2

c2

c2

C3

C3

C3

C3

C3

C3

C3

B0

*0

Bl

*1

»3

*3

*2

written in same manner, and so on.

control bits are 1's and IR stays

8

10

When

buffer

is

full,

Read word "B"

H0

H0

H0

c-o

fo

EO

DO

CO

Hi

Hi

"I

C-1

f\

E|

Ol

Cl

H2

H2

"2

G2

r2

E

2

D2

c2

"3

«3

H3

G3

f3

E3

D3

C3

out,

word "C" moves

to output, and so on.

LOW.

H0

GO

f

0

EO

°0

c0

B0

AO

Hi

Gi

f\

El

Dl

Cl

B,

*1

11

H2

G2

F2

E2

D2

c2

B2

A2

H3

°3

F3

E3

03

C3

B3

A3

HO

H0

H0

H0

H0

H0

Ho

H1

Hi

Hi

Hi

Hi

H1

H

1

Hi

H2

H2

H2

H2

H2

H2

H3

H3

H3

H3

M

H3

H2

H3

H3

HO

3

3 READ OPERATION

FIRST

SO

goes HIGH, indicating indicating "Data Read".

"Ready

to Read".

OR

then goes

LOW

Read word "H".

"H"

"0

°0

F

0

EO

D0

DO

Co

Hi

Gi

El

El

D,

Dl

Cl

Bl

"J

G2

F2

E2

D2

D2

c2

B2

H3

G3

F3

E3

D3

D3

C3

B3

A

A

A

OR

stays

remains in output until

LOW

because FIFO is empty. falls through.

Word

new word

B0

When SO goes LOW, the "0" in the last control bit bubbles toward the memory input. OR goes HIGH as the new word arrives at the output. IR goes HIGH when "0" reaches input. Fig. 6-72.

(Cont.)

The operation

of the

AM3341 FIFO

(see Figure 6-72) taken directly

from

covered by the following description MOS/LSI data book.

is

AMD

REGISTERS AND RAM'S

6-22.2

The semiconductor Random-Access Memory commonly

referred to as a

RAM has

wide applications; however, the major usage is related to computer systems. A is a general multi-register memory system with both READ (accessing data internal to the RAM) and WRITE (loading data from the into a predefined

RAM

RAM

location)

capabilities.

MEMORIES. A

RAM

Thus RAM's is

are often

referred

is

presented to the address decoder

and the input and output data move in and out of I/O lines; and the read/write operation control

what from the actual devices operations of a

READ/ WRITE

as

functionally described in Figure 6-73.

Figure 6-73 shows that the address code

WRITE(L)/READ(H)

to

line.

Granted,

the is

memory on controlled

the

by

same

set of

a

single

somedoes depict the fundamental

this description is simplified

available; however,

it

RAM.

Shift Registers

and Memory

421

r Address input

ADDRESS DECODER


19

+ 16.

Separate I/O

Separate

1

+5,-9

2-4

Static.

Static.

Note

No. +5,-9

Static.

Static.

o o

Page

1024

1024

z

ouppiies [vj

1024

1024


80%

•

Uniform switching characteristics

•

Dual output controls

flexible

Unique Memory Status

low-power,

access memories.

interface signal levels are identical to

All

TTL

specifications,

providing good noise immunity and simplified system design.

The three-state output will drive two full TTL loads or eight low-power Schottky loads for increased fan-out, better capacitive drive and improved bus interface capability. Operational cycles are initiated

output operations

goes

• Address and data registers on-chip • Constant power drain - no large surges •

random

read/write

static,

flexibility.

Low-power -

-

performance,

high

are

They are implemented as 4096 words by 1 bit per word. The data input and output signals use separate pins for maximum

4k-bit,

HIGH. When

when

the read or write

the Chip Enable signal

is

complete, Chip Enable

LOW to prepare the memory for the next cycle. Address and Chip Select signals are latched on-chip to help simplify system timing. Output data is also latched and is available goes

signal

—improves performance

until into the

next operating cycle.

—simplifies timing

•

WE signal HIGH for LOW during the Chip Enable

The

Ml L temperature range available

100% MIL-STD-883

•

assurance testing

reliability

Status

is

is

all

read operations and

time to perform

an output signal that indicates

is

Memory

a write.

when

data

is

pulsed

valid

and

simplifies generation of CE.

These memories may be operated significant reductions in

power

on

VqC

a deselected

BLOCK DIAGRAM

chip with

as

in a

DC

standby mode for

dissipation. Data are retained '

ow

as

1

-5V.

CONNECTION DIAGRAM Top View

AO

ADDRESS BUFFERS

A1

A2

V

A3

ROW

A4

DECODER

Q

'

22

^ V CC

2

21

^] ADDRESS

C,

3

20

^ ADDRESS

1

4

19

^} ADDRESS

2

5

18

^2 ADDRESS

3

6

17

^2 ADDRESS

4

IN \2.

1

16

^2 ADDRESS

5

Q

8

15

^2 WRITE ENABLE

9

14

^} CHIP SELECT

ADDRESS

6

ADDRESS

7

|*S 0VI

STORAGE MATRIX 64 X 64

A5

AODRESS8Q ADDRESS

9

CE

ADDRESS

10

ADDRESS

1

1

Q Q Q

A6

V

ADDRESS BUFFERS

A7

A8

SENSE AMPLIFIERS

MS

DATA

DATA OUT

A9

COLUMN DECODER

A10 A

1

OUTPUT DISABLE

1

CS

CS

DATA BUFFER

-

BUFFER

WE

MEMORY STATUS P" K

13

12 OUTPUT ENABLE

OD

(GND) V ss

12

12 CHIP

|

E

NABLE

OE Dl l

Toe

Note: Pin

1

is

marked

for orientation.

ORDERING INFORMATION Ambient Package

Type

Specification

Hermetic

Access Time

Temperature

0°C

to

+70°C

DIP

-55°C

to

+125°C

400ns

300ns

250ns

200ns

AM9140ADC

AM9140BDC

AM9140CDC

AM9140DDC

AM9140EDC

AM9140ADM

AM9140BDM

AM9140CDM

500ns

Summary

425

o o

o

CJ o

in CM

>

o

q

2

r-.'

c

D

o

o oO > d CD in

E -o 3 o S -

If)

o

If)

I

Q

CD

3 "I CD TO

T3

E

TO

TO

"D

E o

—

CD CJ

E

c TO

o

CD

CD TO

3

O

13

2

^«

2

CD

CD

O

E


o

TO

>

o

o c

CD

Q.

CD

CD

C

.Q

TO

>

TO

c o

re

%0

c CD —CD c> _3 o U o c

u u

>

>

o Lf)

+

-*—

>

o LT)

+

0)

cj

*-

TO

O

o

lc

3

1/1

CD

re k. CD

CJ CD

a

a cd

TO

o

CO

TO

CD

CO

"O

>

D CO k.

3

CO CO

Q.

E

CD

E

C CD

TO k_

O

+—

E

CO

I

*-»

CD

c

O) re

CD CD

O >

3 CD >

cj CD

a

c o

sc

(/>

TO

Q.

b cj

< >

O X

(/>

3 O

CD

T3 ha

a

CD

§ o

CD

Q.

h-

(J

z


cu

"d"

CD

_C

CD

TO

CD

H

.a

3 k» CD

a

>

cd i_

TO

ne

x:

L_

C

E CD

c o

> o

-C

o -C

6

C

TO

c

c o

CJ LO

E

X
.2 —

CD L_

cc

cb

_C

>

CD




CO

CO

t>

CO

5:

<


_l LU

< < Q_

DC

a o

© S CO *-»

aJ

r-

°"0 «1

d

a o

ON

c

3

on Ufa

o on

^SANITY

|

^

ASSERT DONE CLR CNTR RST INVERT

Fig. 7-29.

488

The

ir(b)

(a)

S,,S

r

detailed flow diagram for the 2's

Introduction to Multi-Input

LOAD

complement system.

System Controller Design

CONTROLLER MOVES BACK TO STATE a SHIFTS THE 8th

CONTROLLER MOVES CONTROLLER MOVES CONTROLLER MOVES TO STATE

TO STATE

b

TO STATE d

c

AND PUTS SR HOLD MODE

BIT

IN

SYSCLK

7

BITS SHIFTED(H!

(a)

CONTROLLER MOVES BACK TO a AND 8th BIT IS SHIFTED

CONTROLLER MOVES TO STATED AND 1st BIT SHIFTS SYSCLK

2nd

3rd

STATE 5th

4th

6th

7th

(b)

Fig. 7-30.

(a) Overall

timing relations, (b) Specific timing relations related to state

d.

The Next State Decoder

489

Now

MDS

diagram shown in Figure 7-31 illustrating the adaptation of the detailed flow diagram to a state diagram structure. The flow diagram state constructs enclosed by dotted lines map directly to the states in the MDS diagram; and the action blocks serve as the root of each state, all in accordance with the concepts and illustrations set forth in Section 7-8.3. Note further the use of "conditional-outputs," all of which are conditional on the low period of the SYSCLK. This is a fairly standard technique used to minimize the

number

consider the

of states.

START DONEtl CLR CNTRU RST INVERT!! 5

= L 1

n,s0

= L

H

(CHANGE TO HOLD MODE)

"^N S^HtUo'HU J (CHANGE TO LOAD MODE)

S = L t,S 0 = H

t

1

LOAD THEN CHANGE TO SHIFT MODE! 7

7

BITS SHIFTED

BITS SHIFTED/

INCR CNTR

SET INVERT

Fig. 7-31.

The

MDS

diagram for the

2's

U

=

CLK INVERT [7 BITS SHIFTED = (BIT FLAG 1) CLK]

STATE d

H=

•

•

complement system.

summary, this is one systematic and well-defined implementation for the 2's complement system. Granted there are others, some not so general, but they will perform the function. However, the approach presented here is a structured design philosophy exemplifying the role of the system controller and In

its

relation to the other devices of the system.

Once again

it is

important that

you note the identification of each MDS diagram state in the flow diagram. Here each state starts with an ACTION BLOCK and its definition ends with the entry into another

ACTION BLOCK. The

termined for each branch in the

branching conditions are de-

MDS diagram by tracing out the decision paths

ACTION BLOCK, which defines that state, to ACTION BLOCKS including itself. This same procedure determines leading from the

all

other

the condi-

For example, see the specification for SET INVERT which is a conditional output specified for state d. Here SET INVERT is ASSERTED conditionally with 7 BITS SHIFTED and INVERT SET and BIT tional output specifications.

490

Introduction to Multi-Input

System Controller Design

FLAG =

and CLK,

1

of which can be traced through the detailed flow

all

diagram.

Now

consider one more design problem illustrating the use of the design phases (1-9). This problem requires you to interpret a set of detailed specifications

and further

illustrate the functionality of the

system controller concept.

Young

thanks to Prof. Richard Ohran of Brigham suggesting a problem such as this back in 1971. Special

Example

University for

The Pop Machine Controller

7-5:

and specifications. The El-Rip-O Vending Machine Company its Model 1909 mechanical vending machine. It is desired that a first generation digital controlled prototype system be developed for test and evaluation; nothing really fancy, just an evaluation prototype. The El-Rip-O Company has entered into an OEM (Original Equipment Manufacturers) agreement with the Futzel-Boopsdink Pipe and Die Company to provide the coin receiver, coin changer, and pop dropping systems for the new El-Rip-O Model Introduction

wishes to update

1971 system

when

it is

fully developed.

Preliminary specifications. The initial digital control system should be developed such that it will direct the control of the coin receiver, coin changer, and pop drop mechanics and provide the El-Rip-O Company with a system capable of automatically dispensing soda pop at 300 per can and making the proper change retrieval for the following coin sequences of nickels, dimes quarters,

and

half-dollars.

Prescribed operation.

Upon

the insertion of each coin, the controller

record the coin value and issue the proper change,

then drop a can of soda pop. At

this

time a solenoid

the coins collected in the coin sequence drop into a

system

is

and coins

to

if

is

to

required, in nickels only, is

to

be activated that

common

lets

collector box. This

have a coin release feature for the manual release of jammed coins

collected in "short" sequences,

intended to reset the system to an

Coin receiver

CR-1971 coin

specification.

receiver

is

initial

and the coin

release feature

is

also

condition.

The Futzel-Boopsdink Pipe and Die Model

described by the following features:

(1) single slot coin entry; (2) electronic coin detection; (3)

guaranteed coin detection for U.S. half dollars, quarters, dimes, and nickels;

(4) (5)

automatic nonvalid and bent coin rejection; all control inputs and outputs are standard TTL compatible;

mechanism and manual coin release feature; mechanical mechanism that prevents coin over-run.

(6) coin-catching (7) a special

Electrical specifications. See Figure 7-32.

The Next State Decoder

491

/

/ -H

F-B INC.

MODEL

MANUAL

id

CR- 1971

COIN DC C ACC n C LCnOL 1

— —

COIN DROP

)

COIN PRESENT

(H)

HALF-DOLLAR

(H)

QUARTER NICKEL DIME

(H)

(H)

(H)

CLEAR

(L)

/ Fig. 7-32.

Block diagram of

CR- 1971.

Signal description.

COIN DROP— an

input that

commands

collected coins into the

CLEAR — an

the

CR-1971

common

output that will go to a 5 volt

to

drop

collection box.

± 0.5

level for the

duration of the depression of the coin release.

COIN PRESENT— an

output signifying that a coin

coin

receiver

is

present in the

and denomination has been de-

termined.

HALF DOLLAR,— outputs QUARTER, DIME sent, and NICKEL

The

timing

and

COIN PRESENT, HALF-DOLLAR,

between

relationship

QUARTER, DIME,

signifying the denomination of coin pre-

NICKEL

is

described by the timing diagram shown in

Figure 7-33.

Coin changer. The Futzel-Boopsdink Pipe and Die Model CC-1971 coin changer (see Figure 7-34), developed by the Stuck- Muzzey subsidiary, features:

(1) fast, reliable,

nickel (2) special

electro-mechanical nickel-ejecting system (100 msec per

maximum);

READY

status output

which indicates when another coin

ejection sequence can be started; (3)

automatic load of 50 nickels reserve.

EJECT NICKEL — TTL

compatible input, pulse triggered with mini-

mum width of CHANGER READY — an output respond to

10

msec

status line indicating the

EJECT NICKEL.

Timing relations. See Figure 7-35.

492

Introduction to Multi-Input

restriction.

System Controller Design

changer

will

COIN ENTRY INTO SLOT Typically

300 msec

— 500 msec —

.250 msec

worst case

minimum

HALF-DOLLAR

QUARTER

NICKEL

DIME

50 msec

Typically 1

50 msec

worst case

100 msec

minimum Fig. 7-33.

Timing

detail of the

CR-1971.

EJECT NICKEL F-B INC.

MODEL CC-1971 COIN CHANGER CHANGER READY Fig. 7-34.

The block diagram

of the CC-1971.

10 msec min.

EJECT NICKEL

TO

READY typically

max Fig. 7-35.

Timing

100 msec-

of 100 nsec

detail of the

CC-1971.

The Next State Decoder

Pop-drop mechanism The Futzel-Boopsdink Model PD-1971 pop-drop mechanism developed by Bend-A-Can Division (see Figure 7-36) is a fast solenoid operated device featuring:

(1) single (2) pulse

(3) status

TTL

compatible drop

command

input;

operated with 10 msec niinimum pulse width;

READY

Timing and operation

is

line

identical to that of the coin changer. Fig. 7-36.

PD-1971.

DROP POP F-B INC.

MODEL

PD-1971

POP DROP

READY READY

The block diagram of the Note that POP DROP will

status

not if

return

the

to

the

mechanism

is

jammed.

^POP DROP READY

7-1

1

.3

SYSTEM DEVELOPMENT

be noted that the system to be designed has certain frailties related to its cheating the customer as well as the customer cheating it. However, since this First let

it

development overlooked.

and

left for

is

only an evaluation prototype, these

The specifications for a foolproof system you to work out the fine details.

frailties

can be temporarily

are given as a design exercise

Phase I. Because of your intimate knowledge of vending machines derived from the everyday encounters with these beasts (see Figure 7-37), along with the specifications given, Phase I is pretty well covered.

494

Introduction to Multi-Input

System Controller Design

Phase II. From the knowledge accounted for in Phase I, the bare-bones block diagram as shown in Figure 7-38 can be readily developed. This bare-bones block diagram is supported by the first-cut flow diagram shown in Figure 7-39. Note that this flow diagram clearly defines the proposed big picture sequential behavior of the controller operation. Now keep in mind that this proposed operation is but one of several possible alternatives. However, it was selected on the basis of the following criteria: (1) It (2)

provides a practical and effective system.

The author

(3) It also

feels that

demonstrates

it

nicely demonstrates the logical sequence of events.

how

properly designed "hard wired" systems can

have a reasonable degree of

Though

these criteria are

flexibility.

somewhat

biased, the concept of

making a

selection

from several possible alternatives should not be considered as such. It is very important that you derive several alternatives and then select one of these based on some criteria. Now these criteria can vary depending on the design requirements, but the major cornerstones should be: (1) Practicality (2) Effectiveness

(3) Efficiency (4)

Degree of

flexibility

The flexibility facet should be treated in the light of possible future applications and modifications. This is in keeping with the invariable fact that somebody will want something changed at the most inopportune time. However, don't let these anticipations completely override your preliminary preparations; just keep them in mind. For example, though there is no mention of price changes or multi-pop selection requirements in the specifications for the pop machine, these features are included with no real extra effort or cost. They are simply a natural fallout of the proposed system.

VENDING MACHINE SYSTEM

COIN

SYSTEM

POP

RECEIVER

CONTROLLER

DROP

0

c

Fig. 7-38.

The bare-bones block

diagram of the prototype vending

COIN

RETURN

machine.

The Next State Decoder

495

DETERMINE COIN VALUE AND ADD THIS VALUE TO THE ACCUMULATED SUM

RETURN ONE NICKEL AND REDUCE SUM

DROP SODA POP

AND SET ACCUMULATED SUM

Fig. 7-39.

BY

= 0

A proposed

first-cut

bi

flow diagram defining the

vending machine's basic operation.

7-1

1

.4

The

THE DETAILED FLOW DIAGRAM, FUNCTIONAL PARTITION AND MDS DIAGRAM DESCRIPTION detailed flow diagram

shown

in Figure 7-40 defines the exact sequential

behavior of the functional partition shown in Figure 7-41. It should be clear that this flow diagram is an extension to the first-cut diagram. Along with this it also defines the timing relations of the control signal to

and from the subsystems. The

functional partition typifies the system controller in

its

presiding role.

It

should be

noted that the arithmetic operations called for are carried out by the interconnec-

ADDER, PIPO REGISTER, DOWN COUNTER, and COMPARATOR. The PIPO REGISTER was added to insure the edge- triggered loading of the COUNTER. This register/counter complex is referred to as the ACCUMULAtion of the

496

Introduction to Multi-Input

System Controller Design

TOR (ACQ

in this example.

Further,

it

should be noted that a "strappable"

compare word allows for easy price changing up to 75c. The value of each coin is then encoded to the binary value of the number of nickels it represents in accordance with the indicated encoding

encoded value rising-edge of

is

(h^w^h^w,)

specification table.

This

then added to the present value of the accumulator on the

COIN PRESENT.

Thus the basic functions

called for

by the

and detailed flow diagram are brought to light with a hardware descripNote further that the IC package count is up to six packages, all with 16 pins

first-cut

tion.

or

less.

Fig. 7-40.

The

detailed flow diagram for the prototype

pop machine system

controller.

The Next State Decoder

497

wA w 3 w 2 w 50cf 25ef

104 5i

CODE CODE CODE CODE

= =

= =

1

0 0 0

0

1

1

0

1

1

0

0

1

0 0

y

0

F-B INC CC-1971

> Q

LU

QC CC LU


Q CC

Q.

o QC O Cl O

Q_

O

CL Q_

o QC Q

F-B INC PD-1971

Fig. 7-41.

498

The

functional partition of the

pop vending machine

Introduction to Multi-Input System Controller Design

control system.

The 7-42.

MDS

diagram for the system controller is shown in Figure All branching conditions and outputs are clearly specified in close accorseven-state

dance with the specification set forth in the detailed flow diagram. The branching decisions based on asynchronous inputs are properly identified and are defined by the

GO, NO-GO

decision construct discussed in Section 7-10.1

COIN PRESENT

COIN PRESENT COIN PRESENT

COIN PRESENT

Fig. 7-42. it is

7-1

1

.5

The

assumed

MDS diagram for

CLR ACC

the prototype

pop machine system

controller.

Note

that

\l causes the coins to drop.

THE HARDWARE IMPLEMENTATION OF THE NEXT STATE AND

OUTPUT DECODER Up

major effort has been directed toward the system's three D's: Definition, Description, and Documentation. Now some of the practical aspects of an actual hardware development process are presented. The first step in this development process is to make a state assignment in accordance with the rules set forth earlier, paying strict attention to asynchronous branching (see Figure 7-43). A state map (regular K-map) is used to aid the state assignment process. Here the rules related to asynchronous branching variables are given the highest priority. to this point the

The Next State Decoder

499

This priority

following state assignment constraints:

calls for the

a adjacent to b b adjacent to c

d adjacent to e f adjacent to g ABC

COIN PRESENT

COIN PRESENT

/

"T^CjCOIN PRESENT {b)

( V

001

y

CHANGER READY RETURN NICKEL

U

CHANGER READY DECR ACC

H

\AB

\

C

00

01 0

0

a

1

b

3

C

The system

controller

MDS

A

f

5

7

e

State Fig. 7-43.

6

d

0 i

10

11 2

9

Map

diagram for the prototype pop machine complete with

a state assignment and state map.

The in

rest of the states are assigned

Chapter 6 and the

list

in

Table

with some reference to the simple rules set forth 7-1.

However, no exhaustive attempt

optimize the state assignment.

500

Introduction to Multi-Input

System Controller Design

is

made

to

TABLE

7-1

State assignment listing

Previous

State in

Next

Assignment

States

Question

State

Suggestions

a,ce n o h* a,

a*

b

A* D

D,C

aADJb*; a,c,eADJ L — A T"\ IL* oAUJc*; aADJb*

a d

b

f

.

U AUJ

U,u,J r\UJ

,

cADJ^

c,d

d*

e

t/ADJe*;

d

e

a

cj

I*

g

f

g

c

NR; ^ADJe* /ADJg*; cADJ/ NR /ADJg*

must assignment;

7-12

* t""\ T

NR^NO

C

;

Requirement

NEXT STATE DECODER MAPS Once a state assignment is made, the next design step determines the first commitment to any specific type of hardware. This example demonstrates the

real

ease

with which small sequential machines can be implemented at the SSI gate and

knowing well that other alternatives do exist. This ease is brought about in part by taking advantage of the inherent application of the VARIABLEENTERED MAP. Using VEM's bypasses the tedious detail of filling out a PRESENT/NEXT STATE TABLE by going directly from the MDS diagram to the NEXT STATE maps. The plotting of the VEM's is a simple process. However, it does require a properly documented MDS diagram and some ability to recognize, by Flip-Flop

level,

inspection, the

CONDITIONAL SET OPERATIONS

diagram. This process

is

called for in this

MDS

described in the following paragraph.

Next State

Map

Plotting Process

Using a MDS diagram with a state assignment, select a state, then examine the branching mnemonics to all NEXT STATES of the selected state; and enter into the STATE CELL of the NEXT STATE MAP the Boolean expression that defines all of the SET CONDITIONS (0^1, 1^1) that are required for the chosen state variable in that state.

PRESSIONS become NEXT STATE MAPS. This process

is

CONDITIONAL SET EXMAP ENTERED VARIABLES in the Thus these

repeated for each

the

NEXT STATE

the

D-maps from which JK and T maps can be

maps

STATE until NEXT STATE maps are

STATE VARIABLE

are completed.

Remember,

the

of each

readily obtained.

processes are clearly demonstrated in Figures 7-44 and 7-45. attention to the entry in state cell c in the

DA

(= +

map. Here you

The described Pay particular

see:

» Next State Decoder Maps

501

which indicates that the

A

Flip-Flop

is

by the next clock edge

set

if

the

machine

is

STATE c AND ( = ) OR (>) are ASSERTED. The rest of the MEV ENTRIES are obvious. However, it is recommended that a map be generated for

in:

each Flip-Flop and these maps be plotted in state

parallel,

one

map as a reference for the state cell location. From Figures 7-44 and 7-45 notice that the JK

state at a time, using the

does yield a circuit im-

plementation requiring fewer gates (11 gates or four IC packages). Thus the new grand total for the system equals nine IC packages, some with spare gates, which really isn't too

bad considering the

design for the

OUTPUT DECODER

capabilities of the overall system.

must be completed.

00

01

6

2

0

0

=

1

3

5

7

=+>

DA

4

1

1

0

10

11

0

0

AB(=+

0

» +AC

\AB

\

C

00

01

6

2

0

0

0

3

1

=

4

1

7

CP

DR

10

11

0

5

0

ABM

1

+ BC(CP) + BC +

ABC

\AB

\

C

00

01 0

CP

=

7

0

5

0

1

AB{C?) + £C(PDR) +

/WCR) + BC

CP = COIN PRESENT

Legend:

=+>=

(I = 30cf)

CR PDR

CHANGER READY POP DROP READY

Fig. 7-44.

= =

The

+

(2

NEXT STATE

prototype pop machine system

502

4

CR

PDR 3

1

Dc

6

0 1

10

11 2

Introduction to Multi-Input

>30«0

or

D

maps

controller.

System Controller Design

for the

However, the

AB

4/5

00

01 0

0

0

1

0

6

2

0 3

0

0

0

0

1

0

7

= +>

10

11 6

2

0

0

0

1

4

0 5

7

i

0

»

JA = B[ = 4

1

K A =C

AB

AB 00

01 0

6

0

CP

0

0

0

JB = C(CP) +

6

0 3

i

1

4

0 5

7

0

1

10

11 2

0

7

0

01 0

4

0

0 3

1

00

10

11 2

0

0

1

K g =C( = +AC

AC

)

AB

AB 00

01 0

PDR 3

i

4 (CP)

4-

0

The

CR

0

0 5

0

1

1

1

1

0

6

3

4

0

0

1

0

11 2

0

7 1

1

5

0

KC =B

£(PDR) +4£(CR)

Requires

Fig. 7-45.

01 0

4

7

0

0

Jc =

6

0

00

10

11 2

CP

7-13

01 0

4

0

1

00

10

11

gates, or four IC

NEXT STATE DECODER

packages with spare gates.

maps

for a

JK

implementation.

THE OUTPUT DECODER The design

OUTPUT DECODER

any other combination decoder design problem that can be summed up quickly by the following process: of the

Make up

a

map

is

like

for each output. Plot the

conditional variables, then simplify

map

using

MEV for the

and implement.

However, many times maps serve no useful purpose. For example,

in the present

system controller there is no output that is a function of more than one (1) state. This information can be quickly gleaned from inspecting the MDS diagram.

recommended that you make up a simple nothing more than a list of every required output and

Therefore, in cases such as these,

output

list.

This output

list is

it

is

The Output Decoder

503

the states

the

MDS

and conditions diagram

related to the generation of these outputs.

in Figure 7-43

would have the following

RETURN NICKEL DECR ACC DROP POP CLR ACC From

this

expression

list

For example,

list:

= ABC = ABC = ABC

= ABC

observe that none can be further simplified. There-

(AND function) with the inputs PRESENT STATE VARIABLES (ABC). However, the ever

each requires a simple three-input gate

fore,

connected to the

present glitch problem exists because of our state assignment. 1 1

1—>000 introduces

is

which three

are vulnerable

transition

from

the possibility of a glitch in three states. But the real question

states.

when

Previous studies indicate that

the

1 1 1

—>000

transition

is

all six

of the remaining states

made. Therefore, some

prevention must be introduced. In cases with a smaller

(two in

The

number

sort of glitch

of bits changing

can be traced in a state map for easy problems. However, the 111^000 transition over-

this case), the possible transitions

identification of possible glitch rides the

need for any further

glitch studies.

Since there are no outputs which must remain

ASSERTED

over several

an OUTPUT HOLDING REGISTER would appear to be an overkill. However, DROP POP and RETURN NICKEL generated in states D and F must be held stable all during these states. Therefore, a holding register is probably called for. Therefore, four three-input gates (74LS10) are chosen for the output decoder and a 74LS175 is chosen as the OUTPUT HOLDING REGISTER. For the completed schematic of the total system controller including the OUTPUT DECODER, see Figure 7-46. From this figure observe that the grand total IC package count is 14, all of which are standard or established 14 or 16 pin IC's (see parts list in Table 7-2). states,

NAND

TABLE

7-2

Quantity 1

1

2

2 1

2 2 1

*1

Parts List

Number

Description

74LS283 74LS193 74LS175 74LS112 74LS85 74LS32 74LS10 74LS08 7404

Four-bit adder

1

74LS00 14

Hex up/down counter Quad D PIPO Dual edge-triggered JK Flip-Flop Four-bit comparator

Quad

of two-input

OR

NAND Quad of two-input AND

Triple three-input

Hex

of inverters

Quad

of two-input

NAND

*The standard 7404 was chosen because of the high drive requirement of the clock input on the 74LS112 (four std LS loads per input)

504

Introduction to Multi-Input

System Controller Design

o 00

o A

CO

CO

>

QQ

CO

0

oooo oow oooo

fooootoi tooo ittt tooo tut oito tan tooo I too 0100 1 1 to toio oooo soot list

OOOO 0900 0009 0000 0009 0009 0999 OOOO OOOO 0090 0099 oooo tOOO 0900 9999 4999

1000 1009 otot 0001 1910 0101 OOtO lOtl tut not otto otot OOtO 1091 tilt 0101

noi

>

1101 Otll Olll

1011 HOI 0010 0100 ton out tut out ittt not

mo

•

qsypj- 'mm 0 0 0 0 0

§e eee

-zmim-j*>

-

,

Fig. 7-48.

lOOJC STATE ANALV7tfl

If

e^'r

»-

f f f

t»|

la

Several commercial

sequential logic analyzers.

Control

and Display

509

one of your first considerations should be: "How am I going to check this system, and more importantly, how can I design the system such that check-out can be carried out easily?"

in fact,

7-17

CONCEPTS RELATED TO THE USE OF CONDITIONAL OUTPUTS Up to this point little has been said TIONAL OUTPUTS. However, it

regarding the application and use of

CONDI-

has been mentioned that conditional outputs

are those generated with an input dependency. Further,

it

was pointed out

that this

dependency should not be related to any asynchronous variable, but nothing has been said related to the advantages or disadvantages of conditional outputs. Thus an illustrative example, given shortly, utilizes the conditional output to an apparent advantage. The apparent advantage stems from the fact that using conditional outputs allows the designer to implement this example design using a seven state machine. On the other hand, had a strict Moore machine been used utilizing "immediate outputs," 13 states would have been required to implement the same algorithm. The crux of the question is: "Did the six states saved really constitute a significant savings in the overall hardware costs? Or was a trade-off made beween NEXT STATE DECODER hardware and OUTPUT DECODER hardware?" Instinctively a state reduction seems to result in an overall hardware reduction in NEXT STATE DECODER hardware, and this is reasonably true, but not absolutely true in every case. There are cases when the addition of an extra state variable allows for a more optimal state assignment that ultimately results in a more minimal NEXT STATE DECODER, even though an extra Flip-Flop is used. However, adding an extra state variable generally increases the complexity of the OUTPUT DECODER hardware because of the extra bit added. This same sort of increased complexity

is

prevalent

when

CONDITIONAL OUTPUTS

because each requires extra decoding. Thus general statement as to which

CONDITIONAL OUTPUTS

is

it

is

difficult to

best. Therefore, the

are used

when

make

are defined

a completely

philosophy adopted

their use points to

is

that

one of the follow-

ing advantages or conditions:

(1)

When an

output

is

most

definitely

dependent on a synchronous input;

can be saved without significantly increasing logic complexity; the system's clarity, speed, or power is enhanced.

(2) If states (3) If

Otherwise, use

IMMEDIATE OUTPUTS.

Thus you have a mixed system and, if both worlds. The following example is offered to help

done properly, the best of you further your understanding of the application of CONDITIONAL OUTPUT and you will be asked to carry out some detailed studies related to this problem. STUDY IT CAREFULLY.

510

Introduction to Multi-Input

System Controller Design

Example

7-6:

After the

The Pop Machine initial

Revisited

evaluation of the prototype

pop machine control systems,

some modifications should be made in the COIN RECEIVER, CHANGER, and POP DROP as well as the sequential behavior of the system controller. These modifications would enhance the customer relations and

it

was

felt

that

system acceptability.

The

prevailing philosophy

to develop a system that is to give the pop-buying customer the best possible treatment under system failure conditions (jammed pop or coin mechanisms), yet protect the interest of the vending machine company. In short, this system has the following specifications:

(1)

The system should return the customer's money if the pop drop becomes jammed during a transaction, then proceed to an OUT OF

ORDER (2)

(3)

is

condition.

The system should allow no coins to enter the machine if the machine is out of pop or in process of a transaction. If the coin changer jams or runs low on returnable coins, the system is go into a USE CORRECT CHANGE ONLY mode of operation but remain operational until the system restores itself or an attendant brings the system back. to

customer has more money in the machine than necessary and the coin changer jams, the system should revert to the USE COR-

(4) If the

RECT CHANGE ONLY mode

and attempt

to give the

customer a

pop drop jams under this condition, the system is to revert to an OUT OF ORDER mode, at which time the customer is obliged to contact the vending machine owner for a refund. Under this condition the system should "load" and hold all registers constant so the attendant can determine exactly what he owes the customer.

pop.

If

the

These modifications require only a These are: (1)

(2)

A

slight

change

in the functional partition.

compare value (0) (CK=0) such that the csutomer's money can be returned if the pop drop is jammed. (Use a Flip-Flop driving open collector gate to clamp the compare value. Maybe a cleaner approach would be to use a four- wide 2-to-l

means

of clamping

MUX(74LS157).) A means of storing

the

Flip-Flop that can be

and

storing

USE CORRECT CHANGE MODE. Another RESET by the coin changer and SET by the

system controller. (3)

A means of driving the OUT OF ORDER light and USE CORRECT CHANGE ONLY light.

The following modifications it to the FP Model 1971 -A: (1)

are to be

The manual coin release and made available only

made on

lever

is

to

the

COIN RECEIVER

updating

be removed from customer access

to the attendant.

Concepts Related

to the

Use of Conditional Outputs

511

LEGEND

OUT OF COINS COIN RECEIVER

COMPARISON VALUE COIN CHANGER POP DROP

CONDI" riONAL "OU' r of

ORD ER" id)

DROP POP

CONDITIONAL

CONDITIONAL

USE CORRECT

DEC ACC

CHANGE ONLY

1 CONDITIONAL SET CV

CONDITIONAL

CONDITIONAL

CLR ACC DROP COIN

"OUT OF POP"

Fig. 7-49.

outputs.

512

The

=

0

0

detailed flow diagram for the minimal cheat system controller utilizing conditional

COIN PRESENT

COIN PRESENT (CV = 0)[Z = CV + (I

> CVMUCCO)]

LEGEND

ooc

=

OUT OF COINS

CR CV ucco

=

COIN RECEIVER COMPARISION VALUE

=

cc PD

=

OOP LOOP

-

=

=

Fig. 7-50.

USE CORRECT CHANGE ONLY COIN CHANGER POP DROP OUT OF POP LIGHT OUT OF POP The minimal cheat system

controller

MDS

diagram

Concepts Related

utilizing conditional outputs.

to the

Use of Conditional Outputs

513

A

(2)

special input

DISABLE

ENABLE

CR(L)

the coin receiver.

coins to the coin return

all

If

to

is

be added that

will

ENABLE or

disabled, the coin receiver will reject

slot.

Both the Model CC-1971 coin change and the Model PD-1971 pop drop have been updated to the A models. The update on the CC-1971 -A provides the system controller with three signals (CC READY(H), CC JAM(H) and OUT OF COINS(L)). These internal modes now allow the system controller to ,

ascertain the status of the changer. exclusive,

will

the

If

become

and

CC JAM

are mutually

that the changer will return with one or the other after being

meaning

stimulated.

CC READY

number

of nickels left

ASSERTED

until

more

is


010 at a 1 KHz rate, then stop and wait for the EXECUTE input to be ASSERTED (EX(H)) at which time it will reset to Oil and sequence at a 100 Hz rate from 011^100^101 and stop and wait for the FIN(L) input at which time it will sequence from 101—>1 1 1—»1 10—>000 at a 10 Hz rate and stop, waiting to START the next round of sequence. 7-4.

Design a square wave duty cycle discriminator system controlled by a system controller. This system is to measure the time difference between the alternate low

and high portions of a low frequency quasi square wave are to carry out

516

all

signal (0.1 to 100 Hz).

steps for this design, including documentation.

Introduction to Multi-Input

System Controller Design

You can

You

expect a

variation in duty cycle of

up

to

± 90%.

In other words, the ratio of Hightime /Low-

time can vary from 9/1 to 1/9. Your system is to be controlled by four signals generated by switches START(L), X(H), 7(H), RESET(L). The operation is to be as follows:

RESET(L): initializes START(L): system is

the system to

remain in the

initial state until

START

is

received.

Onprntinvi Tiwip Hiffprpncp wipnvurp-

X

Y

merits should be accurate to

±0.1

msec dKc one umerence idicn cuspiay

i

0

0

and return IVLUi 11 till VI

for

1

and wait TTttll

oniy

mgn

portion

oi

waveform Latch Display and turn to initial state and wait

for

ivicaauic

0

tn IV' initial J lu L^lilillUl staff

START. re-

START. Measure only low portion of waveform latch display and return to initial state and wait for

0

1

START. Continuously update display with 1

1

difference measure.

Develop a

Hint:

troller control the

stable oscillator (crystal controlled),

and have your system con-

cascade of pre-setable modulo 10 up/ down counters that directly

drive seven segment (displays) (TIL 308) for direct readout of the time difference.

See Texas Instruments optoelectronics data book for data related to the TIL 308 display. 7-5.

l's

and

O's catching

problem when using up / down counters.

Carry out all design steps necessary to design a first-cut flow diagram and barebones block diagram for an interface between an eight-bit microcomputer system

and a 7.6.

Watch

twelve-bit

A/D

as

shown

in Figure P7-1.

Carry out the necessary steps to design a first-cut flow diagram (fundamental algorithm) and bare-bones block diagram for a controller and system that will two four-bit unsigned binary numbers (B 3 B 2 B B 0 and A 3A 2 A A^) which are stored in two separate four-bit PIPO's. You are given one single-bit full-adder (see Figure 4-6) and the results of the addition are to be stored in a five-bit SIPO. Your system should RESET itself upon power-up and is to initiate its operation when it receives the START(L) signal (asynchronous input) which indicates both four-bit PIPO's are loaded. Upon completion of the serial addition your system is to issue ANSRDY(L)

ADD

l

and hold 7-7.

this

condition until the next

X

START(L) command.

Carry out the necessary design steps to design a first-cut flow diagram and barebones block diagram for a system that will perform a binary to NBCD conversion using the Shift and six (0110) if the present four binary bits comprise a number greater than 1001 (9). Your system should be designed such that it will

ADD

facilitate

a twelve-bit binary to

START(H) the binary

NBCD

(asynchronous) and signal

number

to

be converted

is

its

conversion initiating

completion with

stored in

PISO

control the serial shift operation of this register.

operation with

BCDRDY(L). Assume

register.

(Hint:

its

Assume Start

that

by

you can

shifting in

Problems and Exercises

517

Examine these to determine if value > 1001. If SN74283) and store and pass the carry, and repeat until

four-bits.

it

is,

the

add 0110

BCD

(use

equivalent

an is

stored in four-bit PIPO's.) 7-8.

Refer back to Problem 7-1. Then carry out the design steps necessary to design the functional partition and detailed flow diagram.

Include timing diagrams

if

neces-

sary. 7-9.

Refer back to Problem 7-2. Then carry out the design steps necessary to design the functional partition

and detailed flow diagram. Include timing diagrams

if

neces-

sary.

7-10.

Refer back to Problem 7-3. Then carry out the design steps necessary to design the functional partition and detailed flow diagram.

Include timing diagrams

if

neces-

sary.

7-11.

Refer back to Problem 7-4. Then carry out the design steps necessary to design the functional partition and detailed flow diagram.

Include timing diagrams

if

sary. Eight-bit input bus

(TRI-STATE)

Eight-bit

micro

computer system

DATA READY DATA RECEIVED RUN

MODE

INTERFACE

SYS

CONTROLLER

CLK

EOC

SOC

Twelve-bit

A/D

A/D

CLK

LEGEND: Run:

An

input from a panel switch that controls the start and

stop of data transfers.

Mode: An input from a panel switch that controls the input word format. If mode is high only the eirght least significant bits are sent

most

in. If

mode

is

low, the four

significant bits are sent in first, followed

by the

eight least significant bits.

SOC: EOC:

command

Is

the

Is

the signal back from the

to start a conversion.

A/D

indicating a conversion

is

complete.

DATAREADY:

Is

the signal that notifies the micro computer

system that data

is

READY to

be put on the input bus

(TRI-STATE).

DATARECEIVED:

the signal from the micro computer indicating in (proceed). All systems operate on different CLOCKS. Is

that data has been read

Note: Fig. P7-1.

518

Introduction to Multi-Input

System Controller Design

neces-

Q

Conditional

RESET

^

Conditional

BUSY

SOC

(e)

YES

3

EOC

NO

(f)

Conditional

BUSY Conditional

Conditional

GATE LSB

GATE MSB

YES

Fig.

P7-2.

Problems and Exercises

519

\b)

AVAIL YES

Conditional

SET

MODE

=01

Conditional

SET MODE = 10

Conditional

Conditional

SET MODE

SET MODE

=

00

id)

CLR RDY

Fig.

520

P

=

1

GATE (c) CLK

7-3.

Introduction to Multi-Input

System Controller Design

7-12.

Refer back to Problem 7-5. Then carry out the design steps necessary to design the functional partition and detailed flow diagram. Include timing diagrams if necessary.

7-13.

Refer back to Problem 7-6. Then carry out the design steps necessary to design the functional partition

and detailed flow diagram. Include timing diagrams

neces-

if

sary.

7-14.

Refer back to Problem 7-7. Then carry out the design steps necessary to design the functional partition

and detailed flow diagram. Include timing diagrams

neces-

if

sary.

7-15.

Given the detailed flow diagram shown in Figure P7-2, develop the Make certain that the MDS diagram is fully documented.

7-16.

Repeat Problem 7-15 for the flow diagram shown

7-17.

Refer back to Problem

diagram 7-18.

to the

to the

to the

to the

to the

to the

(a)

(c)

to the

Make

(b) Plot

MDS

diagram.

MDS

diagram.

MDS

diagram.

MDS

diagram.

(d)

MDS

diagram.

a state assignment for the state diagram shown in Figure 7-31.

and reduce

the next state

maps using MEV's,

thus deriving the next state

decoder logic for a D Flip-Flop implementation. Convert the next state map to JK maps. Reduce and compare with obtained in

7-25.

diagram.

Refer back to Problem 7-14, then carry out the conversion of the detailed flow

diagram 7-24.

then carry out the conversion of the detailed flow

Refer back to Problem 7-13, then carry out the conversion of the detailed flow

diagram 7-23.

7-9,

Refer back to Problem 7-12, then carry out the conversion of the detailed flow

diagram 7-22.

then carry out the conversion of the detailed flow

Refer back to Problem 7-11, then carry out the conversion of the detailed flow

diagram 7-21.

in Figure P7-3.

Refer back to Problem 7-10, then carry out the conversion of the detailed flow

diagram 7-20.

MDS

diagram.

diagram.

Refer back to Problem

diagram 7-19.

MDS

7-8,

MDS

results

(b).

Complete the system shown

in Figure 7-28.

The following problem does not necessarily illustrate the system controller concept which is presently being stressed. However, it is inserted here to illustrate the use of flow and diagrams for conventional sequential designs: It is intended that this problem will give you a sufficient start in using technique for sequential circuit design when the

MDS

MEV

circuit

has more than one input variable. Further,

the information related to (a)

Design the flow and

MEV's and sequential

intended that you be familiar with

design set forth in Section 7-12.

MDS diagram for the sequential system defined as:

X(L)

A

NPUTS Y(L)

it is

Your

g

/4(H)

B(H) >

OUTPUTS

Circuit

C

C(H)

SYSCLK(H) )>CLK Problems and Exercises

521

X

and Y are asynchronous inputs that control outputs A, B, and C according to the following table: Inputs

the output sequence

on

Seq Control

X

Y

ABC Sequence*

0 0

0

Stays in state 0

1

1

0

1

1

^0-*l-^2-»3^4^5

~y

^0^1^-3^-5^-7-^

*The decimal digits represent the minterm number represented by the outputs.

That the only time the circuit is to check for SEQ control changes is in state 0. Make an appropriate state assignment for your state diagram and develop the next state maps using MEV technique. Then develop the JK maps.

Note: (b)

7-26.

Figures P7-4 through P7-10 are typical

MDS

diagrams derived for a variety of

controller applications.

For each of these MDS diagrams, make a state assignment and plot and reduce the next state maps. Convert these maps to JK maps, then plot and reduce the output maps for each of the MDS diagrams. Exercise:

(a)

Figure P7-4.

(b) Figure P7-5. (c)

Figure P7-6.

(d) Figure P7-7. (e)

Figure P7-8.

(f)

Figure P7-9.

(g)

Figure P7-10.

DAT RDY

RSTDTRD U LDANG ENBCNT U t

Fig.

522

P

I

7-4.

Introduction to Multi-Input

System Controller Design

ADR ER tl = ADR EN

STi

•

Fig.

DR ACK OT

P

7-5.

tl

Problems and Exercises

523

524

Introduction to Multi-Input

System Controller Design

ABX

Fig.

P

7-10.

Problems and Exercises

525

7-27.

Refer to Problem 6-44, then consider the two state diagrams shown in Figure P7-1 1. Notice that the input for one machine is defined as the output of the other machine

which we have defined as a "Handshake." Further, note that the state variables of these two machines are to drive the seven segment display. Explain the operation of these "linked" machines as a seven segment drive.

and

Fig.

vice versa,

P

7-11.

Note: The following "idea "problems are system level design problems

—

the ones requiring

Endeavor to make your designs as complete as the same time keep your documentation neat and up to date.

the aforementioned negotiation.

possible 7-28.

with

handle all

traffic

traffic light controller,

flow at high rates in any of four directions. Associate a

one that left

turn

four directions as well as a pedestrian crosswalk switch.

Carry out the steps necessary to design a system controller that controls the elevator for a seven-story building. Be as sophisticated as you like, but keep your system clean and straightforward. Basically what your controller is to do is respond to floor call

526

at

Carry out the steps necessary to design a four-way will

7-29.

and

switches and in-car floor select switches and determining where to go next.

Introduction to Multi-Input

System Controller Design

7-30.

You

are to design a special purpose sub-system to a larger system.

your system is

is

two binary numbers and

to accept

The purpose

of

Number

A

deliver their product.

Number B is delivered to number B (number of bits) is

delivered to your system parallel form, four bits wide.

your system

Your system

variable.

LSB

in serial form, is

the length of

first;

produce the product in serial form. to your system the signal PARLDA(H), which

to

The major system delivers that the four-bit number A is

available

on a

states

Four to ten clock periods SERLDB(H), which states that the serial four-bit bus.

major system delivers the signal data B will be available on the next clock period. Simultaneously with the final serial data bit, the major system delivers the signal SEREND(H), which states that later, the

the final serial data bit

is

now

your system should

being transmitted.

The

If

the sequence of these signals

is

from the major controller have exactly the same period as the clock for your system. However, their phase relationship to the clock is unknown and variable. Thus, all signals from the major controller must be assumed asynchronous. The parallel data A will be valid on the bus from the time PARLDA is asserted until after SERLDB is deasserted. in error,

7-31.

reset.

signals

Carry out the necessary steps to design a special controller and system that is to control the drive circuit for a stepping motor. This controller is to receive a 16-bit word from a computer bus when it sees SDSEL(L) and RDS(L) ASSERTED. The 16-bit

word

is

to

be broken into two segments as shown in Figure P7-12.

14

15

Mode

0

1

>

>

v

bit 1

These 14

'

number

Direction bit 1

=

0 = Fig.

If

the

P

CCW rot CW rot 7-12.

mode

bit

=

motor continuously then stop for

1

,

the system controller

in the

0.1 sec,

mode

bit

= 0,

is

to step (at 100 step/sec) the stepping

CCW direction until a mechanical limit switch

is

activated

then start stepping the motor at a 100 step/sec rate in the

direction until the exact the

bits carry the

of steps to be taken

number

of steps specified

the system controller

is

by the

CW

least significant 14 bits.

to step the stepping

motor from

its

If

present

position in the direction specified by the direction bit until either limit switch has

been reached or the step number 7-32.

completed, then stop.

Carry out the necessary steps for the design of the controller and system for a high speed UART (Universal Asynchronous Receiver and Transmitter). This system should have operation similar to the slow speed integrated circuit UART but it must be able to send and receive

7-33.

is

serial

data at a

1

MHz

rate.

Carry out

all

design steps.

Figures P7-13 and P7-14 illustrate a partial functional partition and control flow

diagram of a system that will perform a multiplication of two numbers. Your task is to complete the design, including the system graphically illustrate

how

certain your design

neatly

is

the

eight-bit binary

controller.

system functions, using several examples.

drawn and documented. Note

that this

is

Then

Make

an excellent

laboratory exercise. Try for high speed operation.

Problems and Exercises

527

EIGHT-BIT TRI STATE

DATA BUS

Fig. P7-13.

I M REG 8-BIT PIPO

EIGHT BITS

(Multiplicand)

LSB

\EIGHT

BITS

1 FULL ADDER 8 BIT

Qi

\7 A REG

Q REG

9-BIT PIPO/PISO (Accumulator)

8-BIT PIPO/PISO

17-BIT

(Multiplier)

ANSWER

LSB _l

_l

> a

> a

cc

DC




CU +CD

QC

c

CD

CO

CD 3 o

co

d)

o Q Q Q

QC CO I- I-

CD

"D CO

*->+->

CJ

3

§ 3 — CD 2 CD CO

CC 00

o

OO

CT

tr

CT

O"

CD

CD

CD

CD

_i

DC QC QC DC


2

'1

'o

0 0 0 0 0 0 0 0

0 0 0 0

0 0

0 0

1

1

0 0

0

1

1

1

0

1

1

1

1

0 0

0 0

1

1

1

1

1

0 0 0 0 0

1

1

1

°3 0 2 0

°o 1

1

0

1

0 0

1

1

1

1

0

1

1

1

0 0

0

0

0 0 0 0

1

1

1

1

0

0

0

0

0

1

0

1

1

0

(b)

INPUT/OUTPUT specification for 4x4 ROM designed to convert BCD to Excess-3.

Fig. 8-15.

The

actual process of getting the Fs

Some ROM's

are

"masking." Other

548

The

programmed

ROM's

System Controllers

and

O's in the

a

output column varies.

semiconductor process called are field-programmable (called PROM's) and are perma-

Utilizing

at the factory using a

Combinational MSI/LSI Circuits

nently

programmed (burned-in) by "burning out"

selected "fusible links" inside the

package by applying current pulse to specific terminals. Others can be programmed by other nondestructible means, and then erased with ultraviolet light. These are called EPROM's (Eraseable PROM) or sometimes READ-MOSTLY-

MEMORIES

(RMM's).

The PROM,

like its

predecessor the

READ-ONLY-MEMORY

(ROM),

is

a

embodying the equivalence of providing an addressable selection of

single-chip large scale integrated solid state device

thousands of gates and multi-bit words.

ROM,

is

used mainly for

Figure 8-16 illustrates the logic of a typical

PROM.

Unlike the

PROM

can be programmed by the user in-house by burning out the fusible links shown, thus saving the manufacturer's masking charges. This simple and inexpensive programming feature not only allows the user to design normal memory functions, but also to select an almost unlimited number of Boolean expressions to be used for combinational and sequential logic design. The following device listing shown in Table 8-3 indicates that there is a wide variety of and PROM devices to choose from. Figure 8-17 is a selection of shortened specification sheets for a generic PROM family. Generic implies a family of devices with a high degree of commonality. the

ROM

D D

r

A oO-

A,Q-

4> 4>

FUSIBLE LINK

A 2 Q-

-OB,

y OUTPUT

INPUT

WORD

ADDRESS A 3

-OB,

A d O-

4>

OB. J

H3

4>

r

W 63

ENABLE < E2

0 Fig. 8-16.

An example

of a

programmable read only memory

logic.

ROM's, PROM's, and Applications

549

HM-76XX

SEMICONDUCTOR A DIVISION


620 7621

HIV,

1

TS

Open-Collector Three -Slate Active Pull-Up

7

—

«-

iso

.

ns

—

i

Ij

300

—

7)0—1

-

15 !

HM

003

TS

APU

7644

HM-764077641 nnnnnnnnnnnn UlltO

98)654371

FEA TORES

.

INOEX

13 14 IS 16

LEAD

24

NOTCH

D.I. P.*

W 16 19 2021222324

uuuuuuuLnjuuu

• Common •

D. C. Electrical Characteristics and

Simple, High Speed Programming Procedure

Programming Procedure (1

Second per 1024

Bits,

Typical)

• Expandable

-

"Open-Collector" or "Three-State" Outputs and Chip

—

Enable Inputs

•

Inputs and Outputs

Low

-

nnnn nnnnn

Logic "1"

400/uA Logic "0",

!

9

Output Drive

Full

-

16mA

Sink,


OUTPUTS

E

R

2"

n{ H)

J n( L)

(b)

Fig. 8-26.

Structure comparison between a

PLA and

a

ROM.

structure.

562

System Controllers

Utilizing

Combinational MSI/LSI Circuits

n

(a)

PLA

structure, (b)

ROM

can accommodate many more inputs than ROM's without stressing the boundary conditions imposed by the practical limits set by the semiconductor process used. What this says is that you can only put so much on a chip. Therefore, for random logic generation, the PLA is more efficient than the ROM. To illustrate the implementation of a simple random logic expression, using a PLA typically

ROM

and a

consider the following example.

Example

8-6:

desired to implement the logic expression set forth in the

It is

following map:

.AB 00

01 0

0

Fpla

=

From =

0

4 1

3

1

1

F-

6

0

1

10

11 2

5

7

1

0

1

SO, 1,3,4,7

AB + BC + BC

(logic expression for a

ABC + ABC + ABC + ABC + ABC

The implementation of Fis shown elementary ROM and PLA.

PLA's are sized or

specified

PLA)

(logic expression for a

in Figures 8 -27(a)

and

ROM)

8 -27(b) using

an

by the following description:

Ax B XC where

A = number of inputs B = total number of unique

product terms capable

(number of inputs each

Therefore

OR gate has)

C = number of outputs (different logic expression available) the specifications for PLA such as the Signetics FPLA 82S100 mean

that:

16

implies that this

with a

maximum

PLA

is

X 48 X

8

capable of generating eight different logic outputs each

of 48 unique product terms

made up

of

any combination of 16

input variables.

The 82S100

serves as

an excellent example for

illustrating the actual internal

FPLA. The structure of this device is shown in Figure 8-28. The circuit shown in Figure 8-29 illustrates the equivalent logic path and TRUTH-TABLE for the 82S100 FPLA. The title of the specification for the 82S100/101 is shown in Figure 8-30. structure of a

Programmed Logic Arrays (PLA's)

563

Exhaustive

Decoder (8-3 input

AND

gates)

0

A(H) B{H)

3-to-8

DECODER

1 3 4

C(H)

5

6 7

Fusible links

N

F(H) B(L) C(L)

>4fl(H)

A(H) B(H) C(H)

(a)

A(L) r B(L) C(L)

BC(H)

A(H) B{H) C(H)

4(L)

A(L)

0(L)

C(L)

A{H)


CO

^

1

CLR

I

74175 i

i

!

Q4

Q 4| Q 3

Q 3| Q 2

I

Q2

CLK) + AC DB = AB( = ) + BC( ~CP) + BC+ABC Dc = AB(CP) + BC(PDR) + AB(CR) + BC DECR ACC CLR ACC DROP POP RETURN NICKEL If

= ABC = ABC = ABC = ABC you find that a total of each made up from 16 possible input

the specifications for the 82S100 are examined,

48 unique product terms are

available,

variables.

Step 2:

Now

simply give each of the different product terms a

Pn

number and proceed: Po

= AB( = )

P9 =

BC

Pi

= AB(>)

P10-

ABC

Pi

= AC

Pn = ABC

P3

= BC( CP )

Pu = ABC

P4

= BC

P5

=

Pe

= AB(CP)

Pi

= 5C(PDR)

Ps

= AB(CK)

ABC

System Controller Design Centered Around an FPLA

575

From

and Figure 8-33 observe:

this listing

F0 = DA = P0 + P + P2 = DB = P0 + P3 + P4 + P5 F2 = Dc = P6 + P 7 + P s + P9 F3 = Not defined F,

This

list is

= DECR ACC = P 5 = CLR ACC = P xo

F4 F5 F6 F7

x

= DROP POP = P u = RETURN NICKEL = P n

then transferred to the approved program table as shown in Table

8-6.

Special note: starting

ments

Fig. 8-35.

The

has been found that program writing

It

is

made

easier

your programming process using a schematic with the "pin" assignFigure 8-35.

like

seven-state

pop machine system

X

controller

O

'l3

'l6

^12

> Q

> Q

h-

DC

DC

LU

CL

DC LU

z CO

o DC Q CL O CL

+5

implemented with an FPLA.

U < X

u

o

O

CO

CO

A

LLI

DC CL

O O

X

X

CO

QQ

X

^10

'l1

CE

FPLA

82S110 +

50

FE

F

DC

< LLI

_l

CJ

_i

o CO > CO I

^4

3

CLR

I

74175 i

^>CLK

3 oA

!

CLR

D3

j

D2

I_

_

QJQ, TT

Q4 Q3

XT

°y j

I

74175

\CLK

Q3

k

Q 2&

X °i

D"

CL

DC =>

DC

O o < CL O DC DC _l O O Q_

CJ CJ

CJ CJ

DC

CJ


>CLK

Multi-Mode Shift Register

Outside

or Counter

World Outputs

CLR

Data

Next


Control Inputs

Fig. 9-1.

The

counters as the

Q

general model of the system controller sequential circuit utilizing shift registers and

memory

element.

Introduction

581

SYSTEM CONTROLLERS CENTERED AROUND A MSI SHIFT REGISTER and follow some design and state assignment constraints, this device can and will produce some very effective results in terms of design flexibility and hardware savings. To illustrate the techniques involved, consider the AM74LS194 or AM74S194 device, which is a fully synchronous SIPO, PIPO, PISO, and SISO four-bit shift register. The specification sheet for this device is shown in Figure 9-2. This device was selected because of its edge-triggered synchronous LOAD/SHIFT operations and asynchronous CLEAR features that are deemed desirable for the applications described If

you

select the

proper and available

shift register

in the introduction.*

As mentioned in the introduction, using a device such as the AM74LS194 imposes some design constraints. However, these design constraints are not formidable; they are simply in keeping with the statement: functional features

The the

first

made (1) (2)

(3) (4) (5)

in

Do Do Do Do Do

limitations,

and use good

such constraint to be addressed when using a

AM74LS194

to be

and operational

"Know

is

Keep

the state assignment problem.

any given shift

a 0 left?

I

shift

a

I

shift

a 0 right?

I

shift

a

I

do a

parallel load?

1

sense." shift register

mind what

such as

decisions are

state:

I

1

in

your devices, the

left?

right?

you should try to do as many simple "shifting" operations as possible. In short, if you could complete a state assignment by simply shifting a 1 to the left without having to perform any other operation, then do it! Understanding increases as you see the actual design Therefore, in making a state assignment, philosophically

process unfold. However, tions governing

(1)

Do

be said again:

The basic device-imposed considera-

NEXT STA TE ASSIGNMENT are:

your

I

let it

call for shift right

or

left

with a

1

or 0? Conditionally or uncondi-

tionally? (2)

Do

Now

I

call for a parallel

load? Conditionally or unconditionally?

consider that you were given the

MDS diagram shown in Figure 9-3 and

and memory element section of a system controller with the AM74LS194 shift register. Of course the first step would be to make a state assignment. As mentioned earlier, this is done by mixing an assortment of shifting Fs and O's right and left or parallel loading the device.

you were asked

*The AM74LS194

582

to design the next state control logic

series

Introduction to

is

not plagued with the Fs and O's catching problem (see data sheet).

Programmable System Controllers

Am54LS/74LS194A Am54LS/74LS195A •

Four-Bit High-Speed Shift Registers

Distinctive Characteristics

• Fully synchronous shifting and

•

• Buffered

or

load

Parallel

JK

with

right

shift

on

inputs

or do

load

paralle

right,

left,

parallel loading

clock

• Buffered active-LOW clear • 100% reliability assurance testing in compliance with

Am54LS/74LS195A • Shift

common common

nothing on

Am54LS/74LS194A

MIL-STD-883

FUNCTIONAL DESCRIPTION The Am54LS/74LS194A and Am54LS/74LS1 95A synchronous operation

registers that exhibit fully

ating modes.

The Am54LS/74LS195A can

oper-

either parallel load

four register bits via the parallel inputs (A, B, C, D) or shift

all

each of the four register bits right one place. parallel loading

When

is

LOW,

is

when the

inputs;

data

via

shifting or

K

the J and

inputs

in

loaded from the

is

shift/load input

loaded from the register bits on the

loaded

The

under control of the shift/load input (S/L).

the shift/load input

parallel data is

are 4-bit

in all

The mode.

left.

the shift

HIGH,

is

first bit,

data

Qa,

is

comes from the flip-flop to the left, with the bit input from R), shift left (data comes from the flip-flop to the right, with the Op input from L), and hold or do nothing (each flip-flop receives data

.

LOW-to-HIGH

3

9

so

10

s,

1

—

5

6

7

I

I

I

I

B

C

D

L

output). fol-

forces

all

of

1

transition

outputs to the

LOW

state

(Qq HIGH) independent

any other inputs.

's,

all

the flip-flops are D-type they

do not catch

and the only requirements on any inputs

is

that they

O's or

meet

the short set-up and hold time intervals with respect to the

clock

LOW-to-HIGH

transition.

LOGIC DIAGRAMS Am54LS/74LS194A A

S/L

C

B

D

j

K

Am54LS/74LS195A

An i54LS/74LS194A

CP

1

1

A

R

4

own

on the clock input, CP. Both devices have an active-LOW synchronous clear (CLR) which a

LOGIC SYMBOLS 2

its

For both devices the outputs change state synchronously lowing

Because

The Am54LS/74LSl94A operates in four modes under control of the two select inputs, Sq and Si The four modes are parallel load (data comes from the parallel inputs), shift right (data

from

CLR

Qa

Qb

Qc

°d

15

14

13

12

CP

CLR

Qa

14

15

V cc

= Pin 16

GND

= Pin 8

12

13

11

CONNECTION DIAGRAMS Top Views

nnnnnnnn pnnnnnnn

vcc

Qa

Qb

Qc

Qq

cp

si

15

14

13

12

11

10

16

so

v cc

Qa

Qb

Qc

qo

Qd

cp

15

14

13

12

11

10

9

Am54LS 74LS195A

An 154LS/74LS194A 8

l

• CLR

s i

2

3

4

5

6

7

R

A

B

C

D

L

GND

Am54LS/74LS195A

UUUUULJUU

CLR

J

K

A

C

B

D

GND

ORDERING INFORMATION Am54LS/ 74LS195A

Am54LS/ Temperature Range

Package

Type

74 LS 194 Order

SN74LS194AN SN74LS194AJ to SN74LS194AX Dice 0°Cto+70°C -55°C to +1 25°C SN54LS194AJ Hermetic DIP Hermetic Flat Pak -55°C to +125°C SN54LS194AW Dice -55°C to +125°C SN54LS1 94AX Molded DIP Hermetic DIP

Fig. 9- 2(a).

0°C 0°C

to

Data sheet

+70°C +70°C

for the

Order

Number

Number

SN74LS195AN SN74LS195AJ SN74LS195AX SN54LS195AJ SN54LS195AW SN54LS195AX

AM74LS194

shift register.

CPo—^»

CI R o

J^o~

(Courtesy of Advanced Micro Devices)

System Controllers Centered Around a MSI

Shift Register

583

Am25LS194A Am25LS195A •

Four-Bit High-Speed Shift Registers Distinctive Characteristics

•

Parallel load or shift right

50mV improved Vol compared 440/x A source current

with JK inputs on

Am25LS195A, • Shift

do nothing on

right, parallel load or

left,

Buffered

common

100% reliability MIL-STD-883

clock frequency sink current over full military temperature range

8mA

Am74LS

Fully synchronous shifting and parallel loading

Am25LS194A • 35 MHz guaranteed •

to

active-

LOW

clear

assurance testing

in

compliance with

FUNCTIONAL DESCRIPTION Am25LS194A

The

Am25LS195A

and

are 4-bit registers that

exhibit fully synchronous operation in

The Am25LS195A can

either

operating modes.

all

load

parallel

one place. The shifting or

register bits right

four register

all

D) or shift each of the four

bits via the parallel inputs (A, B, C,

parallel loading

is

under control of the shift/load input (S/L). When the shift/ load input is LOW, data is loaded from the parallel data inputs;

when

the shift/load input

J

and K inputs

HIGH,

is

The first the shift mode.

on the

register bits

in

data

loaded from the

is

Qa,

bit,

left.

is

loaded via the

(data

comes from the

input from R), shift

flip-flop to the left,

with the

two

the

of

operates inputs,

select

parallel load (data

four

in

So and

comes from the

S-|

.

modes under control The four modes are

parallel inputs), shift right

For

both devices the outputs change state synchronously a LOW-to-HIGH transition on the clock input, CP. Both devices have an active-LOW synchronous clear (CLR) which forces all outputs to the LOW state (Qq HIGH) indefollowing

pendent of any other inputs. all the flip-flops are D-type they do not catch 0's or and the only requirements on any inputs is that they meet the short set-up and hold time intervals with respect to the

1's,

clock

LOW-to-HIGH

LOGIC SYMBOLS 4

3

2

5

6

(OUTPUT LIST) Example: BCQO VF E OT), (EOT)(^ )-(LOAD, RN) reads as continue the count on OVF EOT conditional, or branch on EOT to state A (state A =0000). Also, ASSERT both LOAD and RN. •

•

BIT

FORMAT:

0

1

1

0

0

0

1

0

0

0

0

0

0

1

1

/ Bit assigned '

to

Introduction to

Programmable System Controllers

RN

Note:

MUX

This format indicates that the Count

number

which

6, to

OVF EOT •

MUX

Branch input number is the branch address.

2.

is

connected, and

and

Bits 8, 9, 10,

1 1

addressed to input

is

EOT

connected to to J9000, which

is

are set

NOTES RELATED TO THE MICRO-INSTRUCTIONS It

is

noted that there are some options related to the

NEXT STATE CODE

specifications in a micro-instruction.

For example: (1) If

you already have a

instruction (2) If

when

(0110)

you do not have a

state assignment, is

to

be the next

then BU(6) - (0)

d

is

a valid

state.

state assignment, then

instruction for the case where state

is

to

BU(Z)) -

be the next

(0) is also

a valid

state.

mentioned because it is possible (as in the author's case) that you will have an automatic assembler program that will make the state assignment and assign the variables to the inputs. In this case, you need not worry about giving a numeric value to the BRANCH ADDRESS; it will be taken care of automatically. Further, it should be noted that the outputs are all IMMEDIATE TYPE. CONDITIONAL OUTPUTS require extra program steps or extra hardware between the ROM and output holding register. Now, before considering an actual application of this microprogrammed controller, let us briefly outline one major constraint induced by the instruction code and architecture. This constraint is: Only two-way MDS diagram branches are allowed. Thus we will have to modify our flow and MDS diagram development such that this constraint can be accommodated. However, this is not serious, particularly in view of another configuration that will be introduced later. Now consider an example problem illustrating how the simple programmable architecture can be utilized, as well as how a control program can be written in a This

is

MUX

higher level language.

implementation of the adapted eight-state MDS diagram for the pop machine system controller shown in Figure 9-23. It should

Example

9-5:

be noted that

Illustrate the

this

MDS

diagram has been devised

in order to

conform

to the

two-way branch constraint. We can now write a control program listing using the five basic micro-instructions, which describe the system operation. First, we will write the program assuming that no state assignment has been made (see Table 9-1). Then we will write a program based on the state assignment illustrated in Figure 9-23 (see Table 9-2).

Notes Related

to the Micro-Instructions

605

TABLE

9-1

The micro-program diagram

In

listing

of

MDS

Figure 9-23

Memory Location

A

CC(CP)-(0)

B

BC(CP)(C)-(0)

C

CBC( 2 < 30e- ),(2 < 30ef)(A )-(0) CBC( 2 = 3Q€T),(2 = 30 > o o Q Q CO CO

CO

LU QC CL

+5

+ 5Q

O

7

6

4

5

j-C.

3

DC LU CJ

C

0

2

B

A

Y

X _l CJ CO

>

CMXC(H) CMXB(H)

CMXA(H)

X

DC CO

DC 00


O o Q Q CO CO DC QC V CL DC

_l

6

this

W

Y

FLAG BA 2 BA 2 BA, BA 0

0C oc

V1YCA-1 1

r

RC

clmh;

CLK< CLR

CLR(L]

T 3

/

/

3

0

2

2

/. '1

3

82S123

'2

'1

82S123

o6 o b o4 o3 o 2

o,

o0

°7

0 6 °5 °4 0 3 0 2 0 0 Q 1

LU

CL

o CJ


>'s),

table to

Once

this

is

completed the excitation map is close at hand. Transform the merged table into the excitation map.

Related notes: (a)

This

the final step in the evolution of the primitive state table into

is

the excitation

map.

(b) In this step the alphabetic notations for the stable states in the

merged

table are replaced with the codes of the rows in

which they

reside. (c)

The alphabetic notation

for the unstable or transition states are

given the codes of the next row to which the machine

Here notice how cycles can be prescribed

to transfer.

to assure unit distance

changes (row codes) are guaranteed.

state (7)

is

Derive the expressions for the excitation variables (Y's) by reading the excitation

map.

Related notes: (a)

Once

map

the excitation

is

at

hand, the actual circuit can be

implemented from the expressions read from the map

in a process

exactly opposite to that of analysis. (b)

For multiple feedback systems (those with more than one y\ advisable to plot a single excitation

map

(8)

be

illustrated later.

It is at this

is

for each of the Y's specified

to avoid the confusion of trying to read the will

it

composite map. This

point that hazards are to be

removed by overlapping adjacent groupings. Make an output decoder map.

Related notes: (a)

Based on the knowledge that an output (Z) is in general a function of both the inputs and the state of the machine, the function notation

is:

Z = /(inputs, make up

(b) Therefore,

a

map

feedback)

similar to the excitation

map

to specify

under what input and feedback condition there is to be an output generated. This is done easily for the stable states by simply inser ting the derived output codes into the output map at the location of the stable states in the excitation map. However, considerable care

must be exercised In short, is

the

if

same

through

all

to prevent transient outputs during a transition.

the output condition specified in the beginning state as the ending state,

it

must be specified the same also

of the intervening transition states; otherwise transient

glitches will be generated. (9)

(10)

Draw up schematics to the specifications of the excitation and output maps. Make certain you have properly documented your design. Perform a quick independent analysis of your design to make certain it performs as specified. At

this

time specify the set-up and hold times and

The Design of Asynchronous Machines

663

analyze the circuit's behavior

input changes do happen during a

if

transition.

Consider the very simple design problem outlined in Example

Example

To

10-3:

illustrate the

design process just outlined,

circuit that will duplicate the sequential operation of the

Step

We

1:

conceptualize

SET(L)

Step

shown

of the circuit,

BASIC CELL.

The block diagram of an

asynchronous

circuit that duplicates

BASIC

the sequential operation of a

CELL.

Q D

2:

us design a

in Figure 10-12.

Fig. 10-12.

CIRCUIT

^ o

let

should visualize the circuit in block diagram form to help

physical characteristics as

0 AN ASYNCHRONOUS

0

RESET(L)

its

10-3.

Based on our familiarity with the prescribed sequential behavior we define its operation with a primitive state diagram (see Figure

10-13).

10/10

00/10

10/10

Format:

SET,

(undefined

RESET/Q.Q

)

00/01

x I

Fig.

10-13.

action of a

The

undefined

)

primitive state diagram of the circuit that duplicates the

BASIC CELL.

Step 3: Develop a primitive flow table from the primitive state diagram.

Keep

input change notation along the top edge of the table (see Figure 10-14).

Fig. 10-14.

SR

©

d

0

b

10

- Row

a

0

0

®

10

*0\-+\\ and remain ASSERTED until the end of the input sequence >12?= 1 1-»10—»00. Assume at this time that only one input will change at a time.

10-10.

Develop a primitive state diagram and state table for the following problem. (Keep state diagram tight.) You are to design a sequential door lock using two widely separated debounced momentary switches (A and B). Your system is to open the door when A is pushed, then B is pushed and released twice, then A is pushed again.

Once

the lock

can be relocked by pushing B at least once. {Hint: to be thought of as a continuous sequence problem A, B, B,

is

open,

Remember that this is A using momentary switches, 10-11.

it

widely separated.)

Design a primitive state diagram and state table for an asynchronous circuit that is defined as a sample gate. This circuit is to have two inputs, gate (D), and sample (S); and one output (LD) operates as follows. The output is to be deasserted (low)

when the S input is deasserted (low). When the S input is asserted, the output (LD) moves to the level of the data (D) input and holds this level until S is deasserted. Assume initially that the two inputs never change simultaneously. 10-12.

Design a primitive state diagram and state table for the following circuit. This circuit is to have two inputs and one output. The two inputs are oscillator (O) and gate (G) and the output mnemonic (OP). When the gate (G) is deasserted, the output is to remain at a low level. When the input is asserted (high), the output will

no "shaved" initial or two inputs never change simultaneously.

gate the oscillator (O) to the output with initially that the

final pulses.

Assume

10-13.

Design a primitive state diagram and state table for a circuit with two asynchronous inputs (X and Y) and one output Z. This circuit is to be designed so that if any change takes place on X or Y, Z is to change states. Assume initially that the two inputs never change simultaneously.

10-14.

Design a primitive state diagram and construct the primitive flow table for a special circuit that has two inputs (AB) and two outputs (LE). The two outputs (L and E) are to reflect an indication of which input changed last. Assume at this time that the inputs do not change simultaneously.

10-15.

diagram and construct the primitive flow table which defines the operation of a special circuit. This circuit has three inputs {A, B, and R) and one output (A'). The R (RESET) is the input which drives X back to its NOT-ASSERTED state (LOW). The B input is a varying width pulse which lights an LED but is quasi random in its occurrence. The A input comes from a human actuated debounced switch. When B turns on the LED, the person is to react by pushing the A switch and releasing it. The idea is to have X light another LED if and only if the person under test is able to push and release the A switch while B is still ASSERTED. The X output will remain ASSERTED until R is depressed, at which time the test is to start over. Design a primitive

state

Problems and Exercises

713

Define a primitive state diagram and construct the primitive flow table for a

10-16.

rising-edge triggered

D

Flip-Flop.

Figure P10-8 illustrates several primitive flow tables. First examine these tables for

10-17.

possible redundant states (see Section 6-7 for review of redundant state identification

and removal). Then Figure P10-8

(a).

(b) Figure P10-8

(b).

Figure P10-8

(c).

(a)

(c)

P10-8

(d) Figure

strive for a

01

11

a

10 /PS

— b

e

d© ©@ © — -

c

0 0

b

a a

for:

merge the best possible way.

(d);

XH \ 00

nonmixed merge

1

c

1

c

0

% ®

01

11

10 /sR

d

-

b

d a

© ©b c

a

@d

®A 0 e

a

(a)

00 01

00 00 10

00

(b)

Outputs

x,x 2 00 01

11

10

z

©

-

e

c

-

0 0 0

a

01/0

b

©-

f© ©d®@ ® ~A © a

9

00 01

11

10

UOLC

® ®b

-

d

1001

c

-

a

9

"

h

c

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f

h

"A®

i

-

9

c

e

©d A®d © - -

© ®® - A 9

'

h

~

(D

0 0

(c)

a

•

b

i

A® © j

1000 1001

1000 1100 1000 0000 0100

0000 1010 1010

(d)

Fig. P10-8.

10-18.

Problems 10-9 through 10-16 require the design of a primitive flow table. First examine the flow table for possible redundant states (see Section 6-7 for review of redundant state identification and removal). Then strive for the optimal merge for the primitive flow table defining: (a)

(b)

(d) (d) (e) (f)

(g)

(h)

714

Problem Problem Problem Problem Problem Problem Problem Problem

Asynchronous

10-9.

10-10.

10-11. 10-12. 10-13.

10-14.

10-15. 10-16.

Finite-State

Machines

10-19.

(Refer to Problem 10-17.) Develop a noncritical race transition

map and make

secondary assignment (row assignment) for the merged table for excitation maps):

Problem Problem Problem Problem

(a)

(b) (c)

(d)

10-17(b). 10-17(c).

10-17(d).

hazards, then

(a)

(b) (c)

(d)

10-21.

this process.

Refer to Problem 10-19. Read the excitation all

develop the

10- 17(a).

Refer to Figure 10-23 for aid in 10-20.

(i.e.,

the

draw the

Problem 10- 19(a) Problem 10- 19(b) Problem 10- 19(c) Problem 10-19(d)

circuit

diagrams

map and

plot output

map

eliminating

for:

(refer to Figure P10-8(a)).

(refer to Figure P-10-8(b)). (refer to Figure P-10-8(c)). (refer to Figure P-10-8(d)).

(Refer to Problem 10-18.) Develop a noncritical race transition

map and make

the

secondary assignment (row assignment) for the merged table (develop the excitation (a)

(b) (c)

(d) (e) (f)

(g)

(h)

10-22

maps) for: Problem 10-18(a) (refer to Problem Problem 10-18(b) (refer to Problem Problem 10-18(c) (refer to Problem Problem 10- 18(d) (refer to Problem Problem 10- 18(e) (refer to Problem Problem 10-18(0 (refer to Problem Problem 10- 18(g) (refer to Problem Problem 10-18(h) (refer to Problem

10-9).

10-10). 10-11).

10-12). 10-13). 10-14). 10-15).

10-16).

(Refer to Problem 10-21.) Perform an inspection analysis on your design. Be certain to

determine what happens

and where your

circuit

if simultaneous

Then determine how do you know what stable

input changes do occur.

can be reset after power

up.

In short,

your circuit will be in after power is applied? Can you set the input conditions after power is applied and guarantee that your circuit will move to a known state? Next, examine your problem for essential hazards. Read the excitation map, removing the hazards, and draw up schematic diagrams for: (a) Problem 10-21(a). (b) Problem 10-21(b). (c) Problem 10-21(c). (d) Problem 10-21(d).

state

(e) (f)

(g)

(h)

10-23

Problem Problem Problem Problem

Design a

10-21(e). 10-21(f).

10-21(g).

10-21(h).

circuit of

your choice that

will exhibit

carry out a timing diagram analysis illustrating

a potential essential hazard, then

how

this

hazard can be induced by

adding delay. Then, once it has been induced, assume that this delay is invariable and attempt to eliminate the induced essential hazard by adding delay in a feedback. Then ask the question, "Has this 'curing' delay created other hazard

problems elsewhere 10-24.

in the circuit?"

Refer to Figure 10-37(h).

Problems and Exercises

715

(a)

Could the propagation delay of this Flip-Flop be improved by using three-input NAND gates for the cell and feeding the outputs (2) of the AND functions for

SET/ RESET decoder Would this wiring change

directly to the cell inputs?

the (b)

impair the operation of the complete circuit?

10-25.

Using the model shown in Figure 10-36 and Example 10-9 as references, design a rising edge triggered T Flip-Flop. If possible, make your Flip-Flop operate as fast as possible. Establish setup and hold times for your circuit.

10-26.

one or more of the problem ranging from 10-9 to 10-15 and implement them using the technique demonstrated in Example 10-9. Completely analyze your Select

circuits' operation.

10-27.

diagram shown in Figure P 10-9 defines the handshake control sequence for a high speed direct memory access interface control unit. Use the cell-centered approach treated in Section 10-1 1 to design the logic for this MDS diagram.

The

state

Fig.

10-28.

Design a rising-edge-triggered in Section 10-11.

decoder.

10-29.

P10-9.

Make

(Note that the

D

certain state

Flip-Flop using the cell-centered approach treated all static

716

Compare your

results with Figure 10-37(h).

Select at least

two problems from the

The following problems comprise a

Asynchronous

Finite-State

SET/ RESET

diagram definition must be well thought through.)

complete design process as outlined Note:

hazards are removed from

Machines

set 10-9

through 10-15, then carry out the

in Section 10-12. set of interesting

and

practical circuits to be

designed by methods of your choice.

two ways

in at least

10-30.

for

It is felt

that each circuit should be designed

comparison purposes.

The following two wave forms

are produced

by a certain shaft encoder.

M

Outputs when rotation

is

clockwise (0.1 degree)

Outputs when rotation

is

counterclockwise

Design a special

and turn 10-31.

the

circuit that will light

LED

off

when

an

LED when

the shaft rotation

is

the shaft rotation

is

clockwise

counterclockwise.

Suppose you have two dc motors that turn two separate precision shaft encoders such as the one shown in Problem 10-30. One of these motors is defined as the MASTER Unit and the other is defined as the SLAVE unit. When these motors are running, a course control system maintains the speed of the slave within of the

MASTER. You

± 10%

are to design a sequential circuit that will output a pulse

SLAVE and MASTER. Also, there should be an output indicating that the SLAVE is leading the MASTER(HIGH) and the SLAVE is lagging the MASTER(LOW). Assume

whose width

MASTER

will indicate the

speed

Refer to Problem

1

degree of phase error between the

±20%. Design an asynchronous

10-32.

perform the pulse width discrimination specified, only this time disregard the single sample switch functions. In short, your circuit is to continuously perform the task of controlling the up/ down counter to provide the continuous measurements.

10-33.

Using the single-step-pulse concept, a synchronous decade counter like the SN74160 and a BCD thumb- wheel switch, design a programmable pulse generator.

7-4.

In short, design a circuit that issues the

number

specified

number

circuit that will

of clean clock pulses equal to the

by the thumb-wheel switch.

Problems and Exercises

717

APPENDIX

DRAFTING AND DOCUMENTATION

STANDARDS MANUAL

PREFACE This manual has been prepared in an attempt to standardize digital system

schematic drafting and system documentation done under the auspices of the Digital Systems tried

and

tested

Group at Utah State University. The rules set forth have been and deemed worthy of adoption by anyone doing digital system by anyone working System Group. Any deviations must be approved before

design, but in particular these rules must be followed strictly

within or for the Digital they can be adopted. Further, this

DESIGN

complement the MIXED LOGIC article "Polarized Mnemonics, Logic State Indicators, is therefore assumed that anyone using this standards

manual was prepared

as set forth in the

to

and Zonal Coordinates." It manual is fully familiar with the concepts of MIXED LOGIC DESIGN. The gates and circuits commonly used by the Digital System Group are shown in the appendix. The symbols shown for each circuit will be used for all schematics.

GENERAL DOCUMENTATION STANDARDS drawings and stuff sheets are to be prepared on the same size sheet, using approved drafting techniques. All documentation is to be done in pencil and must be neat and legible. If practical, keep the number of sheets in each subseries below 20.

(1) All logic

(2) (3)

718

Appendix A

(4)

Use blueprints

and wire

listing.

edge card assignment sheets, ECN's, and cable lists are to be placed in a system book. The master drawings and system book must contain a complete record of

(5) All

(6)

of masters for debugging

wire

lists,

documentation for the system, which

will include all engineering- change-

notices (ECN's).

TECHNIQUES SUGGESTED FOR POLARIZED MNEMONICS IMPLEMENTATION AND DOCUMENTATIONS SCHEMATIC (1)

Use paper with zonal coordinates, which

is

a special paper having

addressable sectors for the purpose of identifying geographical locations (see p. (2)

A

1

17).

block, located in the lower right-hand corner, should include

title

system identification, sheet number, board number, and can include a general function description. The sheet number must be unique to that

system only, and the board number identifies the board where the hardware is located. The drawing number is used for filing; initial your design and date

when completed.

Example A- 1:

REV "U.S.U.

APP

DIGITAL SYSTEMS LABORATORY"

DATE

BY W.I.F.

TITLE

DATE

BY

ECN

APP

6/23/76

3700-01-01 I/O BUFFERS

BOARD MODEL

NO.

DWG

2 REV

NO.

B-3 I/O Buffer

— names the drawing on the sheet for quick reference 3700-01 -01=

B—3 =

XXXX-YY-ZZ Product

Sub

Series

Identi-

Unit

No.

fication

No.

drawing identification

Techniques Suggested For Polarized Mnemonics Implementation and Documentations

719

The alphabetic character

of the drawing identification

is

assigned by the

following criteria:

A — index

type of information

— functional schematics PC board, component location) C — equipment layout diagrams and flow charts D— E — timing diagrams F — cabling diagrams and layouts G — block diagrams H — sheet metal drawings K — card cage assembly drawings and layout B

(stuff sheets,

state

(3) All

drawings must be neat,

all

labeling,

clear,

cross-reference

and done

information,

in pencil, allowing

and

possible

room

for

engineering

changes. Drawings must be dark enough for blue printing (use

F

lead).

drawings must flow from top to bottom of the sheets with inputs toward the top and outputs toward the bottom. Use only a MTL-STD-

(4) All logic

(5)

806C three-quarter The recommended on pages 737-742.

(6)

Any

logic

symbols for commonly used

purpose gates not shown in the appendix number.

special

the circuit

size logic template.

circuits are

will

shown

be labeled with

Example A-2:

such as MSI and LSI devices will require special attenno standard drafting symbol is shown in the appendix for a

(7) Special circuits

tion.

If

one must be synthesized using a rectangle. Care must be taken to label all inputs and outputs inside the drafting symbol (rectangle). This labeling should be done in such a manner as to describe the actual circuit operation. Be sure to include the circuit family number. Keep inputs to the device on upper edge and sides; all outputs on the bottom. See the device,

following example.

720

Appendix A

Example A-3:

A

G2A G2B

G^

C

B

74LS138 4

oooooooo 6

7

(8)

Use

5

3

2

1

0

and confusing and cross-referenced.

the cross-reference technique to avoid massive

All nonconnected lines must be labeled (9) All cross-referenced leads

line drawing.

must have a mnemonic that is unique, that defines the and carries the correct polarizing element.

logic function as closely as possible,

The

(a)

polarizing element

is

placed in parenthesis:

RDATA= 1(0) or RDATA =

1(L).

(b)

When

fan- out

demands

alphabetic character

is

require several leads that are logically the same, an

placed after the polarizing element.

Example A-4:

V Edge card pin number (ZZ)—^(Connector pin number)

CBL ZZZ-WW CBL^Cable ZZZ^Cable number

WW— Live pin number »

Example A-6:

V

ECC YYY(ZZ) Edge

TRANSMITTING END

card connector, edge card pin assignment (con-

nector pin number)

CBL ZZZ-WW

Cable, cable number,

XXXX XXXX

System name,

CBL ZZZ-WW ECC YYY(ZZ)

live

pin

number

sheet number, zonal coordinate

System name, sheet number, zonal coordinate Cable number and live pin number Edge card assignments (connector pin number)

RECEIVING END

Special note: In regards to the orderly documentation requirements as set forth, it is

a

known

fact that

when schematics

assignments information

may

are being drawn, edge card

not be known.

It is

therefore acceptable to use

on prototype schematics. However, the master schematmust be updated to satisfy these rules before system documentation is

the following notation ics

and cable

complete.

Y h-

c

C3 H4 12C0 ECC-S1

2(3)

is

as

Complete Example of Cross- Referencing:

V

Transmitting End Sheet 12 Coor D4 SC8I Series

< Q

A3—>Same

sheet, Coor.

A3

6F0^Sheet 6, Coor. FO 7H4^Sheet 7, Coor. H4 ECC-JF2(12)—>Edge card connector JF2 (connector pin CBL-4AA-13^Cable 4AA, live pin 13 DS-4F3—>Data switch series, sheet 4, Coor. F3 $ Cable has Viking connector

*The $ sign has been added

AMP

$ Cable has an

SC8I-12D4^SC8I

on receiving end

to allow for special information that

must be added

connector on transmitting end

series, sheet 12,

CBL-4AA-C4^Cable 4AA,

live

D4

Coor.

pin

C4

ECC-S12(13)—>Edge card connector S12 (connector pin

El^Same sheet, D8—>Same sheet,

12)

13)

Coor. El

Coor.

D8 Receiving End Sheet 4 Coor. F3 Data switch series

V (11) All

communication

ASSERTED (12)

Fan-out fan-out

shall is

reference dinates

at the

low signal

level

never exceed logic family recommended

greater than one, all

boards should be for noise immunity.

leaving or entering the

lines

list all

inputs to that output.

more than once,

list

cross references at the output

When

a signal goes to the

the coordinate that

number

Example A-7: /

C4

C4

Coor C3

C4

C4

Coor.

rr

C5

Coor.

rr

4*Z A?-\Z

LD

10

T

QA Q B Q C Q D

15

74162

BCD

A

10

T

RC

CLK

QA Q B Q C Q D

RC

14

15

1

13

1

2

1

1

74163

16-pin

16-pin

/CLK

D4

D3

\

14

13

1

D6

°5

I

I

I

I

I

I

74174

74174

I

I

I

I

CLR

I

Q3

1

1

I

Q4

i

Q6

i

10

9

4

5

*1

^2

/CLK

—

DN

^4

1

74175

!

74175

Q,

Q i|Q 2

T

2

3

UP

13

^3

CLR

Q 2| Q 3 1^

•T

W

1

14^

10

15

74193 16-pin

10

A

C

B

D CLR

5

4

UP

DN

—

QA QB Q C QD

"TT"75 13

742

12

Appendix A

I

3

I

2

1

10

A B

C

9

D CLR

74193

LD

CY

15

14

74192

BW

6-pin

Q4

16-pin

15

15

|

1

74192

12

12

!

I

6

6-pin

1

LD

BW

CY

QA Q B Q c Q D

2^

3

I

7

13^

1

2

6

7

14

APPENDIX

BOOZER PROGRAM

(87aO03)CANDE/COOE210 ON PACK C333SZ383CS3SB883BBBB3BS3BSS8 X

X X

X X X X

% X X X X X X X X X X X X

X X X X X X

THIS PROGRAM WAS PREPARED BY THE ELECTRICAL ENGINEERING DEPARTMENT UTAH STATE UNIVERSITY SEPT, 1977. IT WAS IMPLEMENTED ON A BURROUGHS 6700 IN EXTENDED ALGOL 60, THE AUTHOR ASSUMES NO RESPONSIBILITY IN THE IMPLEMENTATION OR USE OF THIS PROGRAM, AT

THE PROGRAM FINDS A MINIMALLY REDUCED EXPRESSION OF A BOOLEAN THE PRIME IMPLICANTS ARE ALSO MADE AVAILABLE TO LOGIC PROBLEM, THE USER. THE PROGRAM wlLL ACCEPT MAP ENTERED VARIABLES AS WELL AS PARTIALLY REDUCED EXPRESSIONS,

THE PROGRAM IS A SELF EXPLANATORY T IMESHARE PROGRAM, WHEN THE MAP ENTERED VARIABLES ARE ASKED FUR THEY ARE LISTED ONE PER LINE IN ANY SEQUENCE. THE LIST IS TERMINATED BY A THE TERMS ARF ARE INPUT IN THE FOLLOWING FORMAT I STATE VARIABLE (EXPRESSION OPTIONAL) VALUE. DELIMITERS ARE ANY CHARACTERS OTHER THAN LETTERS, NUMBERS, OPERATORS, OR THE END OF INPUT SYMBOL (#). THE OPERATORS ARE AND (.), OR (), UNARY MINUS ('), DASH (-), AND PARENTHESES (), STATE VARIABLES ARE THE TERMS OR RANGE OF TERMS TO BE ASSIGNED THE VALUE SPECIFIED, EXPRESSIONS ARE EVALUATED FROM LEFT TO RIGHT, NO PRECEDENCE IS ASSUMED. ALL ORDERING MUST BE DONE wITH PARENTHESES, ONLY ONE LEVEL IS ALLOWED, ALL TERMS SPECIFIED BY THE EXPRESSION ARE ASSIGNED AS SPECIFIED BY THE VALUE, TERMS TO BE ASSERTED SPECIFIED BY »»•# DON'T CARE TERMS '0', AND ANY OTHER NUMbER IS NOT ASSERTED,

Boozer Program

743

BEGIN FILE 0UTP(KlND«RfcMQTt#bUFFERSsl#MAxRE.CSIZEsl2)j FILE

INP(KIND=REM0TE, RUFFtRS«l ,MAXRECSIZE=12)

I

TftANSLATETABLE

NUMBERTOEBCUlCCad "0001 020 JOaoSOfeO 708090 A0B0C0U0E0F1 01 113131415 161718 19" TO "ABCUEFGHIJKL^NOPQRSTUVWXYZ" } )

REAL BA3ENUMBER, BEGINRANGE, CHECKUP, COLUMNSLEFT, CON, CNT, CNT1,

XSTART IN FIRST PARTITION XSIZE OF GROUP IN FIRST PARTITION

XCOLUMNS LEFT ON INPUT IMAGE XCONSTRAINT NUMBER LAST USED XTEMPORARY COUNTER USED AS NEEDED XDITTO XDITTO XEND OF GROUP IN FIRST PARTITION XFUNCTION SIZE 2**NUMBER OF VARIABLES XTELLS what TOKEN IS XSIZE OF GROUP LOOKING FOR XLARGEST GROUP POSSIBLE IN PROBLEM XNUMBER OF ME V TERMS 2**MEVS XMINTERM WORKING WITH XNUMBER OF VARIABLES XNUMBER OF VARIABLES MINUS ONE XNUMBER OF MEV'S XNUMBER OF M1NTERMS ASSERTED XNUMBER UF PARENTHESES IN EXPRESSION XPARTITION NUMBER WORKING WITH X2** STATE VARIABLES XNUMBER OF STATE VARIABLES XwHOEVER N££US IT USES IT XDITTO XDITTO XVALUE UF SPECIFIC TERM AT INPUT X*HAT NEXT TUKEN IS XTOP OF SYMBOL STACK XNUMBER OF TERMS X TERM JUST FOUND XASSERTION LEVELS OF TERM JUST FOUND

CM2, ENOR ANGE FS1ZE, INWHAT, LASTCHECK, LGROUP, MEVTERMS, MINNUMBER, i

NOV,

N0VM1

NUM»EROFMEV NUMM

I

N,

PARENCOUNT, PARTNO, STATETERMS, STATEVAR, TEMP, TE^Pl TEMP?, TERM VALUE TUKENV ALUfc

TOPUFSTACk TuPOFTERM,

,

T*YT ERM

TTERMASSERTEO; bOOLE AN ChECKON, ENDINMUT ENDOFC ARO#

XSIGNAL Enu OF INPUT list XlNCOMPLETE INPUT EXPRESSION X ALL EQUAL SOLUTIONS DESIRED XPROCESSING TERM INPUT EXPRESSION XMAP DOESN'T REDUCE TO '1' XMAP DOESN'T REDUCE TO '0' XEXPRESSION OK SO FAR XTO INSURE PROPER SYNTAX XLEFT PARENTH HAS BEEN ENCOUNTERED XPRIME IMOLICANTS WANTED XUSEO IN INPUT OF TERMS XSYMBOL IN SYMBOL TABLE

InExprESSION, NOTALLQNES, NOTALLZEROS, NOTINPUTERROR, UPERATORLAST, PA^ENTH, PRIME, RANGER, TmEREI A

RKAY

ATEMP [0:9] , expression to i0 DO OUTPUT TERM ( TERM tOUTPUTL 1ST ICNTJ) TERMASSERTED IOUTPUTLIST CCNT1) ) end; END ELSE NOT NOTALLZEROS THEN *R I TE (OUTP, //, "THE MINIMIZED EXPRESSION 0 ") "IS ELSE -RITE (OUTP, //, "THE MINIMIZED EXPRESSION i "is ) ; end; IF

•

'

end; end;

760

Appendix B

"

'

•

"

AND I>1

INDEX Absorption, theorem, 87, 130

Accumulator, 496, 498 Action, related:

60 maps, 344, 587, 588, 597 mnemonics, 60-62, 588 Adder, binary, 200, 202, 266 logic,

half adder, 201 Adjacent, groups: adjacencies (in map), 704 kitty corner,

245-46

245 Algorithm, state machine chart, 457 Analog: design, 2 system, 2 Analog to digital converters, 14, 16-18 offset,

Analysis: combinational, 118, 119 sequential:

asynchronous, 653-57 synchronous, 341-47, 353

AND:

number

systems, conversion, 23 Basic cell, 664

1

BCD

(see Codes) Bi-directional bus system, 257

Binary: arithmetic, 25, 26 cell, 282, 283 code (see also Codes), 36

59 system, 12 operator, 85 Binary to decimal conversion, 26-28 Binary sub tractors, 205, 206 logic, 36,

number

half subtractors, 205 Bit,

36

Sequencers) Boole, George, 1, 58, 83 Bit-slice (see

Boolean:

conjunction, 65 function, 68, 69, 92 gate,

244

Arithmetic-logic-unit, 200, 600 ASCII (see Codes) Asserted /Not- Asserted: definition, 61 levels (voltage),

80

level indicator, 70, 72, 81

mixed, 80 symbols, for

MDS

diagram, 459, 460 voltage range, 60, 73, 74 Asterisk (*), symbol definition, 458

Asynchronous: branching, 463, 480 controllers (see Controllers) circuits,

689

decision variables, 462, 465, 661 design, contemporary, 662-64, 700, 702 cell-centered, 692, 693

machine, 644, 650 472 inputs, 451, 585 set/reset register, 471, 472 Axiomatic systems, 83 Axioms, 84 finite state

holding

algebra, 12, 58, 65, 83 variable, 59, 62

BOOZER,

92

AND-OR-INVERT,

low

Balas, Egon, 182 Balas, zero-one subroutine, 182 Bare-bones block diagram, 447, 448 Base, 19

176

walking variable elimination, 176 Bouncing switch, 76, 287 Boundaries (of map), 137 Branch: address, 603 conditionally, 595 controlled by asynchronous variable, 476 decision, 462 flag, 570 unconditionally, 595 Branch/Count instruction, 603 Branch/Output, 336, 460 Burning (ROM's), 549 Busable, gates, 251 Bus: drivers, 251 line, 251 oriented structures, 254 Bytes, 36

register, 471,

CAM'S,

418, 282 73 Canonical form, 102, 154

CMOS,

761

Canonical products of sums, 104 Canonical sum of products, minterms, 102 Carry, look ahead, 202, 204, 226 Catching cell, 467 Catching, one/zero, 318 Characteristic table (flip/flop), 302 Clock (oscillator): design, 298-301 frequency, determination, 506 skew, 324 system, 297 Codes: alphameric, 44 ASCII, 44, 45 Baudot, 44 BCD, 39 binary /gray conversion, 43 biquinary, 38 EBCDIC, 46 error, correcting, 46, 48 excess-three, 38, 231 Gray (reflected binary), 41, 43, 39,

390

Hamming, 46

NBCD,

38 complementing, 39 unit-distant, 40 Code, sequence decoders, 335 Codes, converters, 226 Combinational: self

analysis, 118, 119 circuit model, 263 design steps, 80, 167

design, using decoders, 233, 234, 237 design, using MSI and LSI, 532 design, using MUX's, 212 properties, 280 systems, 49 Commutative laws, 86

Compatibility, 113

Complements: one's two's

416 ring counter using a shift register, 406, 416 ripple,

single

398

mode, 387, 391

specification, 386 unit distance, 394,

390

up/down, 392 uses, 386 Counter rates, 399

Critical races, 668

32 34 34

(r-l's), (r's),

variables, 81

Conditional: inputs, 458, 460, 485, 510, 595, 605 outputs, 336, 338, 359, 360, 363, 464, 510 Coincidence, gate, 92 Conjunctive (pos form), 105

Continuous, definition of, 5 Control and display, 507 Control inputs, 441 Controlled systems, 276 Control sequences, 447 Controller configurations, synchronous: counter centered, 581, 592, 596 direct addressed multiplexer, 537 or PLA, 570 direct addressed indirect addressed multiplexer, 537 indirect addressed multiplexer/ ROM, 572 or PLA, 570 indirect addressed MSI, 534

ROM

ROM

programmable, 601, 607, 615, 618, 621, 634, 642 shift register centered, 581, 582 SSI, 505 Controllers: architecture (choosing), 465, 470

762

asynchronous, 692 asynchronous (handshake), 694 asynchronous multi-input/output, 692 design phases, 444 fixed instruction, 629 programmable, 586, 592, 599, 600, 608 synchronous multi-input/output, 692 system, definition of, 441 system, model, 277, 452 Conversion, numbers, 11 Count/ Branch state assignment, 595 Count, conditionally, 595 Count, unconditionally, 595 Counter: binary, 389 cascadable, 580 controllable, 600 decade, 389 definition of, 387 design, 391, 394 Johnson, 586 model, 387 Moebius, 402 modulo number, 386 multi-mode, 392, 394 programmable, 601 ring, standard and twisted, 349-50, 402, 403,

Cross-coupled NAND/NOR, 283 Cross referenced drawing, 109, 116 Cycle, 668

Comparators, 207

logical,

Controllers (Cont'd)

Index

Data lockout (flip/flop), 318 Data selector (mux), 210 De-assert, 459 Decision/ Action, 460 Decision

state, definition,

461

Decoders/ Demultiplexers, 231 BCD-to-decimal, four line-to- 10, 229, 230 excess 3-to-decimal, 229, 230 four line-to- 16, 233 instruction, 610 in system controllers, 533

I/O

decoder, 237

next-state, 292, 315, 340, 341, 458, 485, 499,

538 output, 340, 341, 366, 381, 472, 474, 485, 538 set/reset, 297, 309 three line-to-8, 227, 232 two line-to-4, 228, 232 use in combinational circuits, 223, 234 Delimiter, 183 DeMorgan's theorem, 87, 90, 153

Design documentation, 444 DeSpain, A.M., 58 Digital design, definition,

Direct-addressed

539

MUX

1,

2, 10, 57, 58,

configuration,

275 537,

Functional partition, 452, 453 Fundamental mode model, 653 Fusible link, 547

Discrete signals, 5 Discrete system, 1, 3, 10 Disjunctive form (SOP), 105 Distinctive shaped symbols:

AND,

68, 69, 72

EXOR, 99 INVERTER,

Gates:

AND, 68, 69, 72 AND-OR-INVERT, EXOR, 99

78

NAND, 93, 71 NEXOR, 99 NOR, OR,

NAND, 71, 93 NEXOR, 99

94, 95

68, 70, 72

NOR,

Distributive laws, 86 flip/flop (see Flip/ Flop)

D

Documentation,

108,

Appendix

OR,

(see also Hazards),

Glitch, 647 Glitch-free outputs, 472

Glitching problem, 473

GO-NO-GO

construct, 480, 483

Graphic logic symbols, 115

677 Half

Edge

94, 95 68, 70, 78

Generic, 549

A

schematic, 57, 110 Dolby system, 588 "Don't Care", 83, 161, 148 Dual bus, 558 Duals, 140

Dynamic hazard

244

triggered, 318

bit (see

Metastable state)

Handshake, 292, 469

Handshake

MDS

construct, 488

Enable operator, 1 14 Encoder, definition of, 240 Encoder, priority, 241 Encoding, 35

Hang

Equivalence, 92, 98 Eraseable programmable read-only-memory,

680 703 static, 676, 706 Heat cycled, 508 Heisenberg uncertainty principle, 474 Hold times, 323 Huffman, D.A., 292, 365 Huntington postulates, 85 Huntington systems, 89

282, 549, 554

Error codes (see also Codes), 46 Error detecting, 46 Essential implicant (see also Implicant), 147 Excitation table (flip/flop), 304 Excitation variable, 654, 657 (EXOR), 92, 98, 244, 246 Exclusive (EXNOR), 98 Exclusive

OR NOR

states,

347

Hazards: cover, 706

dynamic, 677 essential, 677, 678,

MEVs,

Identities,

87 114

Fall time, 7

I incompatibilities,

Fan Fan

259 out, 259 Feedback, 51, 276

Immediate outputs, 510, 605

Feedback variables, 657 FIFO, 418 Finite state machines (FSM), 278, 279, 291 Fixed instruction machine, 629 Flag, 452, 613

necessary, 147 optional, 147 prime, 147 redundant, 147 Indirect-addressed Indirect-addressed

Flip/Flop, 295 clocked flip/flop, 297, 314, 323 clocked "J/K", 306, 320, 321 clocked "T", 305 conversion, 311, 375

Indirect-addressed Information, definition, 59 Infrequently used variables, 162, 224 Inhibit, 114

in,

Filters, 14,

"D" "D"

558

322 304 design steps, 308 edge triggered, 320 general model, 296 master/slave "JK", 307, 317-19 pulse triggered, 302, 304, 307, 316 set/reset, 302, 303 traditional, 302 Flow diagram: constructs, 452 detailed, 452, 453 first cut, 447, 448, 452 Flow/MDS diagram, 460 FPLA (see PLA's) flip/flop, latch,

Implicants: essential, 147

572

MUX configuration, 544 MUX/ROM configuration, ROM configuration, 570

table, truth table, 64, 69 Instruction decoder, 610 Instruction set, fixed, 608 Instruction set for 8X02, 619 Internal control word, 602 Interrupt, 615

Input/Output

Inverter, 78 Inverter, concept of, 77 Inverters, minimized, 81

Islands, 140

"JK"

flip/flop (see Flip/flop) to sub-routine, 613 Juxtapositional notation, 19

Jump

Index

763

Memory

Karnaugh, M., 134

Karnaugh maps

(see

dead, 546 element, 280, 341

Kipling, Rudyard, 2

K-maps

Maps)

(see

(Cont'd) 282, 283

CAM's,

Maps)

RAM's,

RMM's, Large Scale Integration (LSI), 198, 199 Level synchronization, 468 LIFO, stack, 418, 617 Linear control system, 277 Load Jam Address (LJA), 613

Load map

(see

Maps)

power supply, 506

factor,

condition, 483

Logic, definition, 51, 59 Logic, positive and negative, 74 Logic, wired, 251

Logic Logic Logic Logic Logic Logic

Look

Merge, 665 Merge diagram, 666 Merged flow table, 660, 666 Merged mixed and non-mixed, 662, 665 Merge rules, 665

Metas table:

Load/Shift operation, 582

Load

ROM's,

282, 418, 421 282, 549 174, 282, 532, 544, 546

480

level,

region, 482 resolver, 480, 484

action, 58

state,

482

voltage, 483 Micro code instruction, 602, 603, 605

adjacency, 130 adjacency theorem, 90 functions, 59, 65 gates (see Gates) state indicators, 112 up table, 201

Micro code

listing,

608

Microprocessors, 444, 546

Microprogrammed controller, 546, 561, 602,

629

sequencer, 242, 636

Microprogramming, 558, 560 Mapping, 129 Mapping, variable entered, 157

Minimization:

Boolean expressions,

Maps:

131, 175, 174

action, 587, 588

combinational, 129 computer aided, 176

composite, 659 count enable, 597

inverter functions, 81 minimal cover, 140, 147

cycle, 141

multi output, 155

data input, 587

package count, 533

excitation, 654, 657, 685 excitation, plotting and reading,

partially simplified, 154

670

input data, 589 Karnaugh, 134

K-map K-map K-map

plotting, 135

labeling, 137

reading, 140, 150

load, 597

map

entered expression, functions, 160, 162, 708 map entered variable, 344 mode control, 587, 589, 597

NEXOR

and EXOR, 247

next state, 345 output, 342, 657, 685 parallel data, 598 reading steps, 140 ring,

669

Max term,

MDS

theorem, 85, 102 100, 102-5, 134 Minterm recognizer, 231 Mixed logic, 62, 74, 109, 170 Mixed logic concept, 82

Minterm,

Mnemonics, 1 10, 447 Moore, E. F., 292, 365

Moore machines, 294, 360, 510 Multi-mode counter (see Counters) Multi-mode shift register (see Register) Multiplexers (MUX), definition of, 210 mixed rail, 221 Multiplexers: general model, 212 2 to 1, 211, 216

4 to

245

and five variable, 144 state map, 371, 588 six

transition,

single statement algorithm, 150

100, 104, 105 diagram (see also State diagram):

generation, 457 multi-state, 461 shift register sequence, 588 symbology, 457, 458

1,

211

8 to 1, 218, 219 16 to 1, 218, 219 stack (tree), 220, 223 Multipliers, 205 Mux in system controllers, 537 Mux's contemporary design, 214, 221

MYCA MYCA

I,

II,

609, 611-613 612, 615, 618, 619, 636

instructions, 616

MDS

diagrams, 457 Mealy, G. H., 293 Mealy machine, 293, 360 Medium Scale Integration (MSI), 198, 199 Memory address register (see also Register), 600 Memory, concept of, 281

Negative

Memory:

NEXOR,

basic

764

cell,

282, 549

Index

NAND,

92, 93

NAND

function, 93 Necessary implicants (see also Implicants), 147

Next

74 246 340

logic,

92,

state,

Next Next Next Next Next Next

507 decoder (see Decoders) state forming logic (see Decoders)

Radix, 19 Radix divide/ multiply conversion, 26

state branching, state

state

maps

state tables,

Radix point, 19

Random Random

Access Memory (RAM), 282, 418, 421 logic systems controller, 528 Read Mostly Memory (RMM), 282, 549

Map)

(see

347

state variables

map, 343

Read Only Memory (ROM),

Nibble, 36 Noise, 7

Nonadjacent assignments

(see State assignment)

Non-critical race, 669

NOR,

92,

Number Number

174, 282, 532,

Read Only Storage (see also ROM), 561, 601 Reduce input dependency (state assignment), 475

94

Redundant

conversion, 24 systems, 19

On the fly check, 508 One-zero, catching, 318 Open collector, 253 Operator, logic (see also Logic function), 65 Optional implicant (see also Implicant), 147 OR, 65, 68, 72, 92 tie, 253 Oscillators (see Clock)

OR

Output decoder Output holding

(see

Decoder)

register (see also Register), 471,

472, 474, 475, 538

Outputs: conditional, 336, 338, 359, 360, 363, 464, 510 unconditional, 463, 465 Output timing diagram, 359 Outside world inputs, 346, 353 Over Voltage Protection (OVP), 507

Parallel data inputs, 589 Partition arrays, 179

Partitioned truth tables, 160 Past history, 280 Permanent storage (see also ROM's), 532, 561 PLA's (FPLA's), 175, 562, 563, 565, 568 Polarized: element, 61, 74 mnemonics, 60, 109 Polynomial notation, number system, 23 Positive logic, 74

states,

346

Reflective codes (see Codes) Registers: as ring counter, 416 asynchronous input, 471, 472 type, 580 JK type, 580

D

memory, 418

memory

address, 600

multi-mode, 411, 412 output holding, 471, 472, 475, 538 PIPO, 407 PISO, 410 sequences, 415 shift, 307, 415, 587 SIPO, 407 SISO, 410 Reset operation, 284 Rise time, 6 R-l's complement 34, 35 R's complement, 32, 33 Runt pulse, 48

Sample/ Hold, 13 Sampling theorem, 13

Present state, 292

SAM's (seq. accessed memory), 282, 418 Secondary variable, 654 Sequential circuits, 275, 278, 279, 337 architectural distinction, 280, 290 code generations, 335 fundamentals, 290 need for, 276 properties, 280 system, 49 using shift register and counter, 581 Serial 2's complement system, 486

Primitive:

Set operation, 284

Postulates, numbers, 84

Power supply requirements, 506

flow table, 622, 664 state diagram, 359, 455, 655 state table, 363,

Product of

Sum

Set/ Reset decoder (see Decoder) Set up time, 323 Shannon, Claude, 1, 58, 83

662

(POS), 104, 105

Programmable sequential machines

Shift registers (see Register)

(see System

controllers),

Programmable system

controllers (see

controllers),

PROM

(see also

random

ROM's),

557 Propagation delay, 261 Pull up resistor, 252 Pulse catching, 468 logic,

Quine-McCluskey, 288 Races: critical,

544-

48

668, 669

noncritical, 668,

669

545, 549

System

Short pulse catching circuits, 468 Simplifying partially simplified expression, 154 Single statement reduction algorithm, 150 Single step pulse circuit, 684, 702

602 Small Scale Integration (SSI), 198

Slice (bit),

SOP, Sum of Products, 105 expressions, 103 Spike, glitch, 674 Stable, definition of, 654 Stable state, 655 Stack, 418 FIFO, 418, 419, 421 LIFO, 418, 615, 617

memories, 418 Standard form, 154

Index

765

Standard load, 259, 260 Standard ring counter, 402 Standard sum of products, 104 State, definition of, 292, 336 State analyzers, 508

System Controllers centered around (Cont'd) MYCA I, 609, 611-13 MYCA II, 612, 615, 618, 619, 636

State assignment, 356, 365, 475, 660, 667 asynchronous inputs, 476

System design around a 494

ROM/PROM's, shift register,

design,

discrete,

on the fly, 508 Flip/ Flop (see Flip/ flop) Theorems, Boolean, 87 Timing and frequency consideration, 451 Timing diagram, detailed (DTD), 447, 451, 542 Transient codes, 474 Transient output, 264 Transition map (see also Map), 669

Testing,

T

hazard (see Hazards), Sub-minterms, 160 Sub routine, 615 Subtractor, binary, 205 Static

Tri-state,

True next state, 341 True next state code, 371 Truth table, 62, 134, 459

of products, canonical, 102 Superposition, 4 Switch: as a logic signal source, 76

partitioned, 160

TTL,

Two

debouncing, 76, 288 Symbolic, language, 8 Synchronization, 465, 466 improper, 466 level, 468 of two systems, 465

Undefined state Unit distance: 353

analysis, 339, 352 design process, traditional, 353

well behaved, 476 Synch strobe, 472 System clock (see Clock), System controller, definition of, 441 System controller: multi branch, 441, 540 multi input, 440, 441, 540 role, 445, 446 System controller, programmable, 580, 581, 595

microprogrammable

8X02, 619, 623, 628, 636 74S482 (bit slice), 629, 636 642

MYCA 607, 609, 611-13 MYCA II, 612, 615, 618, 619, I,

636 System controllers center around, counters, 581, 592, 596 decoders, 534, 540 FPLA's, 575 MUX'S, 540

766

Index

73, 335 level form, 107

Unconditional outputs, 463, 465

circuits, 348,

(bit slice), 636, 637,

252

bus, 256

Sum

MC2909

1

three D's, 499

#

controller, centered around:

440

development, 497

unit distance, 452 State diagrams, 335-38, 461 State diagram (tight/loose), 360, 361 State identifier, 535 State indicator, 70, 113, 117 State map, 371, 588 State of interest, 336 State of the machine, 340 State reduction, 364 rule 1, 368 rule #2, 369 State variables, 292

System

controller, steps, 444,

Systems: continuous, 2 cycle speed, 506

improper, 477 niinimal locus, 475 reduced input dependency, 475 rule #3, 381

Synchronous sequential

568, 571

582

transition,

466

feedback code, 667 476 Universal gates, 92 Unrecoverable errors, 478 Unresolved synchronization, 480 Unstable, definition of, 654 Useful relationships, 89 state assignment,

entered expression, 162 entered map (see Map) entered mapping, 129 entered plotting, 158 entered reading, 162, 163 Voltage range, 73 Variable Variable Variable Variable Variable

Why

digital, 8

Wired logic, 253 Words, definition, 36

Zero-one optimization, 176, 177 Zonal-coordinates, 109, 116

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